JP2010103927A - Gain adjustment circuit, a/d conversion apparatus, and gain adjustment method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a gain adjustment circuit for reducing time for adjustment by reducing the frequency of gain change for adjusting a gain error, for reducing a load of adjustment, and for reducing the scale of the adjustment circuit. <P>SOLUTION: The gain adjustment circuit for adjusting the value of a digital output signal obtained by converting an analog signal into a digital signal to an ideal value to be output that has a linear relation with the digital output signal includes: a divider 105 for inputting an instruction to set a gain error correction value for converting a digital output signal into an ideal value, and for calculating a gain error correction value only for a predetermined time from the instruction; a register 106 for storing the calculated gain error correction value; and a multiplier 102 for reading the gain error correction value stored in the register 106 according to the adjustment timing of the digital output signal, and for multiplying it by the digital output signal. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a gain adjustment circuit, an A / D conversion device, and a gain adjustment method, and more particularly, to a gain adjustment circuit, an A / D conversion device, and this gain adjustment method suitable for reducing the time required for gain adjustment. .

FIG. 7 is a diagram for explaining a general configuration of the A / D conversion apparatus. The illustrated A / D converter 6 includes an A / D converter 1 and a reference voltage generator 2 that outputs a reference voltage to the A / D converter 1.
In an A / D converter, an error called a gain error may occur due to manufacturing variations or deviation from an ideal circuit as designed. Therefore, the configuration shown in FIG. 7 has a multiplier 3 and a register 4 that adjust the gain of a signal digitally converted by the A / D converter 1 with reference to a reference voltage, and a CPU (Central Processing) that controls the above configuration. Unit) 5.

In the A / D converter, when an input signal Va is input, a state in which an output signal Da to be output, which is desired by the user, is obtained as “ideal”. However, the output signal Dax may be output with respect to the input signal Va due to a gain error.
Such a gain error can be adjusted by the CPU 5 writing the gain in the register 4. For example, in the prior art described in Patent Document 1, the CPU 5 adjusts the gain by writing the difference between the pre-adjustment conversion value and the ideal value conversion value in the register 4. A microcomputer is generally used for the adjustment circuit for gain adjustment.
Japanese Patent Laid-Open No. 9-119853

  However, the conventional technique requires a plurality of adjustments to adjust the gain error, and it has been desired to reduce the time required for the adjustment and the number of processes. For example, in the case of the configuration shown in FIG. 7, the CPU 5 changes the gain value written in the register 4 while monitoring the output Dout of the A / D conversion device 6. The change of the gain value is repeated until the output Dout becomes an ideal value.

  In the invention of Patent Document 1, correction data is calculated using the difference between the actual measurement voltage and the ideal measurement voltage, and the difference between the other actual measurement voltage and the correction data is stored. For this reason, A / D conversion must be performed at least twice for one gain change. For this reason, in the invention of Patent Document 1, it is necessary to give a command to the microcomputer a plurality of times when changing the gain value, and the processing load is further increased.

Further, since the microcomputer has a relatively large circuit scale, there is a drawback that it is difficult to incorporate the microcomputer into an A / D converter.
The present invention has been made in view of the above-described points, and can reduce the time required for adjustment by reducing the number of gain changes for adjusting the gain error, and reduce the load required for the adjustment. In addition, it is an object to provide a gain adjustment circuit, an A / D converter, and a gain adjustment method that can reduce the circuit scale.

  In order to solve the above problems, a gain adjustment circuit according to claim 1 of the present invention is a digital output signal obtained by converting the value of a digital output signal obtained by digitally converting an analog signal into the digital output signal. Is a gain adjustment circuit that adjusts to an ideal value that is linearly related to an input value, and inputs an instruction to set a gain error correction value that converts the digital output signal to the ideal value, and is input within a predetermined time from the instruction A gain error correction value calculation circuit for calculating the gain error correction value using the digital output signal, and a first storage unit for storing the gain error correction value calculated by the gain error correction value calculation circuit; The gain error correction value stored in the first storage unit is read according to the input timing of the digital output signal, and the input digital output signal and the input Characterized in that it comprises a multiplier for multiplying the in-error correction value.

A gain adjustment circuit according to a second aspect of the present invention is the gain adjustment circuit according to the first aspect, wherein the gain error correction value calculation circuit converts a digital output signal obtained by converting an input analog signal into a digital output signal with the ideal value. It includes a divider for dividing and calculating a gain error correction value.
According to a third aspect of the present invention, there is provided a gain adjustment circuit according to the first aspect, wherein the gain error correction value calculation circuit according to the first aspect includes a digital output including an error generated when the ideal value and an analog signal are converted into a digital output signal. A comparator that compares an error value that is a value of a signal, and the comparator outputs a gain error correction value that converts the error value into the ideal value based on a result of comparison. .

  A gain adjustment circuit according to a fourth aspect of the present invention is the gain adjustment circuit according to any one of the first to third aspects, wherein the second storage unit stores a gain error correction value set to an arbitrary value, the first storage unit, A selector that selects one of the second storage units, and the multiplier is a gain error correction value read from either the first storage unit or the second storage unit selected by the selector. And the digital output signal.

  The A / D conversion device according to claim 5 is an ideal value that is a value to be outputted and is linearly related to the digital output signal obtained by digitally converting an analog signal. An A / D converter for adjusting and outputting a value, an analog signal input, an A / D converter for converting to a digital output signal, and a gain for converting the digital output signal to the ideal value A gain error correction value calculation circuit that inputs an instruction to set an error correction value and calculates the gain error correction value using the digital output signal input within a predetermined time from the instruction, and the gain error correction value A first storage unit storing the gain error correction value calculated by the calculation circuit, and the gain error correction value stored in the first storage unit according to the input timing of the digital output signal. Read Te, characterized in that it comprises a multiplier for multiplying the digital output signal input and said gain error correction value.

  According to a sixth aspect of the present invention, in the gain adjustment method, the value of the digital output signal obtained by digital conversion of the analog signal is an ideal value that is a value to be output and is linearly related to the digital output signal. A gain adjustment method for adjusting, wherein an instruction for setting a gain error correction value for converting the digital output signal to the ideal value is input, and the digital output signal input within a predetermined time from the instruction is used. A gain error correction value calculation step for calculating the gain error correction value, a storage step for storing the gain error correction value calculated in the gain error correction value calculation step, and the gain error correction value stored in the storage step Is read according to the input timing of the digital output signal, and multiplies the input digital output signal by the gain error correction value Characterized in that it comprises a degree, the.

  According to the gain adjustment circuit of the first aspect of the present invention, the gain error correction value is calculated only within a predetermined time from the instruction to set the gain error correction value, and the calculated gain error correction value is stored. Can do. Then, the stored gain error correction value can be read out in accordance with the input timing of the digital output signal and used repeatedly for correcting the gain error of the digital output signal.

Further, since the digital output value and the ideal value have a linear relationship, the gain error can be corrected using the same gain error correction value even if the input analog signal fluctuates. For this reason, A / D conversion and calculation for calculating the gain error correction value are only required once, and the digital output signal can be converted into an ideal value by one correction. You can fix it later.
Further, after inputting an instruction for setting a gain error correction value, a circuit or the like can be operated sequentially to correct the gain error of the digital output signal. For this reason, the gain error can be corrected only by outputting a single instruction from a control circuit such as a CPU.

According to the gain adjustment circuit of claim 2 of the present invention, the gain error correction value calculation circuit may be a divider, and the gain adjustment circuit may be configured by a storage unit such as another multiplier or a register. For this reason, it is more advantageous to reduce the circuit area than a configuration in which gain adjustment is performed using a microcomputer.
According to the gain adjustment circuit of the third aspect of the present invention, the gain error correction value calculation circuit may be used as a comparator, and the gain adjustment circuit may be configured by a storage unit such as another multiplier or a register. For this reason, it is more advantageous to reduce the circuit area than a configuration in which gain adjustment is performed using a microcomputer.
According to the gain adjustment circuit of the fourth aspect of the present invention, either the calculated gain error correction value or the gain error correction value set to an arbitrary value is appropriately selected and used to correct the gain error. You can also.

According to the A / D conversion device of claim 5, A / D conversion and calculation for calculating the gain error correction value are only required once, and the digital output signal is converted into an ideal value by one correction. Thus, the gain error can be corrected in a short time. Furthermore, the gain error can be corrected only by outputting a single instruction from a control circuit such as a CPU.
According to the gain adjustment method of the sixth aspect, A / D conversion and calculation for calculating the gain error correction value are only required once, and the digital output signal is converted into an ideal value by one correction. Therefore, the gain error can be corrected in a short time. Furthermore, the gain error can be corrected only by outputting a single instruction from a control circuit such as a CPU.

Embodiments 1 to 3 according to the present invention will be described below with reference to the drawings.
(Embodiment 1)
(Constitution)
FIG. 1 is a block diagram showing an A / D conversion device 100 and a CPU 110 that controls the A / D conversion device 100 according to the first embodiment of the present invention. In the A / D converter 100, the configuration excluding the A / D converter 101 is the gain adjustment circuit of the first embodiment. In addition, a solid line shown in the figure indicates an analog input signal, a calculation value exchanged for A / D conversion of the analog input signal, and a digital signal after conversion.

Control of the A / D converter of the CPU 110 is executed via the sequencer 108. A one-dot chain line in the figure indicates a control signal output from the CPU 110 and the sequencer 108. The control signal includes an instruction signal for instructing to start setting of a gain error described later. The instruction signal is output when the user operates a computer or the like including the CPU 110.
The A / D converter includes an A / D converter 101 and a reference voltage generation unit 103 that generates a reference voltage that is used by the A / D converter 101 to digitally convert the analog input signal Va. The A / D conversion apparatus 100 further includes a divider 105, a memory 104, a register, a selector 107, a multiplier 102, and a sequencer 108.

  The A / D converter 101 compares the reference voltage with the analog input signal Va and outputs a digital output code Dax that becomes a digital output signal. The digital output code Dax includes a gain error generated by the A / D converter 101 and the reference voltage generator 103. The memory 104 stores a digital output code Da (hereinafter also referred to as an ideal value) that the user desires to output. The divider 105 divides the digital output code Da by the digital output code Dax including an error.

The value obtained as a result of the division becomes a digital output signal correction value for converting the digital output code into an ideal value. In the first embodiment, the digital output signal correction value is hereinafter referred to as a gain error correction value Ga. The gain error correction value Ga is stored in the register 106.
The gain error correction value Ga stored in the register 106 is output to the multiplier 102 via the selector 107. The digital output code Dax is multiplied by the gain error correction value Ga in the multiplier 102 and output from the A / D converter 100 as the digital output value Dout.

The gain error correction value Ga stored in the register 106 can also be read from the CPU 110. When the CPU 110 reads the gain error correction value Ga, the CPU 110 outputs the read gain error correction value Ga to the multiplier 102 via the selector 107. The gain error correction value Ga is multiplied by the digital output code Dax in the multiplier 102.
In the first embodiment, only one ideal value Da is stored in the memory 104. Then, when setting the gain error, the user is instructed to input the analog input signal Va having a value corresponding to the ideal value stored in the memory 104. The instruction may describe the value of the analog input signal to be input in the specifications of the A / D converter, or post the value of the analog input signal Va on the HP of the product. It may be a thing.

  In the above configuration, the divider 105 receives an instruction signal for instructing the setting of the gain error correction value Ga from the CPU 110 via the sequencer 108. At this time, the analog input signal Va corresponding to the ideal value Da is input to the A / D converter 101. The A / D converter 101 converts the analog input signal Va into a digital output signal Dax. The divider 105 needs to divide the ideal value Da by this digital output signal Dax to obtain an accurate gain error correction value Ga.

  For this reason, in the first embodiment, the input and division of the digital output signal Dax are executed only within a predetermined time from the input of the instruction signal. The predetermined time may be a certain time such as 1 millisecond, 1 second, or 10 seconds. Alternatively, the user may be instructed to input the analog input signal Va together with the value of the analog input signal Va, and the digital output signal Dax may be input and divided within this time.

  Further, in the above-described first embodiment, the instruction signal may be one time, and the instruction signal output stop instruction is not necessary. However, the instruction signal output stop instruction is given to the sequencer 108 by operating the computer including the CPU 110. The digital output signal input during the time until the instruction signal output stop is instructed may be divided by the ideal value Da. When the digital output signal is executed a plurality of times within a predetermined time, the gain error correction value Ga obtained by the previously executed division is updated with the gain error correction value Ga obtained by the subsequent division. It may be a thing.

  In the first embodiment, the register 109 is provided, and the CPU 110 can write an arbitrary value as a gain error in the register 109. In the first embodiment, a selector 107 that selects either the register 106 or the register 109 is provided. Then, by switching the registers 106 and 109 by the selector 107, the gain of the digital output code Dax can be adjusted using either the calculated gain error correction value Ga or an arbitrary gain error.

  In the configuration described above, the digital output signal corresponds to the digital output code Dax, the ideal value corresponds to the ideal value Da, and the gain error correction value corresponds to the gain error correction value Ga. The divider 105 corresponds to a gain error correction value calculation circuit, and the register 106 corresponds to a first storage unit. Further, the gain error correction value Ga is read according to the timing of inputting the digital output signal, and the multiplier 102 corresponds to a multiplier that multiplies the gain error correction value Ga and the digital output code Dax. The register 109 corresponds to a second storage unit.

(Gain error correction value)
Here, the relationship among the analog input signal Va, the digital output code Dax, the ideal value Da, and the gain error correction value Ga will be described.
FIG. 2 is an ideal input / output characteristic graph of the A / D converter 101, where the vertical axis represents the ideal value Da and the horizontal axis represents the analog input signal Va. With ideal input characteristics, a digital output code Da is obtained for the analog input signal Va. Further, a digital output code 2Da is obtained for the analog input signal 2Va.

FIG. 3 is a diagram illustrating input / output characteristics of the A / D converter 101 including a gain error. The vertical axis represents the ideal value Da, and the horizontal axis represents the analog input signal Va. As shown in the figure, the first embodiment assumes that the input / output characteristics of the A / D converter 101 are linear.
When a gain error is included, when the analog input signal Va is input, the A / D converter 101 outputs a digital output code Dax that is different from the digital output code Da. At this time, the gain error correction value Ga is
Ga = Da / Dax
It is expressed.

  When the gain error correction value Ga is calculated in the divider 105, the gain error correction value Ga is written in the register 106. The selector 107 designates the register 106, reads the gain error correction value Ga, and outputs it to the multiplier 102. The multiplier 102 multiplies the digital output code Dax by a gain error correction value Ga, that is, Da / Dax. As a result of the multiplication, the digital output code Dax is converted into an ideal value Da and output from the A / D converter 100.

At the next adjustment timing of the digital output code Dax, the selector 107 selects the register 106, and the gain error correction value Ga is output from the register 106 to the multiplier 102. In the multiplier 102, similarly to the previous adjustment of the digital output code Dax, the digital output code Dax is multiplied by the gain error correction value Ga, and the digital output code Da is corrected and output.
The correction of the digital output code Dax is periodically repeated. In the first embodiment, the gain error correction value Ga is read from the register 106 to the multiplier 102 and multiplied by the digital output code Dax according to the timing of periodic correction of the digital output code Dax.

  For this reason, in the first embodiment, once the gain error correction value Ga is calculated, the A / D conversion and the calculation by the divider 105 are not performed at the timing of the subsequent adjustment unless the reset or the power is turned off. The gain error correction value Ga can be obtained. For this reason, the time taken to calculate the gain error correction value Ga can be saved and the digital code output code can be adjusted at high speed. Further, after resetting or after the power is turned off, the expected value Da can be obtained without inputting the analog input signal Va by writing the value of the register 106 read in advance into the register 109.

In the configuration described above, consider a case where the analog input signal Va fluctuates, for example, 2Va. As shown in FIG. 2, the ideal value corresponding to the analog input signal 2Va is the digital output code 2Da.
At this time, in the first embodiment, as shown in FIG. 3, since the input / output characteristics of the A / D converter 101 are linear, the A / D converter 101 outputs a digital output code 2Dax. The multiplier 102 reads the gain error correction value Ga from the register 106 and multiplies the digital output code 2Dax. As a result, the digital output code 2Da, which is an ideal value, is output from the A / D converter 100. That is, in the first embodiment, even if the analog input signal Va fluctuates, the gain error correction value Ga obtained by one calculation is written in the register 106 and can be repeatedly used to obtain an ideal value. .

(Operation)
FIG. 4 is a flowchart for explaining an operation for the A / D conversion apparatus 100 according to the first embodiment to store the gain error correction value Ga in the register 106. When a command is output from the CPU 110 to the sequencer 108, the sequencer 108 outputs a control signal to the A / D converter 101 and processing is started. The A / D converter 101 determines that the input signal Ain is the analog input signal Va (step S401). Then, the analog input signal Va is A / D converted using the reference voltage to calculate the digital output code Dax (step S402).

The divider 105 reads the ideal value Da from the memory 104, divides the digital output code by the ideal value Da, and calculates a gain error correction value Ga (step S403). The gain error correction value Ga is written and stored in the register 106 via the selector 107 (step S404).
Through the above processing, in the first embodiment, the gain error correction value Ga obtained by calculation can be stored in the register 106. For subsequent gain adjustment, the gain error correction value Ga stored in the register 106 is read and output to the multiplier 102. Therefore, in the gain adjustment, the digital output code can be converted into an ideal value without performing A / D conversion for obtaining the gain error correction value Ga.

  In the first embodiment, as described with reference to FIG. 4, a series of processing from the calculation of the gain error correction value Ga to the storage in the register 106 can be executed only by issuing a single instruction from the CPU 110. it can. For this reason, the load applied to the CPU 110 can be reduced, and the CPU 110 can adopt a small and inexpensive configuration. Furthermore, the configuration of the first embodiment can configure a circuit that adjusts the digital output code by the divider 105, the register 106, the selector 107, and the multiplier 102. Therefore, the gain adjustment circuit is more effective than the conventional technology that uses a microcomputer. The area cost can also be reduced.

  The first embodiment is not limited to the configuration described above. That is, in the first embodiment, when the gain error correction value Ga is known, the CPU 110 can write the known gain error correction value Ga into the register 109 so that the selector 107 always selects the register. is there. In such a case, the A / D conversion performed to calculate the gain error correction value Ga is not necessary.

  In the first embodiment, the ideal value is stored in advance in the memory 104 and the A / D converter is shipped, but the present invention is not limited to such a configuration. For example, when the user inputs the analog input signal Va and wants to output it as the digital output signal Db, the value of Db may be written in the memory 104 as an ideal value. Writing to the memory 104 can be instructed from the CPU 110. If an arbitrary ideal value is written in the memory 104, the gain error correction value Ga can be set using an analog signal having an arbitrary value.

(Embodiment 2)
FIG. 5 is a block diagram illustrating the A / D conversion device 100 and the CPU 110 that controls the A / D conversion device 100 according to the second embodiment of the present invention. Of the configurations shown in the figure, configurations similar to those described in FIG. 1 are denoted by the same reference numerals, and description thereof is partially omitted.
In the second embodiment, the digital output code Dax is directly input to the divider 105 and the gain error correction value Ga calculated by the divider 105 is stored in the register. The difference is that the data is once stored in a register and then output to the divider 105. In the second embodiment, the gain error correction value Ga is directly read from the divider 105 to the selector 107 and output to the multiplier 102.
Even with the configuration of the second embodiment, the same effects as those of the first embodiment can be obtained.

(Embodiment 3)
FIG. 6 is a block diagram illustrating the A / D conversion device 100 according to the third embodiment of the present invention and the CPU 110 that controls the A / D conversion device 100. Of the configurations shown in the figure, configurations similar to those described in FIG. 1 are denoted by the same reference numerals, and description thereof is partially omitted.
The third embodiment is different from the first embodiment in that the gain error correction value Ga is calculated using the divider 105, but the gain error correction value Ga is calculated using a comparator. That is, in the third embodiment, the initial value Ga ′ of the gain error is stored in advance in the register. Then, the digital output signal Dax output from the A / D converter 101 is input to the multiplier 102, and the multiplier 102 multiplies the digital output signal Dax and the initial value Ga ′.
A result of multiplication in the multiplier 102;
Da ′ = Ga ′ × Dax
Is calculated.

Dax is output to the comparator 601. Also, the ideal value Da stored in the memory 104 is read out to the comparator 601. The comparator 601 compares Dax with the ideal value Da, and changes the Ga ′ of the register 106 so that Da ′ = Da in the multiplier 102. The method of changing the register 106 is to compare Da and Da ′ with the comparator 106. If Da <Da ′, Ga ′ is decreased, and if Da> Da ′, Ga ′ is increased and new Da ′ = Ga. '× Dax is calculated. By repeating the calculation of Da ′ and the change of Ga ′, it becomes possible to obtain Ga ′ where Da = Da ′. The increase / decrease value of Ga ′ is changed each time the change is repeated. For example, the initial value is changed to 1, 1st 1/2, 2nd 1/4, 3rd 1/8... Nth 1 / (2 ⁿ ) And Thus, the third embodiment can obtain the gain error correction value Ga such that Da = Ga × Dax.

Also in the third embodiment described above, the gain error correction value Ga can be determined by one A / D conversion, and the gain error correction value Ga can be repeatedly used for subsequent gain adjustment.
Specifically, for example, when 0.5V (1/2 of the input full-scale voltage) is input as Va, in the ¹⁸ -bit A / D converter, 1/2 full-scale is 2 ¹⁶ = 65536 code, This is the expected value Da. At this time, the gain correction error Ga = 65536 / Ga ′ is obtained. As described above, in this embodiment, by limiting the analog input signal Va to a fixed value, the parameter for obtaining Ga is only the initial value Ga ′, so that the circuit configuration can be simplified.

In the third embodiment, the comparator 601 corresponds to the comparator of claim 3.
All of the A / D converters according to Embodiments 1 to 3 described above mainly target a power meter as an application. In the wattmeter, since the gain error in the A / D converter directly leads to the power error, correction is essential. Furthermore, since there is an individual difference in gain error between power meters, it is not necessary to obtain only one correction value, and correction for each individual is also necessary.

  However, in the past, as shown in FIG. 7, it was necessary to make corrections by changing the register 4 while observing Dout, and this was a time-consuming correction method that required repetitive work. According to the first to third embodiments, the gain error can be corrected without repeating the work, which can contribute to providing a power meter with good operability that can easily correct the gain error. .

It is the block diagram which showed the A / D converter of Embodiment 1 of this invention, and CPU which controls an A / D converter. 2 is an ideal input / output characteristic graph of the A / D converter shown in FIG. FIG. 3 is a diagram showing an A / D converter input / output characteristic including a gain error with respect to the ideal input characteristic shown in FIG. 6 is a flowchart for explaining an operation for the A / D conversion device of the first embodiment to store a gain error correction value Ga in a register. It is the block diagram which showed the A / D converter of Embodiment 2 of this invention, and CPU which controls an A / D converter. It is the block diagram which showed the A / D converter of Embodiment 3 of this invention, and CPU which controls an A / D converter. It is a figure for demonstrating the general structure of an A / D converter.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 A / D converter 101 A / D converter 102 Multiplier 103 Reference voltage generation part 104 Memory 105 Divider 106,109 Register 107 Selector 108 Sequencer

Claims (6)

A gain adjustment circuit that adjusts a value of a digital output signal obtained by digital conversion of an analog signal to an ideal value that is a value to be output and is linearly related to the digital output signal,
A gain for inputting an instruction for setting a gain error correction value for converting the digital output signal into the ideal value, and calculating the gain error correction value using the digital output signal input within a predetermined time from the instruction An error correction value calculation circuit;
A first storage unit for storing the gain error correction value calculated by the gain error correction value calculation circuit;
A multiplier that reads the gain error correction value stored in the first storage unit according to an input timing of the digital output signal and multiplies the input digital output signal by the gain error correction value;
A gain adjustment circuit comprising: The gain error correction value calculation circuit includes:
The gain according to claim 1, further comprising a divider that calculates a gain error correction value by dividing a digital output signal obtained by converting an input analog signal into a digital output signal by the ideal value. Adjustment circuit. The gain error correction value calculation circuit includes:
A comparator that compares the ideal value with an error value that is a value of a digital output signal including an error that occurs when an analog signal is converted into a digital output signal;
The gain adjustment circuit according to claim 1, wherein the comparator outputs a gain error correction value for converting the error value into the ideal value based on a comparison result. A second storage unit for storing a gain error correction value set to an arbitrary value;
A selector for selecting one of the first storage unit and the second storage unit,
The multiplier multiplies a gain error correction value read from either the first storage unit or the second storage unit selected by the selector by a digital output signal. 4. The gain adjustment circuit according to any one of 1 to 3. An A / D converter that adjusts an output value of a digital output signal obtained by digitally converting an analog signal to an ideal value that is to be output and has a linear relationship with the digital output signal. There,
An A / D converter that inputs an analog signal, converts it to a digital output signal, and outputs it;
A gain for inputting a gain error correction value setting instruction for converting the digital output signal into the ideal value, and calculating the gain error correction value using the digital output signal input within a predetermined time from the instruction. An error correction value calculation circuit;
A first storage unit for storing the gain error correction value calculated by the gain error correction value calculation circuit;
A multiplier that reads the gain error correction value stored in the first storage unit according to an input timing of the digital output signal and multiplies the input digital output signal by the gain error correction value;
An A / D conversion device comprising: A gain adjustment method for adjusting a value of a digital output signal obtained by digital conversion of an analog signal to an ideal value that is a value to be output and is linearly related to the digital output signal,
A gain for inputting an instruction for setting a gain error correction value for converting the digital output signal into the ideal value, and calculating the gain error correction value using the digital output signal input within a predetermined time from the instruction An error correction value calculation step;
A storage step of storing the gain error correction value calculated in the gain error correction value calculation step;
A multiplication step of reading the gain error correction value stored in the storage step according to the input timing of the digital output signal and multiplying the input digital output signal by the gain error correction value;
A gain adjustment method comprising:

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