JP2010103752A - Vehicle controller and on-board gateway device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a vehicle controller which allows a controller to recover from a waiting state to a normal state even if a system error occurs in the waiting state. <P>SOLUTION: A gateway device includes a CPU 8 and a WDC part 12A which monitors the CPU 8, wherein the gateway device communicates with other ECUs through a CAN communication bus. When receiving signals from the other ECUs through the CAN communication bus in a waiting state, the WDC part 12A recovers and allows the CPU 8 that is in a waiting state to start. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a vehicle control device and an in-vehicle gateway device, and more particularly to a vehicle control device and an in-vehicle gateway device that communicate with other control devices by CAN (Controller Area Network) communication or the like.

  2. Description of the Related Art In recent years, various types of electronic control have been developed in vehicles, and a plurality of electronic control devices (hereinafter simply referred to as ECU (Electronic Control Unit)) have been mounted on vehicles. By making various types of control electronic, for example, more precise control is realized, vehicle weight is reduced, fuel consumption is improved, and the like. In addition, a plurality of LANs such as CAN communication have been mounted on vehicles in order to coordinately control a plurality of ECUs or to perform distributed control with a plurality of ECUs.

The maximum number of connection nodes for CAN communication is about 30, but in order to improve communication reliability, generally about 10 nodes are connected to one bus. When it is desired to connect more ECUs, an additional bus is provided, and an ECU having a function of gatewaying communication between the ECUs is provided as a gateway device between the plurality of buses.
Such gateway devices are required to gateway communications even when the vehicle ignition (hereinafter simply referred to as IG) key is not turned on due to various control requests. In addition, such a gateway device uses a watchdog (hereinafter also referred to as WDC) unit having a function (watchdog function) for monitoring whether or not the system is functioning normally as a monitoring unit. Can be provided inside or outside.

FIG. 11 is a diagram schematically showing a gateway device 1X which is an example of a conventional gateway device. The gateway device 1X is mounted on a vehicle (not shown), and is communicably connected to another ECU (not shown) via a CAN communication bus. The gateway device 1X includes a microcomputer 2X, a power supply circuit 3, an IF (interface) circuit 4, and a CAN transceiver 5. The microcomputer 2X receives an IG signal via the IF circuit 4 and a CAN communication reception signal Rx (communication signal) via the CAN transceiver 5.
The gateway device 1X is activated when the IG signal is ON or when a communication signal from another ECU is detected, and when the IG signal is OFF and the CAN communication reception signal Rx is not detected, the gateway device 1X shifts to a standby state in order to reduce power consumption. ing. In the gateway device 1X, the WDC unit 12A is provided in the power supply circuit 3 (outside the microcomputer 2X).

  For example, Patent Document 1 or 2 proposes a technique that is considered to be related to the present invention in terms of a technique related to the WDC function.

Japanese Patent Laid-Open No. 05-73344 JP 2004-193865 A

When the gateway apparatus 1X shown in FIG. 11 shifts to the standby state, specifically, a clock circuit is sent from the CPU 8 via the RS-FF (reset set flip-flop) 9 to the microcomputer standby instruction (hereinafter referred to as STOP instruction) signal. 10 and the clock circuit 10 is stopped to shift to a standby state. When shifting to the standby state, from the viewpoint of power saving, a STOP command signal via the RS-FF 9 is output as a WDC stop signal from the port of the microcomputer 2X to the WDC unit 12A provided in the power supply circuit 3. The operation of the WDC unit 12A is also stopped.
On the other hand, when returning from the standby state, the IG signal or the CAN communication reception signal Rx is used as an activation request signal, and the RS-FF 9 cancels the STOP command signal in the microcomputer 2X by interruption based on these signals. At the same time, the WDC unit 12A is also activated. Each configuration of the gateway device 1X will be described in detail in the embodiment.

  As described above, in the gateway device 1X, after the transition to the standby state, the operation of the WDC unit 12A is also stopped. For this reason, in the gateway device 1X, when a circuit abnormality in the microcomputer 2X (for example, an abnormality in the interrupt circuit 7 or an abnormality in the signal path) occurs, the STOP command signal cannot be canceled by an interruption by the activation request signal. In addition to being unable to recover from the standby state, there is a problem that such a system abnormality is monitored and the microcomputer 2X cannot be initialized (RESET) in response to the occurrence of the abnormality.

FIG. 12 shows how the gateway device 1X shifts to the standby state and returns from the standby state when it is normal and abnormal (an abnormality that prevents the release of the signal that stops the clock in response to the start request signal) It is a figure shown in a timing chart about each (when it generate | occur | produces in 2X).
When normal, the IG signal is turned OFF as shown in FIG. 12A, and the STOP command signal is turned ON when the CAN communication reception signal Rx is not detected. As a result, the clock of the clock circuit 10 stops and enters a standby state. Since the WDC stop signal is also turned ON when the STOP command signal is turned ON, the WDC unit 12A is also stopped.
Thereafter, when the IG signal is turned on and an interrupt signal is generated, the STOP command signal is canceled and turned off. As a result, the clock of the clock circuit 10 operates and returns from the standby state. Since the WDC stop signal is also turned off when the STOP command signal is turned off, the WDC unit 12A is also activated.

Even when there is an abnormality, when shifting to the standby state, as shown in FIG. On the other hand, at the time of abnormality, the STOP command signal cannot be canceled even if the IG signal is turned ON when returning from the standby state. For this reason, the clock of the clock circuit 10 remains stopped, and as a result, it cannot return from the standby state. Furthermore, since the STOP command signal remains ON, the WDC stop signal also remains ON. As a result, the WDC unit 12A also remains stopped. For this reason, although the abnormality has occurred, the WDC unit 12A cannot monitor the abnormality.
In this case, since the microcomputer 2X cannot be reset by the RESET signal generated when the WDC unit 12A detects an abnormality, in order to return from the standby state, for example, the battery is once removed. Thus, it takes time to initialize the microcomputer 2X.

  For such a problem, for example, the system monitoring function may be operated during standby, but such a method is not preferable from the viewpoint of power saving. In addition, the gateway device needs to make the communication function work earlier than other ECUs that are communicably connected (for example, within 70 ms after receiving the IG signal). There is also a situation where it is difficult to provide a function for initializing a microcomputer by applying an IG signal or a communication signal.

  The present invention has been made in view of the above circumstances, and provides a vehicle control device and an in-vehicle gateway device that can return the control unit to normal from the standby state even if the system is abnormal in the standby state. The purpose is to provide.

  To achieve this object, a vehicle control apparatus according to the present invention includes a control unit and a monitoring unit that monitors the control unit, and controls a vehicle that communicates with another control device via a communication bus. When the monitoring unit receives a signal from the other control device via the communication bus when the monitoring unit is in a standby state, the monitoring unit returns from the standby state and is in the standby state. It adopts a configuration that restores.

  In the vehicle control apparatus, the control unit includes a count unit that counts the number of signals received via the communication bus when the control unit and the monitoring unit are in a standby state. When the count number exceeds a threshold value, the monitoring unit is preferably returned from the standby state.

  In the vehicle control apparatus, when the count number of the signal exceeds the threshold value, the count unit reverses an output level of a signal for setting the monitoring unit in a standby state, and the monitoring unit It is preferable to return the unit from the standby state.

  The vehicle control apparatus includes a storage unit that stores history information obtained by returning the monitoring unit from the standby state, and the count unit stores the history information when the monitoring unit is returned from the standby state. Preferably, the means is stored.

  In the vehicle control apparatus, it is preferable that the control unit is capable of changing the threshold value of the counting unit when the monitoring unit is set in a standby state.

  The in-vehicle gateway device of the present invention is an in-vehicle gateway device that transfers communication data output from a first control device connected to a first communication bus to a second control device connected to a second communication bus. A monitoring unit that monitors the control unit, and the control unit sets the monitoring unit to a standby state by turning off an ignition switch, and then sets the monitoring unit to a standby state. Adopts a configuration in which when the monitoring unit is in a standby state, when the signal is received from the first control device or the second control device, the monitoring unit returns from the standby state and returns the control unit in the standby state. is doing.

  According to the present invention, even if an abnormality occurs in the system during the standby state, the control unit can be normally returned from the standby state.

  The best embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a diagram schematically showing a configuration of an embodiment in which the present invention is realized by a gateway device equipped with an ECU. This gateway device 1A is different from the above-described conventional gateway device 1X in that it further includes a counter (counter) 11 and an AND gate 13 which will be described later.
The gateway device 1A is mounted on a vehicle (not shown) and is communicably connected to another ECU (not shown) via a CAN communication bus. The gateway apparatus 1A includes a microcomputer 2A, a power supply circuit 3, an IF circuit 4, and a CAN transceiver 5. The power supply circuit 3, the IF circuit 4, and the CAN transceiver 5 are each connected to the microcomputer 2 </ b> A, and the CAN communication bus is specifically connected to the CAN transceiver 5.

  The microcomputer 2A has a CAN protocol controller 6, an interrupt circuit 7, a CPU 8, an RS-FF 9, a clock circuit 10, a counter 11, and an AND gate 13. Specifically, the CAN transceiver 5 is connected to a CAN protocol controller 6, and a CAN communication reception signal Rx is transmitted from the CAN transceiver controller 6 to the CAN protocol controller 6 as a communication signal from another ECU. A CAN communication transmission signal Tx is transmitted to and received from the CAN transceiver 5. Further, the IF circuit 4 is specifically connected to the interrupt circuit 7, and the interrupt circuit 7 receives the IG signal from the IF circuit 4 and the CAN communication reception signal Rx from the CAN transceiver 5. The interrupt circuit 7 is configured to output a signal to the RS-FF 9 when an IG signal or a CAN communication reception signal Rx is input.

  The gateway device 1A shifts to the standby state when the standby condition is satisfied (when the IG signal is OFF and the communication signal is not detected). Here, the processing executed by the CPU 8 when shifting to the standby state is shown in the flowchart of FIG. When the CPU 8 detects that the standby condition is satisfied (step S11), it sets a return interrupt condition (IG signal ON or communication signal detection) (step S12), and further sets the count initial value of the counter 11 to a preset value. The process for setting to is executed (step S13). Then, after these processes are completed, a STOP instruction is executed (step S14). More specifically, the STOP instruction is performed by outputting a STOP instruction signal (stop signal) to the RS-FF 9 as a signal for stopping the clock of the clock circuit 10.

When receiving the STOP command signal “1” from the CPU 8, the RS-FF 9 outputs the STOP command signal “1”. This STOP command signal is input to the clock circuit 10 and also to the WDC unit 12A as a WDC stop signal (stop signal) as will be described later. When the output from the interrupt circuit 7 is input, the RS-FF 9 inverts the STOP command signal “1” and outputs “0”. As a result, the STOP command signal is canceled at the normal time. Note that the STOP command signal and the WDC stop signal may have reverse logic. In addition, the WDC stop signal is not limited to this, and may be an appropriate signal that can be input to the WDC unit 12A as a signal for stopping the WDC unit 12A before the clock of the clock circuit 10 stops, and can be subsequently released in a standby state. That's fine.
The clock circuit 10 is configured to generate a clock. A crystal oscillator (not shown) is connected to XOUT and XIN of the clock circuit 10, and the clock circuit 10 divides the frequency of oscillation of the oscillator to generate a clock having a frequency used in the microcomputer 2A. The generated clock is used as an operation clock for the CPU 8. The WDC unit 12A counts the clock and monitors the abnormality of the CPU 8.

The power supply circuit 3 is provided with a WDC unit 12A having a WDC function as a monitoring unit. The power supply circuit 3 receives a WDC signal for resetting the count number of the WDC unit 12A from the microcomputer 2A at a constant cycle. In decreasing the count number, specifically, the count number is reset. The WDC unit 12A continues to count the clock when the WDC signal is not input, and when the clock count is completed without the WDC signal being input (when the count number reaches a predetermined value), Assuming that an abnormality has occurred in the microcomputer 2A to be monitored, a RESET signal for initializing the microcomputer 2A is output to the microcomputer 2A.
Further, the STOP command signal “1” is input to the power supply circuit 3 from the RS-FF 9 as a WDC stop signal. When the WDC stop signal is input, the operation of the WDC unit 12A is stopped. When the IG signal or the CAN communication reception signal Rx is input in the standby state, the RS-FF 9 inverts the STOP command signal “1” and outputs “0”. As a result, the microcomputer 2A returns from the standby state, and the WDC unit 12A is also activated.

  In the gateway device 1 </ b> A, the above WDC stop signal is input to the power supply circuit 3 through the AND gate 13. Further, the output signal of the counter 11 is input to the AND gate 13. The counter 11 receives a CAN communication reception signal Rx. The counter 11 normally outputs “1” and counts down in response to the input of the reception signal Rx, and when the count is completed (when the communication signal is input more than a predetermined amount, in other words, the count number is a threshold value). "0" (predetermined output) is output. When the input signal from the RS-FF 9 is “1” (that is, when the input signal is a STOP command signal), the AND gate 13 supplies the power supply circuit 3 with the input signal “1”. When “1” is output and an input signal of “0” is received from the counter 11, the input signal from the RS-FF 9 is inverted to “0” and output.

  That is, in this embodiment, the predetermined output of the counter is used for canceling the stop signal in this way, and the stop signal is canceled based on the start request signal in the standby state. As a result, even when an abnormality that cannot be recovered from the standby state even if the activation request signal (IG signal or CAN communication reception signal Rx) is input to the microcomputer 2A, the WDC unit 12A can be activated. Thereafter, the RESET signal is output from the WDC unit 12A to the microcomputer 2A, whereby the microcomputer 2A can be initialized and returned from the standby state.

  FIG. 3 is a timing chart showing how the gateway device 1A shifts to the standby state and returns from the standby state when an abnormality occurs. The counter 11 counts down according to the CAN communication received signal Rx. Here, when the STOP command signal is OFF, “0” is input to one terminal of the AND gate 13. Therefore, when the STOP command signal is OFF, the AND gate 13 outputs “0” to the WDC unit 12A regardless of whether the input from the counter 11 is “1” or “0”. Therefore, when the STOP command signal is OFF and the clock circuit 10 is operating, the WDC unit 12A operates regardless of the output of the counter 11.

When the IG signal is turned OFF and the communication signal for CAN communication is not detected, the standby condition is established, and the STOP command signal is turned ON. Thereby, the clock of the clock circuit 10 is stopped. Since the WDC stop signal is also turned ON when the STOP command signal is turned ON, the WDC unit 12A is also stopped. Further, the counter 11 resets the count number of the counter when the STOP command signal is turned ON. Furthermore, the count initial value of the counter 11 is set to a value set in advance according to the establishment of the standby condition (transition to the standby state). By setting the counter initial value, the timing for operating the WDC unit 12A can be adjusted to an appropriate timing. In this regard, for example, the microcomputer 2A can be configured so that the threshold value can be changed when the WDC unit 12A is set to the standby state. Thereby, it is further possible to adjust the timing for operating the WDC unit 12A to an appropriate timing according to the situation when shifting to the standby state. Note that even if the counter initial value is changed, substantially the same effect can be obtained as when the threshold value is changed, so changing the threshold value includes changing the counter initial value. It is.
Thereafter, when the IG signal is turned ON, an interrupt signal is originally output from the interrupt circuit 7 to the RS-FF 9 in response to this, but here, since an abnormality has occurred, the STOP command signal remains ON and is not released. As a result, the clock circuit 10 remains stopped. Further, since the WDC stop signal remains ON and is not released, the WDC unit 12A also remains stopped.

On the other hand, when the reception signal Rx of CAN communication is input, the counter 11 counts down and outputs “0” to the AND gate 13 when the count is completed. As a result, the WDC stop signal is inverted from “1” to “0” (since the output level of the signal for setting the WDC unit 12A to the standby state is inverted), the WDC unit 12A is activated. Since the microcomputer 2A is stopped at this time, no WDC signal is input from the microcomputer 2A to the WDC unit 12A, and the WDC unit 12A outputs a RESET signal to the microcomputer 2A when a predetermined period has elapsed. As a result, the microcomputer 2A is initialized, and the clock circuit 10 is also restored.
As described above, the gateway device 1A initializes the microcomputer 2A and returns from the standby state even when an abnormality occurs in the system while the operation of the WDC unit 12A is stopped in accordance with the transition to the standby state. can do.

  The gateway device 1A can further be provided with a mechanism capable of detecting that an abnormality has occurred. FIG. 4 is a diagram schematically showing a gateway device 1B in which such a mechanism is further provided for the gateway device 1A. The gateway device 1B further includes a buffer (storage unit) 14 that stores, as history information, that the counter 11 outputs “0” in the standby state (that is, the WDC 12A is returned from the standby state). When the counter 11 outputs in the standby state, the buffer 14 stores the history information accordingly. For this reason, when the gateway apparatus 1B returns from the standby state, it is possible to detect an abnormality of the system based on the information stored in the buffer 14, thereby further notifying the occurrence of the abnormality.

  FIG. 5 is a diagram schematically showing a configuration of a second embodiment in which the present invention is realized by a gateway device equipped with an ECU. The gateway device 1C includes a WDC unit 12B, which is a WDC timer, provided in the microcomputer 2B instead of the power supply circuit 3, a point that the counter 11 and the AND gate 13 are not provided, a clock that is a prescaler 15 and a switching unit. The configuration is substantially the same as that of the gateway device 1A except that the switching circuit 16 is provided. For this reason, in the present embodiment, a description will be given mainly of a portion whose contents differ from the gateway device 1A due to these differences.

  The gateway device 1C shifts to the standby state when the standby condition is satisfied (when the IG signal is OFF and the communication signal is not detected), but when shifting to the standby state, the CPU 8 uses the STOP command as a signal for causing the RS-FF 9 to stop the clock The signal “1” is output. This STOP command signal is input to the clock circuit 10 via the RS-FF 9, whereby the clock of the clock circuit 10 is stopped.

On the other hand, in the gateway device 1C, the clock generated by the clock circuit 10 is also supplied to the WDC unit 12B when it has not shifted to the standby state (that is, during system operation). The WDC unit 12B inputs a clock from a clock input port (not shown) via the prescaler 15. The WDC unit 12B counts down the clock, and resets the count when a WDC signal is input from the CPU 8.
In the gateway device 1C, when shifting to the standby state, the operation of the WDC unit 12B is stopped by stopping the clock used for the operation of the WDC unit 12B. Therefore, in this embodiment, the STOP command signal “1” for stopping the clock is the standby instruction signal.
When the output from the interrupt circuit 7 is input, the RS-FF 9 inverts the STOP command signal “1” and outputs “0”. As a result, the STOP command signal is canceled in the normal state, the microcomputer 2B returns from the standby state, and the clock circuit 10 generates a clock, so that the WDC unit 12B is also activated.

  In the gateway device 1C, the clock generated by the clock circuit 10 is output to the prescaler 15 that divides the frequency. The prescaler 15 is connected to the WDC unit 12B via the clock switching circuit 16. The clock switching circuit 16 is configured to selectively switch the connection destination of the input terminal of the WDC unit 12B between the output terminal of the clock circuit 10 and the reception terminal of the CAN transceiver 5. In this way, the clock switching circuit 16 that switches the signal input path can switch the clock used for the count operation of the WDC unit 12B between the clock generated by the clock circuit 10 and the reception signal Rx of CAN communication.

  In the gateway device 1C, the WDC unit 12B performs down-counting according to the input clock signal. A WDC signal for resetting the count number of the WDC unit 12B is input to the WDC unit 12B at a constant cycle. The WDC unit 12B continues down-counting according to the input clock signal when there is no WDC signal, and an abnormality has occurred in the system when the counting is completed without inputting the WDC signal. The RESET signal for initializing the microcomputer 2B is output.

  As described above, the clock used for the count operation of the WDC unit 12B is switched by the clock switching circuit 16. The clock switching circuit 16 switches the clock to the clock generated by the clock circuit 10 when the input signal from the RS-FF 9 is “0”. On the other hand, when the input signal from the RS-FF 9 is “1” (that is, when the input signal is a STOP command signal), the clock switching circuit 16 switches the clock to the reception signal Rx for CAN communication.

  Thus, even when the standby state is entered, the WDC unit 12B can perform a count operation using the CAN communication reception signal Rx as a clock. Therefore, even if an abnormality occurs in the microcomputer 2B and as a result, it cannot be recovered when the IG signal or the CAN communication reception signal Rx is input, the WDC unit 12B then recovers and the RESET signal is sent to the microcomputer 2B. Output. As a result, the microcomputer 2B can be initialized and returned from the standby state.

FIG. 6 is a timing chart showing how the gateway device 1C shifts to the standby state and returns from the standby state when an abnormality occurs. Since the system is in a normal state at the time of transition to the standby state, when the IG signal is ON and the CAN communication reception signal Rx is not detected, a STOP command signal is output, and the clock of the clock circuit 10 and the operation of the WDC unit 12B are performed. Stop. Further, the clock switching circuit 16 is switched to the reception signal Rx side of the CAN communication by the STOP command signal.
After that, when the IG signal is turned on in the standby state, an interrupt signal is originally output from the interrupt circuit 7 to the RS-FF 9 accordingly. However, here, since an abnormality has occurred, the STOP command signal remains on and is released. As a result, the clock circuit 10 remains stopped.

On the other hand, if there is a CAN communication reception signal Rx, the CAN communication reception signal Rx is input as a clock to the WDC unit 12B via the clock switching circuit 16, so that the WDC unit 12B is activated. When the counting is completed, the RESET signal is output from the WDC unit 12B, and the microcomputer 2B is initialized in response to this, so the clock circuit 10 also operates.
As described above, the gateway device 1C initializes the microcomputer 2B and returns from the standby state even when an abnormality occurs in the system in a state where the operation of the WDC unit 12B is stopped in accordance with the transition to the standby state. can do.

  When the clock used for the count operation of the WDC unit 12B is switched to the CAN communication reception signal Rx, the gateway device 1C does not shift the initial count value of the WDC unit 12B to the standby state (during system operation). It is also possible to further provide a mechanism for setting a value (for example, 7Fh) different from the count initial value (for example, 7FFFh) used for the above. In setting different values, more specifically, it can be set to a value at which counting is completed earlier than the initial count value used during system operation. That is, for example, by changing the count initial value in this way, the predetermined value related to the count number can be set to a value smaller than that when the clock signal is input. Such a setting can be specifically performed based on a STOP command signal.

  FIG. 7 is a timing chart showing how the gateway device 1D further provided with such a mechanism shifts to the standby state and returns from the standby state when an abnormality occurs. In shifting to the standby state, the gateway apparatus 1D sets (changes) the initial count value of the WDC unit 12B to a value different from the initial count value used during system operation, based on the STOP command signal output from the CPU 8. . As a result, when returning from the standby state when an abnormality occurs, it is possible to realize faster return.

  The gateway device 1C or 1D may further include an LPF circuit (low-pass filter) 17 on the input side of the clock switching circuit 16 and on the reception signal Rx side of the CAN communication as shown in FIG. Here, in the case of CAN communication, it is undefined how many pulses are present in one frame of the CAN communication reception signal Rx. Therefore, when the CAN communication reception signal Rx is used as a clock, the WDC unit 12B counts. There will be variations in the time from the start to the completion of counting. Therefore, since the frequency of CAN communication is generally about 250 Hz, for example, if an LPF circuit 17 that cuts a frequency of 100 kHz or more is further provided, and the reception signal Rx of CAN communication is input to the WDC 12B via the LPF circuit 17, the intra frame Can be pulsed. As a result, the WDC unit 12B can count the reception signal Rx filtered by the LPF circuit 17, and thus can perform counting in frame units.

  FIG. 9 is a timing chart showing how the gateway device 1E further provided with the LPF circuit 17 shifts to the standby state with respect to the gateway device 1D and returns from the standby state when an abnormality occurs. Focusing on the return from the standby state (when the IG signal is ON), the WDC unit 12B counts down for each frame of the CAN communication reception signal Rx, so that it can be reliably returned from the standby state with a fixed number of frames. it can. That is, according to the gateway device 1E, it is possible to set the time until the system return further accurately.

  The embodiment described above is a preferred embodiment of the present invention. However, the present invention is not limited to this, and various modifications can be made without departing from the scope of the present invention. For example, although the counter 11 is provided in the microcomputer 2X in the first embodiment, the counter 11 may be provided outside the microcomputer 2X (see FIG. 10).

It is a figure which shows gateway apparatus 1A typically. It is a figure which shows the process which CPU8 performs with a flowchart. It is a figure which shows a mode that the gateway apparatus 1A transfers to a standby state, and a mode that it returns from a standby state at the time of abnormality occurrence. It is a figure which shows gateway apparatus 1B typically. It is a figure which shows 1 C of gateway apparatuses typically. It is a figure which shows a mode that the gateway apparatus 1C transfers to a standby state, and a mode that it returns from a standby state at the time of abnormality occurrence. It is a figure which shows a mode that gateway apparatus 1D transfers to a standby state, and a mode that it returns from a standby state at the time of abnormality occurrence with a timing chart. It is a figure which shows gateway apparatus 1E typically. It is a figure which shows a mode that the gateway apparatus 1E transfers to a standby state, and a mode that it returns from a standby state at the time of abnormality occurrence in a timing chart. It is a figure which shows typically the modification of gateway apparatus 1A. It is a figure which shows gateway apparatus 1X typically. It is a figure which shows a mode that the gateway apparatus 1X transfers to a standby state, and a mode that it returns from a standby state with a timing chart about each at the time of normal time and abnormality.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Gateway apparatus 2 Microcomputer 3 Power supply circuit 4 IF circuit 5 CAN transceiver 6 CAN protocol controller 7 Interrupt circuit 8 CPU
9 RS-FF 10 Clock circuit 11 Counter 12 WDC unit 13 AND gate 14 Buffer 15 Prescaler 16 Clock switching circuit 17 LPF circuit

Claims (6)

A control unit for a vehicle that includes a control unit and a monitoring unit that monitors the control unit, and communicates with other control devices via a communication bus,
When the monitoring unit receives a signal from the other control device via the communication bus when the monitoring unit is in a standby state, the monitoring unit returns from the standby state and returns the control unit in the standby state. A vehicle control device characterized by the above. A counting unit that counts the number of signals received via the communication bus when the control unit and the monitoring unit are in a standby state;
The vehicle control device according to claim 1, wherein the count unit returns the monitoring unit from the standby state when a signal count exceeds a threshold value.   When the count number of the signal exceeds the threshold, the control unit reverses the output level of the signal that sets the monitoring unit to the standby state, and returns the monitoring unit from the standby state. The vehicle control device according to claim 2. Storage means for storing history information obtained by returning the monitoring unit from a standby state;
4. The vehicle control device according to claim 2, wherein the count unit stores the history information in the storage unit when the monitoring unit is returned from a standby state. 5.   5. The vehicle control according to claim 2, wherein the control unit is capable of changing the threshold value of the counting unit when the monitoring unit is set to a standby state. 6. apparatus. An in-vehicle gateway device that transfers communication data output from a first control device connected to a first communication bus to a second control device connected to a second communication bus,
A control unit and a monitoring unit for monitoring the control unit;
The controller sets itself to a standby state after setting the monitoring unit to a standby state by turning off an ignition switch,
When the monitoring unit receives a signal from the first control device or the second control device when the monitoring unit is in a standby state, the monitoring unit returns from the standby state and returns the control unit in the standby state. An in-vehicle gateway device.

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