JP2010103432A - Method for manufacturing semiconductor element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress the generation of side etching in dry etching. <P>SOLUTION: A semiconductor substrate having a mask for forming grooves in a region for forming a semiconductor element on one side of a semiconductor film and an insulation film on the other side of the semiconductor film is placed on the lower electrode of the dry etching device so that a surface with the mask may be a processed surface; the outer periphery of the semiconductor substrate is pressed with a metallic clamp to be the potential substantially the same as that of the lower electrode; dry etching using the insulation film as an etching stopper layer is started; and the region and the clamp are brought into an electrically insulation state after at least the bottom surface of the grooves formed around the region reaches the insulation film. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device. More specifically, the present invention relates to a technique for suppressing side etching when a semiconductor element is manufactured by dry etching a semiconductor substrate having a semiconductor film formed on an insulating film.

  In dry etching, a mask on which an etching pattern is formed is provided on a semiconductor substrate, the semiconductor substrate is loaded on the lower electrode in the reaction chamber, the pressure in the reaction chamber is lowered, and the reaction gas is flowed to This is a technique for processing a semiconductor substrate by applying frequency power to an electrode to generate plasma in a reaction chamber (see, for example, Non-Patent Document 1).

  In dry etching, the semiconductor substrate temperature rises due to plasma heat, reaction heat, radiant heat from a heater, and the like. For this reason, when a photoresist material is used as the material for the mask layer, it is necessary to avoid damage to the resist layer and changes in pattern dimensions. Therefore, in order to cool the semiconductor substrate, helium as a heat conduction gas of a cooling medium installed outside is generally sprayed (see, for example, Patent Document 1). At this time, the semiconductor substrate is pressed and fixed by applying a force toward the lower electrode using a clamp so that the semiconductor substrate does not move by blowing helium gas or the like.

JP 2000-40694 A Makoto Sekine, “Development of Plasma Etching Technology, Issues and Prospects”, Journal of Plasma and Fusion Research, Vol. 83, no. 4 (20070425) pp. 319-324, The Society for Plasma and Fusion Research

  In recent years, various elements have been formed using the technology of MEMS (Micro Electro Mechanical Systems). In the formation of such an element, it is necessary to perform etching with a higher aspect ratio than conventional dry etching, and for example, a DRIE (Deep Reactive Ion Etching) technique is used. In this case, in order to form a mask using a photoresist material, it is necessary to make the thickness of the mask film several tens of μm larger than that in the conventional dry etching for forming a semiconductor element.

  When the thickness of the mask of the photoresist material is increased in this way, when dry etching is performed using a clamp formed of insulating ceramics, the semiconductor substrate is attached to the clamp due to the temperature rise of the semiconductor substrate. This often occurs and it becomes very difficult to separate the clamp from the semiconductor substrate. Therefore, a metal such as aluminum having high conductivity and high heat dissipation is used as a material for the clamp. However, when a conductive clamp is used in an etching apparatus, a bias power loss occurs if a potential difference occurs between the lower electrode and the clamp and a current flows through the semiconductor substrate. In order to prevent this, the lower electrode and the clamp are configured to have the same potential.

  However, in such a configuration, when the semiconductor substrate has a semiconductor layer formed on the insulating layer such as an SOI (Silicon on Insulator) substrate, a groove formed by etching the semiconductor layer is formed in the insulating layer. When it reaches, a portion that is electrically conductive with the clamp and a portion that is insulative with the clamp are generated on the upper surface of the semiconductor substrate, and a potential difference may occur between these portions. Such a potential difference occurs when an electrically isolated region that is not electrically connected to the clamp is formed on the semiconductor substrate. For this reason, ions are attracted to the wall surface of the portion that is electrically connected to the clamp, and side etching occurs, resulting in processing defects.

  Therefore, the present invention provides a technique for manufacturing a semiconductor element while suppressing the occurrence of side etching at least in a region where the semiconductor element is formed.

  That is, in one embodiment of the present invention, a semiconductor substrate including a mask for forming a groove in a region where a semiconductor element is formed is provided on one side of a semiconductor film, and an insulating film is provided on the other side of the semiconductor film. Place on the electrode. At this time, the surface provided with the mask is placed so as to be the surface to be processed. Then, the outer peripheral portion of the semiconductor substrate is pressed by a metallic clamp having substantially the same potential as the lower electrode. Thereafter, dry etching using the insulating film as an etching stopper layer is started. In the dry etching, at least after the bottom surface of the groove formed around the region reaches the insulating film, the region and the clamp are electrically insulated.

  Accordingly, at least after the bottom surface of the groove formed around the region where the semiconductor element is formed reaches the insulating film which is the etching stopper layer, the region where the semiconductor element is formed and the clamp are electrically insulated. Since it will be in a state, the side etching mentioned above is suppressed and a subject is solved.

  In order to make a predetermined region, which is a region where a semiconductor element is formed, electrically insulated from the clamp, a groove may be formed around the region where the semiconductor element is formed prior to the dry etching. Good.

  Further, after the bottom surface of the groove surrounding the region where the semiconductor element is formed reaches the insulating film, the mask may be formed on one of the semiconductor films.

  Further, another mask material is disposed to form a second mask corresponding to the groove formed around the region, and the groove formed around the region is formed using the second mask. Then, after the second mask is removed, the dry etching may be performed.

  Further, the width of the groove formed around the region in the mask may be larger than the width of the groove formed in the region. Thereby, due to the microloading effect, the groove surrounding the region where the semiconductor element is formed reaches the insulating film before the groove formed in the region, and the bottom surface of the groove for forming the semiconductor element is the etching stopper layer. An insulating film in which a predetermined region, which is a region where a semiconductor element is formed, is electrically insulated from the clamp before reaching the insulating film, and the bottom surface of the groove for forming the semiconductor element is an etching stopper layer After reaching, the region where the semiconductor element is formed is electrically insulated from the clamp.

  Further, the outer peripheral portion of the semiconductor substrate in the semiconductor film may be removed up to the insulating film, and the region and the clamp may be electrically insulated.

  Further, an insulating material may be formed on the outer peripheral portion of the semiconductor substrate on the upper surface to electrically insulate the predetermined region and the clamp.

  According to the present invention, it is possible to suppress the occurrence of side etching when a wall surface of a groove for forming a semiconductor element is formed by dry etching. Thereby, generation | occurrence | production of a process defect can be suppressed and the quality and yield of the semiconductor element formed can be improved.

  Hereinafter, the best mode for carrying out the present invention will be described with reference to the drawings. The present invention is not limited to the following description. Extensions and changes can be made as appropriate, and such extended and changed forms are also included in the gist of the present invention.

(Dry etching apparatus used for carrying out the present invention)
FIG. 1 shows a schematic configuration example (cross-sectional view) when a dry etching apparatus is observed from the side. In FIG. 1, an upper electrode 2 and a lower electrode 3 are provided in a reaction chamber 1. A support portion 4 is disposed around the lower electrode 4, and a clamp 5 can be installed thereon. The clamp 5 is made of a conductive metal. For example, the clamp 5 is made of aluminum. The clamp 5 and the lower electrode 3 are set to substantially the same potential. If there is a potential difference between the clamp 5 and the lower electrode 3, the upper surface and the lower surface are electrically connected such as when the semiconductor substrate is composed of a silicon single crystal or when there is a contact penetrating the semiconductor substrate. This is because when conducting, a current flows between the clamp 5 and the lower electrode 3 and energy loss occurs. In order to make the clamp 5 and the lower electrode 3 have substantially the same potential, for example, a conductive contact 6 is disposed between the lower electrode 3 and the clamp 5, and the lower electrode 3 and the clamp 5 are electrically connected. Conduct. The contact 6 has a columnar shape, and a plurality of contacts are disposed on the lower electrode 3. Alternatively, the contact 6 may be annular or spring-shaped, and is disposed around the lower electrode 3. Further, the role of the contact 6 may include supporting the clamp 5 together with the support portion 4.

  The semiconductor substrate 7 is placed on the lower electrode 3. In the present invention, a semiconductor substrate whose upper surface and lower surface are not electrically connected is used as the semiconductor substrate. Such a semiconductor substrate includes a mask corresponding to a groove for forming a semiconductor element on one side of the semiconductor film and an insulating film on the other side of the semiconductor film. For example, there is a semiconductor substrate having a silicon oxide layer between silicon layers, such as an SOI substrate, and further having a mask formed on one of the silicon layers. In this case, the silicon oxide film becomes an insulating film. In addition, there is a semiconductor substrate having a semiconductor film over a glass substrate. In this case, the glass substrate becomes an insulating film.

  The mask is provided on one surface of the semiconductor film, for example, by applying a photoresist material to form a pattern with openings formed by removing the resist in the groove portion for forming the semiconductor element. The material of the mask is not limited to the photoresist material, and the mask may be formed of silicon nitride or the like. In this case, after depositing silicon nitride or the like, a photoresist is applied to form a pattern on the photoresist, and etching of silicon nitride or the like is performed to form a mask. By placing the semiconductor substrate with the surface including the mask opposite to the lower electrode 3, the surface including the mask becomes the surface to be processed. When dry etching is performed, ions collide through an opening formed in the mask and the semiconductor film is etched. By appropriately selecting the material of the etching gas, the etching generally has anisotropy, and the etching proceeds in a direction perpendicular to the semiconductor substrate. Therefore, the wall surface of the groove formed by etching is perpendicular to the semiconductor substrate.

  The clamp 5 is placed on the outer peripheral portion of the semiconductor substrate 7, and the semiconductor substrate 7 is pressed by applying a force toward the lower electrode to the semiconductor substrate 7. Thereby, the semiconductor substrate 7 is fixed on the lower electrode 3. The entire lower surface of the semiconductor substrate 7 may be in contact with the lower electrode 3, but the outer peripheral portion of the lower surface corresponding to the outer peripheral portion of the upper surface to which the force from the clamp 5 is applied is lower. The gap may exist so that the gas can be blown to the semiconductor substrate 7 by cooling gas such as helium.

  A shield 8 may be provided so as to cover the upper part of the clamp 5. The shield 8 is formed of a conductive material and is grounded at least during dry etching. When a bias frequency power having a low frequency (for example, several kilohertz to several megahertz) is applied to the lower electrode 3, ions in the plasma follow the bias frequency and move so as to collide with the lower electrode 3 and the clamp 4. For this reason, if the shield 8 is not provided, ions collide with the clamp 5, sputtering occurs, and the semiconductor substrate 7 is contaminated. In order to prevent this, the grounding shield 8 covers the upper part of the clamp 5 so that a potential difference is generated between the shield 8 and the plasma, thereby preventing the sputtering of the clamp 5.

  Note that when a bias frequency power having a high frequency (for example, several gigahertz) is applied to the lower electrode 3, ions in the plasma cannot follow the bias frequency due to the presence of ion mass. For this reason, the sputtering of the clamp 5 does not occur even without the shield 8. However, when the potential change of the bias is large and the atmospheric pressure in the reaction chamber 1 is low, sputtering of the clamp 5 can occur. Therefore, the shield 8 is preferably provided.

  A power source 9 is connected to the lower electrode 3 to supply bias frequency power to the lower electrode 3. The upper electrode 2 is connected to a power source 10 for supplying frequency power. In this case, a matching circuit (not shown) is provided between the power source 9 and the lower electrode 3 and between the power source 10 and the upper electrode 2. The power supply 9 and the power supply 10 may supply the same frequency power or different frequency power. Further, it is not necessary to use two power sources, that is, the power source 9 and the power source 10, and one power source may be connected to the upper electrode 2 and the lower electrode 3, for example, the upper electrode 2 may be grounded.

  Then, the exhaust pipe 12 is evacuated to lower the pressure in the reaction chamber 1, and an etching gas is supplied into the reaction chamber 1 from the introduction pipe 11 to generate plasma 13. Further, during dry etching, in order to prevent the temperature of the semiconductor substrate 7 from rising, a cooling gas such as helium is supplied from the cooling gas introduction pipe 13 and is blown onto the semiconductor substrate 7 to cool it.

  FIG. 2 shows a top view and a cross-sectional view of the clamp. FIG. 2A is an example of a top view of the clamp. In FIG. 2A, the clamp 21 is annular and has a circular opening at the center. This is because a normal semiconductor substrate is circular, so that a force is applied to the outer peripheral portion of the semiconductor substrate to hold and fix it. If the opening is circular, the shape of the other part of the clamp may be arbitrary, but it is preferable that the outer peripheral part is circular for convenience of formation.

  FIG. 2B is an example of a top view of another clamp. In FIG. 2B, the clamp 22 is formed in an annular shape. On the inner periphery of the clamp 22, a claw 23 for fixing the lower electrode 3 by pressing the outer periphery of the semiconductor substrate by applying a point contact force. Is provided.

  FIG. 2C is an example of a cross-sectional view of the clamp cut along the AA line in FIG. 2A or the BB line in FIG. For example, the length of the lower surface is larger than the upper surface of the clamp 24. The outer wall surface of the clamp 24 is substantially perpendicular to the upper and lower surfaces, and the opening side surface of the clamp 24 is tapered.

  FIG. 3A is an example of a top view of an intermediate product of a semiconductor element formed by the dry etching apparatus according to this embodiment, and FIG. 3B is a cross-sectional view taken along the line CC. An example is shown. In FIG. 3A, a substantially clover-shaped weight portion 142 is formed inside the frame 121. The frame 121 and the weight part 142 are formed of the same material (for example, silicon single crystal), and a groove is formed between the frame 121 and the weight part 142 by etching. In FIG. 3B, a silicon oxide film 130 is formed on the silicon film 30, and another silicon film is formed thereon. Here, the thicknesses of the silicon film 30, the silicon oxide film 130, and the other silicon film are, for example, 5 μm, 2 μm, and 600 μm. The other silicon film is subjected to a dry etching process using the silicon oxide film 130 as an etching stopper layer (etching stopper layer) using the above-described dry etching apparatus, whereby the frame 121 and the weight portion 142 are obtained. Between these, a trench reaching the silicon oxide film 130 is formed.

  When an acceleration sensor or the like is manufactured using the intermediate product shown in FIG. 3A, a piezoresistive element may be formed on the silicon film 30 in some cases. By providing an opening or the like in a portion other than where the piezoresistive element is formed, a flexible part having the piezoresistive element is formed. When the flexible portion is bent by the force applied to the weight portion 142, the resistance value of the piezoresistive element changes. In FIG. 3B, the frame 121 and the weight portion 142 are at the same height, but a processing for reducing the height of the weight portion 142 is performed after or before the formation of the groove. In other words, the weight 142 may be freely movable to some extent.

  The length of one side of the semiconductor element shown in FIG. 3 is, for example, 1 to 2 mm. On the other hand, the diameter of a general semiconductor substrate is about 150 mm to 200 mm. Therefore, a large number of semiconductor elements can be formed on one semiconductor substrate. FIG. 4A is a schematic diagram in which a large number of patterns 32 for manufacturing semiconductor elements are arranged on a single semiconductor substrate 31.

  FIG. 4B is an example of a cut surface cut along the line D-D in FIG. 4B, a silicon film 34 is formed on the insulating film 33, and a resist pattern in which the pattern 32 shown in FIG. 4A is formed is formed on the silicon film 34. In FIG. When dry etching is started with respect to FIG. 4B using the dry etching apparatus described above, the upper surface of the semiconductor substrate is almost at the same potential as the lower electrode 3 by the clamp 5 for a while from the start. Etching is performed vertically, and the wall surface of the formed groove is perpendicular to the semiconductor substrate. However, side etching may occur when the bottom surface of a part of the groove formed by etching reaches the insulating film 33.

  The pattern 32 corresponds to a groove for forming a semiconductor element and has an opening. As dry etching proceeds, ions generated by the plasma enter the openings of the pattern 32 and are etched to form grooves. In general, due to the microloading effect generated by the different widths of the pattern 32, the groove formation does not progress uniformly, and the progress of the groove formation varies. FIG. 4C shows a state where dry etching has progressed and the bottom surfaces of some of the grooves have reached the insulating film 33. That is, the bottom surface of the groove formed by the wall surface 36 and the wall surface 37 and the bottom surface of the groove formed by the wall surface 38 and the wall surface 37 reach the insulating film 33, and the bottom surfaces of the other grooves become the insulating film 33. Not reached. For this reason, the region of the silicon layer 34 surrounded by the wall surface 37 and the wall surface 38 is not electrically connected to other portions and is in an isolated state. In this case, the portion 35 and the wall surface 36, and the portion 35 and the wall surface 39, which are in contact with the clamp, have substantially the same potential as the lower electrode 3, but the wall surface 37 and the wall surface 38 are in a floating state. For this reason, for example, ions that have entered the groove formed by the wall surface 36 and the wall surface 37 are attracted toward the wall surface 36, collide with the wall surface 36, the wall surface 36 is dry etched, and side etching occurs. End up. For this reason, the wall surface 36 cannot be maintained vertically, and the characteristics of the semiconductor element formed using the wall 36 are inferior. The same can be said for the wall surface 39. The present invention suppresses the occurrence of such side etching.

(Embodiment 1)
As Embodiment 1 of the present invention, an embodiment will be described in which generation of side etching is suppressed by surrounding a region where a semiconductor element is formed (also referred to as a pattern region) with a groove in advance. Therefore, in this embodiment, the pattern region and the clamp are electrically connected by causing the bottom surface of the groove formed around the pattern region to reach the insulating film before the groove formed in the pattern region. Maintain insulation.

  FIG. 5 shows a vertical section of the semiconductor substrate. As shown in FIG. 5A, a semiconductor film 52 is formed on the insulating film 51. A groove 54 surrounding the pattern region 53 is formed. That is, the groove 54 is formed before the groove for forming the semiconductor element is formed. The groove 54 is formed from the upper surface of the semiconductor film 52, and the bottom surface of the groove 54 reaches the insulating film 51. “Enclose the pattern region 53” means that when the semiconductor substrate is observed from the upper surface on the semiconductor film 52 side, the groove 54 includes a closed curve, and the region inside the closed curve matches the pattern region 53. Alternatively, the pattern region 53 is included. The “pattern region 53” refers to a region where a pattern corresponding to a groove for forming a semiconductor element is formed. A plurality of pattern regions 53 may be formed on the semiconductor substrate, and a plurality of closed curves may be formed by the grooves 54.

  Moreover, the groove | channel 54 is formed in the area | region which does not contact a clamp among the upper surfaces of a semiconductor substrate. In other words, the groove 54 is formed inside the outer peripheral portion. By forming the groove 54 in this way, the pattern region 53 is not electrically connected to the clamp even when the clamp is in contact with the outer periphery when the semiconductor substrate is loaded into the dry etching apparatus. That is, the pattern region 53 and the clamp can be electrically insulated. Therefore, as shown in FIG. 5B, the wall surface of the groove newly formed in the pattern region 53 is kept in a floating state regardless of whether the bottom surface of the groove reaches the insulating film 51 or not. It is. For this reason, in the pattern region 53, ions are not drawn into the wall surface, and the occurrence of side etching is suppressed.

  FIG. 6 is an example of the semiconductor substrate observed from the upper surface on the semiconductor film 52 side. In FIG. 6, the groove 54 is formed inside the outer periphery of the semiconductor substrate and includes one closed curve. Therefore, in the case of FIG. 6, there is one internal region surrounded by the closed curve, and a pattern region is provided in the only region. Further, the clamp when loaded in the dry etching apparatus comes into contact with the outside partitioned by the groove 54. In other words, the outer peripheral portion is located on the outside partitioned by the groove 54. The closed curve does not need to be a single ring (ring), and may include a plurality of rings as described below.

  7 and 8 show an example in which the closed curve formed by the groove on the semiconductor substrate includes a plurality of rings. That is, this is an example in which there are a plurality of inner regions surrounded by a closed curve, a pattern region is formed therein, and a plurality of pattern regions exist as a whole. In FIG. 7 and FIG. 8, a part of a state in which a plurality of grooves are arranged in the vertical direction and the horizontal direction, they are orthogonal to each other, and a pattern region is arranged in a plurality of rectangles or squares surrounded by the grooves. Take out and show. In FIG. 7, the inner region surrounded by the groove 54 is larger than the pattern region, and a dicing line for dicing the semiconductor substrate into individual elements is separated from the edge of the pattern region. On the other hand, in FIG. 8, the inner region surrounded by the groove 54 coincides with the pattern region, and the dicing line is in contact with the pattern region. 7 can prevent the semiconductor element from being damaged during dicing. On the other hand, by making it as shown in FIG. 8, the number of semiconductor elements formed of one semiconductor substrate can be increased.

  In this embodiment, dry etching may be performed after the mask formation process on the semiconductor film 52 is performed twice. That is, in the first formation process, the pattern of the groove 54 and the pattern of the groove formed in the pattern region are formed as the first mask. In the next formation step, the mask of the groove 54 is formed as a second mask on the first mask using another mask material. Then, etching is performed using the second mask to form the groove 54, the second mask is removed, and the first mask is left. Then, dry etching of the pattern region 53 is performed. Note that it is mainly assumed that dry etching is performed using the second mask, but wet etching may be performed in some cases. This is because the width of the groove 54 may be larger than the width of the groove formed in the pattern region 53.

  In the present embodiment, it is not necessary to start dry etching of the pattern region 53 after the bottom surface of the groove 54 reaches the insulating film 51. For example, as shown in FIG. 9A, when the trench 94 is formed in the semiconductor film 92 formed on the insulating film 91, the trench 94 is etched before the bottom surface of the trench 94 reaches the insulating film 91. You may stop. Next, dry etching of the pattern region 93 and the groove 94 is performed. By doing so, as shown in FIG. 9B, the groove 94 reaches the insulating film earlier than the groove formed in the pattern region 93, and the pattern region 93 and the clamp that contacts the outer peripheral portion are formed. Can be electrically insulated.

  As described above, in the present embodiment, the pattern region can be electrically insulated from the clamp by forming the groove surrounding the pattern region first. Thereby, a pattern area | region can be maintained in a floating state and side etching can be suppressed.

(Embodiment 2)
As a second embodiment of the present invention, the microloading effect is used to at least electrically isolate the predetermined region and the clamp after the bottom surface of the groove formed around the pattern region reaches the insulating film. Will be explained. In the first embodiment, the mask formation process needs to be performed twice, but in the second embodiment, the formation process can be performed once.

  In this embodiment, when a mask is formed on the insulating film 101 of the semiconductor substrate shown in FIG. 10A, the width of the pattern in the pattern region is different from the width of the groove pattern surrounding the pattern region. For example, the width of the groove pattern surrounding the pattern region is made larger than the width of the groove pattern in the pattern region. By varying the width of the pattern in this way, when dry etching is performed, the progress of dry etching in the groove surrounding the pattern region can be made larger than the method of proceeding dry etching in the pattern region (micro). Loading effect). Further, the width of the pattern of the groove surrounding the pattern region may be smaller than the width of the pattern in the pattern region. For example, when the pattern width in the pattern region becomes extremely larger than the width of the pattern of the groove surrounding the pattern region, the etching progress of the groove surrounding the pattern region may be increased.

  As a result, as shown in FIG. 10B, the bottom surface of the groove 104 surrounding the pattern region 104 reaches the insulating film 101 faster than the bottom surface of the groove formed in the pattern region 103 reaches the insulating film 101. be able to. Thereby, a predetermined area | region and the said clamp can be made into an electrically insulated state. Therefore, the pattern region 104 can be brought into a floating state, and occurrence of side etching in the pattern region 104 can be suppressed.

(Embodiment 3)
As a third embodiment of the present invention, a method of manufacturing a semiconductor element by electrically isolating a predetermined region of the pattern region and the clamp from the start of dry etching of the pattern region will be described.

  FIG. 11A is a cross-sectional view of a semiconductor substrate according to the fourth embodiment. In this embodiment, the semiconductor film 1102 is formed on the insulating film 1101. However, a portion including the outer peripheral portion where the clamp is in contact with the semiconductor substrate is in a state where the semiconductor film 1102 is missing as the notch portion 1104 to the insulating film 1101. The pattern region 1103 can be electrically insulated from the clamp by bringing the clamp into contact with the outer peripheral portion included in the cutout portion 1104 so as not to contact the pattern region 1103.

  For example, in a semiconductor substrate in which the entire surface of the insulating film 1101 is covered with the semiconductor film 1102, exposure and development are performed so that the outer peripheral portion of the semiconductor film 1102 and the portion other than the portion where the clamp of the dry etching apparatus contacts are covered with photoresist. The notch 114 is formed by wet etching or the like. Thereby, the state of FIG. 11A is obtained. Thereafter, the photoresist is removed, another photoresist is applied, a pattern for forming a groove in the pattern region 1103 is exposed and developed, loaded into a dry etching apparatus, and dry etching is performed, and the state of FIG. obtain.

  In the present embodiment, since the clamp contacts only the notch 114, the pattern region 1103 is electrically insulated from the clamp. That is, the pattern region 1103 is kept in a floating state. Thereby, generation | occurrence | production of side etching can be suppressed.

Further, as shown in FIG. 12A, a film 1204 of an insulating material such as SiO ₂ or Si ₃ N ₄ is formed on the entire surface of the semiconductor film 1202 formed on the insulating film 1201, and dry The clamp of the etching apparatus is removed by etching (both dry etching and wet etching are possible) except for the portion of the outer peripheral portion that contacts the semiconductor substrate. For example, as shown in FIG. 12B, a ring-shaped insulating substance film 1204 is formed in the width of the length of the portion in contact with the clamp from the outer periphery of the semiconductor substrate. Then, the pattern region 1203 can be included in a portion where the film 1204 is not formed.

  In this state, if a pattern is formed in the pattern region 1203 with a photoresist, loaded in a dry etching apparatus and dry etching is performed, the pattern region 1203 can be kept in a floating state, and the occurrence of side etching can be suppressed. it can.

It is a schematic block diagram at the time of observing a dry etching apparatus from the side. It is the upper side figure and sectional drawing of the clamp of a dry etching apparatus. It is the upper side figure and sectional drawing of an example of the element manufactured by dry etching. It is the upper side figure and sectional drawing of the semiconductor substrate which formed the element pattern in the apply | coated resist. It is sectional drawing of the semiconductor substrate which concerns on Embodiment 1 of this invention. It is a top view of the semiconductor substrate which concerns on Embodiment 1 of this invention. It is an example of the part of the upper surface of the semiconductor substrate which concerns on Embodiment 1 of this invention. It is an example of the part of the upper surface of the semiconductor substrate which concerns on Embodiment 1 of this invention. It is sectional drawing of the semiconductor substrate which concerns on Embodiment 1 of this invention. It is sectional drawing of the semiconductor substrate which concerns on Embodiment 2 of this invention. It is sectional drawing of the semiconductor substrate which concerns on Embodiment 3 of this invention. It is sectional drawing and a top view of a semiconductor substrate concerning Embodiment 3 of the present invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 51 ... Insulating film, 52 ... Semiconductor film, 53 ... Pattern region, 54 ... Groove surrounding pattern region

Claims (7)

A surface provided with a mask for forming a groove in a region for forming a semiconductor element on one side of the semiconductor film and a semiconductor substrate provided with an insulating film on the other side of the semiconductor film on a lower electrode of a dry etching apparatus. Is placed on the work surface,
Holding the outer periphery of the semiconductor substrate with a metallic clamp that has substantially the same potential as the lower electrode,
Start dry etching using the insulating film as an etching stopper layer,
A method for manufacturing a semiconductor device, wherein at least after the bottom surface of a groove formed around the region reaches the insulating film, the region and the clamp are electrically insulated.   The method for manufacturing a semiconductor element according to claim 1, wherein a groove is formed around the region before the dry etching.   3. The method of manufacturing a semiconductor element according to claim 2, wherein the mask is provided on one side of the semiconductor film after the bottom surface of the groove formed around the region reaches the insulating film. Disposing another mask material to form a second mask corresponding to the grooves formed around the region;
Forming a groove formed around the region using the second mask;
The method of manufacturing a semiconductor element according to claim 2, wherein the dry etching is performed after removing the second mask.   The method for manufacturing a semiconductor device according to claim 1, wherein a width of a groove formed around the region in the mask is larger than a width of a groove formed in the region.   2. The method of manufacturing a semiconductor element according to claim 1, wherein an outer peripheral portion of the semiconductor substrate in the semiconductor film is removed up to the insulating film to electrically insulate the predetermined region and the clamp.   2. The method of manufacturing a semiconductor element according to claim 1, wherein an insulating portion is formed on an outer peripheral portion of the surface of the semiconductor film including the mask to electrically isolate the predetermined region and the clamp.

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