JP2010102700A5 - - Google Patents

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Publication number
JP2010102700A5
JP2010102700A5 JP2009218306A JP2009218306A JP2010102700A5 JP 2010102700 A5 JP2010102700 A5 JP 2010102700A5 JP 2009218306 A JP2009218306 A JP 2009218306A JP 2009218306 A JP2009218306 A JP 2009218306A JP 2010102700 A5 JP2010102700 A5 JP 2010102700A5
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JP
Japan
Prior art keywords
placement
description
circuit
routing
netlist
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JP2009218306A
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English (en)
Japanese (ja)
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JP2010102700A (ja
JP5409231B2 (ja
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Priority to JP2009218306A priority Critical patent/JP5409231B2/ja
Priority claimed from JP2009218306A external-priority patent/JP5409231B2/ja
Publication of JP2010102700A publication Critical patent/JP2010102700A/ja
Publication of JP2010102700A5 publication Critical patent/JP2010102700A5/ja
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Publication of JP5409231B2 publication Critical patent/JP5409231B2/ja
Expired - Fee Related legal-status Critical Current
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JP2009218306A 2008-09-26 2009-09-23 設計システム Expired - Fee Related JP5409231B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009218306A JP5409231B2 (ja) 2008-09-26 2009-09-23 設計システム

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2008247509 2008-09-26
JP2008247509 2008-09-26
JP2009218306A JP5409231B2 (ja) 2008-09-26 2009-09-23 設計システム

Publications (3)

Publication Number Publication Date
JP2010102700A JP2010102700A (ja) 2010-05-06
JP2010102700A5 true JP2010102700A5 (cg-RX-API-DMAC7.html) 2012-11-01
JP5409231B2 JP5409231B2 (ja) 2014-02-05

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Family Applications (1)

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JP2009218306A Expired - Fee Related JP5409231B2 (ja) 2008-09-26 2009-09-23 設計システム

Country Status (2)

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US (1) US8209645B2 (cg-RX-API-DMAC7.html)
JP (1) JP5409231B2 (cg-RX-API-DMAC7.html)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8555211B2 (en) * 2012-03-09 2013-10-08 Taiwan Semiconductor Manufacturing Company, Ltd. Mask making with error recognition
FR2990283A1 (fr) * 2012-05-04 2013-11-08 Commissariat Energie Atomique Bibliotheque de cellules et procede de conception d'un circuit integre asynchrone
JP6435892B2 (ja) * 2015-02-03 2018-12-12 京セラドキュメントソリューションズ株式会社 回路設計方法、回路設計ツール用セル・ライブラリのコンポーネント
US10394994B2 (en) 2017-05-04 2019-08-27 International Business Machines Corporation Field-effect transistor placement optimization for improved leaf cell routability

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5067091A (en) * 1988-01-21 1991-11-19 Kabushiki Kaisha Toshiba Circuit design conversion apparatus
JPH09231259A (ja) * 1996-02-28 1997-09-05 Dainippon Printing Co Ltd 論理設計支援装置および論理合成ツール
JPH1185810A (ja) * 1997-09-09 1999-03-30 Mitsubishi Electric Corp 半導体集積回路の論理回路検証装置および論理回路検証装置における論理回路検証方法
JP2003108619A (ja) * 2001-09-27 2003-04-11 Toshiba Corp 半導体集積回路の設計方法および設計プログラム
JP2006049638A (ja) * 2004-08-05 2006-02-16 Renesas Technology Corp 半導体装置の設計方法および半導体装置
US7584449B2 (en) * 2004-11-22 2009-09-01 Fulcrum Microsystems, Inc. Logic synthesis of multi-level domino asynchronous pipelines
US7418676B2 (en) * 2005-01-19 2008-08-26 Seiko Epson Corporation Asynchronous circuit design tool and computer program product
US7610567B2 (en) * 2006-04-27 2009-10-27 Achronix Semiconductor Corporation Systems and methods for performing automated conversion of representations of synchronous circuit designs to and from representations of asynchronous circuit designs
US7614029B2 (en) * 2007-01-05 2009-11-03 Achronix Semiconductor Corporation Methods and systems for converting a synchronous circuit fabric into an asynchronous dataflow circuit fabric
US7739628B2 (en) * 2008-02-15 2010-06-15 Achronix Semiconductor Corporation Synchronous to asynchronous logic conversion

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