JP2010097097A - Display device and method of driving the same, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device that is compatible with switching a frame rate by a simple adjustment system. <P>SOLUTION: A pixel 2 performs correction operation of a drive transistor while a sampling transistor is turned on depending on a control signal for correction and a reference potential is applied to a control end of the drive transistor. Subsequently, the pixel performs write operation by writing a signal potential at the control end of the drive transistor when the sampling transistor is turned on, depending on a control signal for write. Then, the pixel performs light emission by supplying a current, based on the signal potential which is written in, from the drive transistor to a light emitter. A drive unit 7 has a switch unit 71 for switching a velocity of line progressive scan depending on the selected frame rate, and a controlling unit 72 for changing a level of the reference potential depending on the selected frame rate. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an active matrix display device using a light emitting element for a pixel and a driving method thereof. The present invention also relates to an electronic device using such a display device.

  In recent years, development of flat self-luminous display devices using organic EL devices as light-emitting elements has become active. An organic EL device is a device that utilizes the phenomenon of light emission when an electric field is applied to an organic thin film. Since the organic EL device is driven at an applied voltage of 10 V or less, it has low power consumption. In addition, since the organic EL device is a self-luminous element that emits light, it does not require an illumination member and can be easily reduced in weight and thickness. Furthermore, since the response speed of the organic EL device is as high as several μs, an afterimage does not occur when displaying a moving image.

Among planar self-luminous display devices that use organic EL devices as pixels, active matrix display devices in which thin film transistors are integrated and formed as driving elements in each pixel are particularly active. An active matrix type flat self-luminous display device is described in, for example, Patent Documents 1 to 6 below.
JP 2003-255856 A JP 2003-271095 A JP 2004-133240 A JP 2004-029791 A JP 2004-093682 A JP2007-310311

  An active matrix type flat self-luminous display device basically includes a pixel array section and a driving section for driving the pixel array section. The pixel array section is composed of row-shaped scanning lines, column-shaped signal lines, and matrix-shaped pixels arranged at portions where each scanning line and each signal line intersect. Each pixel includes a sampling transistor for sampling a video signal, a pixel capacity for holding the sampled video signal, a drive transistor for driving a light emitting element in accordance with the held video signal, and the like. Furthermore, a high-accuracy and high-luminance pixel incorporates a threshold voltage correction function for correcting variations in the threshold voltage of the drive transistor. On the other hand, the peripheral driver includes a selector that supplies a reference potential necessary for executing the threshold voltage correction function in addition to the signal potential of the video signal to the signal line.

  The driving unit of the conventional display device has a vertical scanner in addition to the horizontal selector to drive the pixel array unit. The vertical scanner supplies a control signal for threshold voltage correction during a correction period assigned to each scanning line, and further supplies a control signal for writing during a writing period assigned to each scanning line to thereby connect each scanning line. Scan sequentially. The horizontal selector supplies a predetermined reference potential to each signal line in accordance with the correction period, and supplies a signal potential to each signal line prior to the writing period.

  The display device displays an image while rewriting a screen (frame) at a predetermined frame rate (frame frequency). Conventional display devices sometimes increase the frame rate in order to reduce the feeling of afterimage when moving images are displayed. At this time, for a user who needs to interpolate the video signal but is concerned about errors caused by the interpolation, the video signal may be sent with a mode for increasing the frame rate while the interpolation function is turned off. In addition, there is an international difference in the frame frequency, and the standard is 60 Hz for Japanese specifications and 50 Hz for European specifications. In order to deploy display devices in a global market, it is necessary to have different frame rate settings.

  Here, when the frame rate is changed by the user's switching selection, the operation speed (line sequential scanning speed) of the vertical scanner changes. As the frame frequency increases, the line sequential scanning speeds up, and the time (one horizontal period, 1H) allocated to one scanning line is compressed accordingly. When one horizontal period (1H) changes, the correction period also inevitably changes, so the threshold voltage correction operation condition changes. For example, the time of 1H is about 30 μs at 60 Hz drive, about 20 μs at 90 Hz drive, and about 15 μs at 120 Hz. If 1H is compressed by increasing the frame frequency in this way, the threshold voltage correction period is shortened accordingly. Since the method of threshold voltage correction varies depending on the frame rate, this affects the screen brightness. In other words, the γ characteristic representing the relationship between the signal potential and the luminance changes depending on the frame rate. In order to cope with this, it is necessary to adjust the dynamic range of the signal potential and adjust the γ characteristic every time the frame frequency is switched. However, when the dynamic range of the signal potential reaches 256 gradations, the amount of data for adjusting the level of the signal potential is enormous, which is a problem to be solved.

  In view of the above-described problems of the conventional technology, an object of the present invention is to provide a display device that can cope with frame rate switching by a simple adjustment method. The following measures were taken in order to achieve this purpose. That is, the display device according to the present invention basically includes a pixel array section and a drive section that drives the pixel array section. The pixel array section includes row-like scanning lines, column-like signal lines, and matrix-like pixels arranged at portions where these intersect. The driving unit supplies a control signal for correction during a correction period assigned to each scanning line, and further supplies a control signal for writing during a writing period assigned to each scanning line to line-sequentially scan each scanning line. A scanner for scanning and a selector for supplying a predetermined reference potential to each signal line in accordance with the correction period and supplying a signal potential to each signal line prior to the writing period. The pixel includes a light emitting element, a drive transistor having one current end connected to the light emitting element and the other current end connected to a power supply, one current end connected to the signal line, and the other current end connected to the drive A sampling transistor connected to the control terminal of the transistor, and a pixel capacitor connected between the control terminal and the current terminal of the drive transistor. The pixel performs a correction operation of the drive transistor in a state where the sampling transistor is turned on in response to a correction control signal and the reference potential is applied to the control terminal of the drive transistor. Subsequently, when the sampling transistor is turned on in response to a write control signal, the signal potential is written to the control terminal of the drive transistor to perform a write operation. Thereafter, a current corresponding to the written signal potential is supplied from the drive transistor to the light emitting element to perform a light emitting operation. The driving unit includes a switching unit that switches the line-sequential scanning speed according to the selected frame rate, and an adjustment unit that changes the level of the reference potential according to the selected frame rate.

  In an embodiment, the adjustment unit lowers the level of the reference potential as the selected frame rate is higher. The adjusting unit has a table memory storing a correspondence relationship between different frame rates and reference potential levels, and reads the reference potential level corresponding to the selected frame rate from the table memory to adjust the reference potential. To do.

  According to the present invention, the drive unit of the display device includes the reference potential adjusting unit in addition to the frame rate switching unit. The switching unit switches the line sequential scanning speed of the vertical scanner according to the selected frame rate. The adjustment unit changes the level of the reference potential according to the selected frame rate. With such a configuration, even when the frame rate is switched, it is possible to cope with the change in the level of the reference potential so that the γ characteristic does not change. The present invention does not adjust the dynamic range of the signal potential according to the frame rate, but changes the level of the reference potential, and can cope with switching of the frame rate with a simple method and with a small amount of data.

The best mode for carrying out the invention (hereinafter referred to as an embodiment) will be described below. The description will be given in the following order.
First embodiment
Application form

<First embodiment>
[Overall configuration of display device]
FIG. 1 is a block diagram showing a main part of a display device according to the present invention. As shown in the figure, the display device includes a pixel array unit 1 and a drive unit that drives the pixel array unit 1. The pixel array unit 1 includes a row-like scanning line WS, a column-like signal line SL, a matrix-like pixel 2 arranged at a portion where both intersect, and a power supply line arranged corresponding to each row of the pixels 2 DS. The drive unit sequentially supplies a control signal to each scanning line WS to scan the pixels 2 line-sequentially in units of rows, and switches each power supply line DS to a high potential and a low potential according to the line sequential scanning. A drive scanner 5 for supplying a power supply voltage to be replaced, and a horizontal selector 3 for supplying a signal potential as a video signal and a reference potential to the columnar signal lines SL in accordance with the line sequential scanning are provided.

  Each pixel 2 includes a sampling transistor Tr1, a drive transistor Trd, a holding capacitor Cs, an auxiliary capacitor Csub, and a light emitting element EL. Each light emitting element EL emits light in one of the three primary colors RGB. A pixel trio is composed of a pixel including a red light emitting element, a pixel including a green light emitting element, and a pixel including a blue light emitting element. Color display can be performed by arranging the pixel trio in a matrix on the pixel array section 1.

[Pixel circuit configuration]
FIG. 2 is a circuit diagram showing a specific configuration and connection relationship of the pixel 2 included in the display device shown in FIG. As illustrated, the pixel 2 includes a light emitting element EL represented by an organic EL device, a sampling transistor Tr1, a drive transistor Trd, a pixel capacitor Cs, and an auxiliary capacitor Csub. The sampling transistor Tr1 has its gate connected to the corresponding scanning line WS, one of its source and drain connected to the corresponding signal line SL, and the other connected to the gate G of the drive transistor Trd. The drive transistor Trd has a source S connected to the light emitting element EL and a drain connected to the corresponding power supply line DS. The cathode of the light emitting element EL is connected to the ground potential Vcath. This ground wiring is wired in common to all the pixels 2. The pixel capacitance (pixel capacitance) Cs is connected between the source S and the gate G of the drive transistor Trd.

  In general, each pixel 2 basically includes at least a sampling transistor Tr1, a drive transistor Trd, a light emitting element EL, a pixel capacitor Cs, and an auxiliary capacitor Csub. The sampling transistor Tr1 has a control terminal (gate) connected to the scanning line WS, and a pair of current terminals (source and drain) connected between the signal line SL and the control terminal of the drive transistor Trd. The drive transistor Trd has one of a pair of current ends (source and drain) connected to the light emitting element EL and the other connected to the power supply line DS. The pixel capacitor Cs is connected between the control end (gate G) of the drive transistor Trd and one of the pair of current ends (source and drain) (source S) of the drive transistor Trd. The auxiliary capacitor Csub is connected in parallel with the light emitting element EL.

[Timing chart 1 of operation of display device]
FIG. 3 is a timing chart for explaining the operation of the pixel circuit 2 shown in FIG. This timing chart is when the display device is driven at a frame rate of 60 Hz, for example. The change in the potential of the scanning line WS, the change in the potential of the power supply line DS, and the change in the potential of the signal line SL are shown with a common time axis. In parallel with these potential changes, changes in the gate G and source S of the drive transistor Trd are also shown.

  In this timing chart, the period is divided into (0) to (7) for convenience in accordance with the transition of the operation of the pixel 2. First, in the light emission period (0), the feeder line DS is at the high potential Vccp, and the drive transistor Trd supplies the drive current Ids to the light emitting element EL. The drive current Ids flows from the power supply line DS at the high potential Vccp through the light emitting element EL via the drive transistor Trd to the common ground wiring Vcath.

  Subsequently, in the period (1), the feeder line DS is switched from the high potential Vccp to the low potential Vini. As a result, the power supply line DS is discharged to Vini, and the source potential of the drive transistor Trd transits to a potential close to Vini. When the wiring capacity of the feeder line DS is large, the feeder line DS may be switched from the high potential Vccp to the low potential Vini at a relatively early timing.

  Next, in the period (2), the sampling transistor Tr1 becomes conductive by switching the scanning line WS from the low level to the high level. At this time, the signal line SL is at the reference potential Vofs. Therefore, the gate potential of the drive transistor Trd becomes the reference potential Vofs of the signal line SL through the conducting sampling transistor Tr1. At the same time, the source potential of the drive transistor Trd is immediately fixed to the low potential Vini. Thus, the source potential of the drive transistor Trd is initialized (reset) to the potential Vini that is sufficiently lower than the reference potential Vofs of the video signal line SL. Specifically, the low potential Vini of the power supply line DS is set so that the gate / source voltage Vgs (the difference between the gate potential and the source potential) of the drive transistor Trd is larger than the threshold voltage Vth of the drive transistor Trd.

  As is clear from the above description, the period (1) and the period (2) are preparation processes for the threshold voltage correction operation. That is, in this preparation process, the control terminal, which is the gate G of the drive transistor Trd, is held at the reference potential Vofs, while the gate / source voltage Vgs between the current terminals serving as the source S of the drive transistor Trd is larger than the threshold voltage Vth. Then, the drive transistor Trd is turned on.

  Next, in the Vth cancel period (3), the power supply line DS changes from the low potential ini to the high potential Vccp, and the source potential of the drive transistor Trd starts to rise. Eventually, the current is cut off when the gate-source voltage Vgs of the drive transistor Trd reaches the threshold voltage Vth. In this way, a voltage corresponding to the threshold voltage Vth of the drive transistor Trd is written to the pixel capacitor (pixel capacitor) Cs. This is the threshold voltage correction operation. At this time, in order to prevent current from flowing exclusively to the pixel capacitor Cs and not to the light emitting element EL, the potential of the common ground wiring Vcath is set so that the light emitting element EL is cut off.

  As is apparent from the above description, this Vth cancellation period (3) is the energization process of the threshold voltage correction operation. In this energization process, the drive transistor Trd is energized while maintaining the gate G at the reference potential Vofs, and when the drive transistor Trd is cut off, a voltage corresponding to the threshold voltage appearing between the gate / source is held in the pixel capacitor Cs.

  In the period (4), the scanning line WS shifts to the low potential side, and the sampling transistor Tr1 is turned off once. At this time, the gate G of the drive transistor Trd is in a floating state, but the gate / source voltage Vgs is equal to the threshold voltage Vth of the drive transistor Trd, so that it is in a cut-off state, and the drain current Ids does not flow. However, this is an ideal state, and since there is actually a current leak in the drive transistor Trd, the drain current Ids flows though it is slight. This causes a so-called bootstrap phenomenon in which the source potential of the drive transistor Trd varies and the potential of the gate G in a floating state also varies accordingly.

  Subsequently, in period (5), the potential of the signal line SL changes from the reference potential Vofs to the sampling potential (signal potential) Vsig. Thus, preparations for the next sampling operation and mobility correction operation (signal writing and mobility μ cancellation) are completed.

  In the signal writing / mobility μ cancel period (6), the scanning line WS transits to the high potential side, and the sampling transistor Tr1 is turned on. Therefore, the gate potential of the drive transistor Trd becomes the signal potential Vsig. Here, since the light emitting element EL is initially in a cut-off state (high impedance state), the drain-source current Ids of the drive transistor Trd flows into the light emitting element capacitor and the auxiliary capacitor Csub and starts charging. Therefore, the source potential of the drive transistor Trd starts to rise, and the gate / source voltage Vgs of the drive transistor Trd eventually becomes Vsig + Vth−ΔV. In this way, the signal potential Vsig is sampled and the correction amount ΔV is adjusted simultaneously. Ids increases as Vsig increases, and the absolute value of ΔV also increases. Therefore, the mobility correction according to the light emission luminance level is performed. When Vsig is constant, the absolute value of ΔV increases as the mobility μ of the drive transistor Trd increases. In other words, since the negative feedback amount ΔV increases as the mobility μ increases, it is possible to remove variations in the mobility μ from pixel to pixel.

  Finally, in the light emission period (7), the scanning line WS shifts to the low potential side, and the sampling transistor Tr1 is turned off. As a result, the gate G of the drive transistor Trd is disconnected from the signal line SL. At the same time, the drain current Ids starts to flow through the light emitting element EL. As a result, the anode potential of the light emitting element EL rises according to the drive current Ids. The increase in the anode potential of the light emitting element EL is nothing but the increase in the source potential of the drive transistor Trd. When the source potential of the drive transistor Trd rises, the gate potential of the drive transistor Trd also rises in conjunction with the bootstrap operation of the pixel capacitor Cs. The amount of increase in gate potential is equal to the amount of increase in source potential. Therefore, the gate / source voltage Vgs of the drive transistor Trd is kept constant at Vsig + Vth−ΔV during the light emission period (7). In the above description, Vgs is obtained with Vofs = Vcath = 0V.

[Timing chart 2 of operation of display device]
FIG. 4 is a timing chart for explaining the operation of the display device. The difference from the timing chart shown in FIG. 3 is that this example scans the display device line-sequentially at a frame frequency of 90 Hz. Therefore, the time axis of the timing chart is compressed by about 2/3 as compared with the timing chart of FIG. However, the operation sequence itself is the same as the timing chart of FIG. 3, and the time is divided into (0) to (7) for convenience according to the transition of the operation of the pixel 2.

  As shown in FIG. 4, when proceeding to the Vth cancellation period (3), the feeder line DS transitions from the low potential Vini to the high potential Vccp, and the source potential of the drive transistor Trd starts to rise. However, unlike the timing chart of FIG. 3, in this example, the gate / sort voltage Vgs of the drive transistor Trd does not reach the threshold voltage Vth, and the threshold voltage cancellation period (3) ends when Vgs is wider than Vth. End up. Compared to the timing chart of FIG. 3, in the example of FIG. 4, the Vth cancellation period (3) is compressed to 2/3. Therefore, before the source potential of the drive transistor Trd reaches the Vth level indicated by the dotted line, It stays at a low solid line level. As a result, when the frame rate is 90 Hz and 60 Hz, a difference appears in the degree of Vth correction. Therefore, if no measures are taken, even when the same signal potential Vsig is written, a difference in luminance occurs between 60 Hz driving and 90 Hz driving. In other words, the γ characteristic representing the relationship between the signal potential and the luminance changes depending on the frame rate.

[Γ characteristics]
FIG. 5 is a graph showing the γ characteristics of the display device. In this graph, the horizontal axis represents the signal potential V, and the vertical axis represents the luminance L. Two kinds of frame frequencies of 60 Hz and 90 Hz are taken as parameters. As is apparent from the graph, even when the same luminance L is obtained, the signal potential V is greater than 60 Hz when driven at 90 Hz. In this way, when the frame frequency is switched, if no countermeasure is taken, the γ characteristics of the display device are different, and when the same signal potential is applied, the screen luminance is shifted. In order to cope with this, it is necessary to switch the range of the signal potential V according to the frame frequency. However, if the range of the signal potential is adjusted for each frame frequency, the amount of table data for conversion becomes enormous.

[Timing chart 3 of operation of display device]
FIG. 6 is a timing chart according to the first embodiment of the present invention. In order to facilitate understanding, the same notation as the timing chart shown in FIG. 5 is used. FIG. 6 shows the case of driving at a frame frequency of 90 Hz as in the case of FIG. Therefore, the time axis of the timing chart is compressed by 2/3 as compared with the case of FIG. Compared with FIG. 5, since both drive at 90 Hz, the length of the Vth cancellation period (3) is equal. The difference from the timing chart of FIG. 5 is that the reference potential is changed from Vofs to Vofs ′. The reference potential Vofs ′ is set lower than the reference potential Vofs. While the reference potential is Vofs in the case of 60 Hz driving, the reference potential is Vofs ′ in the 90 Hz driving and is adjusted downward. According to this embodiment, the higher the selected frame rate, the lower the reference potential level.

  For example, in the case of driving at 60 Hz under the condition of the reference potential Vofs = 2V, the signal potential range is 2V to 7V. On the other hand, the signal potential range is 2.2 V to 7.2 V when driven at 90 Hz. As described above, there is a difference in the range of the signal potential between the 60 Hz driving and the 90 Hz driving, and the γ characteristics are shifted. Therefore, in this embodiment, the reference potential in the 90 Hz drive is changed from Vofs = 2V to Vofs ′ = 1.8V. In this way, the signal potential range can be set to 2V to 7V. Therefore, in the present embodiment, the reference potential Vofs is simply changed in accordance with the frame rate switching, so that no deviation occurs in the γ characteristic. In this embodiment, the higher the selected frame rate, the lower the reference potential level. However, the present invention is not limited to this. Depending on the operation sequence of the display device, the level of the reference potential may be lowered as the selected frame becomes lower. In either case, the level of the reference potential is appropriately changed according to the selected frame rate so that no difference occurs in the γ characteristics.

[Driver circuit configuration]
FIG. 7 is a circuit diagram illustrating a configuration of a drive unit included in the display device according to the first embodiment. As shown in the figure, the display device includes a pixel array unit 1 and a drive unit that drives the pixel array unit 1. The pixel array unit 1 is formed on the panel 0 and includes row-like scanning lines WS, column-like signal lines SL, and matrix-like pixels 2 arranged at the intersections thereof. The present embodiment further includes a feeder line DS arranged in parallel with the scanning line WS.

  The drive unit is divided into a part mounted on the panel 0 and a part arranged outside the panel 0. The part mounted on the panel 0 includes a horizontal selector 3, a write scanner 4, and a drive scanner 5. The write scanner 4 supplies a control signal for correction during the correction period assigned to each scanning line WS, and further supplies a control signal for writing during the writing period assigned to each scanning line. Line sequential scanning. The horizontal selector 3 supplies a predetermined reference potential to each signal line SL in accordance with the correction period, and supplies a signal potential to each signal line SL prior to the writing period. In the present embodiment, a pair of horizontal selectors 3 is arranged above and below the panel 0 and drives each signal line SL from above and below. In addition to the light scanner 4 and the horizontal selector 3, a drive scanner 5 is also mounted on the panel 0. The drive scanner 5 switches the potential of the power supply line DS between a high potential and a low potential in synchronization with line sequential scanning.

  The pixel 2 includes a light emitting element, a drive transistor in which one current end is connected to the light emitting element and the other current end is connected to the feeder line DS, and one current end is connected to the signal line SL and the other current end is driven. Including a sampling transistor connected to the control terminal (gate) of the transistor, a pixel capacitor connected between the control terminal (gate) and the current terminal (source) of the drive transistor, and an auxiliary capacitor connected in parallel to the light emitting element. Yes.

  The pixel 2 performs the drive transistor correction operation in a state where the sampling transistor is turned on in response to the correction control signal and the reference potential is applied to the control terminal of the drive transistor. Subsequently, when the sampling transistor is turned on in response to the write control signal, the signal potential is written to the control terminal of the drive transistor to perform the write operation. Thereafter, a current corresponding to the written signal potential is supplied from the drive transistor to the light emitting element to perform a light emitting operation.

  As a feature of the present invention, the drive unit includes a regulator 7 disposed outside the panel 0. The regulator 7 is connected to a pair of upper and lower horizontal selectors 3 formed on the panel 0 through a power supply line, and supplies a reference potential Vofs. The horizontal selector 3 alternately switches between the reference potential Vofs and the signal potential and applies them to the signal line SL.

  The regulator 7 includes a clock unit 70, a frame rate switching unit 71, a frame rate / Vofs voltage conversion data storage unit 72, and a variable power source 73. The clock unit 70 supplies a frame rate reference clock to the frame rate / Vofs voltage conversion data storage unit 72. The frame rate switching unit 71 switches the line-sequential scanning speed according to the selected frame rate. The frame rate / Vofs voltage conversion data storage unit 72 constitutes an adjustment unit, and changes the level of the reference potential Vofs according to the selected frame rate. Specifically, the output voltage of the variable power source 73 is adjusted according to the selected frame rate. The frame rate / Vofs voltage conversion data storage unit 72 has a table memory that stores the correspondence between different frame rates and the level of the reference potential Vofs. The level of the reference potential corresponding to the selected frame rate is stored in the table memory. The output potential of the variable power source 73 is adjusted by reading.

<Application form>
Hereinafter, application forms of the display device according to the present invention will be described. The display device according to the present invention has a thin film device configuration as shown in FIG. In FIG. 8, the TFT portion has a Bottom gate structure (the gate electrode is below the channel PS layer), but in addition to this, the TFT portion is a Sandwich gate structure (the channel PS layer is sandwiched between the upper and lower gate electrodes), There are variations such as a Top gate structure (the gate electrode is above the channel PS layer).

  This figure shows a schematic cross-sectional structure of a pixel formed on an insulating substrate. As shown in the figure, the pixel includes a transistor portion (a single TFT is illustrated in the figure) including a plurality of thin film transistors, a capacitor portion such as a pixel capacitor, and a light emitting portion such as an organic EL element. A transistor portion and a capacitor portion are formed on a substrate by a TFT process, and a light emitting portion such as an organic EL element is laminated thereon. A transparent counter substrate is pasted thereon via an adhesive to form a flat panel.

  The display device according to the present invention includes a flat module shape as shown in FIG. For example, a pixel array portion in which pixels made up of organic EL elements, thin film transistors, thin film capacitors and the like are integrated and formed in a matrix is provided on an insulating substrate. An adhesive is disposed so as to surround the pixel array portion (pixel matrix portion), and a counter substrate such as glass is attached to form a display module. If necessary, this transparent counter substrate may be provided with a color filter, a protective film, a light shielding film, and the like. For example, an FPC (flexible printed circuit) may be provided in the display module as a connector for inputting / outputting a signal to / from the pixel array unit from the outside.

  The display device according to the present invention described above has a flat panel shape and is applied to various electronic devices such as a digital camera, a notebook personal computer, a mobile phone, and a video camera. The present display device can be applied to a display of an electronic device in any field that displays a drive signal input to the electronic device or generated in the electronic device as an image or a video. Examples of electronic devices to which such a display device is applied are shown below. The electronic device basically includes a main body unit that processes information, and a display unit that displays information input to the main body unit or information output from the main body unit.

  FIG. 10 shows a television to which the present invention is applied, which includes a video display screen 11 composed of a front panel 12, a filter glass 13, and the like, and is manufactured by using the display device of the present invention for the video display screen 11. .

  FIG. 11 shows a digital camera to which the present invention is applied, in which the top is a front view and the bottom is a rear view. This digital camera includes an imaging lens, a flash light emitting unit 15, a display unit 16, a control switch, a menu switch, a shutter 19, and the like. It is manufactured by using the display device of the present invention for the display portion 16.

  FIG. 12 shows a notebook personal computer to which the present invention is applied. The main body 20 includes a keyboard 21 that is operated when inputting characters or the like. The main body cover includes a display unit 22 for displaying an image, and is manufactured by using the display device of the present invention for the display unit 22.

  FIG. 13 shows a portable terminal device to which the present invention is applied. The left side shows an open state and the right side shows a closed state. The portable terminal device includes an upper housing 23, a lower housing 24, a connecting portion (here, a hinge portion) 25, a display 26, a sub display 27, a picture light 28, a camera 29, and the like. It is manufactured by using the display device of the present invention for the display 26 or the sub-display 27.

  FIG. 14 shows a video camera to which the present invention is applied. The main body 30 includes an object photographing lens 34, a start / stop switch 35 at the time of photographing, a monitor 36, and the like on the side facing forward. It is manufactured by using the display device of the present invention for the monitor 36.

It is a block diagram which shows the principal part of 1st embodiment of the display apparatus which concerns on this invention. FIG. 2 is a circuit diagram illustrating a configuration of a pixel included in the display device illustrated in FIG. 1. It is a timing chart with which it uses for operation | movement description of a display apparatus. 3 is a timing chart for explaining the display device. It is a graph which shows the (gamma) characteristic of a display apparatus. It is a timing chart with which it uses for operation | movement description of 1st embodiment of a display apparatus. It is a circuit diagram which shows the specific structure of 1st embodiment. It is sectional drawing which shows the device structure of the display apparatus concerning this invention. It is a top view which shows the module structure of the display apparatus concerning this invention. It is a perspective view which shows the television set provided with the display apparatus concerning this invention. It is a perspective view which shows the digital still camera provided with the display apparatus concerning this invention. 1 is a perspective view illustrating a notebook personal computer including a display device according to the present invention. It is a schematic diagram which shows the portable terminal device provided with the display apparatus concerning this invention. It is a perspective view which shows the video camera provided with the display apparatus concerning this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Pixel array part, 2 ... Pixel, 3 ... Horizontal selector, 4 ... Write scanner, 5 ... Drive scanner, 7: Regulator, 70 ... Clock part, 71 ... Frame rate switching unit, 72... Frame rate / Vofs voltage conversion data storage unit, 73... Variable power supply, Tr 1. Sampling transistor, Trd... Drive transistor, EL.・ Pixel capacity

Claims (5)

It consists of a pixel array part and a drive part that drives it,
The pixel array unit includes a row-shaped scanning line, a column-shaped signal line, and a matrix-shaped pixel arranged at a portion where these intersect.
The driving unit supplies a control signal for correction during a correction period assigned to each scanning line, and further supplies a control signal for writing during a writing period assigned to each scanning line to line-sequentially scan each scanning line. A scanner that scans, and a selector that supplies a predetermined reference potential to each signal line in accordance with the correction period and supplies a signal potential to each signal line prior to the writing period,
The pixel includes a light emitting element, a drive transistor having one current end connected to the light emitting element and the other current end connected to a power supply, one current end connected to the signal line, and the other current end connected to the drive A sampling transistor connected to the control end of the transistor, and a pixel capacitor connected between the control end and the current end of the drive transistor,
The pixel performs a correction operation of the drive transistor in a state in which the sampling transistor is turned on in response to a correction control signal and the reference potential is applied to a control terminal of the drive transistor, and the pixel is converted into a control signal for writing. Accordingly, when the sampling transistor is turned on, the signal potential is written to the control terminal of the drive transistor to perform a write operation, and then a current corresponding to the written signal potential is supplied from the drive transistor to the light emitting element. To supply light emission,
The drive unit includes a switching unit that switches the line-sequential scanning speed according to a selected frame rate, and an adjustment unit that changes the level of the reference potential according to the selected frame rate.   The display device according to claim 1, wherein the adjustment unit lowers the level of the reference potential as the selected frame rate is higher.   The adjusting unit has a table memory storing a correspondence relationship between different frame rates and reference potential levels, and reads the reference potential level corresponding to the selected frame rate from the table memory to adjust the reference potential. The display device according to claim 1. It consists of a pixel array part and a drive part that drives it,
The pixel array unit includes a row-shaped scanning line, a column-shaped signal line, and a matrix-shaped pixel arranged at a portion where these intersect.
The driving unit supplies a control signal for correction during a correction period assigned to each scanning line, and further supplies a control signal for writing during a writing period assigned to each scanning line to line-sequentially scan each scanning line. A scanner that scans, and a selector that supplies a predetermined reference potential to each signal line in accordance with the correction period and supplies a signal potential to each signal line prior to the writing period,
The pixel includes a light emitting element, a drive transistor having one current end connected to the light emitting element and the other current end connected to a power supply, one current end connected to the signal line, and the other current end connected to the drive A sampling transistor connected to the control end of the transistor, and a pixel capacitor connected between the control end and the current end of the drive transistor,
The pixel performs a correction operation of the drive transistor in a state in which the sampling transistor is turned on in response to a correction control signal and the reference potential is applied to a control terminal of the drive transistor, and the pixel is converted into a control signal for writing. Accordingly, when the sampling transistor is turned on, the signal potential is written to the control terminal of the drive transistor to perform a write operation, and then a current corresponding to the written signal potential is supplied from the drive transistor to the light emitting element. To supply light emission,
The drive unit includes: a switching procedure for switching the line-sequential scanning speed according to the selected frame rate; and an adjustment procedure for changing the reference potential level according to the selected frame rate. Driving method. A main body for processing information, and a display for displaying information input to the main body or information output from the main body,
The display unit includes a pixel array unit and a drive unit that drives the pixel array unit.
The pixel array unit includes a row-shaped scanning line, a column-shaped signal line, and a matrix-shaped pixel arranged at a portion where these intersect.
The driving unit supplies a control signal for correction during a correction period assigned to each scanning line, and further supplies a control signal for writing during a writing period assigned to each scanning line to line-sequentially scan each scanning line. A scanner that scans, and a selector that supplies a predetermined reference potential to each signal line in accordance with the correction period and supplies a signal potential to each signal line prior to the writing period,
The pixel includes a light emitting element, a drive transistor having one current end connected to the light emitting element and the other current end connected to a power supply, one current end connected to the signal line, and the other current end connected to the drive A sampling transistor connected to the control end of the transistor, and a pixel capacitor connected between the control end and the current end of the drive transistor,
The pixel performs a correction operation of the drive transistor in a state in which the sampling transistor is turned on in response to a correction control signal and the reference potential is applied to a control terminal of the drive transistor, and the pixel is converted into a control signal for writing. Accordingly, when the sampling transistor is turned on, the signal potential is written to the control terminal of the drive transistor to perform a write operation, and then a current corresponding to the written signal potential is supplied from the drive transistor to the light emitting element. To supply light emission,
The electronic device includes: a switching unit that switches the line-sequential scanning speed according to a selected frame rate; and an adjustment unit that changes the level of the reference potential according to the selected frame rate.

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