JP2010093926A - Control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a control circuit of a DC-DC converter having improved load response characteristics and reduced input/output voltage difference. <P>SOLUTION: The control circuit includes: a PWM comparison output circuit generating a PWM comparison signal from an input signal; a timing generation circuit generating a control signal from the PWM comparison signal; and a control driver circuit generating a first driving signal and a second driving signal from the control signal. The timing generation circuit includes: a first holding circuit detecting and holding that an on-period rate of the first driving signal becomes 100%; an oscillation circuit which on/off-controls oscillation output by the first holding circuit; and a second holding circuit holding a state of the first driving signal. The first holding circuit operates at a rising edge of oscillation output and is reset by the second driving signal. The second holding circuit operates at a trailing edge of oscillation output, and is reset by a signal obtained by masking the PWM comparison signal with the first driving signal or the second driving signal. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a control circuit, and more particularly to a control circuit for a step-down DC-DC converter.

As the power supply voltage of semiconductor elements is reduced and diversified, the need for a highly efficient power supply with a small input / output voltage difference is increasing. As such a power source, a synchronous rectification type DC-DC converter is known (for example, Patent Document 1).
A synchronous rectification type DC-DC converter includes two switch elements connected in series between an input terminal and a ground, an inductor connected between a connection point of the two switch elements and an output terminal, and a current of the inductor. Has a PWM comparator that inverts when it reaches a predetermined value and a clock signal, and turns on and off the two switch elements alternately to obtain a constant output voltage.

Such a DC-DC converter operates in synchronization with a fixed clock.
One cycle starts by turning on the high-side switch element and turning off the low-side switch element at the rising edge of the clock signal. Then, as the output voltage rises, the PWM comparator is inverted, and the high-side switch element is turned off and the low-side switch element is turned on.
The next cycle starts by turning on the high-side switch element and turning off the low-side switch element at the rising edge of the clock signal, and repeats the above operation.
In this way, a constant output voltage can be obtained.

  However, if the PWM comparator does not invert within one clock, such as when the input voltage drops sharply or the load current changes suddenly, the switch element on the high side will also turn on for the next clock, and the PWM comparator After the inversion, the switch element on the high side is turned off to complete one cycle. In this way, one cycle may be stabilized with two clocks, and the apparent operating frequency may be halved.

  In this case, there is a problem that the characteristics are affected, for example, the ripple of the output voltage is increased.

  Further, as a countermeasure against the above-described phenomenon, there is a method of providing a period during which the high-side switch element is always turned off within one cycle and defining the maximum duty ratio (on-period of the high-side switch element / 1 cycle). is there.

However, this method has a drawback in that the off period is always included within one cycle, so that a necessary amount of power cannot be supplied due to the limitation of the maximum duty ratio, and the load response characteristic deteriorates. Further, since the duty ratio is basically determined by the ratio of the input / output voltage, if the maximum duty ratio is defined, the input / output voltage difference is also limited. Furthermore, the off period is a fixed value for setting in consideration of the response speed of the circuit, and as the operating frequency is increased, the maximum duty ratio is reduced and the input voltage range is narrowed. There is a problem.
JP 2007-209135 A

  The present invention provides a control circuit for a DC-DC converter with improved load response characteristics and reduced input / output voltage difference.

  According to one aspect of the present invention, a PWM comparison output circuit that generates a PWM comparison signal from an input signal, a timing generation circuit that generates a control signal from the PWM comparison signal, a first drive signal and a first drive signal from the control signal A control driver circuit for generating a second drive signal, wherein the timing generation circuit detects and holds that the ON period ratio of the first drive signal has reached 100%. A first holding circuit, an oscillation circuit capable of on / off control of oscillation output by the first holding circuit, and a second holding circuit for holding the state of the first drive signal, The first holding circuit operates at a rising edge of the oscillation output and is reset by the second drive signal, and the second holding circuit operates at a falling edge of the oscillation output, and the PWM comparison Trust Control circuit, characterized in that the reset is provided by a signal the mask in the first drive signal or the second drive signal.

  According to another aspect of the present invention, a PWM comparison output circuit that generates a PWM comparison signal from an input signal, a timing generation circuit that generates a control signal from the PWM comparison signal, and a first from the control signal A control driver circuit for generating a drive signal and a second drive signal, wherein the timing generation circuit has confirmed that the ON period ratio of the first drive signal has reached 100%. A first holding circuit for detecting and holding; an oscillation circuit capable of on / off control of oscillation output by the first holding circuit; a second holding circuit for holding the state of the first drive signal; A delay circuit that generates a delay signal of the oscillation output, wherein the first holding circuit operates at a rising edge of the oscillation output, is reset by the second drive signal, and the second holding circuit Circuit before Operates at the rising edge of the delayed signal, the control circuit of the PWM comparison signal, characterized in that resetting the mask signal in the first drive signal or said second drive signal is provided.

  According to another aspect of the present invention, a PWM comparison output circuit that generates a PWM comparison signal from an input signal, a timing generation circuit that generates a control signal from the PWM comparison signal, and a first from the control signal A control driver circuit that generates a drive signal, wherein the timing generation circuit detects and holds that an on-period ratio of the first drive signal has reached 100%. A first holding circuit; a second holding circuit that holds a state of the first drive signal; and a first holding circuit. The holding circuit operates at the rising edge of the oscillation output and is reset by the first drive signal, and the second holding circuit operates at the falling edge of the oscillation output and outputs the PWM comparison signal to the Control circuit, characterized in that the reset mask signal is provided by one of the drive signals.

  According to the present invention, there is provided a control circuit for a DC-DC converter with improved load response characteristics and reduced input / output voltage difference.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  Note that, in the present specification and each drawing, the same elements as those described above with reference to the previous drawings are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.

(First embodiment)
FIG. 1 is a block diagram illustrating the configuration of a DC-DC converter using a control circuit (portion surrounded by a broken line) according to the first embodiment of the invention.

The DC-DC converter shown in FIG. 1 includes a control circuit 60, an inductor L1, and resistors R1 and R2.
As illustrated in FIG. 1, the illustrated DC-DC converter inputs the input VIN to the control circuit 60. The step-down DC-DC converter obtains an output VOUT lower than the input VIN by alternately turning on / off the two switch elements Q1 and Q2 incorporated in the control circuit 60.

  A connection point SW (connection terminal) between the two switch elements Q1 and Q2 is connected to the input VIN when the switch element Q1 is turned on. Further, the connection point SW (connection terminal) is connected to the ground when the switch element Q2 is turned on. The connection point SW (connection terminal) outputs the output VOUT through the inductor L1. A voltage obtained by dividing the output VOUT by the two resistors R1 and R2 is input to the control circuit 60 as a feedback voltage VREF, and the output VOUT is controlled. Note that the output VOUT may be smoothed by connecting a capacitor (not shown) between the output VOUT and the ground.

The control circuit 60 shown in FIG. 1 has a structure in which the switch elements Q1 and Q2, the timing generation circuit 50, the PWM comparison output circuit 20, and the control driver circuit 40 are formed on the same semiconductor substrate to form a single chip.
The resistors R1 and R2 can be built in the control circuit 60.

  As shown in FIG. 1, the PWM comparison output circuit 20 generates an output signal PWM_OUT (PWM comparison signal) from the feedback voltage VFB and the input VIN. The timing generation circuit 50 generates an output signal T_OUT from the input signals PWM_OUT (PWM comparison signal), Q1_GATE (first drive signal), Q2_GATE (second drive signal), and T_IN. The control driver circuit 40 generates an output signal Q1_GATE (first drive signal), Q2_GATE (second drive signal), and T_IN from the input signal T_OUT. The two switch elements Q1 and Q2 connected in series between the input VIN and the ground are switched by the switch element Q1 using the first drive signal Q1_GATE and the switch element Q2 using the second drive signal Q2_GATE, A connection point SW (connection terminal) between the switch elements Q1 and Q2 is driven.

  In the control circuit 60 shown in FIG. 1, the case where the switch element Q1 is a P-type MOSFET and the switch element Q2 is an N-type MOSFET is illustrated. Therefore, when the first drive signal Q1_GATE = “0”, the switch element Q1 is on, and when the first drive signal Q1_GATE = “1”, the switch element Q1 is off. When the second drive signal Q2_GATE = “0”, the switch element Q2 is off, and when the second drive signal Q2_GATE = “1”, the switch element Q2 is on. The two switch elements Q1 and Q2 are not limited to the present embodiment, and other elements, for example, both N-type MOSFETs or bipolar transistors may be used.

FIG. 2 is a block diagram illustrating the configuration of the timing generation circuit 50 shown in FIG.
As shown in FIG. 2, the timing generation circuit 50 includes an oscillation circuit 10 that can be controlled on / off, D flip-flops 11 and 12, an inverter 13, and a NOR 14.
The transmission circuit 10 can be controlled on / off by the Q-output ENB of the D flip-flop 11 (first holding circuit). When the signal ENB = “1”, it is on, that is, the oscillation output CLK1 is continuously output, and when ENB = “0”, it is off, that is, the oscillation output CLK1 is stopped. Hereinafter, the oscillation output CLK1 and its derived signals (CLK2 and CLK3 described later) are referred to as clocks.

  The D flip-flop 12 (second holding circuit) latches the D input signal T_IN at the rising edge of the clock CLK2 obtained by inverting the clock CLK1 by the inverter 13 and outputs the signal T_OUT. The NOR 14 generates a nor (inverted logical OR) signal T_R (a signal obtained by masking the PWM comparison signal with the first drive signal) between the PWM comparison signal PWM_OUT and the first drive signal Q1_GATE, and the D flip-flop 12. To reset.

  In the timing generation circuit 50, the case where the inverted clock CLK2 of CLK1 is used as the clock of the D flip-flop 12 is shown. However, the present invention is not limited to this, and the clock of the D flip-flop 12 may be a clock obtained by delaying the clock CLK1 by, for example, a delay circuit.

  In this embodiment, the NOR 14 outputs a nor signal T_R of the PWM comparison signal PWM_OUT and the first drive signal Q1_GATE. However, one of the input signals of the NOR 14 is not limited to the first drive signal Q1_GATE, and may be the second drive signal Q2_GATE (a signal obtained by masking the PWM comparison signal with the second drive signal).

  The D flip-flop 11 (first holding circuit) latches the D input signal T_OUT at the rising edge of the clock CLK1 (detects and holds that the ON period ratio of the first drive signal has reached 100%). ), The signal ENB is output to the Q-terminal. Further, the D flip-flop 11 is reset by the second drive signal Q2_GATE. The reset signal input of the D flip-flop 11 is not limited to the second drive signal Q2_GATE, but may be the first drive signal Q1_GATE.

FIG. 3 is a block diagram illustrating the configuration of the PWM comparison output circuit 20 shown in FIG.
The PWM comparison output circuit 20 illustrated in FIG. 3 exemplifies a configuration in the case of current mode control. The reference voltage VREF, the subtraction circuit 21, the phase compensation 22, the PWM comparator 23, the addition circuit 24, the current detection 25, and the slope compensation 26 are illustrated. Have

The subtraction circuit 21 inputs a signal obtained by subtracting the feedback voltage VFB from the reference voltage VREF to the phase compensation 22 and inputs the phase compensation output VC to the positive input terminal of the PWM comparator 23. The adder circuit 24 adds the output of the current detection 25 and the output of the slope compensation 26 and inputs the addition signal VIL to the negative input terminal of the PWM comparator 23.
The PWM comparator 23 outputs the PWM comparison signal PWM_OUT = “1” when the voltage VIL at the negative input terminal is smaller than the voltage VC at the positive input terminal, and when the voltage VIL at the negative input terminal is larger than the voltage VC at the positive input terminal. , PWM comparison signal PWM_OUT = “0” is output.

That is, when the feedback voltage VFB is smaller than the reference voltage VREF and the current detection output after slope compensation (the output of the addition circuit 24) is smaller than the output VC of the phase compensation 22, the PWM comparison signal PWM_OUT = “1”. In cases other than the above, the PWM comparison signal PWM_OUT = “0”.
The overcurrent can be limited by clamping the positive input terminal of the PWM comparator 23 with, for example, a Zener diode.

  Note that the PWM comparison output circuit 20 illustrated in FIG. 3 exemplifies a configuration of current mode control.

Here, returning to FIG. 1 again, the control driver circuit 40 shown in FIG. 1 will be described.
The control driver circuit 40 is a logic circuit that generates, from the input signal T_OUT, output signals Q1_GATE (first drive signal), Q2_GATE (second drive signal), and T_IN shown in a timing chart described later.

  In order to inhibit the two switch elements Q1 and Q2 from being turned on simultaneously, the second drive signal Q2_GATE has a waveform in which the pulse width is narrowed at both edges of the first drive signal Q1_GATE. When the first drive signal Q1_GATE = “1” and the second drive signal Q2_GATE = “0”, the two switch elements Q1 and Q2 are simultaneously turned off (dead time).

  When the two switch elements Q1 and Q2 are simultaneously turned off, the connection point SW (connection terminal) becomes high impedance. In this case, since there is a possibility that a high voltage is generated in the inductor L1 connected to the connection point SW (connection terminal), a diode (not shown) is connected in parallel with the switch element Q2 and flows a regenerative current through the inductor L1.

  The output signal T_IN of the control driver circuit 40 is a signal obtained by adding an overcurrent protection function to the output signal Q1_GATE (first drive signal) of the circuit.

  Next, the operation of the control circuit 60 shown in FIGS. 1 to 3 will be described using a timing chart.

  FIG. 4 is a timing chart of main signals CLK1, CLK2, T_IN, T_OUT, PWM_OUT, T_R, Q1_GATE, Q2_GATE, and SW in the control circuit 60 shown in FIGS.

  FIG. 4 shows a case where the input ENB of the transmission circuit 10 shown in FIG. 2 is “1”, that is, a continuous oscillation state.

  As shown in FIG. 4, at the rising edge of the clock CLK1 shown in FIG. 4A, the signal T_OUT shown in FIG. 4D is “0” (the switch element Q1 is in an OFF state, and the duty ratio is 100% or less). The signal ENB (not shown) is always “1”.

  As shown in (g), (h), and (i) of FIG. 5, when the first drive signal Q1_GATE = “0” and the second drive signal Q2_GATE = “0”, the switch element Q1 is in the ON state. The switch element Q2 is off. At this time, the connection point SW (connection terminal) is connected to the input VIN via the switch element Q1 in the low resistance state, accumulates energy in the inductor L1 connected to the connection point SW (connection terminal), and charges the output. To increase the output VOUT.

  As the output VOUT rises, the feedback voltage VFB also rises, and the PWM comparison signal PWM_OUT changes from “1” to “0” as shown in FIG. The nor signal T_R of the PWM comparison signal PWM_OUT and the first drive signal Q1_GATE in FIG. 5G rises from “0” to “1” as shown in FIG. Then, as shown in FIG. 4D, the signal T_OUT changes from “1” to “0”.

  The change from “1” to “0” of the signal T_OUT changes the first drive signal Q1_GATE from “0” to “1”. The nor signal T_R of the PWM comparison signal PWM_OUT and the first drive signal Q1_GATE changes from “1” to “0”.

  Further, when the signal T_OUT changes from “1” to “0”, the second drive signal Q2_GATE is changed from “0” to “1” after the dead time has elapsed. The switch element Q1 is turned off and the switch element Q2 is turned on. At this time, the connection point SW (connection terminal) is connected to the ground via the switch element Q2 in the low resistance state, and output to the output by the electromotive force due to the energy accumulated in the inductor L1 connected to the connection point SW (connection terminal). A regenerative current is supplied to supply power to the output. The output VOUT decreases as the energy stored in the inductor L1 decreases.

  When the first drive signal Q1_GATE = “1” and the second drive signal Q2_GATE = “0”, the two switch elements Q1 and Q2 are both in the off state. Although the connection point SW (connection terminal) is in a high impedance state, as described above, the connection point SW (connection terminal) is represented as a ground potential in FIG. ing.

As shown in FIGS. 7B and 7C, since the signal T_IN is “1” at the rising edge of the clock CLK2 (in FIG. 8B, the inverted signal of CLK1), the signal T_OUT Is changed from “0” to “1”. Further, as shown in FIGS. 5G and 5H, the second drive signal Q2_GATE is changed from “1” to “0”, and the first drive signal Q1_GATE is changed to “1” after the dead time elapses. To “0”. In this way, as shown in (g), (h), (i) in the same figure, the state of the first drive signal Q1_GATE = “0” and the second drive signal Q2_GATE = “0” again. Become. The switch element Q1 returns to the on state, the switch element Q2 returns to the off state, and the same operation is repeated after the next cycle.
As described above, the DC-DC converter using the control circuit 60 of the present embodiment operates in the same manner as the conventional example when the duty ratio is equal to or less than the specified value.

Next, the operation of the DC-DC converter using the control circuit 60 of this embodiment when the duty ratio is equal to or higher than a specified value (hereinafter referred to as 100% mode) will be described.
FIG. 5 is another timing chart of the main signals CLK1, CLK2, T_IN, T_OUT, PWM_OUT, T_R, Q1_GATE, Q2_GATE, SW, and ENB in the control circuit 60 shown in FIGS.

FIG. 5 shows the 100% mode, that is, the case where the input ENB of the transmission circuit 10 shown in FIG. 2 becomes “0” (the oscillation is stopped).
As shown in FIG. 5, when the signal T_OUT shown in FIG. 5D is “1” at the rising edge of the clock CLK1 shown in FIG. 5A, the signal ENB shown in FIG. "(100% mode).

  The 100% mode is a case where the switching device Q1 is on and the switching device Q2 is off in one cycle, and the PWM comparison signal PWM_OUT in FIG.

This may occur due to a voltage drop of the input VIN, load fluctuation, or the like.
In this case, as shown in (a), (e), and (j) of the figure, the signal ENB = “0” and the clock CLK1 is stopped. Until the PWM comparison signal PWM_OUT changes from “1” to “0”, the first drive signal Q1_GATE = “0” and the second drive signal Q2_GATE = “0” (the switch element Q1 is on and the switch element Q2 is off) Status).

  As shown in FIG. 5E, when the PWM comparison signal PWM_OUT changes from “1” to “0”, the signal T_OUT in FIG. 5D is changed to “1” by the same operation as described in FIG. It changes from “0” to “0”. Further, the second drive signal Q2_GATE in FIG. 5H changes from “0” to “1”.

  Due to the change of the second drive signal Q2_GATE from “0” to “1”, the signal ENB in FIG. 10J changes from “0” to “1”, and the clock CLK1 in FIG. Resume oscillation.

  As shown in FIGS. 7A and 7J, when the signal ENB changes from “1” to “0”, the clock CLK1 stops at “1”. Therefore, the inverted signal CLK2 of the clock CLK1 rises at a predetermined timing. When the delayed signal of the clock CLK1 is used as the clock CLK2, the clock CLK1 is stopped at “0” when the signal ENB changes from “1” to “0”. Further, when the signal ENB changes from “0” to “1”, the clock CLK1 may change from “0” to “1”.

The PWM comparator may not be inverted within one clock when the input voltage drops sharply or when the load current changes suddenly. According to the DC-DC converter using the control circuit 60 of this embodiment, since the clock is stopped at this time, there is no disadvantage that one cycle is stabilized by two clocks. Further, since there is no restriction on the maximum duty ratio, there is no disadvantage that the input / output voltage difference is restricted, the required amount of power cannot be supplied, and the load response characteristic is deteriorated. Furthermore, since the off period does not necessarily enter within one cycle, there is no restriction on the increase in frequency due to the insertion of the off period.
Therefore, if the control circuit 60 of this embodiment is used for a DC-DC converter, a DC-DC converter with improved load response characteristics and reduced input / output voltage difference is provided.

(Comparative example)
The configuration of the control circuit 60 according to the first embodiment of the present invention is constructed so as to solve the problems newly found by the comparative example described below.
The inventor constructed a control circuit to solve the problems of the prior art and examined its operation in detail.
The control circuit 160 of the comparative example has the same configuration as the block diagram of the control circuit 60 of the present embodiment shown in FIG. 1, and the timing generation circuit 50 shown in FIG. 1 is changed to the timing generation circuit 150 of the comparative example. The configuration is as follows.

FIG. 6 is a block diagram illustrating the configuration of the timing generation circuit of the comparative example.
As illustrated in FIG. 6, the timing generation circuit 150 of the comparative example includes an oscillation circuit 10 that can be controlled on / off, a D flip-flop 11, an SR latch 17, and an AND 18.
The transmission circuit 10 and the D flip-flop 11 are the same as those in the timing generation circuit 50 of the above embodiment, and the description thereof is omitted.

  The SR latch 17 is reset by the PWM comparison signal PWM_OUT. The AND 18 outputs an AND signal CLK3 of the clock CLK1 and the second drive signal Q2_GATE, and sets the SR latch.

Next, the operation of the DC-DC converter using the control circuit 160 of the comparative example will be described.
FIG. 7 is a timing chart of main signals CLK1, CLK3, T_IN, T_OUT, PWM_OUT, T_R, Q1_GATE, Q2_GATE, SW, and ENB in the DC-DC converter using the timing generation circuit 60 of the comparative example shown in FIG. is there.

  Due to a decrease in the input voltage, the duty ratio is increased to near 100%, and the PWM comparison signal PWM_OUT in FIG. 5E masks the clock CLK3 in FIG. 4B, and the switching element Q1 cannot be turned on in the next cycle. There is a case. FIG. 7 shows such a case with a portion surrounded by a broken line in FIG.

  As shown in (g), (h), and (i) of FIG. 5, when the first drive signal Q1_GATE = “0” and the second drive signal Q2_GATE = “0”, the switch element Q1 is in the ON state. The switch element Q2 is off. At this time, the connection point SW (connection terminal) is connected to the input VIN via the switch element Q1 in the low resistance state, accumulates energy in the inductor L1 connected to the connection point SW (connection terminal), and charges the output. To increase the output VOUT.

  As the output VOUT rises, the feedback voltage VFB also rises, and the PWM comparison signal PWM_OUT changes from “1” to “0” as shown in FIG. . Due to the change of the PWM comparison signal PWM_OUT, the signal T_OUT changes from “1” to “0” as shown in FIG.

  As shown in (g) and (h) of the figure, the change from “1” to “0” of the signal T_OUT changes the first drive signal Q1_GATE from “0” to “1”. Further, after the dead time elapses, the second drive signal Q2_GATE is changed from “0” to “1”.

  The switch element Q1 is turned off and the switch element Q2 is turned on, and the connection point SW (connection terminal) is connected to the ground via the switch element Q2 in the low resistance state. A regenerative current flows through the output by the electromotive force generated by the energy stored in the inductor L1 to supply power to the output. The output VOUT decreases as the energy stored in the inductor L1 decreases.

  However, since the clock CLK3 in FIG. 5C is masked by the PWM comparison signal PWM_OUT in FIG. 5E, the signal T_OUT cannot be changed to “1” when the clock CLK3 = “1”. The signal T_OUT remains “0” until the next cycle. During this time, the switch element Q1 remains off and the output VOUT continues to decrease.

  When the signal T_OUT = “1” is set with the clock CLK3 = “1” in the next cycle, the first drive signal Q1_GATE = “0” and the second drive signal Q2_GATE = “0” are changed. The switch element Q1 is turned on and the switch element Q2 is turned off. However, since the previous cycle is OFF, the output VOUT and the feedback voltage VFB are decreased, and the phase compensation output VC is increased, so that the ON period is lengthened. As shown in the figure, there is a case where the next cycle also becomes an ON period, which causes a problem that output voltage ripple and current ripple become large.

  As described above, the DC-DC converter using the timing generation circuit 150 of the comparative example has a duty ratio of around 100% due to a decrease in input voltage or the like under the condition that the response (recovery) time of the PWM comparator is slower than the clock CLK3 width. The PWM comparison signal PWM_OUT spreads out to mask the clock CLK3, which may cause a problem that the next cycle cannot be turned on.

  This problem can be improved by increasing the response time of the PWM comparator. However, increasing the bias current in order to speed up the response time has an adverse effect of increasing the power consumption and reducing the efficiency of the DC-DC converter, and the bias current cannot be increased more than necessary.

  Further, the malfunction can be avoided by expanding the width of the clock CLK3 beyond the response time of the PWM comparator. However, since the width of the clock CLK3 is the minimum on-pulse width of the connection point SW (connection terminal), the characteristic of the current discontinuous mode is deteriorated, so that the width of the clock CLK3 cannot be increased more than necessary.

Thus, the DC-DC converter using the timing generation circuit 150 of the comparative example may not be able to smoothly shift to the 100% mode operation. This is because the maximum duty ratio that can be normally used is limited by the response time of the PWM comparator because there are restrictions on the response characteristics of the PWM comparator and the width of the clock CLK3.
On the other hand, the DC-DC converter using the timing generation circuit 50 of the embodiment solves the above problem and can smoothly shift to the 100% mode.

  Referring to FIG. 5 again, the timing that becomes a problem in the comparative example corresponds to the portion surrounded by the broken line in FIG.

  As shown in FIG. 5, the signal T_R in FIG. 5F is a signal obtained by masking the PWM comparison signal PWM_OUT in FIG. 5E with the first drive signal Q1_GATE in FIG. Therefore, in the 100% mode of the signal ENB = “0” in FIG. 10J, the PWM comparison signal PWM_OUT passes only when the first drive signal Q1_GATE = “0”, and depends on the pulse width of the PWM comparison signal PWM_OUT. There is no narrow pulse.

As the signal T_R changes from “0” to “1”, the signal T_OUT in FIG. 4D changes from “1” to “0”. The first drive signal Q1_GATE in FIG. 5G changes from “0” to “1”, and the second drive signal Q2_GATE in FIG. 5H changes from “0” to “1” after the dead time elapses. To do.
When the second drive signal Q2_GATE changes from “0” to “1”, the signal ENB is reset to “1”. The 100% mode ends and the clock CLK1 resumes oscillation.

  When the first drive signal Q1_GATE changes from “0” to “1”, the signal T_R returns from “1” to “0”, and the signal T_IN becomes “1”. At the next rising edge of the clock CLK2, the signal T_OUT changes from “0” to “1”. The second drive signal Q2_GATE changes from “1” to “0”, and after the dead time elapses, the first drive signal Q1_GATE changes from “1” to “0”.

  In this manner, at the rising edge of the clock CLK2, the first drive signal Q1_GATE = “0” and the second drive signal Q2_GATE = “0” (switch element Q1 is on and switch element Q2 is off) return to the next state. After the cycle, it returns to normal operation. In addition, since the signal D_OUT is set at the rising edge (falling edge of the clock CLK1) of the clock CLK2, the minimum on-pulse width of the connection point SW (connection terminal) is independent of the width of the clock CLK2 (clock CLK1). . Therefore, the width of the clock CLK2 (clock CLK1) can be arbitrarily set.

  Accordingly, the time from the rising edge of the clock CLK2 until the second drive signal Q2_GATE changes from “1” to “0” and the first drive signal Q1_GATE changes from “1” to “0” is expressed as PWM. By setting the comparison signal PWM_OUT longer than the width of the comparison signal PWM_OUT, it is possible to avoid a phenomenon in which the switch element Q1 is erroneously turned off by being reset with the PWM comparison signal PWM_OUT = “0”.

  The first drive signal Q1_GATE changes from “1” to “0” after the second drive signal Q2_GATE changes from “1” to “0” (the switch element Q1 turns on after the switch element Q2 turns off) ) Is set to be longer than the width of the normal PWM comparison signal PWM_OUT, and a dead time (simultaneous OFF time) is provided to prevent a through current.

As described above, according to the control circuit 60 using the timing generation circuit 50 of this embodiment, the above-described malfunction is not caused in most cases without particularly increasing the speed of the PWM comparator and regardless of the width of the clock CLK1. It can be avoided. In addition, there is no limit when shifting from normal operation to 100% mode operation, and improvement in characteristics can be expected in the operating range and load response characteristics, the input / output voltage difference is reduced, and the load response is improved. A converter is provided.

  Compared to the DC-DC converter of the comparative example, the timing for detecting the 100% mode is earlier by the width of the clock CLK1 as seen from the rising edge of the clock CLK2, but the pulse width required for the 100% mode itself is controlled. Therefore, there is almost no problem in practical use.

  Further, the timing generation circuit 50 of this embodiment masks the PWM comparison signal signal PWM_OUT with the first drive signal Q1_GATE, but the response time of the PWM comparator is from the rise of the clock CLK1 until the switch element Q2 is turned off. When the time is shorter than the time, the same effect can be obtained by masking the PWM comparison signal PWM_OUT with the second drive signal Q2_GATE.

(Second Embodiment)
FIG. 8 is a block diagram illustrating a configuration when a control circuit (portion surrounded by a broken line) according to the second embodiment of the present invention is used in a DC-DC converter.
The DC-DC converter shown in FIG. 8 includes a control circuit 61, a switch element Q2, an inductor L1, and resistors R1 and R2.
As illustrated in FIG. 8, the illustrated DC-DC converter is the same as the DC-DC converter illustrated in FIG. 1, and thus detailed description thereof is omitted.

The control circuit 61 shown in FIG. 8 has a structure in which the switch element Q1, the timing generation circuit 50, the PWM comparison output circuit 20, and the control driver circuit 40 are formed on the same semiconductor substrate to form a single chip.
That is, the control circuit 61 is obtained by removing the switch element Q2 from the control circuit 60 shown in FIG.
The operation of each part is the same as that of the control circuit 60 shown in FIG. 1, and detailed description thereof is omitted.

According to the DC-DC converter using the control circuit according to the present embodiment, a DC-DC converter is provided in which the duty ratio 100% mode is allowed, thereby reducing the input / output voltage difference and improving the load response. Is done.
Further, by removing the switch element Q2 from the control circuit, the degree of freedom of selection is increased, and a diode can be used as Q2.

(Third embodiment)
FIG. 9 is a block diagram illustrating a configuration when a control circuit (portion surrounded by a broken line) according to the third embodiment of the present invention is used in a DC-DC converter.
The DC-DC converter shown in FIG. 9 includes a control circuit 62, switching elements Q1, Q2, an inductor L1, and resistors R1, R2, R3.

As illustrated in FIG. 9, the illustrated DC-DC converter is the same as the DC-DC converter illustrated in FIG. 1 except that a resistor R3 is added for current detection of the switch element Q1, and thus detailed description thereof is omitted. To do.
The control circuit 62 shown in FIG. 9 has a structure in which the timing generation circuit 50, the PWM comparison output circuit 20, and the control driver circuit 40 are formed on the same semiconductor substrate into one chip.
That is, the control circuit 62 is obtained by removing the switch elements Q1 and Q2 from the control circuit 60 shown in FIG.
The operation of each part is the same as that of the control circuit 60 shown in FIG. 1, and detailed description thereof is omitted.

  According to the DC-DC converter using the control circuit according to the present embodiment, a DC-DC converter is provided in which the duty ratio 100% mode is allowed, thereby reducing the input / output voltage difference and improving the load response. Is done.

  Further, by removing the two switch elements Q1 and Q2 from the control circuit, it is possible to reduce the size and power consumption of the control circuit. Further, the degree of freedom of selection is further increased, and the optimum switch elements Q1 and Q2 can be selected according to the operating voltage and current.

(Fourth embodiment)
FIG. 10 is a block diagram illustrating a configuration when a control circuit (portion surrounded by a broken line) according to the fourth embodiment of the present invention is used in a DC-DC converter.
The DC-DC converter shown in FIG. 10 includes a control circuit 63, a switch element Q1, a diode D1, an inductor L1, and resistors R1 and R2.

  As illustrated in FIG. 10, the illustrated DC-DC converter inputs the input VIN to the control circuit 63. This is a step-down DC-DC converter that obtains an output VOUT lower than the input VIN by turning on / off the switch element Q1 built in the control circuit 63. A connection point SW (connection terminal) between the switch element Q1 and the diode D1 is connected to the input VIN when the switch element Q1 is turned on, and is connected to the ground via the diode D1 when the switch element Q1 is turned off. The connection point SW (connection terminal) outputs the output VOUT through the inductor L1. Further, a voltage obtained by dividing the output VOUT by the two resistors R1 and R2 is input to the control circuit 63 as the feedback voltage VREF, and the output VOUT is controlled. Note that the output VOUT may be smoothed by connecting a capacitor (not shown) between the output VOUT and the ground.

The control circuit 63 shown in FIG. 10 has a structure in which the timing generation circuit 50, the PWM comparison output circuit 20, and the control driver circuit 41 are formed on the same semiconductor substrate into one chip.
The PWM comparison output circuit 20 is the same as that in the DC-DC converter illustrated in FIG.

  The timing generation circuit 51 illustrated in FIG. 10 is a circuit that generates an output signal T_OUT from the input signals PWM_OUT (PWM comparison signal), Q1_GATE (first drive signal), and T_IN. The control driver 41 is a circuit that generates an output signal Q1_GATE (first drive signal) and T_IN from the input signal T_OUT.

  The timing generation circuit 51 illustrated in FIG. 10 has a configuration in which the second drive signal Q2_GATE is replaced with the first drive signal Q1_GATE in the timing generation circuit 50 illustrated in FIG. Further, the control driver 41 has a configuration obtained by removing the second drive signal Q2_GATE from the control driver 40 shown in FIG.

Next, the operation of the control circuit 63 shown in FIG. 10 will be described using a timing chart.
FIG. 11 is a timing chart of main signals CLK1, CLK2, T_IN, T_OUT, PWM_OUT, T_R, Q1_GATE, and SW in the control circuit 63 illustrated in FIG.

  As shown in FIG. 11, the transition from the 100% mode of the signal ENB = “0” in FIG. 11 (i) to the steady state of ENB = “1” is the signal first drive signal in FIG. 11 (g). This is performed by resetting with Q1_GATE = “1”. The use of the first drive signal Q1_GATE is different from the DC-DC converter using the control circuit 50 of the embodiment shown in FIG.

  In the DC-DC converter using the control circuit 63, the low-side driver signal Q2_GATE (second drive signal) becomes unnecessary by using the diode D1. Therefore, the high-side driver signal Q1_GATE (first drive signal) is used as the reset signal for the D flip-flop 11 of the timing generation circuit 51 shown in FIG. Thereby, an effect equivalent to that of the DC-DC converter using the control circuit 60 illustrated in FIG. 1 can be obtained.

  However, since it is not necessary to set a delay time (dead time) for preventing a through current, when the control circuit 60 is used as shown in FIG. 11, the time from the rising edge of the clock CLK1 to the turning on of the switch element Q1 is used. Shorter than It is necessary to set the width of the clock CLK1 as necessary.

  Since the state of the D flip-flop 12 shown in FIG. 2 is set at the rising edge of the clock CLK2 (falling edge of the clock CLK1), the minimum on-pulse width of the connection point SW (connection terminal) is the clock CLK2 (clock CLK1). Becomes independent of width. Therefore, the width of the clock CLK2 (clock CLK1) can be arbitrarily set.

  According to the DC-DC converter using the control circuit 63 according to the present embodiment, there is provided a DC-DC converter that reduces the input / output voltage difference and improves the load response by allowing the duty ratio 100% mode. Provided.

  Further, by removing the drive signal Q2_GATE (second drive signal) for the low-side switch element from the control circuit, the control circuit can be reduced in size.

The embodiments of the present invention have been described above with reference to the examples. However, the present invention is not limited to these examples. For example, with regard to the specific configuration of each element constituting the control circuit, the present invention is similarly implemented by appropriately selecting from the well-known range by those skilled in the art, and as long as the same effects can be obtained, Included in the range.
Moreover, what combined any two or more elements of each Example in the technically possible range is also included in the scope of the present invention as long as the gist of the present invention is included.

In addition, all elements and devices that can be implemented by those skilled in the art based on the control circuit described above as an embodiment of the present invention are included in the scope of the present invention as long as they include the gist of the present invention. Belongs.
In addition, in the category of the idea of the present invention, those skilled in the art can conceive of various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

It is a block diagram which illustrates the composition of the DC-DC converter using the control circuit concerning a 1st embodiment of the present invention. FIG. 2 is a block diagram illustrating a configuration of a timing generation circuit illustrated in FIG. 1. FIG. 2 is a block diagram illustrating a configuration of a PWM comparison output circuit illustrated in FIG. 1. 4 is a timing chart of the DC-DC converter illustrated in FIGS. 4 is another timing chart of the DC-DC converter illustrated in FIGS. It is a block diagram which shows the structure of the timing generation circuit of a comparative example. It is a timing chart of a comparative example. It is a block diagram which illustrates the composition of the DC-DC converter using the control circuit concerning a 2nd embodiment of the present invention. It is a block diagram which illustrates the composition of the DC-DC converter using the control circuit concerning a 3rd embodiment of the present invention. It is a block diagram which illustrates the composition of the DC-DC converter using the control circuit concerning a 4th embodiment of the present invention. 11 is a timing chart of the DC-DC converter illustrated in FIG. 10.

Explanation of symbols

10 Transmitter 11 D flip-flop (first holding circuit)
12 D flip-flop (second holding circuit)
DESCRIPTION OF SYMBOLS 13 Inverter circuit 14 NOR circuit 17 RS latch 18 AND circuit 20 PWM comparison output circuit 21 Subtraction circuit 22 Phase compensation 23 PWM comparator 24 Adder circuit 25 Current detection 26 Slope compensation 40, 41 Control driver circuit 50, 51, 150 Timing generation circuit 60 , 61, 62, 63, 160 Control circuit D1 Diode L1 Inductor Q1 Transistor (first switch element)
Q2 transistor (second switch element)
R1, R2, R3 Resistance SW Connection point (connection terminal)
VFB feedback voltage VIN input voltage VOUT output voltage

Claims (5)

A PWM comparison output circuit for generating a PWM comparison signal from the input signal;
A timing generation circuit for generating a control signal from the PWM comparison signal;
A control driver circuit for generating a first drive signal and a second drive signal from the control signal;
A control circuit comprising:
The timing generation circuit includes:
A first holding circuit for detecting and holding that the ON period ratio of the first drive signal has reached 100%;
An oscillation circuit capable of controlling on / off of an oscillation output by the first holding circuit;
A second holding circuit for holding the state of the first drive signal;
Have
The first holding circuit operates at a rising edge of the oscillation output, and is reset by the second driving signal.
The second holding circuit operates at a falling edge of the oscillation output, and resets the PWM comparison signal with the signal masked with the first drive signal or the second drive signal. circuit. A PWM comparison output circuit for generating a PWM comparison signal from the input signal;
A timing generation circuit for generating a control signal from the PWM comparison signal;
A control driver circuit for generating a first drive signal and a second drive signal from the control signal;
A control circuit comprising:
The timing generation circuit includes:
A first holding circuit for detecting and holding that the ON period ratio of the first drive signal has reached 100%;
An oscillation circuit capable of controlling on / off of an oscillation output by the first holding circuit;
A second holding circuit for holding the state of the first drive signal;
A delay circuit for generating a delay signal of the oscillation output;
Have
The first holding circuit operates at a rising edge of the oscillation output, and is reset by the second driving signal.
The second holding circuit operates at a rising edge of the delay signal, and resets the PWM comparison signal with a signal masked by the first drive signal or the second drive signal. . A PWM comparison output circuit for generating a PWM comparison signal from the input signal;
A timing generation circuit for generating a control signal from the PWM comparison signal;
A control driver circuit for generating a first drive signal from the control signal;
A control circuit comprising:
The timing generation circuit includes:
A first holding circuit for detecting and holding that the ON period ratio of the first drive signal has reached 100%;
An oscillation circuit capable of controlling on / off of an oscillation output by the first holding circuit;
A second holding circuit for holding the state of the first drive signal;
Have
The first holding circuit operates at a rising edge of the oscillation output, and is reset by the first drive signal.
The control circuit, wherein the second holding circuit operates at a falling edge of the oscillation output and resets the PWM comparison signal with a signal masked by the first drive signal. A first switch element;
A connection terminal connected to the first switch element;
Further comprising
The control circuit according to claim 1, wherein the first drive signal drives the first switch element. A first switch element;
A second switch element connected in series with the first switch element;
Further comprising
The first drive signal drives the first switch element;
The control circuit according to claim 1, wherein the second drive signal drives the second switch element.

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