JP2010092623A - Electronic breaker - Google Patents

Electronic breaker Download PDF

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JP2010092623A
JP2010092623A JP2008258815A JP2008258815A JP2010092623A JP 2010092623 A JP2010092623 A JP 2010092623A JP 2008258815 A JP2008258815 A JP 2008258815A JP 2008258815 A JP2008258815 A JP 2008258815A JP 2010092623 A JP2010092623 A JP 2010092623A
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cpu
reset signal
circuit
trip coil
monitoring circuit
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JP5226450B2 (en
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Koji Konishi
功次 小西
Takashi Yamato
敬史 大和
Toshiyuki Nakagawa
敏幸 中川
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Kawamura Electric Inc
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Kawamura Electric Inc
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Abstract

<P>PROBLEM TO BE SOLVED: To prevent secondary damage caused by runaway of a CPU by assuring fail-safe of the CPU in an electronic breaker. <P>SOLUTION: A CPU monitoring circuit 22 monitors the operation of the CPU 18 based on a periodical pulse output by the CPU 18. When the CPU 18 runs away, and the periodical pulse stops, the monitoring circuit 22 outputs a reset signal to the CPU 18 and a trip coil driving circuit 21. The CPU 18 responds to the reset signal to initialize it, and when it can not be initialized, a drive circuit 21 drives a trip coil 10 to open a main contact 9. When the control program of the CPU 18 is written in a flush ROM 24, a switch 26 is opened to interrupt the reset signal from the monitoring circuit 22 to the CPU 18. The monitoring circuit 22 is made to output the reset signal, and the response of the trip coil 10 to the reset signal is observed to confirm return failure of the switch 26. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、電路に過電流が流れたときに、CPUの制御によりトリップコイルを駆動して主接点を開く電子式ブレーカに関する。   The present invention relates to an electronic breaker that opens a main contact by driving a trip coil under the control of a CPU when an overcurrent flows in an electric circuit.

従来、電路に流れる電流を電流センサで検出し、電流センサの出力が閾値を超えたときに、CPUの制御によりトリップコイルを駆動して主接点を開く電子式ブレーカが知られている。CPU制御によると、遮断機能のほかに表示機能や通信機能などを容易に装備でき、ブレーカの機能性および機動性を高めることができる利点がある。   2. Description of the Related Art Conventionally, an electronic breaker that detects a current flowing in an electric circuit with a current sensor and drives a trip coil under the control of a CPU to open a main contact when an output of the current sensor exceeds a threshold value is known. According to the CPU control, in addition to the shut-off function, a display function, a communication function, and the like can be easily provided, and there is an advantage that the functionality and mobility of the breaker can be improved.

例えば、特許文献1には、記憶媒体に記録した定格電流をCPUに読み取らせ、ブレーカの内部メモリに登録する技術が記載されている。特許文献2には、ブレーカと外部操作機器との無線通信をCPUで制御し、定格電流を外部操作機器により無線通信を介して切り替える技術が記載されている。
特開2008−79412号公報 特開2008−78007号公報
For example, Patent Document 1 describes a technique in which a rated current recorded in a storage medium is read by a CPU and registered in an internal memory of a breaker. Patent Document 2 describes a technology in which wireless communication between a breaker and an external operation device is controlled by a CPU, and the rated current is switched by the external operation device via wireless communication.
JP 2008-79412 A JP 2008-78007 A

ところが、従来の電子式ブレーカでは、CPUのフェイルセーフが確保されていなかった。このため、外来ノイズや雷サージなどでCPUが暴走したときに、電路に流れる電流を監視できなくなり、遮断機能に障害を来たし、二次被害を招くおそれがあった。   However, the conventional electronic breaker has not ensured failsafe of the CPU. For this reason, when the CPU runs away due to external noise or lightning surge, it becomes impossible to monitor the current flowing in the electric circuit, which may cause a failure in the interruption function and cause secondary damage.

そこで、本発明の目的は、CPUのフェイルセーフを確保し、暴走時の二次被害を未然に防止できる電子式ブレーカを提供することにある。   Therefore, an object of the present invention is to provide an electronic breaker that can ensure fail-safe CPU and prevent secondary damage during runaway.

上記課題を解決するために、本発明は、電路に流れる電流を電流センサで検出し、電流センサの出力が閾値を超えたときに、CPUの制御によりトリップコイルを駆動して主接点を開く電子式ブレーカにおいて、次のような手段を採用したことを特徴とする。   In order to solve the above-described problems, the present invention detects an electric current flowing in an electric circuit with a current sensor, and when the output of the current sensor exceeds a threshold value, the trip coil is driven under the control of the CPU to open the main contact. The type breaker is characterized by adopting the following means.

(1)CPUが出力する定期パルスに基づいてCPUの動作を監視する監視回路と、定期パルスが途絶えたときの監視回路の出力に応答してトリップコイルを駆動する駆動回路と備えたことを特徴とする電子式ブレーカ。 (1) A monitoring circuit that monitors the operation of the CPU based on a periodic pulse output from the CPU, and a drive circuit that drives the trip coil in response to the output of the monitoring circuit when the periodic pulse is interrupted. Electronic breaker.

(2)定期パルスが途絶えたときに、監視回路がCPUを初期化するためのリセット信号を出力し、駆動回路がCPUの初期化に要する時間よりも長い時間が経過した後にトリップコイルを駆動することを特徴とする電子式ブレーカ。 (2) When the periodic pulse is interrupted, the monitoring circuit outputs a reset signal for initializing the CPU, and the drive circuit drives the trip coil after a time longer than the time required for initialization of the CPU has elapsed. This is an electronic breaker.

(3)CPUの制御プログラムを記憶するメモリと、メモリに制御プログラムを書き込むときにリセット信号を遮断するスイッチとを備え、スイッチが遮断位置に操作されている状態で監視回路がリセット信号を出力したときに、駆動回路がトリップコイルを駆動することを特徴とする電子式ブレーカ。 (3) A memory for storing a control program for the CPU and a switch for shutting off the reset signal when the control program is written to the memory are provided, and the monitoring circuit outputs the reset signal while the switch is operated at the shut-off position. An electronic breaker characterized in that the drive circuit drives the trip coil.

上記(1)の電子式ブレーカによれば、監視回路が駆動回路と連系してCPUのフェイルセーフを確保するので、CPUの暴走に伴う二次被害を未然に防止できるという効果がある。   According to the electronic breaker of the above (1), the monitoring circuit is linked with the drive circuit to ensure the fail safe of the CPU, so that it is possible to prevent secondary damage accompanying the runaway of the CPU.

上記(2)の電子式ブレーカによれば、監視回路が出力したリセット信号でCPUを初期化し、初期化中に主接点をむやみに開くことなく、CPUを自動的に復旧できるという効果がある。   According to the electronic breaker of (2), there is an effect that the CPU can be automatically restored without initializing the main contact during initialization, by initializing the CPU with the reset signal output from the monitoring circuit.

上記(3)の電子式ブレーカによれば、スイッチを遮断位置に操作した状態で、CPUの制御プログラムをメモリに書き込むことができ、スイッチを遮断位置から戻し忘れたときに、駆動回路によりトリップコイルを駆動できるうえ、人為的なリセット信号に対するトリップコイルの応答に基づいて、スイッチの戻し忘れを容易に確認できるという効果がある。   According to the electronic breaker of (3) above, the CPU control program can be written into the memory while the switch is operated to the shut-off position, and when the switch is forgotten to return from the shut-off position, the trip coil is driven by the drive circuit. In addition, it is possible to easily check forgetting to return the switch based on the response of the trip coil to the artificial reset signal.

以下、本発明の実施形態を図面に基づいて説明する。図1は単相3線式電路用の電子式ブレーカの外観を示し、図2はケーシングの内部機構を示す。図3は電子式ブレーカの制御回路を示し、図4は制御回路中のCPU監視回路とトリップコイル駆動回路を詳細に示す。図5〜図8は監視回路と駆動回路の連係動作を示し、図5はCPU正常時、図6は過電流発生時、図7はCPU暴走時、図8はCPU復旧時の状態を示す。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows the external appearance of an electronic breaker for a single-phase three-wire circuit, and FIG. 2 shows the internal mechanism of the casing. FIG. 3 shows the control circuit of the electronic breaker, and FIG. 4 shows the CPU monitoring circuit and trip coil drive circuit in the control circuit in detail. 5 to 8 show the linking operation of the monitoring circuit and the drive circuit, FIG. 5 shows the state when the CPU is normal, FIG. 6 shows the state when an overcurrent occurs, FIG. 7 shows the state when the CPU is out of control, and FIG.

図1に示すように、この実施例の電子式ブレーカ1は、ケーシング2の上端部に3つの電源側端子3を備え、下端部に3つの負荷側端子4を備えている。ケーシング2の前面には、単相3線式電路を手動で開閉するハンドル5と、ブレーカ1の定格電流や動作状態を表示する表示部6と、表示や動作モードを切り替える手元スイッチ7と、パソコンや携帯端末等の外部操作機器に接続されるLAN配線接続口8とが設けられている。   As shown in FIG. 1, the electronic breaker 1 of this embodiment includes three power-side terminals 3 at the upper end portion of the casing 2 and three load-side terminals 4 at the lower end portion. On the front surface of the casing 2 are a handle 5 for manually opening and closing a single-phase three-wire electric circuit, a display unit 6 for displaying the rated current and operating state of the breaker 1, a hand switch 7 for switching the display and operating mode, and a personal computer. And a LAN wiring connection port 8 connected to an external operation device such as a portable terminal.

図2に示すように、ケーシング2の内部には、電路15(図3参照)に過電流が流れたときに主接点9を開くトリップコイル10と、電路15に短絡電流が流れたとときに主接点9を瞬時に開く瞬時遮断機構11と、トリップコイル10および瞬時遮断機構11の動力を主接点9に伝える開閉機構12とが設置されている。そして、ケーシング2の背面に電子回路基板13が取り付けられ、この基板13上に表示部6やトリップコイル10等を制御するための電子制御回路が設けられている。   As shown in FIG. 2, the casing 2 includes a trip coil 10 that opens the main contact 9 when an overcurrent flows through the electric circuit 15 (see FIG. 3), and a main circuit when a short-circuit current flows through the electric circuit 15. An instantaneous interruption mechanism 11 that instantaneously opens the contact 9 and an opening / closing mechanism 12 that transmits the power of the trip coil 10 and the instantaneous interruption mechanism 11 to the main contact 9 are installed. An electronic circuit board 13 is attached to the back surface of the casing 2, and an electronic control circuit for controlling the display unit 6, trip coil 10, and the like is provided on the board 13.

図3に示すように、単相3線式電路15は二本の電圧線15X,15Yと一本の中性線15Nとを備え、電圧線15X,15Y上に線路電流を検出する電流センサ16が設けられている。電子回路基板13には、電流センサ16の出力を数値化する電流検出回路17と、電流検出回路17の出力を監視するCPU18と、CPU18の動作電圧を主接点9より一次側(電源側)の電圧線15X,15Yから取得する制御電源回路19とが設けられている。制御電源回路19は、内部に異常が発生したときに、ヒューズ20を溶断し、CPU18等への電源の供給を停止するように構成されている。   As shown in FIG. 3, the single-phase three-wire electric circuit 15 includes two voltage lines 15X and 15Y and one neutral line 15N, and a current sensor 16 that detects a line current on the voltage lines 15X and 15Y. Is provided. The electronic circuit board 13 includes a current detection circuit 17 that digitizes the output of the current sensor 16, a CPU 18 that monitors the output of the current detection circuit 17, and the operating voltage of the CPU 18 on the primary side (power supply side) from the main contact 9. A control power supply circuit 19 that is obtained from the voltage lines 15X and 15Y is provided. The control power supply circuit 19 is configured to blow the fuse 20 and stop the supply of power to the CPU 18 or the like when an abnormality occurs inside.

また、電子回路基板13には、主接点9より二次側(負荷側)の電圧線15X,15Yから取得した電圧(200V)でトリップコイル10を駆動するトリップコイル駆動回路21と、CPU18の動作を監視するCPU監視回路22と、赤外線リモコンを含む外部操作機器との通信を制御する通信制御部23と、外部のプログラム書込み装置が接続されるプログラム書込み接続部25と、プログラム書込みスイッチ26とが配設されている。CPU18は制御プログラムを記憶するフラッシュROM24を備えている。ROM24に制御プログラムを書き込むときには、書込みスイッチ26をプログラム書込み接続部25側に操作し(図3参照)、監視回路22の動作がCPU18に影響しないように、監視回路22が出力したリセット信号を遮断する。こうすれば、監視回路22の動作が無効となるので、制御プログラムをROM24に容易に書き込むことができる。書込み作業が終了したときには、スイッチ26を監視回路22と駆動回路21との接続点32側に操作し(図4参照)、リセット信号をCPU18に伝送できる状態に戻しておく。   The electronic circuit board 13 has a trip coil drive circuit 21 that drives the trip coil 10 with a voltage (200 V) acquired from the voltage lines 15X and 15Y on the secondary side (load side) from the main contact 9, and the operation of the CPU 18 A CPU monitoring circuit 22 that monitors the communication, a communication control unit 23 that controls communication with an external operation device including an infrared remote controller, a program write connection unit 25 to which an external program writing device is connected, and a program write switch 26. It is arranged. The CPU 18 includes a flash ROM 24 that stores a control program. When the control program is written in the ROM 24, the write switch 26 is operated to the program write connection unit 25 side (see FIG. 3), and the reset signal output from the monitoring circuit 22 is cut off so that the operation of the monitoring circuit 22 does not affect the CPU 18. To do. By doing so, the operation of the monitoring circuit 22 becomes invalid, and the control program can be easily written in the ROM 24. When the writing operation is completed, the switch 26 is operated to the connection point 32 side between the monitoring circuit 22 and the drive circuit 21 (see FIG. 4), and the reset signal is returned to a state where it can be transmitted to the CPU 18.

図4に示すように、トリップコイル駆動回路21は、トリップコイル10を駆動するサイリスタSCRと、サイリスタSCRのゲートGに定電圧を印加するツェナーダイオードZDと、コンデンサCおよび抵抗RからなるCR遅延回路27と、CPU18の二つのデジタル出力端子P1,P2から出力された操作信号を受け取るD−FF(Dフリップフロップ)28と、D−FF28とサイリスタSCRを電気的に絶縁した状態でD−FF28の出力信号を中継するフォトカプラ29とが設けられている。フォトカプラ29は発光部29aと受光部29bとを備え、発光部29aの動作電圧が制御電源回路19(図3参照)から供給される。   As shown in FIG. 4, the trip coil drive circuit 21 includes a thyristor SCR that drives the trip coil 10, a Zener diode ZD that applies a constant voltage to the gate G of the thyristor SCR, a CR delay circuit that includes a capacitor C and a resistor R. 27, a D-FF (D flip-flop) 28 that receives operation signals output from the two digital output terminals P1 and P2 of the CPU 18, and the D-FF 28 and the thyristor SCR are electrically insulated from each other. A photocoupler 29 that relays the output signal is provided. The photocoupler 29 includes a light emitting unit 29a and a light receiving unit 29b, and the operating voltage of the light emitting unit 29a is supplied from the control power supply circuit 19 (see FIG. 3).

CPU監視回路22はWDT−IC(ウオッチドッグタイマIC)30を備え、CPU18がもう一つのデジタル出力端子P3からWDT−IC30のWD端子にクロックパルスCP(図5参照)を定期的に出力する。WDT−IC30のRST端子はD−FF28のCLK端子に接続されるとともに、書込みスイッチ26を介してCPU18のリセット端子に接続され、Tc端子が抵抗RとコンデンサCとに接続されている。WDT−IC30は、抵抗RとコンデンサCとで決まる時間中にクロックパルスCPがWD端子に与えられないときに、CPU18のクロックパルスCPが途絶えたと判断し、リセット信号をRST端子からCPU18とD−FF28とに出力する。そして、リセット信号に応答し、CPU18が制御プログラムのメインルーチンを実行して初期化作業を行うとともに、D−FF28がフォトカプラ29をOFFしてトリップコイル10を駆動するように構成されている。   The CPU monitoring circuit 22 includes a WDT-IC (watchdog timer IC) 30, and the CPU 18 periodically outputs a clock pulse CP (see FIG. 5) from the other digital output terminal P3 to the WD terminal of the WDT-IC 30. The RST terminal of the WDT-IC 30 is connected to the CLK terminal of the D-FF 28, is connected to the reset terminal of the CPU 18 through the write switch 26, and the Tc terminal is connected to the resistor R and the capacitor C. The WDT-IC 30 determines that the clock pulse CP of the CPU 18 has been interrupted when the clock pulse CP is not applied to the WD terminal during the time determined by the resistor R and the capacitor C, and sends a reset signal from the RST terminal to the CPU 18 and the D−. Output to FF28. In response to the reset signal, the CPU 18 executes the main routine of the control program to perform initialization work, and the D-FF 28 turns off the photocoupler 29 and drives the trip coil 10.

次に、上記のように構成された電子式ブレーカ1の動作について説明する。図5に示すように、CPU18が正常に動作しているときには、制御プログラムのメインルーチンでクロックパルスCPが出力端子P3からWDT−IC30のWD端子に定期的に出力される。このとき、Tc端子の電圧レベルはクロックパルスCPによりリセット信号の出力ライン(RST端子のLレベル)よりも低く抑えられ、RST端子がHレベルを維持し、リセット信号を出力しない。そして、電路15に正常な電流が流れている状態で、CPU18が出力端子P1,P2から操作パルスをD−FF28のCLR端子とPRE端子とに出力し、両方の端子を共にHレベルに維持し、Q端子をLレベルに保つ。これにより、フォトカプラ29がONし、サイリスタSCRがターンオフし、トリップコイル10が消磁し、主接点9が閉じた状態に保持される。   Next, the operation of the electronic breaker 1 configured as described above will be described. As shown in FIG. 5, when the CPU 18 is operating normally, the clock pulse CP is periodically output from the output terminal P3 to the WD terminal of the WDT-IC 30 in the main routine of the control program. At this time, the voltage level of the Tc terminal is suppressed to be lower than the output line of the reset signal (L level of the RST terminal) by the clock pulse CP, the RST terminal maintains the H level, and no reset signal is output. Then, in a state where a normal current is flowing through the electric circuit 15, the CPU 18 outputs an operation pulse from the output terminals P1 and P2 to the CLR terminal and the PRE terminal of the D-FF 28, and both the terminals are maintained at the H level. , Q terminal is kept at L level. As a result, the photocoupler 29 is turned on, the thyristor SCR is turned off, the trip coil 10 is demagnetized, and the main contact 9 is held closed.

図6に示すように、電路15に過電流が流れたときには、CPU18が出力端子P2側の操作パルスを停止し、D−FF28のPRE端子がH→Lレベルに切り替わり、Q端子がL→Hレベルに変化し、フォトカプラ29がOFFする。これにより、ツェナーダイオードZDの基準電圧がサイリスタSCRのゲートGに印加され、CR遅延回路27の設定時間(CR遅延時間)が経過した後にサイリスタSCRがターンオンし、トリップコイル10が主接点9を開く。そして、線路電流が消滅すると、CPU18が出力端子P1側の操作パルスを一時的に停止し、D−FF28のCLR端子をH→L→Hレベルに切り替え、CLR端子とPRE端子を共にHレベルに保った状態で、ハンドル5による主接点9の閉成操作を待つ。なお、CR遅延時間はCPU18の初期化に要する時間(図8参照)よりも長い値で設定されている   As shown in FIG. 6, when an overcurrent flows through the electric circuit 15, the CPU 18 stops the operation pulse on the output terminal P2, the PRE terminal of the D-FF 28 switches from H to L level, and the Q terminal changes from L to H. The level changes and the photocoupler 29 is turned off. As a result, the reference voltage of the Zener diode ZD is applied to the gate G of the thyristor SCR, the thyristor SCR is turned on after the set time (CR delay time) of the CR delay circuit 27 has elapsed, and the trip coil 10 opens the main contact 9. . When the line current disappears, the CPU 18 temporarily stops the operation pulse on the output terminal P1, switches the CLR terminal of the D-FF 28 from H → L → H level, and sets both the CLR terminal and the PRE terminal to H level. In this state, it waits for the closing operation of the main contact 9 by the handle 5. The CR delay time is set to a value longer than the time required for initialization of the CPU 18 (see FIG. 8).

図7に示すように、CPU18が暴走し、クロックパルスCPが途絶えたときには、WDT−IC30において、Tc端子の電圧レベルがリセット信号の出力ラインまで上昇し、RST端子がH→Lレベルに切り替わり、リセット信号がRST端子から書込みスイッチ26を介してCPU18に出力される。そして、Tc端子の電圧レベルがリセット信号の停止ライン(0V)まで下降すると、RST端子がL→Hレベルに切り替わり、D−FF28のQ端子がL→Hレベルに変化し、フォトカプラ29がOFFする。この間、CPU18はリセット信号に応答して制御プログラムを再起動し、メインルーチンを実行してD−FF28をリセットする。   As shown in FIG. 7, when the CPU 18 runs away and the clock pulse CP stops, the voltage level of the Tc terminal rises to the output line of the reset signal in the WDT-IC 30, and the RST terminal is switched from the H level to the L level. A reset signal is output from the RST terminal to the CPU 18 via the write switch 26. When the voltage level of the Tc terminal falls to the reset signal stop line (0 V), the RST terminal is switched from L to H level, the Q terminal of the D-FF 28 is changed from L to H level, and the photocoupler 29 is turned off. To do. During this time, the CPU 18 restarts the control program in response to the reset signal, executes the main routine, and resets the D-FF 28.

ここで、CPU18がメインルーチンを実行できないときには、D−FF28がリセットされず、Q端子がHレベルを維持し、フォトカプラ29がOFF状態を継続する。このため、サイリスタSCRがCR遅延時間の経過後にターンオンし、トリップコイル10が励磁し、主接点9が開放される。したがって、WDT−IC30のリセット信号でCPU18を初期化できないときに、トリップコイル10で電路15を遮断し、CPU18の暴走に伴う二次被害を未然に防止できる。また、施工者が制御プログラムを書き込んだ後に、書込みスイッチ26を閉じ忘れてリセット信号の遮断位置(図3に示す位置)に放置していた場合は、リセット信号がCPU18に伝送されず、D−FF28のCLK端子に入力され、Q端子がL→Hレベルに切り替わり、フォトカプラ29がOFFする。このため、スイッチ26を戻し忘れていた場合でも、トリップコイル10を駆動して、主接点9を確実に開くことができる。   Here, when the CPU 18 cannot execute the main routine, the D-FF 28 is not reset, the Q terminal maintains the H level, and the photocoupler 29 continues to be in the OFF state. For this reason, the thyristor SCR is turned on after the lapse of the CR delay time, the trip coil 10 is excited, and the main contact 9 is opened. Therefore, when the CPU 18 cannot be initialized by the reset signal of the WDT-IC 30, the trip coil 10 cuts off the electric circuit 15 and can prevent secondary damage caused by the runaway of the CPU 18. Also, if the installer forgets to close the write switch 26 after writing the control program and leaves it at the reset signal blocking position (position shown in FIG. 3), the reset signal is not transmitted to the CPU 18, and the D- The signal is input to the CLK terminal of the FF 28, the Q terminal is switched from L to H level, and the photocoupler 29 is turned OFF. For this reason, even if the switch 26 is forgotten to be returned, the trip coil 10 can be driven to open the main contact 9 reliably.

図8に示すように、CPU18が初期化を実行できたときには、クロックパルスCPが立ち上がり、CPU18が正常な状態に復旧する。CPU18が復旧すると、WDT−IC30のTc端子の電圧レベルが上昇し、D−FF28のCLR端子がH→Lレベルに変化し、Q端子がH→Lレベルに切り替わり、D−FF28がリセットされ、フォトカプラ22がONする。このとき、駆動回路21のCR遅延回路27にCPU18の初期化に要する時間よりも長いCR遅延時間が設定されているため、サイリスタSCRのゲート電圧が上昇する前にフォトカプラ29がONし、サイリスタSCRはターンオンしない。したがって、CPU18の初期化中に主接点9をむやみに開くことなく、CPU18を自動的に復旧することができる。   As shown in FIG. 8, when the CPU 18 can execute initialization, the clock pulse CP rises and the CPU 18 is restored to a normal state. When the CPU 18 recovers, the voltage level of the Tc terminal of the WDT-IC 30 increases, the CLR terminal of the D-FF 28 changes from H to L level, the Q terminal switches from H to L level, the D-FF 28 is reset, The photocoupler 22 is turned on. At this time, since the CR delay time longer than the time required for initialization of the CPU 18 is set in the CR delay circuit 27 of the drive circuit 21, the photocoupler 29 is turned on before the gate voltage of the thyristor SCR rises, and the thyristor The SCR does not turn on. Therefore, the CPU 18 can be automatically recovered without unnecessarily opening the main contact 9 during initialization of the CPU 18.

また、CPU18を人為的に暴走状態とすることで、プログラム書込みスイッチ26の操作位置を容易に確認することができる。すなわち、CPU18のクロックパルスを意図的に停止し、WDT−IC30にリセット信号を出力させ、リセット信号に対するトリップコイル10の応答を確認する。施工者が書込みスイッチ26を閉じ忘れていた場合は、リセット信号がCPU18に伝送されず、図7に示すように、サイリスタSCRがターンオンしてトリップコイル10を駆動するので、施工者はハンドル5の突出状態を見て、スイッチ26の閉じ忘れを確認できる。書込みスイッチ26がリセット信号の伝送位置(図4に示す位置)に正しく閉じられていた場合は、リセット信号がCPU18に伝送され、図8に示すように、サイリスタSCRがターンオフしてトリップコイル10を駆動しないので、施工者はハンドル5の平伏状態を見て、スイッチ26の正規位置を確認できる。   Moreover, the operation position of the program write switch 26 can be easily confirmed by manually setting the CPU 18 in a runaway state. That is, the CPU 18 intentionally stops the clock pulse, causes the WDT-IC 30 to output a reset signal, and confirms the response of the trip coil 10 to the reset signal. If the installer forgets to close the writing switch 26, the reset signal is not transmitted to the CPU 18, and the thyristor SCR is turned on to drive the trip coil 10 as shown in FIG. By looking at the protruding state, it can be confirmed that the switch 26 has been forgotten to be closed. When the write switch 26 is correctly closed at the reset signal transmission position (the position shown in FIG. 4), the reset signal is transmitted to the CPU 18, and the thyristor SCR is turned off as shown in FIG. Since it is not driven, the builder can check the normal position of the switch 26 by looking at the flat state of the handle 5.

なお、本発明は上記実施例に限定されるものではなく、以下に例示するように、本発明の趣旨を逸脱しない範囲で、各部の構成や形状を任意に変更して実施することも可能である。
(イ)CPU18が暴走したときに、監視回路22の出力に応答し、駆動回路21がトリップコイル10を直ちに駆動するように構成すること。
(ロ)制御プログラムを記憶するメモリをCPU18の外部に設置すること。
(ハ)CPU監視回路22を単相2線式電路や3相3線式電路用の電子式ブレーカに適用すること。
Note that the present invention is not limited to the above-described embodiments, and can be implemented by arbitrarily changing the configuration and shape of each part without departing from the spirit of the present invention, as exemplified below. is there.
(A) When the CPU 18 runs out of control, the drive circuit 21 is configured to immediately drive the trip coil 10 in response to the output of the monitoring circuit 22.
(B) A memory for storing the control program is installed outside the CPU 18.
(C) The CPU monitoring circuit 22 is applied to an electronic breaker for a single-phase two-wire circuit or a three-phase three-wire circuit.

本発明の一実施形態を示す電子式ブレーカの正面図である。It is a front view of the electronic breaker which shows one Embodiment of this invention. 電子式ブレーカの内部機構を示す斜視図である。It is a perspective view which shows the internal mechanism of an electronic breaker. 電子式ブレーカの制御回路を示すブロック図である。It is a block diagram which shows the control circuit of an electronic breaker. CPU監視回路とトリップコイル駆動回路を詳細に示す回路図である。It is a circuit diagram which shows a CPU monitoring circuit and a trip coil drive circuit in detail. CPU正常時の動作を示すタイムチャートである。It is a time chart which shows operation | movement at the time of normal CPU. 過電流発生時の動作を示すタイムチャートである。It is a time chart which shows the operation | movement at the time of overcurrent generation | occurrence | production. CPU暴走時の動作を示すタイムチャートである。It is a time chart which shows operation | movement at the time of CPU runaway. CPU復旧時の動作を示すタイムチャートである。It is a time chart which shows operation | movement at the time of CPU recovery.

符号の説明Explanation of symbols

1 電子式ブレーカ
9 主接点
10 トリップコイル
15 単相3線式電路
16 電流センサ
18 CPU
21 トリップコイル駆動回路
22 CPU監視回路
24 フラッシュROM
26 プログラム書込みスイッチ
27 CR遅延回路
1 Electronic breaker 9 Main contact 10 Trip coil 15 Single-phase 3-wire circuit 16 Current sensor 18 CPU
21 Trip coil drive circuit 22 CPU monitoring circuit 24 Flash ROM
26 Program Write Switch 27 CR Delay Circuit

Claims (3)

電路に流れる電流を電流センサで検出し、電流センサの出力が閾値を超えたときに、CPUの制御によりトリップコイルを駆動して主接点を開く電子式ブレーカにおいて、
CPUが出力する定期パルスに基づいてCPUの動作を監視する監視回路と、定期パルスが途絶えたときの監視回路の出力に応答してトリップコイルを駆動する駆動回路と備えたことを特徴とする電子式ブレーカ。
In an electronic breaker that detects the current flowing in the electric circuit with a current sensor and drives the trip coil under the control of the CPU to open the main contact when the output of the current sensor exceeds a threshold value.
An electronic circuit comprising: a monitoring circuit that monitors the operation of the CPU based on a periodic pulse output by the CPU; and a drive circuit that drives a trip coil in response to the output of the monitoring circuit when the periodic pulse stops. Formula breaker.
前記定期パルスが途絶えたときに、監視回路がCPUを初期化するためのリセット信号を出力し、駆動回路がCPUの初期化に要する時間よりも長い時間が経過した後にトリップコイルを駆動することを特徴とする請求項1記載の電子式ブレーカ。   When the periodic pulse is interrupted, the monitoring circuit outputs a reset signal for initializing the CPU, and the driving circuit drives the trip coil after a time longer than the time required for initialization of the CPU has elapsed. The electronic breaker according to claim 1, characterized in that: 前記CPUの制御プログラムを記憶するメモリと、メモリに制御プログラムを書き込むときに前記リセット信号を遮断するスイッチとを備え、スイッチが遮断位置に操作されている状態で監視回路がリセット信号を出力したときに、駆動回路がトリップコイルを駆動することを特徴とする請求項2記載の電子式ブレーカ。   A memory for storing a control program for the CPU, and a switch for cutting off the reset signal when the control program is written to the memory, and the monitoring circuit outputs a reset signal in a state where the switch is operated at the shut-off position. 3. The electronic breaker according to claim 2, wherein the drive circuit drives the trip coil.
JP2008258815A 2008-10-03 2008-10-03 Electronic breaker Active JP5226450B2 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018216167A1 (en) * 2017-05-25 2018-11-29 三菱電機株式会社 Electronic circuit breaker
CN112147498A (en) * 2020-09-23 2020-12-29 广州市扬新技术研究有限责任公司 Module for monitoring and controlling direct current breaker

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05250978A (en) * 1992-03-03 1993-09-28 Mitsubishi Electric Corp Circuit breaker

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05250978A (en) * 1992-03-03 1993-09-28 Mitsubishi Electric Corp Circuit breaker

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018216167A1 (en) * 2017-05-25 2018-11-29 三菱電機株式会社 Electronic circuit breaker
CN112147498A (en) * 2020-09-23 2020-12-29 广州市扬新技术研究有限责任公司 Module for monitoring and controlling direct current breaker

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