JP2010092623A - Electronic breaker - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent secondary damage caused by runaway of a CPU by assuring fail-safe of the CPU in an electronic breaker. <P>SOLUTION: A CPU monitoring circuit 22 monitors the operation of the CPU 18 based on a periodical pulse output by the CPU 18. When the CPU 18 runs away, and the periodical pulse stops, the monitoring circuit 22 outputs a reset signal to the CPU 18 and a trip coil driving circuit 21. The CPU 18 responds to the reset signal to initialize it, and when it can not be initialized, a drive circuit 21 drives a trip coil 10 to open a main contact 9. When the control program of the CPU 18 is written in a flush ROM 24, a switch 26 is opened to interrupt the reset signal from the monitoring circuit 22 to the CPU 18. The monitoring circuit 22 is made to output the reset signal, and the response of the trip coil 10 to the reset signal is observed to confirm return failure of the switch 26. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an electronic breaker that opens a main contact by driving a trip coil under the control of a CPU when an overcurrent flows in an electric circuit.

  2. Description of the Related Art Conventionally, an electronic breaker that detects a current flowing in an electric circuit with a current sensor and drives a trip coil under the control of a CPU to open a main contact when an output of the current sensor exceeds a threshold value is known. According to the CPU control, in addition to the shut-off function, a display function, a communication function, and the like can be easily provided, and there is an advantage that the functionality and mobility of the breaker can be improved.

For example, Patent Document 1 describes a technique in which a rated current recorded in a storage medium is read by a CPU and registered in an internal memory of a breaker. Patent Document 2 describes a technology in which wireless communication between a breaker and an external operation device is controlled by a CPU, and the rated current is switched by the external operation device via wireless communication.
JP 2008-79412 A JP 2008-78007 A

  However, the conventional electronic breaker has not ensured failsafe of the CPU. For this reason, when the CPU runs away due to external noise or lightning surge, it becomes impossible to monitor the current flowing in the electric circuit, which may cause a failure in the interruption function and cause secondary damage.

  Therefore, an object of the present invention is to provide an electronic breaker that can ensure fail-safe CPU and prevent secondary damage during runaway.

  In order to solve the above-described problems, the present invention detects an electric current flowing in an electric circuit with a current sensor, and when the output of the current sensor exceeds a threshold value, the trip coil is driven under the control of the CPU to open the main contact. The type breaker is characterized by adopting the following means.

(1) A monitoring circuit that monitors the operation of the CPU based on a periodic pulse output from the CPU, and a drive circuit that drives the trip coil in response to the output of the monitoring circuit when the periodic pulse is interrupted. Electronic breaker.

(2) When the periodic pulse is interrupted, the monitoring circuit outputs a reset signal for initializing the CPU, and the drive circuit drives the trip coil after a time longer than the time required for initialization of the CPU has elapsed. This is an electronic breaker.

(3) A memory for storing a control program for the CPU and a switch for shutting off the reset signal when the control program is written to the memory are provided, and the monitoring circuit outputs the reset signal while the switch is operated at the shut-off position. An electronic breaker characterized in that the drive circuit drives the trip coil.

  According to the electronic breaker of the above (1), the monitoring circuit is linked with the drive circuit to ensure the fail safe of the CPU, so that it is possible to prevent secondary damage accompanying the runaway of the CPU.

  According to the electronic breaker of (2), there is an effect that the CPU can be automatically restored without initializing the main contact during initialization, by initializing the CPU with the reset signal output from the monitoring circuit.

  According to the electronic breaker of (3) above, the CPU control program can be written into the memory while the switch is operated to the shut-off position, and when the switch is forgotten to return from the shut-off position, the trip coil is driven by the drive circuit. In addition, it is possible to easily check forgetting to return the switch based on the response of the trip coil to the artificial reset signal.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows the external appearance of an electronic breaker for a single-phase three-wire circuit, and FIG. 2 shows the internal mechanism of the casing. FIG. 3 shows the control circuit of the electronic breaker, and FIG. 4 shows the CPU monitoring circuit and trip coil drive circuit in the control circuit in detail. 5 to 8 show the linking operation of the monitoring circuit and the drive circuit, FIG. 5 shows the state when the CPU is normal, FIG. 6 shows the state when an overcurrent occurs, FIG. 7 shows the state when the CPU is out of control, and FIG.

  As shown in FIG. 1, the electronic breaker 1 of this embodiment includes three power-side terminals 3 at the upper end portion of the casing 2 and three load-side terminals 4 at the lower end portion. On the front surface of the casing 2 are a handle 5 for manually opening and closing a single-phase three-wire electric circuit, a display unit 6 for displaying the rated current and operating state of the breaker 1, a hand switch 7 for switching the display and operating mode, and a personal computer. And a LAN wiring connection port 8 connected to an external operation device such as a portable terminal.

  As shown in FIG. 2, the casing 2 includes a trip coil 10 that opens the main contact 9 when an overcurrent flows through the electric circuit 15 (see FIG. 3), and a main circuit when a short-circuit current flows through the electric circuit 15. An instantaneous interruption mechanism 11 that instantaneously opens the contact 9 and an opening / closing mechanism 12 that transmits the power of the trip coil 10 and the instantaneous interruption mechanism 11 to the main contact 9 are installed. An electronic circuit board 13 is attached to the back surface of the casing 2, and an electronic control circuit for controlling the display unit 6, trip coil 10, and the like is provided on the board 13.

  As shown in FIG. 3, the single-phase three-wire electric circuit 15 includes two voltage lines 15X and 15Y and one neutral line 15N, and a current sensor 16 that detects a line current on the voltage lines 15X and 15Y. Is provided. The electronic circuit board 13 includes a current detection circuit 17 that digitizes the output of the current sensor 16, a CPU 18 that monitors the output of the current detection circuit 17, and the operating voltage of the CPU 18 on the primary side (power supply side) from the main contact 9. A control power supply circuit 19 that is obtained from the voltage lines 15X and 15Y is provided. The control power supply circuit 19 is configured to blow the fuse 20 and stop the supply of power to the CPU 18 or the like when an abnormality occurs inside.

  The electronic circuit board 13 has a trip coil drive circuit 21 that drives the trip coil 10 with a voltage (200 V) acquired from the voltage lines 15X and 15Y on the secondary side (load side) from the main contact 9, and the operation of the CPU 18 A CPU monitoring circuit 22 that monitors the communication, a communication control unit 23 that controls communication with an external operation device including an infrared remote controller, a program write connection unit 25 to which an external program writing device is connected, and a program write switch 26. It is arranged. The CPU 18 includes a flash ROM 24 that stores a control program. When the control program is written in the ROM 24, the write switch 26 is operated to the program write connection unit 25 side (see FIG. 3), and the reset signal output from the monitoring circuit 22 is cut off so that the operation of the monitoring circuit 22 does not affect the CPU 18. To do. By doing so, the operation of the monitoring circuit 22 becomes invalid, and the control program can be easily written in the ROM 24. When the writing operation is completed, the switch 26 is operated to the connection point 32 side between the monitoring circuit 22 and the drive circuit 21 (see FIG. 4), and the reset signal is returned to a state where it can be transmitted to the CPU 18.

  As shown in FIG. 4, the trip coil drive circuit 21 includes a thyristor SCR that drives the trip coil 10, a Zener diode ZD that applies a constant voltage to the gate G of the thyristor SCR, a CR delay circuit that includes a capacitor C and a resistor R. 27, a D-FF (D flip-flop) 28 that receives operation signals output from the two digital output terminals P1 and P2 of the CPU 18, and the D-FF 28 and the thyristor SCR are electrically insulated from each other. A photocoupler 29 that relays the output signal is provided. The photocoupler 29 includes a light emitting unit 29a and a light receiving unit 29b, and the operating voltage of the light emitting unit 29a is supplied from the control power supply circuit 19 (see FIG. 3).

  The CPU monitoring circuit 22 includes a WDT-IC (watchdog timer IC) 30, and the CPU 18 periodically outputs a clock pulse CP (see FIG. 5) from the other digital output terminal P3 to the WD terminal of the WDT-IC 30. The RST terminal of the WDT-IC 30 is connected to the CLK terminal of the D-FF 28, is connected to the reset terminal of the CPU 18 through the write switch 26, and the Tc terminal is connected to the resistor R and the capacitor C. The WDT-IC 30 determines that the clock pulse CP of the CPU 18 has been interrupted when the clock pulse CP is not applied to the WD terminal during the time determined by the resistor R and the capacitor C, and sends a reset signal from the RST terminal to the CPU 18 and the D−. Output to FF28. In response to the reset signal, the CPU 18 executes the main routine of the control program to perform initialization work, and the D-FF 28 turns off the photocoupler 29 and drives the trip coil 10.

  Next, the operation of the electronic breaker 1 configured as described above will be described. As shown in FIG. 5, when the CPU 18 is operating normally, the clock pulse CP is periodically output from the output terminal P3 to the WD terminal of the WDT-IC 30 in the main routine of the control program. At this time, the voltage level of the Tc terminal is suppressed to be lower than the output line of the reset signal (L level of the RST terminal) by the clock pulse CP, the RST terminal maintains the H level, and no reset signal is output. Then, in a state where a normal current is flowing through the electric circuit 15, the CPU 18 outputs an operation pulse from the output terminals P1 and P2 to the CLR terminal and the PRE terminal of the D-FF 28, and both the terminals are maintained at the H level. , Q terminal is kept at L level. As a result, the photocoupler 29 is turned on, the thyristor SCR is turned off, the trip coil 10 is demagnetized, and the main contact 9 is held closed.

  As shown in FIG. 6, when an overcurrent flows through the electric circuit 15, the CPU 18 stops the operation pulse on the output terminal P2, the PRE terminal of the D-FF 28 switches from H to L level, and the Q terminal changes from L to H. The level changes and the photocoupler 29 is turned off. As a result, the reference voltage of the Zener diode ZD is applied to the gate G of the thyristor SCR, the thyristor SCR is turned on after the set time (CR delay time) of the CR delay circuit 27 has elapsed, and the trip coil 10 opens the main contact 9. . When the line current disappears, the CPU 18 temporarily stops the operation pulse on the output terminal P1, switches the CLR terminal of the D-FF 28 from H → L → H level, and sets both the CLR terminal and the PRE terminal to H level. In this state, it waits for the closing operation of the main contact 9 by the handle 5. The CR delay time is set to a value longer than the time required for initialization of the CPU 18 (see FIG. 8).

  As shown in FIG. 7, when the CPU 18 runs away and the clock pulse CP stops, the voltage level of the Tc terminal rises to the output line of the reset signal in the WDT-IC 30, and the RST terminal is switched from the H level to the L level. A reset signal is output from the RST terminal to the CPU 18 via the write switch 26. When the voltage level of the Tc terminal falls to the reset signal stop line (0 V), the RST terminal is switched from L to H level, the Q terminal of the D-FF 28 is changed from L to H level, and the photocoupler 29 is turned off. To do. During this time, the CPU 18 restarts the control program in response to the reset signal, executes the main routine, and resets the D-FF 28.

  Here, when the CPU 18 cannot execute the main routine, the D-FF 28 is not reset, the Q terminal maintains the H level, and the photocoupler 29 continues to be in the OFF state. For this reason, the thyristor SCR is turned on after the lapse of the CR delay time, the trip coil 10 is excited, and the main contact 9 is opened. Therefore, when the CPU 18 cannot be initialized by the reset signal of the WDT-IC 30, the trip coil 10 cuts off the electric circuit 15 and can prevent secondary damage caused by the runaway of the CPU 18. Also, if the installer forgets to close the write switch 26 after writing the control program and leaves it at the reset signal blocking position (position shown in FIG. 3), the reset signal is not transmitted to the CPU 18, and the D- The signal is input to the CLK terminal of the FF 28, the Q terminal is switched from L to H level, and the photocoupler 29 is turned OFF. For this reason, even if the switch 26 is forgotten to be returned, the trip coil 10 can be driven to open the main contact 9 reliably.

  As shown in FIG. 8, when the CPU 18 can execute initialization, the clock pulse CP rises and the CPU 18 is restored to a normal state. When the CPU 18 recovers, the voltage level of the Tc terminal of the WDT-IC 30 increases, the CLR terminal of the D-FF 28 changes from H to L level, the Q terminal switches from H to L level, the D-FF 28 is reset, The photocoupler 22 is turned on. At this time, since the CR delay time longer than the time required for initialization of the CPU 18 is set in the CR delay circuit 27 of the drive circuit 21, the photocoupler 29 is turned on before the gate voltage of the thyristor SCR rises, and the thyristor The SCR does not turn on. Therefore, the CPU 18 can be automatically recovered without unnecessarily opening the main contact 9 during initialization of the CPU 18.

  Moreover, the operation position of the program write switch 26 can be easily confirmed by manually setting the CPU 18 in a runaway state. That is, the CPU 18 intentionally stops the clock pulse, causes the WDT-IC 30 to output a reset signal, and confirms the response of the trip coil 10 to the reset signal. If the installer forgets to close the writing switch 26, the reset signal is not transmitted to the CPU 18, and the thyristor SCR is turned on to drive the trip coil 10 as shown in FIG. By looking at the protruding state, it can be confirmed that the switch 26 has been forgotten to be closed. When the write switch 26 is correctly closed at the reset signal transmission position (the position shown in FIG. 4), the reset signal is transmitted to the CPU 18, and the thyristor SCR is turned off as shown in FIG. Since it is not driven, the builder can check the normal position of the switch 26 by looking at the flat state of the handle 5.

Note that the present invention is not limited to the above-described embodiments, and can be implemented by arbitrarily changing the configuration and shape of each part without departing from the spirit of the present invention, as exemplified below. is there.
(A) When the CPU 18 runs out of control, the drive circuit 21 is configured to immediately drive the trip coil 10 in response to the output of the monitoring circuit 22.
(B) A memory for storing the control program is installed outside the CPU 18.
(C) The CPU monitoring circuit 22 is applied to an electronic breaker for a single-phase two-wire circuit or a three-phase three-wire circuit.

It is a front view of the electronic breaker which shows one Embodiment of this invention. It is a perspective view which shows the internal mechanism of an electronic breaker. It is a block diagram which shows the control circuit of an electronic breaker. It is a circuit diagram which shows a CPU monitoring circuit and a trip coil drive circuit in detail. It is a time chart which shows operation | movement at the time of normal CPU. It is a time chart which shows the operation | movement at the time of overcurrent generation | occurrence | production. It is a time chart which shows operation | movement at the time of CPU runaway. It is a time chart which shows operation | movement at the time of CPU recovery.

Explanation of symbols

1 Electronic breaker 9 Main contact 10 Trip coil 15 Single-phase 3-wire circuit 16 Current sensor 18 CPU
21 Trip coil drive circuit 22 CPU monitoring circuit 24 Flash ROM
26 Program Write Switch 27 CR Delay Circuit

Claims (3)

In an electronic breaker that detects the current flowing in the electric circuit with a current sensor and drives the trip coil under the control of the CPU to open the main contact when the output of the current sensor exceeds a threshold value.
An electronic circuit comprising: a monitoring circuit that monitors the operation of the CPU based on a periodic pulse output by the CPU; and a drive circuit that drives a trip coil in response to the output of the monitoring circuit when the periodic pulse stops. Formula breaker.   When the periodic pulse is interrupted, the monitoring circuit outputs a reset signal for initializing the CPU, and the driving circuit drives the trip coil after a time longer than the time required for initialization of the CPU has elapsed. The electronic breaker according to claim 1, characterized in that:   A memory for storing a control program for the CPU, and a switch for cutting off the reset signal when the control program is written to the memory, and the monitoring circuit outputs a reset signal in a state where the switch is operated at the shut-off position. 3. The electronic breaker according to claim 2, wherein the drive circuit drives the trip coil.

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