JP2010091837A - Plasma display device, and method of driving plasma display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a high quality image display by generating a stable write discharge. <P>SOLUTION: A plasma display device 1 includes: a plasma display panel 10; a scanning electrode driving circuit 43 for generating a scanning pulse in a writing period to scan a scanning electrode; and a partial lighting ratio detection circuit 47 for detecting a ratio of the number of discharge cells to be lighted to the number of discharge cells in each of the areas every subfield as a partial lighting ratio, by dividing a display area of the plasma display panel 10 into a plurality of areas. A correction value generation circuit 53 outputs a correction value based on an arrangement position of a heating element included in the plasma display device. The partial lighting ratio detection circuit 47 calculates a lighting ratio after correction by adding the correction value to the partial lighting ratio. The scanning electrode driving circuit 43 gives priority of scanning to an area having a higher lighting ratio after correction, which is calculated in the partial lighting ratio detection circuit 47. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a plasma display device and a plasma display panel driving method used for a wall-mounted television or a large monitor.

  A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front plate and a back plate arranged to face each other. In the front plate, a plurality of display electrode pairs each consisting of a pair of scan electrodes and sustain electrodes are formed in parallel with each other on the front glass substrate, and a dielectric layer and a protective layer are formed so as to cover the display electrode pairs. Yes. The back plate has a plurality of parallel data electrodes on the back glass substrate, a dielectric layer so as to cover them, and a plurality of barrier ribs in parallel with the data electrodes formed on the back glass substrate. A phosphor layer is formed on the side walls of the barrier ribs. Then, the front plate and the back plate are arranged opposite to each other so that the display electrode pair and the data electrode are three-dimensionally crossed and sealed, and a discharge gas containing, for example, 5% xenon is enclosed in the internal discharge space. Has been. Here, a discharge cell is formed at a portion where the display electrode pair and the data electrode face each other. In the panel having such a configuration, ultraviolet rays are generated by gas discharge in each discharge cell, and the phosphors of red (R), green (G) and blue (B) colors are excited and emitted by the ultraviolet rays, thereby performing color display. It is carried out.

  A subfield method is generally used as a method for driving the panel. In the subfield method, one field is divided into a plurality of subfields, and gradation display is performed by causing each discharge cell to emit light or not emit light in each subfield. Each subfield has an initialization period, an address period, and a sustain period.

  In the initialization period, an initialization waveform is applied to each scan electrode, and an initialization discharge is generated in each discharge cell. Thus, wall charges necessary for the subsequent address operation are formed in each discharge cell, and priming particles (excited particles for generating the address discharge) for stably generating the address discharge are generated.

  In the address period, a scan pulse is sequentially applied to the scan electrode (hereinafter, this operation is also referred to as “scan”), and an address pulse corresponding to an image signal to be displayed is selectively applied to the data electrode (hereinafter, referred to as “scan”). These operations are collectively referred to as “write”). Thereby, an address discharge is selectively generated between the scan electrode and the data electrode, and a wall charge is selectively formed.

  In the sustain period, a predetermined number of sustain pulses corresponding to the luminance to be displayed are alternately applied to the display electrode pair composed of the scan electrode and the sustain electrode. As a result, a sustain discharge is selectively generated in the discharge cell in which the wall charge is formed by the address discharge, and the discharge cell emits light. In this way, an image is displayed in the display area of the panel.

  In this subfield method, for example, an all-cell initializing operation for discharging all discharge cells is performed in an initializing period of one subfield among a plurality of subfields, and in an initializing period of another subfield. By performing the selective initialization operation for selectively performing the initializing discharge on the discharge cells that have undergone the sustain discharge, it is possible to reduce the light emission not related to the gradation display as much as possible and to improve the contrast ratio.

  On the other hand, in recent years, power consumption in a panel tends to increase with an increase in screen size and brightness. Further, in a panel with a large screen and high definition, the load at the time of driving the panel increases, so that the discharge tends to become unstable. In order to generate the discharge stably, the drive voltage applied to the electrode may be increased, but this contributes to further increasing the power consumption. Further, if the drive voltage is increased or the power consumption is increased to exceed the rated values of the components constituting the drive circuit, the circuit may malfunction.

For example, the data electrode driving circuit performs an address operation in which an address pulse voltage is applied to the data electrode to generate an address discharge in the discharge cell, but the power consumption at the time of writing is equal to the rated value of the IC constituting the data electrode driving circuit. If it exceeds the maximum value, the IC malfunctions, and there is a possibility that an address failure such as an address discharge not occurring in a discharge cell that should generate an address discharge or an address discharge occurring in a discharge cell that should not generate an address discharge may occur. Therefore, in order to suppress the power consumption at the time of writing, a method for predicting the power consumption of the data electrode driving circuit based on the image signal to be displayed and limiting the gradation when the predicted value exceeds a set value is disclosed. (For example, refer to Patent Document 1).
JP 2000-66638 A

  In the address period, as described above, the address discharge is generated by applying the scan pulse voltage to the scan electrode and applying the address pulse voltage to the data electrode. Therefore, it is difficult to perform stable writing only with the technology for stabilizing the operation of the data electrode driving circuit disclosed in Patent Document 1, and the operation in the circuit for driving the scanning electrode (scanning electrode driving circuit) is stabilized. The technology to plan is also important.

  In addition, since the scan pulse voltage is sequentially applied to the scan electrodes in the address period, the time spent in the address period becomes longer due to the increase in the number of scan electrodes, particularly in a high-definition panel. End up. Therefore, in the discharge cell in which the address is written at the end of the address period, the disappearance of the wall charge is increased and the address discharge is likely to be unstable compared to the discharge cell in which the address is written at the beginning of the address period. There was also.

  Also, the disappearance of wall charges depends on the temperature, and in the region heated by a member whose temperature is higher than that of the panel (hereinafter referred to as “heating element”), the wall charge disappears more than the other region. As a result, the address discharge tends to become unstable.

  The present invention has been made in view of these problems, and the scan pulse voltage (amplitude) necessary for generating a stable address discharge is increased even in a panel with a large screen and high definition. An object of the present invention is to provide a plasma display device and a panel driving method capable of preventing and generating stable address discharge and realizing high image display quality.

  The plasma display apparatus according to the present invention includes a plurality of subfields having an initialization period, an address period, and a sustain period in one field, sets a luminance weight for each subfield, and sets a number corresponding to the luminance weight in the sustain period. Driven by the subfield method of generating sustain pulses and displaying gray scales, a panel having a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode, and generating a scan pulse during an address period And a scanning electrode driving circuit for sequentially applying the scanning electrodes to scan the scanning electrodes, and dividing the display area of the panel into a plurality of areas, and the ratio of the number of discharge cells to be lit to the number of discharge cells in each of these areas And a partial lighting rate detection circuit that detects each partial field as a partial lighting rate, and the partial lighting rate detection circuit includes a panel having the above-described panel. Based on the arrangement position of the heating elements provided in the zuma display device, the corrected lighting rate is calculated by adding the correction value to the partial lighting rate, and the scan electrode driving circuit is subjected to the correction calculated in the partial lighting rate detection circuit. Scanning is performed first from a region with a high lighting rate.

  Thereby, the display area of the panel is divided into a plurality of areas, and the partial lighting rate in each area is detected, and the corrected lighting rate is added to the detected partial lighting rate based on the arrangement position of the heating element. Can be scanned first from an area with a high corrected lighting rate, so that a scan necessary for generating a stable address discharge in an area with a high partial lighting rate and an area heated by a heating element is possible. It is possible to prevent the pulse voltage (amplitude) from increasing and generate a stable address discharge.

  In the plasma display device, the partial lighting rate detection circuit adds a correction value having a magnitude corresponding to the amount of heating of the panel by the heating element to the partial lighting rate. As a result, the corrected lighting rate can be calculated by adding the correction value according to the arrangement position of the heating element and the heating amount by the heating element, so that stable address discharge can be performed in a region where the heating amount by the heating element is large. It is possible to prevent a scan pulse voltage (amplitude) required for generation from increasing and to generate stable address discharge.

  The plasma display device also includes a data electrode drive circuit having a data electrode drive IC that applies a write pulse to the data electrode in the write period, and the partial lighting rate detection circuit is corrected after the data electrode drive IC is used as the heating element. The structure which calculates a lighting rate may be sufficient. This prevents an increase in the scan pulse voltage (amplitude) necessary for generating a stable address discharge even in a region where a data electrode driving IC having a relatively large amount of heat is disposed, thereby stabilizing the address. It becomes possible to generate discharge.

  In addition, the plasma display device includes a power supply circuit that supplies power to each circuit included in the plasma display device, and the partial lighting rate detection circuit is configured to calculate the corrected lighting rate using the power supply circuit as a heating element. May be. This prevents a scan pulse voltage (amplitude) required for generating a stable address discharge from increasing even in a region where a power supply circuit having a relatively large amount of heat is disposed, thereby preventing a stable address discharge. Can be generated.

  Also, the panel driving method of the present invention provides a panel having a plurality of discharge cells each having a display electrode pair composed of a scan electrode and a sustain electrode, and a subfield having an initialization period, an address period, and a sustain period in one field. A plurality of sub-fields are provided with luminance weights, scanning pulses are generated in the address period and sequentially applied to the scanning electrodes to scan the scanning electrodes, and in the sustain period, the number of sustain pulses corresponding to the luminance weights is provided. Drive method of a panel driven by a subfield method for generating gradation and dividing the display area of the panel into a plurality of areas, and in each of these areas, the number of discharge cells to be lit with respect to the number of discharge cells The ratio of the illuminance is detected as a partial lighting rate for each subfield, and the plasma display device having the above-described panel is provided. Based on the placement position of the heat member, by adding the correction value to the partial light-emitting rate to calculate the corrected lighting rate, calculated corrected lighting rate and performing a previously scanned from a high region.

  Thereby, the display area of the panel is divided into a plurality of areas, and the partial lighting rate in each area is detected, and the corrected lighting rate is added to the detected partial lighting rate based on the arrangement position of the heating element. Can be scanned first from an area with a high corrected lighting rate, so that a scan necessary for generating a stable address discharge in an area with a high partial lighting rate and an area heated by a heating element is possible. It is possible to prevent the pulse voltage (amplitude) from increasing and generate a stable address discharge.

  According to the present invention, even in a panel with a large screen and high definition, a stable address discharge is generated by preventing an increase in scan pulse voltage (amplitude) necessary for generating a stable address discharge. Thus, it is possible to provide a plasma display device and a panel driving method capable of realizing high image display quality.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is an exploded perspective view showing the structure of panel 10 in accordance with the first exemplary embodiment of the present invention. On the front plate 21 made of glass, a plurality of display electrode pairs 24 each including a scanning electrode 22 and a sustain electrode 23 are formed. A dielectric layer 25 is formed so as to cover the scan electrode 22 and the sustain electrode 23, and a protective layer 26 is formed on the dielectric layer 25.

  The protective layer 26 has been used as a panel material in order to lower the discharge start voltage in the discharge cell, and has a large secondary electron emission coefficient and durability when neon (Ne) and xenon (Xe) gas is sealed. It is formed from a material mainly composed of MgO having excellent properties.

  A plurality of data electrodes 32 are formed on the back plate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. A phosphor layer 35 that emits light of each color of red (R), green (G), and blue (B) is provided on the side surface of the partition wall 34 and on the dielectric layer 33.

  The front plate 21 and the back plate 31 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 cross each other across a minute discharge space, and the outer periphery thereof is sealed with a sealing material such as glass frit. It is worn. A mixed gas of neon and xenon is sealed as a discharge gas in the internal discharge space. In the present embodiment, a discharge gas having a xenon partial pressure of about 10% is used in order to improve luminous efficiency. The discharge space is partitioned into a plurality of sections by partition walls 34, and discharge cells are formed at the intersections between the display electrode pairs 24 and the data electrodes 32. These discharge cells discharge and emit light to display an image.

  Note that the structure of the panel 10 is not limited to the above-described structure, and for example, the panel 10 may include a stripe-shaped partition wall. Further, the mixing ratio of the discharge gas is not limited to the above-described numerical values, and may be other mixing ratios.

  FIG. 2 is an electrode array diagram of panel 10 in accordance with the first exemplary embodiment of the present invention. The panel 10 includes n scan electrodes SC1 to SCn (scan electrodes 22 in FIG. 1) and n sustain electrodes SU1 to SUn (sustain electrodes 23 in FIG. 1) that are long in the row direction. M data electrodes D1 to Dm (data electrodes 32 in FIG. 1) that are long in the column direction are arranged. A discharge cell is formed at a portion where one pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects one data electrode Dj (j = 1 to m), and the discharge cell is in the discharge space. M × n are formed. A region where m × n discharge cells are formed becomes a display region of the panel 10.

  Next, a driving voltage waveform for driving the panel 10 and an outline of the operation will be described. Note that the plasma display device in this embodiment is a subfield method, that is, one field is divided into a plurality of subfields on the time axis, luminance weights are set for each subfield, and each discharge cell is set for each subfield. It is assumed that gradation display is performed by controlling light emission / non-light emission.

  In this subfield method, for example, one field is composed of eight subfields (first SF, second SF,..., Eighth SF), and each subfield is 1, 2, 4, 8, 16, 32, A configuration having luminance weights of 64 and 128 can be adopted. In addition, in the initializing period of one subfield among a plurality of subfields, an all-cell initializing operation for generating an initializing discharge in all discharge cells is performed (hereinafter, the subfield for performing the all-cell initializing operation is referred to as a subfield for performing all-cell initializing operations). In the initializing period of other subfields, a selective initializing operation for selectively generating initializing discharge is performed for the discharge cells that have undergone sustain discharge (hereinafter referred to as “all-cell initializing subfield”). The subfield that performs the selective initialization operation is referred to as “selective initialization subfield”), and it is possible to reduce light emission not related to gradation display as much as possible and improve the contrast ratio.

  In the present embodiment, the all-cell initialization operation is performed in the initialization period of the first SF, and the selective initialization operation is performed in the initialization period of the second SF to the eighth SF. As a result, the light emission not related to the image display is only the light emission due to the discharge of the all-cell initialization operation in the first SF, and the black luminance, which is the luminance of the black display area that does not generate the sustain discharge, is weak in the all-cell initialization operation. Only the emission of light makes it possible to display an image with high contrast. In the sustain period of each subfield, the number of sustain pulses obtained by multiplying the luminance weight of each subfield by a predetermined proportional constant is applied to each of the display electrode pairs 24. The proportionality constant at this time is the luminance magnification.

  However, in the present embodiment, the number of subfields and the luminance weight of each subfield are not limited to the above values, and the subfield configuration may be switched based on an image signal or the like.

  FIG. 3 is a drive voltage waveform diagram applied to each electrode of panel 10 in accordance with the first exemplary embodiment of the present invention. FIG. 3 shows drive waveforms of scan electrode SC1 that scans first in the address period, scan electrode SCn that scans last in the address period, sustain electrode SU1 to sustain electrode SUn, and data electrode D1 to data electrode Dm. .

  FIG. 3 also shows driving voltage waveforms of two subfields, that is, a first subfield (first SF) that is an all-cell initializing subfield and a second subfield (second SF) that is a selective initializing subfield. It shows. The drive voltage waveform in the other subfields is substantially the same as the drive voltage waveform of the second SF except that the number of sustain pulses generated in the sustain period is different. Scan electrode SCi, sustain electrode SUi, and data electrode Dk in the following represent electrodes selected based on image data (data indicating light emission / non-light emission for each subfield) from among the electrodes.

  First, the first SF, which is an all-cell initialization subfield, will be described.

  In the first half of the initializing period of the first SF, 0 (V) is applied to data electrode D1 to data electrode Dm, sustain electrode SU1 to sustain electrode SUn, and sustain electrode SU1 to sustain is applied to scan electrode SC1 to scan electrode SCn. A ramp voltage (hereinafter referred to as “up-ramp voltage”) that gradually increases (for example, at a slope of about 1.3 V / μsec) from the voltage Vi1 that is equal to or lower than the discharge start voltage to the voltage Vi2 that exceeds the discharge start voltage with respect to the electrode SUn. L1 is applied.

  While the rising ramp voltage L1 rises, between scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn, and between scan electrode SC1 through scan electrode SCn and data electrode D1 through data electrode Dm. Each weak initializing discharge occurs continuously. Negative wall voltage is accumulated above scan electrode SC1 through scan electrode SCn, and positive wall voltage is accumulated above data electrode D1 through data electrode Dm and sustain electrode SU1 through sustain electrode SUn. The wall voltage above the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

  In the latter half of the initialization period, positive voltage Ve1 is applied to sustain electrode SU1 through sustain electrode SUn, 0 (V) is applied to data electrode D1 through data electrode Dm, and scan electrode SC1 through scan electrode SCn. A ramp voltage (hereinafter referred to as “down-ramp voltage”) L2 that gently decreases from voltage Vi3 that is equal to or lower than the discharge start voltage to voltage Vi4 that exceeds the discharge start voltage with respect to sustain electrode SU1 through sustain electrode SUn. Apply.

  During this time, weak initialization discharges occur between scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn, and between scan electrode SC1 through scan electrode SCn and data electrode D1 through data electrode Dm, respectively. . Then, the negative wall voltage above scan electrode SC1 through scan electrode SCn and the positive wall voltage above sustain electrode SU1 through sustain electrode SUn are weakened, and the positive wall voltage above data electrode D1 through data electrode Dm is used for the write operation. It is adjusted to a suitable value. Thus, the all-cell initializing operation for performing the initializing discharge on all the discharge cells is completed.

  Note that, as shown in the initialization period of the second SF in FIG. 3, a drive voltage waveform in which the first half of the initialization period is omitted may be applied to each electrode. That is, voltage Ve1 is applied to sustain electrode SU1 through sustain electrode SUn, and 0 (V) is applied to data electrode D1 through data electrode Dm. Scan electrode SC1 to scan electrode SCn have a voltage equal to or lower than the discharge start voltage (for example, ground The down-ramp voltage L4 that gently falls from the potential) toward the voltage Vi4 is applied. As a result, a weak initializing discharge is generated in the discharge cell that has caused the sustain discharge in the sustain period of the immediately preceding subfield (first SF in FIG. 3), and the wall voltage on the scan electrode SCi and the sustain electrode SUi is weakened. The wall voltage at the upper part of the data electrode Dk (k = 1 to m) is also adjusted to a value suitable for the address operation by discharging an excessive portion. On the other hand, the discharge cells that did not cause the sustain discharge in the immediately preceding subfield are not discharged, and the wall charges at the end of the initializing period of the immediately preceding subfield are maintained. Thus, the initializing operation in which the first half is omitted is a selective initializing operation in which initializing discharge is performed on the discharge cells in which the sustaining operation has been performed in the sustain period of the immediately preceding subfield.

  In the subsequent address period, scan pulse voltage Va is sequentially applied to scan electrode SC1 through scan electrode SCn, and data electrode Dk (k = k = corresponding to the discharge cell to emit light to data electrode D1 through data electrode Dm). 1 to m) is applied with a positive address pulse voltage Vd to selectively generate an address discharge in each discharge cell. At this time, in this embodiment, the order of the scan electrodes 22 to which the scan pulse voltage Va is applied or the order of the write operation of the IC that drives the scan electrodes 22 is changed based on the detection result in the partial lighting rate detection circuit described later. ing. Although details will be described later, here, description will be made assuming that scan pulse voltage Va is applied sequentially from scan electrode SC1.

  In the address period, voltage Ve2 is first applied to sustain electrode SU1 through sustain electrode SUn, and voltage Vc is applied to scan electrode SC1 through scan electrode SCn.

  The negative scan pulse voltage Va is applied to the scan electrode SC1 in the first row, and the data electrode Dk (k = 1 to m) of the discharge cell that should emit light in the first row among the data electrodes D1 to Dm. A positive write pulse voltage Vd is applied to. At this time, the voltage difference at the intersection between the data electrode Dk and the scan electrode SC1 is the difference between the externally applied voltage (voltage Vd−voltage Va) between the wall voltage on the data electrode Dk and the wall voltage on the scan electrode SC1. The difference is added and exceeds the discharge start voltage. As a result, a discharge is generated between data electrode Dk and scan electrode SC1. Further, since voltage Ve2 is applied to sustain electrode SU1 through sustain electrode SUn, the voltage difference between sustain electrode SU1 and scan electrode SC1 is maintained at a difference between externally applied voltages (voltage Ve2−voltage Va). The difference between the wall voltage on the electrode SU1 and the wall voltage on the scan electrode SC1 is added. At this time, by setting the voltage Ve2 to a voltage value that is slightly lower than the discharge start voltage, the sustain electrode SU1 and the scan electrode SC1 are not easily discharged but are likely to be discharged. Can do. Thereby, the discharge generated between data electrode Dk and scan electrode SC1 can be triggered to generate a discharge between sustain electrode SU1 and scan electrode SC1 in the region intersecting with data electrode Dk. Thus, an address discharge occurs in the discharge cell to emit light, a positive wall voltage is accumulated on scan electrode SC1, a negative wall voltage is accumulated on sustain electrode SU1, and a negative wall voltage is also accumulated on data electrode Dk. Accumulated.

  In this manner, an address operation is performed in which an address discharge is caused in the discharge cells to be lit in the first row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection of data electrode D1 to data electrode Dm to which scan pulse SC1 is not applied with address pulse voltage Vd does not exceed the discharge start voltage, so that address discharge does not occur. The above address operation is performed until the discharge cell in the nth row, and the address period ends.

  In the subsequent sustain period, sustain pulses of the number obtained by multiplying the luminance weight by a predetermined luminance magnification are alternately applied to the display electrode pair 24 to generate a sustain discharge in the discharge cells that have generated the address discharge, thereby causing light emission.

  In this sustain period, first, positive sustain pulse voltage Vs is applied to scan electrode SC1 through scan electrode SCn, and a ground potential serving as a base potential, that is, 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn. Then, in the discharge cell in which the address discharge has occurred, the voltage difference between scan electrode SCi and sustain electrode SUi is the difference between the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi. Exceeding the discharge start voltage.

  Then, a sustain discharge occurs between scan electrode SCi and sustain electrode SUi, and phosphor layer 35 emits light by the ultraviolet rays generated at this time. Then, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Further, a positive wall voltage is accumulated on the data electrode Dk. In the discharge cells in which no address discharge has occurred during the address period, no sustain discharge occurs, and the wall voltage at the end of the initialization period is maintained.

  Subsequently, 0 (V) as the base potential is applied to scan electrode SC1 through scan electrode SCn, and sustain pulse voltage Vs is applied to sustain electrode SU1 through sustain electrode SUn. Then, in the discharge cell in which the sustain discharge has occurred, the voltage difference between the sustain electrode SUi and the scan electrode SCi exceeds the discharge start voltage, so that the sustain discharge occurs again between the sustain electrode SUi and the scan electrode SCi. A negative wall voltage is accumulated on SUi, and a positive wall voltage is accumulated on scan electrode SCi. Thereafter, similarly, sustain electrodes of the number obtained by multiplying the luminance weight by the luminance magnification are applied alternately to scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn, and a potential difference is given between the electrodes of display electrode pair 24. As a result, the sustain discharge is continuously performed in the discharge cells that have caused the address discharge in the address period.

  After generation of the sustain pulse in the sustain period, a ramp voltage (hereinafter referred to as “erase ramp voltage”) L3 that gradually increases from 0 (V) toward voltage Vers is applied to scan electrode SC1 through scan electrode SCn. Apply. As a result, a weak discharge is continuously generated in the discharge cell in which the sustain discharge is generated, and the wall voltage on the scan electrode SCi and the sustain electrode SUi is maintained while the positive wall voltage on the data electrode Dk remains. Erase part or all.

  Specifically, after the sustain electrode SU1 to the sustain electrode SUn are returned to 0 (V), the erase ramp voltage L3 that rises from 0 (V) that is the base potential toward the voltage Vers that exceeds the discharge start voltage is increased. It is generated with a steeper gradient (for example, about 10 V / μsec) than the ramp voltage L1, and is applied to scan electrode SC1 through scan electrode SCn. Then, a weak discharge is generated between sustain electrode SUi and scan electrode SCi of the discharge cell in which the sustain discharge has occurred. This weak discharge is continuously generated while the voltage applied to scan electrode SC1 through scan electrode SCn increases. When the increasing voltage reaches the predetermined voltage Vers, the voltage applied to scan electrode SC1 through scan electrode SCn is decreased to 0 (V) as the base potential.

  At this time, the charged particles generated by the weak discharge are accumulated as wall charges on the sustain electrode SUi and the scan electrode SCi so as to reduce the voltage difference between the sustain electrode SUi and the scan electrode SCi. To go. As a result, the wall voltage between scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn remains as positive voltage applied to scan electrode SCi while leaving positive wall charges on data electrode Dk. It is weakened to the extent of the difference between the discharge start voltages, ie, (voltage Vers−discharge start voltage). Hereinafter, the last discharge in the sustain period generated by the erase lamp voltage L3 is referred to as “erase discharge”.

  Subsequent operations in the subfield after the second SF are substantially the same as the operations described above except for the number of sustain pulses in the sustain period, and thus description thereof is omitted. The above is the outline of the drive voltage waveform applied to each electrode of panel 10 in the present embodiment.

  Next, the structure of the plasma display apparatus 1 in this Embodiment is demonstrated. FIG. 4 is a circuit block diagram of plasma display device 1 according to the first exemplary embodiment of the present invention. The plasma display device 1 includes a panel 10, an image signal processing circuit 41, a data electrode drive circuit 42, a scan electrode drive circuit 43, a sustain electrode drive circuit 44, a timing generation circuit 45, a partial lighting rate detection circuit 47, and a lighting rate comparison circuit 48. A correction value generating circuit 53 and a power supply circuit 46 for supplying necessary power to each circuit block are provided.

  The power supply circuit 46 includes a household power supply inlet 70 (for example, a plug for an outlet). The power supply circuit 46 has a circuit element (not shown) for performing a switching operation. When the circuit element is turned on, the plasma display device 1 is turned on to supply the main power, and the household power supply (usually used) Electric power is taken into the power supply circuit 46 through a household power supply inlet 70 from an outlet (for example, an outlet) of a commercial power source or the like. The power supply circuit 46 converts the AC voltage of the household power supply into a DC voltage, and generates a power supply voltage necessary for driving the panel 10 from each power supply voltage generation circuit provided therein.

  The image signal processing circuit 41 converts the input image signal sig into image data indicating light emission / non-light emission for each subfield.

  The partial lighting rate detection circuit 47 divides the display area of the panel 10 into a plurality of areas, and the number of discharge cells to be lit with respect to the number of discharge cells in each area for each area and each subfield based on the image data for each subfield. (Hereinafter, the ratio of the number of discharge cells to be lit to be detected for each region is referred to as “partial lighting ratio”). The partial lighting rate detection circuit 47 can also detect, for example, the lighting rate in one pair of display electrodes 24 as a partial lighting rate, but here, an IC that drives the scanning electrode 22 (hereinafter referred to as “scanning IC”). It is assumed that the partial lighting rate is detected using a region formed of a plurality of scanning electrodes 22 connected to one of the two regions as one region.

  The correction value generation circuit 53 generates a correction value based on the arrangement position of the heating elements provided in the plasma display device 1. Specifically, a power supply circuit having a relatively large heat generation amount or an IC having a relatively large heat generation amount included in a drive circuit for driving the panel 10 is regarded as a heating element, and the partial lighting rate detection circuit 47 includes the above-described regions. The correction value is generated so that the correction value is added to the region corresponding to the arrangement position of these heating elements. At this time, the magnitude of the correction value is determined according to the heating amount of the panel 10 by the heating element, and a relatively large correction value is generated if the heating amount is large, and a relatively small correction value is generated if the heating amount is small. And

  The generated correction value is added by the partial lighting rate detection circuit 47 to the partial lighting rate of the region corresponding to the arrangement position of the heating element. Then, the partial lighting rate detection circuit 47 transmits the partial lighting rate obtained by adding the correction value to the subsequent lighting rate comparison circuit 48 as the corrected lighting rate.

  In the present embodiment, for example, during operation of the plasma display device 1, a member that rises above the temperature of the panel 10 and heats the panel 10 is handled as a heating element. Examples of the heating element include a data electrode driving IC that drives the power supply circuit 46 and the data electrode 32.

  Note that the scan IC that drives the scan electrode 22 and the sustain electrode drive IC that drives the sustain electrode 23 can also be cited as heating elements, but these ICs often have an arrangement position over the entire region, When these ICs are handled as heating elements, correction values are added equally to all areas. In this case, there is a high possibility that the magnitude relationship of the corrected lighting rate after adding the correction value is not different from the magnitude relationship of the partial lighting rate before adding the correction value. In such a case, these ICs need not be treated as heating elements. Hereinafter, in this embodiment, these ICs are not handled as heating elements, but the power supply circuit 46 and the data electrode driving IC are handled as heating elements, and an operation example at that time will be described.

  The lighting rate comparison circuit 48 compares the corrected lighting rate values calculated by the partial lighting rate detection circuit 47 with each other, and determines which region has the largest size in descending order. Then, a signal representing the result is output to the timing generation circuit 45 for each subfield.

  The timing generation circuit 45 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal H, the vertical synchronization signal V, and the output from the lighting rate comparison circuit 48, and supplies them to the respective circuit blocks.

  Scan electrode drive circuit 43 includes an initialization waveform generation circuit (not shown) for generating an initialization waveform voltage to be applied to scan electrode SC1 through scan electrode SCn in the initialization period, and scan electrode SC1 through scan electrode in the sustain period. A sustain pulse generating circuit (not shown) for generating a sustain pulse to be applied to SCn, and a scan for generating scan pulse voltage Va to be applied to scan electrode SC1 through scan electrode SCn in the address period, having a plurality of scan ICs. A pulse generation circuit 50 is provided. Then, each scan electrode SC1 to scan electrode SCn is driven based on the timing signal. At this time, in this embodiment, the scanning ICs are sequentially switched to perform the writing operation so that the writing is performed first from the region where the corrected lighting rate is high. Thereby, stable address discharge is realized. Details of this will be described later.

  The data electrode drive circuit 42 has a write pulse generation circuit 54 that generates a write pulse in the write period, and a plurality of data electrode drives that apply the write pulse generated by the write pulse generation circuit 54 to each of the data electrodes D1 to Dm. An IC 49 is provided, and the data electrodes D1 to Dm are driven based on the timing signal supplied from the timing generation circuit 45. In the present embodiment, as described above, since the order of writing may change for each subfield, the timing generation circuit 45 matches the order of the writing operation of the scan IC in the data electrode driving circuit 42. The timing signal is generated so that the write pulse voltage Vd is generated. Thereby, the correct writing operation according to the display image can be performed.

  Sustain electrode drive circuit 44 includes a sustain pulse generation circuit and a circuit (not shown) for generating voltage Ve1 and voltage Ve2, and drives sustain electrode SU1 through sustain electrode SUn based on a timing signal.

  Next, details and operation of the scan electrode drive circuit 43 will be described.

  FIG. 5 is a circuit diagram showing a configuration of scan electrode drive circuit 43 of plasma display device 1 in accordance with the first exemplary embodiment of the present invention. The scan electrode drive circuit 43 includes a scan pulse generation circuit 50, an initialization waveform generation circuit 51, and a sustain pulse generation circuit 52 on the scan electrode 22 side. Each output of the scan pulse generation circuit 50 is scanned by the panel 10. Connected to each of electrode SC1 through scan electrode SCn.

  The initialization waveform generation circuit 51 raises or lowers the reference potential A of the scan pulse generation circuit 50 in a ramp shape during the initialization period, and generates the initialization waveform voltage shown in FIG.

  The sustain pulse generating circuit 52 generates the sustain pulse shown in FIG. 3 by setting the reference potential A of the scan pulse generating circuit 50 to the voltage Vs or the ground potential.

  Scan pulse generating circuit 50 includes a switch 79 for connecting reference potential A to negative voltage Va in a write period, a power supply VC for applying voltage Vc, and n scan electrodes SC1 to SCn. Switching elements QH1 to QHn for applying scan pulse voltage Va and switching elements QL1 to QLn are provided. Switching element QH1 to switching element QHn and switching element QL1 to switching element QLn are integrated into a plurality of outputs and integrated into an IC. This IC is a scanning IC. Then, by turning off the switching element QHi and turning on the switching element QLi, the negative scan pulse voltage Va is applied to the scan electrode SCi via the switching element QLi.

  When the initialization waveform generating circuit 51 or the sustain pulse generating circuit 52 is operated, the switching elements QH1 to QLn are turned off and the switching elements QL1 to QLn are turned on to turn on the switching elements QL1 to QL1. Initializing waveform voltage or sustain pulse voltage Vs is applied to each of scan electrode SC1 through scan electrode SCn via switching element QLn.

  Here, the following description will be given on the assumption that switching elements for 90 outputs are integrated as one monolithic IC and the panel 10 includes 1080 scanning electrodes 22. Then, it is assumed that scan pulse generation circuit 50 is configured using 12 scan ICs, and n = 1080 scan electrodes SC1 to SCn are driven. In this way, by making a large number of switching elements QH1 to QHn and switching elements QL1 to QLn into an IC, the number of parts can be reduced and the mounting area can be reduced. However, the numerical values given here are merely examples, and the present invention is not limited to these numerical values.

  In the present embodiment, SID (1) to SID (12) output from the timing generation circuit 45 are input to each of the scan IC (1) to scan IC (12) in the writing period. SID (1) to SID (12) are operation start signals for causing the scan IC to start an address operation. The scan IC (1) to scan IC (12) are SID (1) to SID (12). Based on this, the order of the write operation is switched.

  For example, when a write operation is performed on the scan IC (3) connected to the scan electrode SC181 to the scan electrode SC270 and then the scan IC (2) connected to the scan electrode SC91 to the scan electrode SC180 is written, It becomes the operation like this.

  The timing generation circuit 45 changes SID (3) from Lo (for example, 0 (V)) to Hi (for example, 5 (V)), and instructs the scan IC (3) to start the writing operation. The scan IC (3) detects the voltage change of the SID (3), and starts the write operation. First, switching element QH181 is turned off, switching element QL181 is turned on, and scan pulse voltage Va is applied to scan electrode SC181 via switching element QL181. After the writing at scan electrode SC181 is completed, switching element QH181 is turned on, switching element QL181 is turned off, switching element QH182 is turned off, switching element QL182 is turned on, and scanning electrode SC182 is passed via switching element QL182. A scan pulse voltage Va is applied to. The series of address operations are sequentially performed, and scan pulse voltage Va is sequentially applied to scan electrode SC181 to scan electrode SC270, and scan IC (3) ends the address operation.

  After the write operation of the scan IC (3) is completed, the timing generation circuit 45 changes the SID (2) from Lo (for example, 0 (V)) to Hi (for example, 5 (V)), and the scan IC ( Instruct 2) to start the write operation. Scan IC (2) detects the voltage change of SID (2), thereby starting the address operation similar to the above, and sequentially applying scan pulse voltage Va to scan electrode SC91 to scan electrode SC180.

  In this embodiment, the order of the write operation of the scan IC can be controlled using the SID that is the operation start signal as described above.

  In this embodiment, as described above, the order of the write operation of the scan IC is determined according to the corrected lighting rate calculated by the partial lighting rate detection circuit 47, and the region where the corrected lighting rate is high is driven. The write operation is performed first from the scan IC. An example of these operations will be described with reference to the drawings.

  FIG. 6 is a schematic diagram showing an example of the connection between the region for detecting the partial lighting rate and the scan IC in Embodiment 1 of the present invention. FIG. 6 simply shows a state of connection between the panel 10 and the scan IC, and each area surrounded by a broken line in the panel 10 represents an area for detecting a partial lighting rate. In addition, the display electrode pairs 24 are arranged to extend in the left-right direction in the drawing similarly to FIG.

  As described above, the partial lighting rate detection circuit 47 detects the partial lighting rate using a region formed by the plurality of scan electrodes 22 connected to one scan IC as one region. For example, if the number of scan electrodes 22 connected to one scan IC is 90 and the scan electrode driving circuit 43 has 12 scan ICs (scan IC (1) to scan IC (12)), As shown in FIG. 6, the partial lighting rate detection circuit 47 uses the 90 scan electrodes 22 connected to each of the scan IC (1) to the scan IC (12) as one area, and displays the display area of the panel 10. The partial lighting rate of each region is detected by dividing into 12. Then, the lighting rate comparison circuit 48 compares the corrected lighting rate values calculated by the partial lighting rate detection circuit 47 with each other, and ranks the regions in order from the largest value. Then, the timing generation circuit 45 generates a timing signal based on the ranking, and the scan electrode drive circuit 43 performs the write operation first from the scan IC connected to the region where the corrected lighting rate is high by the timing signal.

  FIG. 7 is a schematic diagram showing an example of the order of write operations of scan IC (1) to scan IC (12) in the first embodiment of the present invention. Here, in order to make the explanation easy to understand, first, an example will be described in which the correction value is set to “0%” in all the regions and the scanning IC that drives the region having a high partial lighting rate is operated first. In FIG. 7, the area where the partial lighting rate is detected is the same as the area shown in FIG. 6, and the hatched portion represents the distribution of non-lighted cells that do not generate a sustain discharge, The portion represents the distribution of the lighting cells that generate discharge.

  For example, when the lighting cells are distributed as shown in FIG. 7 in a certain subfield, the region with the highest partial lighting rate is the region to which the scan IC (12) is connected (hereinafter referred to as the scan IC (n)). The area connected to is referred to as "area (n)"), and the area with the next highest partial lighting rate is the area (10) to which the scan IC (10) is connected, followed by the area with the highest partial lighting rate. Is the region (7) to which the scan IC (7) is connected. At this time, in the case of the conventional writing operation, the writing operation is sequentially switched from the scan IC (1) to the scan IC (2) and the scan IC (3), and the scan IC connected to the region having the highest partial lighting rate. (12) Finally, the write operation is started. However, in this embodiment, since the write operation is performed first from the scan IC in the region where the partial lighting rate is high, the write operation is first performed in the scan IC (12) as shown in FIG. 10), the write operation is performed on the scan IC (7). In the present embodiment, if the partial lighting rates are the same, the write operation is performed first from the scan IC connected to the upper scan electrode 22 in terms of arrangement. Therefore, the order of the write operation after the scan IC (7) is as follows: scan IC (1), scan IC (2), scan IC (3), scan IC (4), scan IC (5), scan IC (6). , Scan IC (8), scan IC (9), scan IC (11), and the write operation is region (12), region (10), region (7), region (1), region (2), region (3), region (4), region (5), region (6), region (8), region (9), region (11) are performed in this order.

  Next, an example will be described in which the correction value is added to the partial lighting rate based on the arrangement position of the heating element, and the writing operation is first performed from the scanning IC that drives the region where the corrected lighting rate is high.

  FIG. 8 is a plan view showing an example of an arrangement of a printed circuit board on which each drive circuit of the plasma display device 1 according to Embodiment 1 of the present invention is mounted. In FIG. 8, only the arrangement of the printed boards is shown, and wirings for electrically connecting the printed boards are omitted.

  The scanning electrode driving printed circuit board 71 is equipped with a scanning electrode driving circuit 43 (not shown), and an output terminal of the scanning electrode driving circuit 43 is a flexible printed circuit (hereinafter referred to as “FPC”) 76. It is connected to scan electrode SC <b> 1 through scan electrode SCn of panel 10. The drive voltage output from the scan electrode drive circuit 43 is applied to each scan electrode SC1 to scan electrode SCn via the FPC 76.

  Sustain electrode drive printed circuit board 72 mounts sustain electrode drive circuit 44 (not shown), and the output terminal of sustain electrode drive circuit 44 is connected to sustain electrode SU1 through sustain electrode SUn of panel 10 by FPC 77. The drive voltage output from sustain electrode drive circuit 44 is applied to sustain electrode SU1 through sustain electrode SUn via FPC 77.

  The data electrode driving printed circuit board 73 has the data electrode driving circuit 42 mounted thereon, and the output terminals of the data electrode driving IC 49 included in the data electrode driving circuit 42 are connected to the data electrodes D1 to Dm of the panel 10 by the FPC 78. (FIG. 8 shows only the data electrode driving IC 49). The data electrode driving IC 49 is desirably arranged in the vicinity of the FPC 78 so that the wiring distance between the data electrodes D1 to Dm is as short as possible. For example, the data electrode driving IC 49 is arranged on the data electrode driving printed board 73 in the row direction ( They are arranged in a line (in the drawing in the horizontal direction). The driving voltage output from the data electrode driving IC 49 is applied to the data electrode Dk via the FPC 78. Although FIG. 8 shows a configuration in which more FPCs 78 are installed than the data electrode driving ICs 49, this is merely an example configuration, and the FPCs 78 may be smaller than the data electrode driving ICs 49, or the FPCs 78. May be provided in the same number as the data electrode driving ICs 49 and correspond to each other one to one.

  The control printed circuit board 74 is equipped with a timing generation circuit 45 and performs overall control of the plasma display device 1.

  The power supply printed circuit board 75 includes a power supply circuit 46 having a voltage Vd generation circuit that generates a voltage Vd (for example, 75 (V)), and supplies power to each circuit block provided in the plasma display device 1. Since the power supply circuit 46 supplies power to each circuit block of the plasma display device 1, it is desirable that the distance from each printed circuit board be as uniform as possible. Therefore, in the present embodiment, the power printed board 75 is disposed near the center of the panel 10.

  In the present embodiment, as described above, the temperature rises above the temperature of the panel 10, and the power supply circuit 46 and the data electrode driving IC 49, which are members that heat the panel 10, are regarded as heating elements and a correction value is generated. .

  FIG. 9 is a schematic diagram showing an example of the order of write operations of scan IC (1) to scan IC (12) according to the corrected lighting rate in the first embodiment of the present invention. In FIG. 9, similarly to FIG. 7, a region where non-lighted cells are distributed is indicated by hatching, and a region where lighted cells are distributed is indicated by white without hatching. Moreover, in FIG. 9, in order to show each area | region clearly, the boundary between areas is shown with a broken line. Further, the arrangement positions of the power supply circuit 46 and the data electrode driving IC 49 arranged on the back surface of the panel 10 are indicated by solid lines.

  In this display image, the partial lighting rate of each region is 100% for the region (1) connected to the scan IC (1), and hereinafter, the region (2) is 92% and the region (3) is 84. %, Area (4) 75%, area (5) 67%, area (6) 58%, area (7) 50%, area (8) 42%, area (9) 33%, Assume that the region (10) is 25%, the region (11) is 17%, and the region (12) is 8%. Therefore, in this display image, for example, when writing is performed with the correction value of all the regions set to “0%”, the scanning order of each region is as follows: region (1), region (2), region (3), region (4), region (5), region (6), region (7), region (8), region (9), region (10), region (11), region (12) in this order.

  On the other hand, as shown in FIG. 9, the power supply circuit 46 is disposed at a position corresponding to the region (5) and the region (6), and the data electrode driving IC 49 is disposed at a position corresponding to the region (12). . Therefore, the correction value in the region (5) and the region (6) is set to, for example, “10%”, the correction value in the region (12) is set to, for example, “30%”, and the correction value in the remaining region is set to “0%”. Then, the corrected lighting rates of the region (5) and the region (6) are 77% in the region (5), 68% in the region (6), and the corrected lighting rate in the region (12) is 38%. . Therefore, the corrected lighting rate of the region (5) is larger than 75% of the region (4), and the corrected lighting rate of the region (12) is larger than 33% of the region (9).

  Therefore, when writing is performed based on the corrected lighting rate, the scanning order of each region is as follows: region (1), region (2), region (3), region (5), region (4), region (6). , Region (7), region (8), region (12), region (9), region (10), region (11) in this order, scanning region (5) before region (4), Region (12) can be scanned before region (9).

  Thus, in this embodiment, in the region heated by the heating element, a correction value corresponding to the heating amount is added to the partial lighting rate. Then, by performing the address operation first from the scan IC connected to the area where the corrected lighting rate is high, the address is written first from the area where the partial lighting rate is high or the heating amount by the heating element is large, and stable address discharge Is realized. This is due to the following reason.

  FIG. 10 is a characteristic diagram showing the relationship between the order of address operation of the scan IC and the scan pulse voltage (amplitude) necessary for generating a stable address discharge in the first embodiment of the present invention. In FIG. 10, the vertical axis represents the scan pulse voltage (amplitude) necessary for generating a stable address discharge, and the horizontal axis represents the order of the address operation of the scan IC. In this experiment, one screen was divided into 16 areas, and the scan pulse generation circuit 50 was provided with 16 scan ICs to drive the scan electrodes SC1 to SCn. Then, it was measured how the scan pulse voltage (amplitude) required to generate a stable address discharge changes depending on the order of the address operation of the scan IC.

  As shown in FIG. 10, the scan pulse voltage (amplitude) necessary for generating a stable address discharge also changes in accordance with the order of the address operation of the scan IC. Then, the scan pulse voltage (amplitude) required to generate a stable address discharge increases as the scan IC has a slower address operation order. For example, in the scan IC that performs the address operation first, the scan pulse voltage (amplitude) necessary for generating a stable address discharge is about 80 (V), but the address operation is performed last (here, 16th). In the scan IC, the required scan pulse voltage (amplitude) is about 150 (V), which is about 70 (V).

  This is presumably because the wall charges formed during the initialization period gradually decrease with time. Further, since the address pulse voltage Vd is applied to each data electrode 32 during the address period (according to the display image), the address pulse voltage Vd is also applied to the discharge cells that are not scanned. Since the wall charge is reduced by such a voltage change, it is considered that the wall charge is further reduced in the discharge cell in which writing is performed at the end of the writing period.

  FIG. 11 is a characteristic diagram showing the relationship between the partial lighting rate and the scan pulse voltage (amplitude) necessary for generating a stable address discharge in the first embodiment of the present invention. In FIG. 11, the vertical axis represents the scan pulse voltage (amplitude) necessary for generating a stable address discharge, and the horizontal axis represents the partial lighting rate. In this experiment, as in the measurement in FIG. 10, one screen is divided into 16 areas, and in one of the areas, the scan pulse necessary for generating a stable address discharge while changing the ratio of the lighting cells. It was measured how the voltage (amplitude) changes.

  As shown in FIG. 11, the scan pulse voltage (amplitude) necessary for generating a stable address discharge also changes in accordance with the ratio of the lighted cells. As the lighting rate increases, the scan pulse voltage (amplitude) necessary for generating a stable address discharge increases. For example, when the lighting rate is 10%, the scan pulse voltage (amplitude) necessary to generate a stable address discharge is about 118 (V), but when the lighting rate is 100%, the necessary scan pulse voltage (amplitude) is It becomes about 149 (V), and about 31 (V) becomes large.

  This is presumably because the discharge current increases and the voltage drop of the scan pulse voltage (amplitude) increases as the number of lighting cells increases and the lighting rate increases. Further, when the driving load increases due to the enlargement of the screen of the panel 10 such as the length of the scanning electrode 22 being increased, the voltage drop is further increased.

  In a discharge cell having a high temperature, for example, a discharge cell heated by a member that generates a large amount of heat and having a temperature higher than that of the surroundings, wall charges are more likely to decrease than discharge cells that do not, and a stable address discharge is generated. It was experimentally confirmed that the scan pulse voltage (amplitude) required for the adjustment is likely to increase.

  FIG. 12 is a characteristic diagram showing the relationship between the panel temperature and the scan pulse voltage (amplitude) necessary for generating a stable address discharge in the first embodiment of the present invention. In FIG. 12, the vertical axis represents the scan pulse voltage (amplitude) necessary for generating a stable address discharge, and the horizontal axis represents the temperature of the panel 10. In this experiment, it was measured how the scan pulse voltage (amplitude) required to generate a stable address discharge changes while changing the temperature of the panel 10.

  Then, as shown in FIG. 12, it was confirmed that the scan pulse voltage (amplitude) necessary for generating a stable address discharge increases as the temperature of the panel 10 increases. For example, when the temperature of the panel 10 is 40 ° C., the scan pulse voltage (amplitude) necessary for generating a stable address discharge is about 91 (V), but is necessary when the temperature of the panel 10 is 80 ° C. The scan pulse voltage (amplitude) is about 130 (V), which is about 39 (V).

  As described above, the scan pulse voltage (amplitude) necessary for generating a stable address discharge increases as the order of the address operation of the scan IC becomes slower, that is, as the elapsed time from the initialization operation to the address operation becomes longer. In addition, the higher the lighting rate, the larger the discharge rate, and the higher the discharge cell temperature. Therefore, when the order of the write operation of the scan IC is slow, the partial lighting rate of the area to which the scan IC is connected is high, and the area to which the scan IC is connected is heated by the heating element, it is stable. The scan pulse voltage (amplitude) necessary for generating the address discharge is further increased.

  However, even in a region where the partial lighting rate is high similarly, if the order of the write operation of the scan IC connected to the region is advanced, the order of the write operation of the scan IC connected to the region is late. As a result, the scan pulse voltage (amplitude) necessary for generating a stable address discharge can be reduced. Further, even in a region heated by a heating element, if the order of the write operation of the scan IC connected to the region is made earlier, the order of the write operation of the scan IC connected to the region is slower than that of the region. It is possible to reduce the scan pulse voltage (amplitude) necessary for generating a stable address discharge.

  Therefore, in the present embodiment, the partial lighting rate is detected for each region, the correction value is set to “0%” in the region where the heating element is not heated, and the heating value is determined in the region heated by the heating element. The corrected lighting rate is calculated by adding a correction value of a certain size to the partial lighting rate, and the writing operation is performed first from the scan IC connected to the region where the corrected lighting rate is high. In this way, by performing the writing operation first from the region where the lighting rate after correction is high, the writing operation in the region where the partial lighting rate is high or the heating amount by the heating element is large, than the writing operation in the region where it is not, It is possible to shorten the elapsed time from the initialization operation to the write operation. Thereby, it is possible to prevent an increase in the scan pulse voltage (amplitude) necessary for generating a stable address discharge and to generate a stable address discharge. In the experiment conducted by the present inventor, the scan pulse voltage (amplitude) necessary for generating a stable address discharge is about 20 (V) depending on the display image by adopting the configuration in the present embodiment. It was confirmed that it can be reduced.

  In the present embodiment, the correction value “10%” is added to the partial lighting rates of the region (5) and the region (6), and the correction value “30%” is added to the partial lighting rate of the region (12). Although the example has been described, these correction values are set according to the magnitude of the heating amount of the panel 10 by the heating element, that is, how much heat generated by the heating element heats the panel 10. The setting factors at this time include, for example, the amount of heat generated by the heating element, the size of the heating element (installation area when viewed from the panel 10 side), the magnitude of heat conduction from the heating element to the panel 10, and the like. Further, when the plasma display device 1 is provided with a heat radiating element for cooling the heat generating element, specifically, a heat radiating fan is provided in the vicinity of the heat generating element, or a heat radiating fin, a heat radiating plate, etc. Is attached, it is desirable to reduce the correction value by the amount that the heat generating element is cooled by the heat radiating element. The magnitude of the correction value is preferably set to a value that is considered to be optimal and confirmed by experiments, simulations, and the like in consideration of the characteristics of the panel 10 and the specifications of the plasma display device 1.

  Next, an example of a circuit that generates SIDs (here, SID (1) to SID (12)) that are operation start signals to the scan IC shown in FIG. 5 will be described with reference to the drawings.

  FIG. 13 is a circuit block diagram showing a configuration example of the scan IC switching circuit 60 in the first embodiment of the present invention. The timing generation circuit 45 includes a scan IC switching circuit 60 that generates SIDs (here, SID (1) to SID (12)). Although not shown here, each scan IC switching circuit 60 is supplied with a clock signal that serves as a reference for the operation timing of each circuit.

  As shown in FIG. 13, the scan IC switching circuit 60 includes the same number (here, 12) of SID generation circuits 61 as the number of SIDs to be generated, and each SID generation circuit 61 includes a lighting rate comparison circuit 48. A switching signal generated based on the comparison result, a selection signal generated during the scanning IC selection period in the writing period, and a start signal generated when the writing operation of the scanning IC is started are input. Each SID generation circuit 61 outputs an SID based on each input signal. Each signal is generated in the timing generation circuit 45. As for the selection signal, the selection signal delayed by a predetermined time in each SID generation circuit 61 is used for the SID generation circuit 61 in the next stage. For example, the selection signal (1) input to the first SID generation circuit 61 is delayed by a predetermined time in the SID generation circuit 61 to be the selection signal (2), and this selection signal (2) is sent to the SID generation circuit 61 in the next stage. Shall be entered. Therefore, in each SID generation circuit 61, the switching signal and the start signal are input at the same timing, but the selection signals are all input at different timings.

  FIG. 14 is a circuit diagram showing a configuration example of the SID generation circuit 61 in the first embodiment of the present invention. The SID generation circuit 61 includes a flip-flop circuit (hereinafter abbreviated as “FF”) 62, a delay circuit 63, and an AND gate 64.

  The FF 62 has the same configuration and operation as a generally known flip-flop circuit, and has a clock input terminal, a data input terminal, and a data output terminal. Then, the state (Lo or Hi) of the data input terminal (here, the selection signal is inputted) at the time of rising of the signal (here, the switching signal) inputted to the clock input terminal (when changing from Lo to Hi). The data that is held and inverted is output as a gate signal from the data output terminal.

  The AND gate 64 inputs the gate signal output from the FF 62 to one input terminal, inputs the start signal to the other input terminal, performs an AND operation, and outputs the result. That is, Hi is output only when the gate signal is Hi and the start signal is Hi, and Lo is output otherwise. The output of the AND gate 64 becomes the SID.

  The delay circuit 63 has the same configuration and operation as a generally known delay circuit, and has a clock input terminal, a data input terminal, and a data output terminal. Then, the signal input to the data input terminal (here, the selection signal) is output from the data output terminal after being delayed by a predetermined period (here, one period) of the clock signal input to the clock input terminal. To do. This output becomes a selection signal used for the SID generation circuit 61 in the next stage.

  These operations will be described using a timing chart. FIG. 15 is a timing chart for explaining the operation of scan IC switching circuit 60 according to the first embodiment of the present invention. Here, the operation of the scan IC switching circuit 60 when the write operation is performed on the scan IC (2) after the scan IC (3) will be described as an example.

  In the present embodiment, it is assumed that the next scan IC to be written is determined in the scan IC selection period provided in the write period. However, it is assumed that the scan IC selection period for determining the scan IC to perform the address operation first is performed immediately before the address period. A scan IC selection period for determining the next scan IC to perform the write operation is provided immediately before the write operation of the scan IC during the write operation is completed.

  In the scan IC selection period, first, the selection signal (1) is input to the SID generation circuit 61 for generating SID (1). As shown in FIG. 15, the selection signal (1) is normally Hi and has a negative pulse waveform that becomes Lo for one cycle of the clock signal. The selection signal (1) is delayed by one cycle of the clock signal in the SID generation circuit 61, and is input to the SID generation circuit 61 for generating the SID (2) as the selection signal (2). Thereafter, the selection signals (3) to (12) delayed by one cycle of the clock signal are input to the SID generation circuits 61, respectively.

  As shown in FIG. 15, the switching signal is normally Lo and has a positive pulse waveform that becomes Hi for one cycle of the clock signal. Then, of the selection signals (1) to (12) delayed by one cycle of the clock signal, the positive polarity is selected at the timing when the selection signal for selecting the scan IC to be operated next becomes Lo. Generate a pulse. As a result, in the FF 62, a signal obtained by inverting the state of the selection signal at the rising edge of the switching signal input to the clock input terminal is output as the gate signal. Note that the positive polarity pulse in the switching signal is generated by the timing generation circuit 45 by determining the generation timing based on the comparison result from the lighting rate comparison circuit 48.

  For example, when the scan IC (2) is selected, as shown in FIG. 15, a positive pulse is generated in the switching signal when the selection signal (2) becomes Lo. At this time, since the selection signals excluding the selection signal (2) are Hi, only the gate signal (2) is Hi and the other gate signals are Lo. Here, the gate signal (3) changes from Hi to Lo at this timing.

  The switching signal may be generated such that the state changes in synchronization with the falling edge of the clock signal. In this way, a time shift corresponding to a half cycle of the clock signal can be provided with respect to a change in the state of the selection signal, and the operation in the FF 62 can be ensured.

  Then, at the timing when the write operation of the scan IC is started, a positive pulse that becomes Hi for one cycle of the clock signal is generated in the start signal. The start signal is input to each SID generation circuit 61 in common, but only the AND gate 64 whose gate signal is Hi can output a positive pulse. As a result, the scan IC for the next write operation can be arbitrarily determined. Here, since the gate signal (2) is Hi, a positive pulse is generated in the SID (2), and the scanning IC (2) starts the writing operation.

  Although the SID can be generated by the circuit configuration as described above, the circuit configuration shown here is merely an example, and the present invention is not limited to the circuit configuration shown here. Any circuit configuration may be used as long as it can generate an SID that instructs the scan IC to start the write operation.

  FIG. 16 is a timing chart for explaining another example of the scan IC switching operation in the first embodiment of the present invention.

  For example, as shown in FIG. 16, instead of the switching signal, a positive pulse that becomes Hi for two cycles of the clock signal may be generated in the start signal. That is, when a positive pulse that becomes Hi for two cycles of the clock signal is generated in the start signal, the pulse is used as an input to the clock input terminal in the FF 62 and becomes positive for one cycle of the clock signal. When the above pulse is generated, the original start signal may be used. Even with such a configuration, the same operation as described above can be performed.

  As described above, according to the present embodiment, the display area of panel 10 is divided into a plurality of areas, and the partial lighting rate in each area is detected by partial lighting rate detection circuit 47 and the detected partial lighting rate. In addition, a corrected lighting rate is calculated by adding a correction value according to the arrangement position of the heating element and the heating amount by the heating element, and scanning is performed first from a region where the corrected lighting rate is high. This prevents an increase in the scan pulse voltage (amplitude) required to generate a stable address discharge in an area where the partial lighting rate is high and an area where the heating amount by the heating element is large, thereby stabilizing the address discharge. Can be generated.

(Embodiment 2)
In the first embodiment, the correction value “10%” is added to the partial lighting rate in the region corresponding to the position where the power supply circuit 46 is arranged, and the partial lighting rate is set in the region corresponding to the position where the data electrode driving IC 49 is arranged. Although an example in which the correction value “30%” is added to the above has been described, the correction value may be changed according to the display image.

  For example, the power consumption of the data electrode driving IC 49 changes according to the design of the image displayed on the panel 10. Therefore, the amount of heat generated in the data electrode driving IC 49 varies according to the display image.

  Therefore, in the present embodiment, a configuration example will be described in which the power consumption of the data electrode driving IC 49 is calculated based on the display image, and the correction value is changed according to the calculation result.

  FIG. 17 is a circuit block diagram of plasma display device 2 in the second exemplary embodiment of the present invention. The plasma display device 2 includes a panel 10, an image signal processing circuit 41, a data electrode drive circuit 42, a scan electrode drive circuit 43, a sustain electrode drive circuit 44, a timing generation circuit 45, a partial lighting rate detection circuit 47, and a lighting rate comparison circuit 48. A data power calculation circuit 65, a correction value generation circuit 66, and a power supply circuit 46 for supplying power necessary for each circuit block are provided. Each circuit block excluding the data power calculation circuit 65 and the correction value generation circuit 66 has the same configuration and the same operation as the circuit block of the same name shown in FIG. 4 in the first embodiment.

  The data power calculation circuit 65 calculates the power consumption in the data electrode driving IC 49 based on the image data for each subfield generated from the image signal in the image signal processing circuit 41. The calculation of power consumption in the data electrode driving IC 49 can be performed, for example, as follows.

  The power consumption in the data electrode driving IC 49 increases as the number of discharge cells (lighting cells) that generate address discharges and discharge cells (lighting cells) that do not generate address discharges increases. The more adjacent the number, the smaller. This is because the data electrode driving IC 49 generates a write pulse by switching a plurality of switching elements included therein, and the number of switching of the switching elements increases as the number of lighting cells and non-lighting cells increases. Conversely, the larger the number of adjacent lighting cells or non-lighting cells is, the more the switching frequency of the switching element is reduced.

  The data power calculation circuit 65 uses this to calculate the power consumption in the data electrode drive IC 49. For example, a lighted cell is set to “1”, a non-lighted cell is set to “0”, an exclusive OR operation is performed between adjacent discharge cells, and the results are cumulatively added. Thereby, the number of locations where the lighted cell and the non-lighted cell are adjacent can be counted. If the relationship between the cumulative addition value thus obtained and the power consumption in the data electrode driving IC 49 is examined in advance and the data is provided to the data power calculation circuit 65, the cumulative addition value described above can be calculated. Thus, power consumption can be calculated. However, the present invention is not limited to this method for calculating power consumption, and may be configured to calculate power consumption by other methods.

  In the present embodiment, the data electrode driving circuit 42 has twelve data electrode driving ICs 49, and all the data electrode driving ICs 49 are included in one region. Therefore, the data power calculation circuit 65 calculates the sum of the power consumption of the twelve data electrode drive ICs 49 and outputs it to the correction value generation circuit 66 at the subsequent stage.

  Then, the correction value generation circuit 66 adds a correction value corresponding to the power consumption calculated by the data power calculation circuit 65 to the partial lighting rate in the area corresponding to the position where the data electrode driving IC 49 is disposed. Shall. The setting range of the correction value at this time can be, for example, “40%” to “10%”. These values are the rated value of the data electrode driving IC 49, the characteristics of the panel 10, the plasma display device 2's characteristics, and the like. It is desirable to set according to specifications.

  The power consumption in the data electrode driving IC 49 changes sequentially according to the display image, whereas the temperature of the data electrode driving IC 49 changes with a time constant corresponding to the heat capacity of the data electrode driving IC 49. Therefore, in the correction value generation circuit 66, the correction value is changed so that the correction value in the region where the data electrode driving IC 49 is arranged changes gently following the temperature change in the data electrode driving IC 49. It is desirable to have a configuration that passes through.

  As described above, according to the present embodiment, it is possible to appropriately change the correction value in accordance with the heating amount by the data electrode driving IC 49 or the like that changes depending on the display image.

  In the embodiment of the present invention, the configuration in which each region is set based on the scan electrode 22 connected to one scan IC has been described. However, the present invention is not limited to this configuration, and other configurations are possible. The configuration may be such that each area is set by division. For example, if the scanning order of the scanning electrodes 22 can be arbitrarily changed one by one, the partial lighting rate is detected for each scanning electrode 22 with one scanning electrode 22 as one region, and the detection result is Accordingly, the scanning order may be changed for each scanning electrode 22.

  In the embodiment of the present invention, the configuration in which the partial lighting rate in each region is detected and the corrected lighting rate is calculated by adding the correction value to the detection result has been described. However, the present invention is not limited to this configuration. It is not limited to. For example, the lighting rate in one pair of display electrodes 24 is detected for each display electrode pair 24 as the line lighting rate, and the highest line lighting rate is detected as the peak lighting rate for each region, and corrected to the peak lighting rate. It is good also as a structure which makes a lighting rate after correction | amendment by adding a value.

  In the embodiment of the present invention, the scan electrode 22 and the scan electrode 22 are adjacent to each other, and the sustain electrode 23 and the sustain electrode 23 are adjacent to each other. .. It is also effective in a panel having an electrode structure of “scan electrode, scan electrode, sustain electrode, sustain electrode, scan electrode, scan electrode,.

  In the embodiment of the present invention, the configuration in which erase lamp voltage L3 is applied to scan electrode SC1 through scan electrode SCn has been described. However, the erase ramp voltage L3 is applied to sustain electrode SU1 through sustain electrode SUn. You can also. Alternatively, an erasing discharge may be generated not by the erasing ramp voltage L3 but by a so-called narrow erasing pulse.

  Note that the polarities of the signals shown when explaining the operation of the scan IC switching circuit 60 are merely examples, and may be opposite to the polarities shown in the explanation.

  Note that the timing chart shown in the embodiment of the present invention is merely an example of the operation, and may have other configurations.

  The specific numerical values shown in the embodiment of the present invention are set based on the characteristics of the panel 10 having 50 inches and the number of display electrode pairs 24 of 1080 pairs, and are merely examples in the embodiments. It is just what was shown. The present invention is not limited to these numerical values, and each numerical value is desirably set optimally according to the characteristics of the panel 10, the specifications of the plasma display devices 1 and 2, and the like. Further, the number of subfields and the luminance weight of each subfield are not limited to the values shown in the embodiment of the present invention, and the subfield configuration may be switched based on an image signal or the like. Good.

  The present invention generates a stable address discharge by preventing an increase in scan pulse voltage (amplitude) necessary for generating a stable address discharge even in a panel with a large screen and high definition, Since high image display quality can be realized, it is useful as a driving method of a plasma display device and a panel.

The disassembled perspective view which shows the structure of the panel in Embodiment 1 of this invention. Electrode arrangement of the panel Drive voltage waveform diagram applied to each electrode of the panel Circuit block diagram of plasma display device according to Embodiment 1 of the present invention Circuit diagram showing configuration of scan electrode driving circuit of same plasma display device Schematic which shows an example of the connection of the area | region which detects the partial lighting rate in Embodiment 1 of this invention, and scanning IC Schematic which shows an example of the order of the write-in operation | movement of the scan IC in Embodiment 1 of this invention. The top view which shows an example of arrangement | positioning of the printed circuit board carrying each drive circuit of the plasma display apparatus in Embodiment 1 of this invention Schematic which shows an example of the order of the write-in operation | movement of scan IC according to the lighting rate after correction | amendment in Embodiment 1 of this invention. FIG. 5 is a characteristic diagram showing the relationship between the order of address operation of the scan IC and the scan pulse voltage (amplitude) necessary for generating stable address discharge in the first embodiment of the present invention. The characteristic view which shows the relationship between the partial lighting rate in Embodiment 1 of this invention, and the scanning pulse voltage (amplitude) required in order to generate the stable address discharge The characteristic view which shows the relationship between the temperature of the panel in Embodiment 1 of this invention, and the scanning pulse voltage (amplitude) required in order to generate the stable address discharge 1 is a circuit block diagram showing a configuration example of a scan IC switching circuit according to Embodiment 1 of the present invention. 1 is a circuit diagram showing a configuration example of an SID generation circuit according to Embodiment 1 of the present invention. Timing chart for explaining the operation of the scan IC switching circuit according to the first embodiment of the present invention Timing chart for explaining another example of the scan IC switching operation in the first embodiment of the present invention Circuit block diagram of plasma display device in accordance with the second exemplary embodiment of the present invention

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 2 Plasma display apparatus 10 Panel 21 Front plate (made of glass) 22 Scan electrode 23 Sustain electrode 24 Display electrode pair 25, 33 Dielectric layer 26 Protective layer 31 Back plate 32 Data electrode 34 Partition 35 Phosphor layer 41 Image signal Processing circuit 42 Data electrode drive circuit 43 Scan electrode drive circuit 44 Sustain electrode drive circuit 45 Timing generation circuit 46 Power supply circuit 47 Partial lighting rate detection circuit 48 Lighting rate comparison circuit 49 Data electrode drive IC
50 scan pulse generation circuit 51 initialization waveform generation circuit 52 sustain pulse generation circuit 53, 66 correction value generation circuit 54 write pulse generation circuit 60 scan IC switching circuit 61 SID generation circuit 62 FF (flip-flop circuit)
63 Delay circuit 64 AND gate 65 Data power calculation circuit 70 Household power supply port 71 Scan electrode driving printed circuit board 72 Sustain electrode driving printed circuit board 73 Data electrode driving printed circuit board 74 Control printed circuit board 75 Power supply printed circuit board 76, 77,78 FPC (Flexible Wiring Board)
79 switches QH1 to QHn, QL1 to QLn switching elements

Claims (5)

A plurality of subfields having an initialization period, an address period, and a sustain period are provided in one field, a luminance weight is set for each subfield, and a number of sustain pulses corresponding to the luminance weight are generated during the sustain period. A plasma display panel that is driven by a sub-field method for gray scale display and includes a plurality of discharge cells each having a display electrode pair and a data electrode each including a scan electrode and a sustain electrode;
A scan electrode driving circuit that generates a scan pulse in the address period and sequentially applies the scan pulse to the scan electrode to scan the scan electrode;
A display area of the plasma display panel is divided into a plurality of areas, and in each of the areas, a partial lighting rate detection circuit that detects, for each subfield, a ratio of the number of discharge cells to be lit with respect to the number of discharge cells as a partial lighting rate; Prepared,
The partial lighting rate detection circuit is:
Based on the arrangement position of the heating element provided in the plasma display device having the plasma display panel, calculating a corrected lighting rate by adding a correction value to the partial lighting rate,
The scan electrode driving circuit includes:
The plasma display apparatus characterized in that the scanning is performed first from the region where the corrected lighting rate calculated by the partial lighting rate detection circuit is high. 2. The plasma display device according to claim 1, wherein the partial lighting rate detection circuit adds the correction value having a magnitude corresponding to a heating amount of the plasma display panel by the heating element to the partial lighting rate. . A data electrode driving circuit having a data electrode driving IC for applying an address pulse to the data electrode in the address period;
The partial lighting rate detection circuit is:
The plasma display apparatus according to claim 2, wherein the corrected lighting rate is calculated using the data electrode driving IC as the heating element. A power supply circuit for supplying power to each circuit provided in the plasma display device;
The partial lighting rate detection circuit is:
The plasma display apparatus according to claim 2, wherein the corrected lighting rate is calculated using the power supply circuit as the heating element. A plasma display panel having a plurality of discharge cells each having a display electrode pair composed of a scan electrode and a sustain electrode is provided with a plurality of subfields having an initialization period, an address period, and a sustain period in one field, Luminance weights are provided, scan pulses are generated during the address period and sequentially applied to the scan electrodes to scan the scan electrodes, and a number of sustain pulses corresponding to the luminance weight are generated during the sustain period. A method for driving a plasma display panel driven by a subfield method for displaying a tone,
The display area of the plasma display panel is divided into a plurality of areas, and in each of the areas, the ratio of the number of discharge cells to be lit with respect to the number of discharge cells is detected for each subfield as a partial lighting rate, and the plasma display panel is Based on the arrangement position of the heating element provided in the plasma display device having, calculate a corrected lighting rate by adding a correction value to the partial lighting rate,
A method for driving a plasma display panel, wherein the scanning is performed first from the region where the calculated lighting rate after correction is high.

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