JP2010091315A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which generates a large number of control signals by as few control pins as possible and which is easy to switch between a normal operation mode and a plurality of test modes. <P>SOLUTION: The semiconductor circuit includes a test control circuit which switches between the normal operation mode and the plurality of test modes, according to the signal input from an external connection terminal. The test control circuit includes: a current mirror circuit, having first and second transistors; an operational amplifier which controls a current passing through the first transistor so that the voltage at the terminal of the first transistor connected to the external connection terminal matches a reference voltage; and an analog-to-digital conversion circuit which outputs a digital signal, corresponding to the current passing through the second transistor according to the current passing through the first transistor. Switching between the normal operation mode and the plurality of test modes is performed through the digital signal output from the analog-to-digital conversion circuit. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit including a test control circuit that switches between a normal operation mode and a plurality of test modes.

  In a semiconductor integrated circuit, for example, a plurality of test modes are provided for the purpose of, for example, changing a current value flowing through a circuit from a default value or verifying the operation of a circuit in a test mode other than the normal operation mode of the circuit. It is common to evaluate a semiconductor integrated circuit by setting a control pin (external connection terminal) for controlling the operation mode outside the semiconductor integrated circuit so that the setting (operation mode) can be changed on the evaluation board. Is.

  However, in order to set a desired operation mode from among a plurality of operation modes, as the number of operation modes to be set increases, the number of control pins that must be brought out of the semiconductor integrated circuit increases, and thus the number of pads increases. There are cost disadvantages.

  On the other hand, in order to reduce the number of control pins to be output to the outside, a method (serial test controller) for inputting a control signal from the outside as a serial signal and generating a large number of control signals using a decoder inside the semiconductor integrated circuit is patented. Proposed by reference 1.

  Also, an analog signal is input from the outside, the input analog signal is converted into a digital signal using an analog / digital converter, a mode setting permission signal for permitting mode setting is input, and a mode setting permission signal is given. In Japanese Patent Application Laid-Open No. 2004-228688, a method for generating a test signal for selecting a test mode using the converted digital signal and keeping the internal circuit in a testable state is proposed.

JP 62-115857 A JP 2005-265704 A

  However, when a control signal is input as a serial signal from the outside as in the method proposed in Patent Document 1, a dedicated signal generator for generating a serial signal is required on the evaluation board.

  In addition, when a mode setting permission signal and an analog signal are externally input as in the method proposed in Patent Document 2, the analog signal input pin and the mode setting permission signal input pin are shown in FIG. Thus, high-level and low-level reference voltage input pins supplied to the analog-to-digital converter are required. Therefore, a large number of control pins for switching the operation mode are required.

  An object of the present invention is to provide a semiconductor integrated circuit that can more easily generate a large number of switching signals with as few control pins as possible and switch between a normal operation mode and a plurality of test modes.

To achieve the above object, the present invention is a semiconductor integrated circuit including a test control circuit that switches between a normal operation mode and a plurality of test modes in accordance with a signal input from an external connection terminal.
The test control circuit comprises:
A current mirror circuit having first and second transistors;
An operational amplifier that controls a current flowing through the first transistor so that a voltage of a terminal of the first transistor connected to the external connection terminal matches a reference voltage;
An analog-to-digital conversion circuit that outputs a digital signal corresponding to the current flowing through the second transistor in response to the current flowing through the first transistor;
The present invention provides a semiconductor integrated circuit characterized in that the normal operation mode and a plurality of test modes are switched by a digital signal output from the analog-digital conversion circuit.

  Here, the analog-to-digital conversion circuit is a voltage input type analog-to-digital converter that outputs a resistor that converts the current flowing through the second transistor into a voltage and a digital signal corresponding to the voltage converted by the resistor. It is preferable to have.

  Alternatively, it is preferable that the analog-digital conversion circuit includes a current input type analog-digital converter that outputs a digital signal corresponding to a current flowing through the second transistor.

  According to the present invention, it is possible to freely switch between a normal operation mode and a plurality of test modes, that is, a plurality of operation modes, only by changing the resistance value of the external resistor connected to the external connection terminal. Moreover, it is not necessary to mount a dedicated circuit such as a signal generator on the evaluation board in order to switch the operation mode, and only one external connection terminal is required, so the number of external connection terminals of the semiconductor integrated circuit can be reduced. The cost can be reduced.

  Hereinafter, a semiconductor integrated circuit of the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings.

  FIG. 1 is a schematic view of an embodiment showing the configuration of a semiconductor integrated circuit according to the present invention. A semiconductor integrated circuit 10 shown in FIG. 1 includes a test control circuit 12 that switches between a normal operation mode and a plurality of test modes in accordance with a signal input from a control pin (external connection terminal) 20. The test control circuit 12 includes a current mirror circuit 14, an operational amplifier 16, and an analog / digital conversion circuit (AD conversion circuit) 18.

  In FIG. 1, the semiconductor integrated circuit 10 and the external resistor 22 are mounted on the evaluation board 24, and the control pin 20 of the semiconductor integrated circuit 10 described above is connected to the ground via the external resistor 22.

  Hereinafter, the test control circuit 12 will be described.

  In the case of this embodiment, the current mirror circuit 14 includes two P-type MOS transistors (PMOS) 14a and 14b having the same transistor size. The sources of the PMOSs 14a and 14b are connected to a power source. Also, the drain side terminal of the PMOS 14a is connected to the control pin 20, and the drain of the PMOS 14b is connected to the ground via a resistor 18a described later.

  Since the output of the operational amplifier 16 is commonly input to the gates of the two PMOSs 14a and 14b constituting the current mirror circuit 14 as described below, an equal current flows through the PMOSs 14a and 14b.

  The operational amplifier 16 receives the reference voltage Vref and the voltage at the drain side terminal of the PMOS 14a. The operational amplifier 16 controls the drain current Iref flowing through the PMOS 14a by the output so that the voltage of the drain side terminal of the PMOS 14a matches the reference voltage Vref. The output of the operational amplifier 16 is input to the gates of the two PMOSs 14 a and 14 b constituting the current mirror circuit 14.

  The reference voltage Vref is generated inside the semiconductor integrated circuit 10 using, for example, a band gap reference circuit (BGR circuit) or the like, and is a constant voltage that does not depend on parameters such as temperature, power supply voltage, and process variation.

  Here, the resistance value of the external resistor 22 is Rext, and the voltage at the control pin 22 is Vp. As described above, the operational amplifier 16 performs feedback control so that the voltage at the drain side terminal of the PMOS 14a, that is, the voltage Vp at the control pin 22 is exactly equal to the reference voltage Vref. Therefore, the drain current Iref flowing through the PMOS 14a is expressed by Iref = Vp / Rext.

  Since Vp (= Vref) and Rext are constant without depending on parameters such as temperature, power supply voltage, process fluctuation, etc., the current Iref is constant regardless of fluctuation of these parameters, and depends on the resistance value of the external resistor 22. Only changes. As described above, since the PMOSs 14a and 14b constitute the current mirror circuit 14, a current Iref equal to the PMOS 14a flows through the PMOS 14b.

  Finally, the AD conversion circuit 18 outputs a digital signal corresponding to the current flowing through the PMOS 14b in accordance with the current Iref flowing through the PMOS 14a. In the case of the present embodiment, the AD conversion circuit 18 outputs a built-in resistor 18a that converts the current flowing through the PMOS 14b into a voltage Vo, and a digital signal (switching signal) corresponding to the voltage Vo converted by the resistor 18a. Type analog-to-digital converter (AD converter (ADC)) 18b.

  Next, the operation of the test control circuit 12 will be described.

  The current Iref flowing through the PMOS 14a constituting the current mirror circuit 14 is determined by the resistance value of the external resistor 22 (signal input from the control pin 20). When the resistance value of the external resistor 22 is determined, the operational amplifier 16 performs feedback control so that the voltage Vp at the control pin 22 is exactly equal to the reference voltage Vref. As a result, the current Iref flowing through the PMOSs 14a and 14b is changed. It is determined.

  When the current Iref flowing through the PMOS 14b is determined, the voltage Vo converted by the built-in resistor 18a is determined accordingly. The voltage Vo is converted into a digital signal having a predetermined number of bits by the ADC 18b.

  As described above, the current Iref flowing through the PMOSs 14 a and 14 b constituting the current mirror circuit 14 can be changed by the resistance value of the external resistor 22. Therefore, by changing the resistance value of the external resistor 22, the current Iref can be changed. As a result, the voltage Vo can be changed, and the value of the digital signal output from the ADC 18b can be changed. .

  For example, if the number of test modes is seven, a total of eight operation modes including the normal operation mode may be switched by the value of the digital signal. In this case, if the number of bits of the digital signal is 3 bits, the value of the digital signal is changed to '000', '001', '010', '011', 'by changing the resistance value of the external resistor 22. It changes as “100”, “101”, “110”, and “111”.

  Here, for example, the case where the value of the digital signal is '000' is assigned to the normal operation mode. Also, seven cases from “001” to “111” are assigned to seven test modes. In this manner, in the semiconductor integrated circuit 10, the normal operation mode and a plurality of tests are performed according to the value of the digital signal (switching signal) output from the AD conversion circuit 18 by appropriately changing the resistance value of the external resistor 22. Mode switching can be performed.

  As described above, in the semiconductor integrated circuit 10, it is possible to freely switch between the normal operation mode and the plurality of test modes, that is, the plurality of operation modes, only by changing the resistance value of the external resistor 22. In addition, since it is not necessary to mount a dedicated circuit such as a signal generator on the evaluation board 24 in order to switch the operation mode, only one control pin is required, so the number of external connection terminals of the semiconductor integrated circuit 10 The cost can be reduced.

  The external resistor 22 is preferably a variable resistor. By using a variable resistor as the external resistor 22, it is possible to eliminate the trouble of replacing the resistor 22 and change the test time in order to change the resistance value of the external resistor 22. The test control circuit 12 is suitable for switching between a normal operation mode and a plurality of test modes, but can also be applied to a case where there is one test mode.

  The current mirror circuit 14 is not limited to the configuration of the PMOSs 14a and 14b, and various configurations having similar functions can be used. Further, in the circuit example of FIG. 1, the transistor sizes of the PMOSs 14a and 14b may be changed to change the ratio of the current flowing through them.

  The AD conversion circuit 18 may be a current input type AD converter that outputs a digital signal corresponding to the current flowing through the PMOS 14b. By using the current input type AD converter, the resistor 18a can be omitted.

  In the example shown in FIG. 1, the sources of the PMOSs 14a and 14b constituting the current mirror circuit 14 are connected to the power source, and one terminal of the external resistor 22 and the built-in resistor 18a is connected to the ground. On the other hand, the current mirror circuit 14 may be constituted by two N-type MOS transistors (NMOS), the source of the NMOS is connected to the ground, and one terminal of the resistors 22 and 18a is connected to the power source. .

The present invention is basically as described above.
Although the present invention has been described in detail above, the present invention is not limited to the above-described embodiment, and it is needless to say that various improvements and modifications may be made without departing from the gist of the present invention.

It is the schematic of one Embodiment showing the structure of the semiconductor integrated circuit of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor integrated circuit 12 Test control circuit 14 Current mirror circuit 14a, 14b P-type MOS transistor (PMOS)
16 operational amplifier 18 analog-digital conversion circuit (AD conversion circuit)
18a Built-in resistor 18b Analog to digital converter (AD converter)
20 Control pin (external connection terminal)
22 External resistor

Claims (3)

A semiconductor integrated circuit including a test control circuit that switches between a normal operation mode and a plurality of test modes according to a signal input from an external connection terminal,
The test control circuit comprises:
A current mirror circuit having first and second transistors;
An operational amplifier that controls a current flowing through the first transistor so that a voltage of a terminal of the first transistor connected to the external connection terminal matches a reference voltage;
An analog-to-digital conversion circuit that outputs a digital signal corresponding to the current flowing through the second transistor in response to the current flowing through the first transistor;
A semiconductor integrated circuit, wherein the normal operation mode and a plurality of test modes are switched by a digital signal output from the analog-digital conversion circuit.   The analog-to-digital conversion circuit includes a resistor that converts the current flowing through the second transistor into a voltage, and a voltage input type analog-to-digital converter that outputs a digital signal corresponding to the voltage converted by the resistor. The semiconductor integrated circuit according to claim 1.   2. The semiconductor integrated circuit according to claim 1, wherein the analog-to-digital conversion circuit includes a current input type analog-to-digital converter that outputs a digital signal corresponding to a current flowing through the second transistor.

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