JP2010087234A - Nonvolatile semiconductor memory and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the chip size of a nonvolatile semiconductor memory. <P>SOLUTION: The nonvolatile semiconductor memory includes a memory cell transistor that has a stacked gate composed of a floating gate electrode and a control gate electrode and a resistor element. The resistor element has a resistive layer 30 formed of the same material as that of the floating gate electrode and contact layers 50A and 50B formed at one and other ends of the resistive layer 30, respectively. The resistive layer 30 includes at least two first portions 31A and 31B and at least one second portion 32 having a thickness smaller than those of the first portions 31A and 31B. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory, and more particularly to a structure of a resistance element used in a flash memory and a manufacturing method thereof.

  Nonvolatile semiconductor memories, such as flash memories, are mounted on various electronic devices. A flash memory is composed of a circuit including a transistor and a resistance element. Resistive elements are required to have a high resistance value with a small size and to have stable characteristics because of a reduction in chip size, and various manufacturing methods are being studied (for example, Patent Document 1). reference).

  One of them is a technique in which the resistor of the resistance element is formed simultaneously with the same material as the floating gate electrode of the memory cell transistor.

  However, in order to prevent the gate from being depleted, a polysilicon film having a high impurity concentration and a low resistivity is used for the floating gate electrode. Therefore, a resistor using the same material as that of the floating gate electrode has to be used with a high impurity concentration, and the resistivity of the resistor is lowered. Therefore, in order to obtain a high resistance value from this resistor, the length of the resistor must be increased. Therefore, the area occupied by the resistive element on the chip increases.

Further, when adjusting the resistance value by the length of the resistor, if the resistance value of the resistance element formed on the semiconductor substrate is different from the desired resistance value in the design, the desired resistance value is obtained. The length or line width of the resistance value must be adjusted, and the layout in the exposure mask needs to be redesigned.
JP 2007-266499 A

  The present invention proposes a technique for reducing the chip size of a nonvolatile semiconductor memory.

  A nonvolatile semiconductor memory according to an example of the present invention is a nonvolatile semiconductor memory including a memory cell transistor having a stacked gate structure including a floating gate electrode and a control gate electrode, and a resistance element, wherein the resistance element is A first insulating film provided on the semiconductor substrate; a resistance layer provided on the first insulating film; and two openings provided on the resistance layer, made of the same material as the floating gate electrode. A second insulating film and a contact layer made of the same material as the control gate electrode and provided on one end and the other end of the resistance layer through the opening of the second insulating film, respectively. The resistance layer includes at least two first portions, and at least one second portion having a thickness smaller than the thickness of the first portion; Which comprise.

  A method for manufacturing a nonvolatile semiconductor memory according to an embodiment of the present invention is a method for manufacturing a nonvolatile semiconductor memory including a memory cell transistor having a stacked gate structure including a floating gate electrode and a control gate electrode and a resistance element. A step of forming a resistance layer made of the same material as the floating gate electrode on the first insulating film on the surface of the semiconductor substrate in the resistance element region; and two openings on the resistance layer. Forming a second insulating film; forming a conductive layer made of the same material as the control gate electrode on the second insulating film; separating the conductive layer by etching; Two contact layers connected to the resistance layer through the opening of the insulating film are formed, and at the same time, the resistance layer is formed. Thinning by a self-aligned manner with said etched relative Ntakuto layer comprises at least two first portions, and forming at least one second part which is thinned by the etching.

  According to the present invention, the chip size of the nonvolatile semiconductor memory can be reduced.

  Hereinafter, embodiments for carrying out examples of the present invention will be described in detail with reference to the drawings.

1. Overview
Embodiments described herein relate generally to a resistance element used in a nonvolatile semiconductor memory, for example, a flash memory.

In the flash memory according to the embodiment of the present invention, the memory cell is a MOS (Metal-Insulator-Semiconductor) transistor having a stacked gate structure including a floating gate electrode and a control gate electrode.
In the resistance element according to the embodiment of the present invention, a conductive layer made of the same material as that of the floating gate electrode is used as a resistor (hereinafter referred to as a resistance layer).

  In the resistance element according to the embodiment of the present invention, the resistance layer includes a first portion and a second portion having a thickness smaller than that of the first portion.

  The resistance value of the resistance element is proportional to the length and impurity concentration of the resistance layer, and inversely proportional to the cross-sectional area of the resistance layer. The cross-sectional area of the resistance layer is defined by the line width of the resistance layer and the film thickness of the resistance layer.

  According to the embodiment of the present invention, the thickness of the second portion of the resistance layer is thin, and the cross-sectional area of the second portion is smaller than the cross-sectional area of the first portion of the resistance layer. For this reason, the resistance value of the second portion is higher than the resistance value of the first portion, and as a result, the resistance value of the entire resistance layer is increased.

  As described above, the resistance element according to the embodiment of the present invention can obtain a high resistance value without reducing the impurity concentration of the resistance layer and without increasing the length of the resistance layer.

  Therefore, according to the embodiment of the present invention, the chip size of the nonvolatile semiconductor memory can be reduced.

2. Embodiment
(1) First embodiment
A nonvolatile semiconductor memory according to the first embodiment of the present invention will be described with reference to FIGS.

(A) Configuration
FIG. 1 shows the overall configuration of the nonvolatile semiconductor memory according to this embodiment. The nonvolatile semiconductor memory according to the present embodiment is, for example, a flash memory.

  As shown in FIG. 1, the flash memory 50 includes a memory cell array 100 and peripheral circuits 102, 103, 104, and 200 arranged around the memory cell array 100.

  A plurality of memory cells are arranged in the memory cell array 100. The peripheral circuit includes, for example, a word line / select gate line driver 102, a sense amplifier 103, and a control circuit 104. The word line / select gate line driver 102 controls the operation of a plurality of word lines provided in the memory cell array 100. The sense amplifier 103 senses data in the selected memory cell. The control circuit 104 controls the operation of the entire flash memory.

  A resistance element region 200 is provided in the flash memory 50, for example, in the vicinity of the control circuit 104, and a plurality of resistance elements are provided in the resistance element region 200.

  The structure in the memory cell array 100 and the resistance element region 200 will be described with reference to FIGS.

  2 to 4 show the structure of the memory cell array 100. FIG. FIG. 2 illustrates a planar structure of the memory cell array 100. 3 illustrates a cross-sectional structure taken along line III-III in FIG. 2, and FIG. 4 illustrates a cross-sectional structure taken along line IV-IV in FIG.

  As shown in FIG. 2, in the memory cell array 100 of the flash memory, the surface region of the semiconductor substrate 1 is adjacent to the element isolation region STI in which an element isolation insulating film having an STI (Shallow Trench Isolation) structure is embedded in the x direction. The active area AA is sandwiched between two element isolation areas. The element isolation region STI and the active region AA extend in the y direction orthogonal to the x direction. On the active area AA, a plurality of memory cells MC and select transistors ST1, ST2 are provided.

  In the present embodiment, a plurality of memory cells MC connected in series along the y direction are arranged on the active area AA, and connected to one end and the other end of the plurality of memory cells MC connected in series. The selection transistors ST1 and ST2 are arranged. Hereinafter, the plurality of memory cells connected in series are referred to as a memory cell string, and the memory cell string and the select transistors ST1 and ST2 connected to one end and the other end thereof are referred to as a memory cell unit.

  The plurality of memory cells MC adjacent in the x direction are commonly connected to the word lines WL1 to WLn extending in the x direction, and the select transistors ST1 and ST2 adjacent in the x direction are connected in the x direction. Are connected to the common select gate lines SGDL and SGDL extending to One bit line BL extending in the y direction is connected to one end of one memory cell unit via a bit line contact BC, and a source line SL is connected to the other end of the memory cell unit. Connected via contact SC.

  As shown in FIGS. 3 and 4, the memory cell MC (hereinafter referred to as a memory cell transistor) is a stacked gate MOS (Metal-Insulator-Semiconductor) transistor, and the gate structure of the memory cell transistor MC is a floating gate electrode. 3A and the control gate electrode 5A are stacked through an inter-gate insulating film 4A.

  The gate insulating film 2A of the memory cell transistor MC is provided on the surface of the semiconductor substrate 1 (active area AA). In the memory cell transistor MC, the gate insulating film 2A functions as the tunnel insulating film 2A.

The floating gate electrode 3A is provided on the tunnel insulating film 2A on the surface of the semiconductor substrate 1. The floating gate electrode 3A functions as a charge storage layer for holding data written in the memory cell, and is made of, for example, a polysilicon film. The impurity concentration of the polysilicon film serving as the floating gate electrode 3A is increased so that the gate of the floating gate electrode 3A is not depleted when a voltage is applied to the gate electrode of the memory cell transistor MC. It is set to about ²⁰ / cm ³ .

  The inter-gate insulating film 4A is provided on the floating gate electrode 3A. For the inter-gate insulating film 4A, for example, an ONO (Oxide-Nitride-Oxide) film or a high dielectric insulating film such as hafnium oxide or aluminum oxide is used.

A control gate electrode 5A is provided on the inter-gate insulating film 4A. For example, a silicide film is used for the control gate electrode 5A in order to reduce the resistance. However, the present invention is not limited to this, and a single-layer structure of a polysilicon film or a two-layer structure (polycide structure) in which a polysilicon film and a silicide film are stacked on the polysilicon film may be used. As the silicide film, for example, a tungsten silicide film (WSi ₂ ), a molybdenum silicide film (MoSi ₂ ), a cobalt silicide film (CoSi ₂ ), a titanium silicide film (TiSi ₂ ), a nickel silicide film (NiSi ₂ ), or the like is used. .

  The control gate electrode 5A functions as the word line WL and is shared between memory cell transistors adjacent in the x direction as described above. Therefore, as shown in FIG. 4, the control gate electrode 5A is provided not only on the floating gate electrode 3A but also on the element isolation insulating film 8 in the element isolation insulating region STI via the inter-gate insulating film 4A. ing.

  Since the upper end of the element isolation insulating film 8 is located at a position lower than the upper end of the floating gate electrode 3A (on the semiconductor substrate side), the side surface in the x direction (channel width direction) of the floating gate electrode 3A defines the inter-gate insulating film 4A. Thus, the structure is covered with the control gate electrode 5A. Therefore, the facing surface of the floating gate electrode 3A and the control gate electrode 5A is secured not only on the upper surface of the floating gate electrode 3A but also on the side surface thereof, thereby improving the coupling ratio of the memory cell transistor MC.

  A diffusion layer 7A (hereinafter referred to as a source / drain diffusion layer) functioning as a source / drain region of the memory cell MC is provided in the semiconductor substrate 1. The diffusion layer 7A is shared between the memory cell transistors MC adjacent in the y direction (channel length direction), whereby the current paths (channels) of the plurality of memory cell transistors MC are connected in series.

  Select transistors ST1 and ST2 are respectively provided at one end and the other end of a plurality of memory cell transistors MC (memory cell strings) connected in series.

  Select transistors ST1 and ST2 are formed simultaneously with the memory cell transistor MC. Therefore, similarly to the memory cell transistor MC, the gate structure of the select transistors ST1, ST2 is a structure in which two gate electrodes (conductive layers) 3B, 5B are stacked via an inter-gate insulating film 4B. However, in the select transistors ST1 and ST2, the inter-gate insulating film 4B has an opening P, and through this opening P, the gate electrode 3B on the gate insulating film 2B and the gate electrode on the inter-gate insulating film 4B. 5B is connected. The select transistors ST1, ST2 share the source / drain diffusion layer 7A with the adjacent memory cell transistor MC. As a result, the plurality of memory cell transistors MC and the select transistors ST1, ST2 are connected in series in the y direction to constitute one memory cell unit.

  In this memory cell unit, the source / drain diffusion layer 7D of the select transistor ST1 located on the drain side of the memory cell string is composed of a bit line contact portion BC, a wiring layer M0, and a via embedded in the interlayer insulating films 10A and 10B. It is connected to the bit line BL via the contact V1. Further, the diffusion layer 7S of the select transistor ST2 located on the source side of the memory cell string is connected to the source line SL via the source line contact SC embedded in the interlayer insulating films 10A and 10B. For example, aluminum (Al) or copper (Cu) is used for the bit line BL, the source line SL, and the wiring layer M0, and the bit line contact BC and the source line contact SC are, for example, tungsten (W) or molybdenum (Mo). Is used.

  5 to 8 show the structure of the resistance element. FIG. 5 illustrates a planar structure of the resistance element. FIG. 6 shows a cross-sectional structure taken along line VI-VI in FIG. 7 illustrates a cross-sectional structure taken along line VII-VII in FIG. 5, and FIG. 8 illustrates a cross-sectional structure taken along line VIII-VIII in FIG. In addition, although one resistance element is illustrated and demonstrated here, it is not limited to this number.

As shown in FIGS. 5 to 8, the resistance layer 30 of the resistance element has a predetermined length L and width W, and is surrounded by the element isolation insulating film 80 via the first insulating film 2. It is provided above. The resistance layer 30 functions as a resistor of the resistance element. Since the resistance element is formed simultaneously with the memory cell transistor MC, the resistance layer 30 is made of the same material (for example, polysilicon) as the floating gate electrode 3A of the memory cell transistor MC. The resistance layer 30 includes first portions 31A and 31B having a film thickness T1 and a second portion 32A having a film thickness T2 smaller than the film thickness T1. The first portion 31A, the thickness T1 of 31B is, for example, the same thickness as the thickness _{T FG} of the floating gate electrode 3A. In the example shown in FIG. 6, two first portions 31A and 31B are provided in the resistance layer 30, and a second portion 32A is provided between the two first portions 31A and 31B.

On the resistance layer 30, two conductive layers 50 </ b> A and 50 </ b> B are provided via the second insulating film 40. The conductive layer 50 is made of the same material (for example, a silicide film) as the control gate electrode of the memory cell MC.
The conductive layers 50A and 50B provided on the resistance layer 3 are electrically connected to the resistance layer 30 through the opening Q provided in the second insulating film 40, and the wiring layer M0 and the resistance layer 30 are connected to each other. It functions as a contact for connecting. As described above, the conductive layers 50A and 50B functioning as contacts are hereinafter referred to as contact layers 50A and 50B. The contact layers 50A and 50B are provided on the first portions 31A and 31B in the resistance layer 30.

The resistance layer 30 and the contact layers 50A and 50B are covered with the interlayer insulating films 10A and 10B. Contact plugs CP are embedded in the interlayer insulating films 10A and 10B, and the contact plugs CP are connected to the contact layers 50A and 50B. The contact plug CP is made of, for example, tungsten or molybdenum. The contact plug CP is connected to the first wiring layer M0 in the interlayer insulating film 12.
The interlayer insulating film 10A is buried between the two contact layers 50A and 50B and is in contact with the upper surface of the second portion 32A of the resistance layer 30.

  In the flash memory as the nonvolatile semiconductor memory according to the first embodiment of the present invention, the resistance layer 30 of the resistance element has the first portions 31A and 31B having the film thickness T1 and the film thickness T2 smaller than the film thickness T1. The second portion 32A is included.

The resistance value of the resistance element is proportional to the resistivity ρ and the length L of the resistance layer 30 and inversely proportional to the cross-sectional areas S1 and S2 of the resistance layer 30. The cross-sectional areas S1 and S2 are products of the film thicknesses T1 and T2 and the width W of the resistance layer 30.
In the present embodiment, since the film thickness T2 of the second portion 32A of the resistance layer 30 is smaller than the film thickness T1 of the first portions 31A and 31B, the cross-sectional area S2 (= W × T2) of the second portion 30B is The cross-sectional area S1 (= W × T1) of the first portion 30A is smaller. As a result, the resistance value of the second portion 32A is larger than the resistance values of the first portions 31A and 31B. Therefore, the resistance layer 30A has a configuration in which the first portions 31A and 31B and the second portion 30B are connected in series, so that the resistance value of the entire resistance layer 30 is improved.
As described above, since the resistance layer 30 includes the thin second portion 32A, a high resistance value can be obtained without increasing the length of the resistance layer 30. Therefore, the size of the resistance element region 200 can be reduced, which can contribute to the reduction of the chip size.

Further, the resistivity ρ of the resistance layer 30 is determined by the impurity concentration of the material constituting the resistance layer 30. In order to increase the resistivity ρ, the impurity concentration of the resistance layer must be decreased. When the resistance layer 30 and the floating gate electrode 3A are simultaneously formed using a material having a low impurity concentration, depletion of the gate of the floating gate electrode 3A becomes a problem.
If the floating gate electrode 3A and the resistance layer 30 are made of different materials in order to avoid depletion of the floating gate electrode 3A and increase the resistance of the resistance layer 30A, the floating gate electrode 3A and the resistance layer 30 Must be formed in different processes, increasing the number of manufacturing processes.

  On the other hand, the resistance element of this embodiment reduces the resistance value of the resistance element by reducing the film thickness of a part of the resistance layer 30 instead of reducing the impurity concentration of the floating gate electrode 3A and the resistance layer 30. It is high. Therefore, the floating gate electrode 3A and the resistance layer 30 can be formed at the same time using a material having an impurity concentration that can prevent the gate of the floating gate electrode 3A from being depleted.

  Thus, the resistance element of the present embodiment can obtain a high resistance value without increasing the size of the resistance element region by thinning a part (second part) 32A of the resistance layer 30. In addition, since the resistance value of the resistance element of this embodiment is increased, there is no adverse effect on the memory cell transistor such as depletion of the gate of the floating gate electrode, so that the characteristics of the memory cell are not deteriorated. In addition, the number of flash memory manufacturing processes does not increase.

  As described above, according to the nonvolatile semiconductor memory (flash memory) according to the first embodiment of the present invention, the chip size of the nonvolatile semiconductor memory can be reduced.

(B) Manufacturing method
A manufacturing process of the nonvolatile semiconductor memory (flash memory) according to the first embodiment of the present invention will be described with reference to FIGS.

First, the manufacturing process of the nonvolatile semiconductor memory of this embodiment will be described with reference to FIG. FIG. 9 is a cross-sectional view taken along the y direction for explaining one process of manufacturing the memory cell array 100 and the resistive element region 200.
As shown in FIG. 9, the insulating film 2 to be the gate insulating film of the memory cell transistor is formed on the semiconductor substrate 1 in the memory cell array 100 and the resistive element region 200 by, for example, a thermal oxidation method.
Then, the first polysilicon films 3 and 30 serving as the floating gate electrode of the memory cell transistor and the resistance layer of the resistance element are formed by, for example, an insulating film in the memory cell array 100 and the resistance element region 200 by a CVD (Chemical Vapor Deposition) method. 2 is formed. Since the polysilicon films 3 and 30 are simultaneously formed in the memory cell array 100 and the resistance element region 200, they have the same impurity concentration. The impurity concentration of the polysilicon films 3 and 30 is an impurity concentration at which the floating gate electrode is not depleted during the operation of the memory cell transistor, and is, for example, about 10 ²⁰ / cm ³ .

  Next, the manufacturing process following FIG. 9 will be described with reference to FIGS. FIG. 10 is a cross-sectional view along the x direction for explaining one process of manufacturing the memory cell array 100 and the resistive element region 200. 11 is a cross-sectional view taken along the y direction for explaining one process of the manufacturing process of the memory cell array 100, and FIG. 12 is taken along the y direction for explaining one process of the manufacturing process of the resistance element region 200. It is sectional drawing.

  As shown in FIGS. 10 to 12, element isolation grooves Z <b> 1 and Z <b> 2 are formed in the semiconductor substrate 1 in the memory cell array 100 and the resistance element region 200. In the memory cell array 100, a plurality of elements are formed in the semiconductor substrate 1 by using, for example, a photolithography technique and an RIE (Reactive Ion Etching) method so that a plurality of active areas AA having a predetermined x-direction size are formed. A separation groove Z1 is formed.

  Further, in the resistance element region 200, the element isolation groove Z2 is formed in the semiconductor substrate 1 so that the size of the resistance element in the x direction and the y direction, that is, the width W and the length L of the resistance layer have a predetermined size. Formed. The element isolation insulating films 8 and 80 are embedded in the formed element isolation grooves Z1 and Z2. Then, the element isolation film 8 formed in the memory cell array 100 is etched until, for example, the side surface in the x direction of the polysilicon film 3 is exposed.

  Subsequently, an insulating film 4 serving as an inter-gate insulating film of the memory cell transistor is formed on the polysilicon films 3 and 30 in the memory cell array 100 and the resistance element region 200. As the insulating film 4, for example, a high dielectric insulating film such as an ONO film, a hafnium oxide film, or an aluminum oxide film is used. A single layer film of a silicon oxide film or a silicon nitride film may be used. In addition, an opening P is formed in the insulating film 4 in the select transistor formation region of the memory cell array 100. At the same time, an opening Q is formed in the insulating film (second insulating film) 40 also in the contact formation region of the resistance element region 200.

In the memory cell array 100 and the resistive element region 200, second polysilicon films (conductive layers) 5, 50A, 50B are deposited on the insulating films 4, 40, and further, resist masks 90A, 90B are formed on the polysilicon film 5, 50 is formed. Then, in the resistance element region 200, the resist mask 90B is subjected to patterning in order to separate the polysilicon films 50A and 50B into at least two portions.
Using the resist mask 90B as a mask, the second polysilicon films 50A and 50B in the resistance element region 200 are etched using, for example, the RIE method. Thus, the second polysilicon films 50A and 50B are divided into two parts 50A and 50B, and the two separated parts 50A and 50B become contact layers, respectively.
At this time, the insulating film 40 and the first polysilicon film 30 in the resistance element region 200 are also etched using the resist mask 90B as a mask. As a result, the first polysilicon film 30 serving as the resistance layer is self-aligned with the formed contact layers 50A and 50B. The first portions 31A and 31B that are not etched and the second portions that are thinned by etching. 32A is included. The first portions 31A and 31B that are not etched have a thickness T1, and the etched second portion 32A has a thickness T2 that is smaller than the thickness T1. The film thickness T1 is, for example, the same film thickness as the film thickness _TFG of the first polysilicon film 3 in the memory cell array 100.
In the memory cell array 100, the second polysilicon film 5 and the underlying film are not etched because they are covered with the resist mask 90A.

  After removing the resist masks 90A and 90B, a new resist mask is formed, and gate processing is performed on the memory cell array 100 as shown in FIGS. A long floating gate electrode 3A, a control gate electrode 5A, and gate electrodes 3B and 5B of selection transistors are formed. Then, using the formed stacked gates 3A, 5A, 3B, and 5B as masks, the source / drain diffusion layers 7A, 7B, and 7C of the memory cell transistor MC and the select transistors ST1 and ST2 are formed in the semiconductor substrate 1 of the memory cell array 100. For example, it is formed by an ion implantation method. During the gate processing and the formation of the source / drain diffusion layer for the memory cell array 100, the resistance element region 200 is covered with a resist mask.

  After forming the memory cell transistor MC and the select transistors ST1 and ST2, interlayer insulating films 10A and 10B are deposited on the semiconductor cell array 100 and the semiconductor substrate 1 in the resistance element region 200.

  Here, when the control gate electrode 5A has a single layer structure (full silicide structure) of a silicide film or a stacked structure (polycide structure) of a silicide film and a polysilicon film, the control gate electrode 5A is stacked by an interlayer insulating film 10A. After the entire gates 3A, 5A, 3B, 5B are covered, the upper portion of the interlayer insulating film 10A is removed using, for example, the RIE method so that the upper portions of the control gate electrodes (polysilicon films) 5A, 5B are exposed. Is done. Then, for example, any one metal of cobalt (Co), tungsten (Wi), or nickel (Ni) is deposited on the exposed polysilicon films 5A and 5B, and the polysilicon film is heated by a predetermined condition. Silicidation is performed. As a result, a control gate electrode 5B having a full silicide structure or a polycide structure is formed. Then, after the metal film that has not reacted with the polysilicon is removed, an interlayer insulating film 10B is formed on the interlayer insulating film 10A and the gate electrodes 5A and 5B. For example, the silicidation of the control gate electrode 5B is simultaneously performed on the resistance element region 200. In the resistance element region 200, the contact layers 50A and 50B are silicided.

  Contact holes are formed in the interlayer insulating films 10A and 10B deposited on the semiconductor substrate 1, and bit line contacts BC, source line contacts SC and contact plugs CP are embedded in the contact holes.

  In the memory cell array 100, the wiring layer M0 is connected to the bit line contact BC, and the source line SL is connected to the source line contact SC. In the resistance element region 200, the wiring layer M0 is connected to the contact plug CP.

Further, the second interlayer insulating film 11 is formed on the first interlayer insulating films 10A and 10B. A via contact V1 is buried in the contact hole formed in the second interlayer insulating film 11, and the bit line BL is connected to the via contact V1.
The flash memory according to this embodiment is completed through the above steps.

  In the present embodiment, when the second polysilicon films 50A and 50B in the resistance element region 200 are separated into two contact layers 50A and 50B by using the RIE method, the first polysilicon film in the resistance element region 200 is used. 30 is also etched to form a second portion 32A having a thickness T2 that is smaller than the thickness T1 of the first portions 31A and 31B of the first polysilicon film 30.

  Thereby, the cross-sectional area of the second portion 32A becomes smaller than the cross-sectional area of the first portions 31A and 31B, and the resistance value of the second portion 32A becomes larger than the resistance values of the first portions 31A and 31B. That is, the resistance value of the entire resistance layer (first polysilicon film 30) increases.

  Therefore, according to the present embodiment, the impurity concentration of the polysilicon films 3 and 30 serving as the floating gate electrode and the resistance layer is increased (resistance) so that the gate is not depleted in the floating gate electrode 3A of the memory cell transistor. Even if the rate is reduced, the resistance value of the resistance layer 30 can be increased by reducing the thickness of the resistance layer 30.

  Further, according to the present embodiment, the first polysilicon film to be the floating gate electrode 3A and the resistance layer 30 can be formed at the same time, and further, the formation process of the second portion 32A in the resistance layer 30 (thinning of the resistance layer). Is performed simultaneously with the step of forming the contact layers 50A and 50B (separation of the second polysilicon film), so that the number of manufacturing steps is not increased.

  Therefore, a nonvolatile semiconductor memory having a small chip size can be provided by the manufacturing method described in the first embodiment of the present invention.

(2) Second embodiment
A second embodiment of the present invention will be described with reference to FIGS. In addition, the same code | symbol is attached | subjected about the same member as 1st Embodiment, and the description of the member is demonstrated as needed. Further, since the structure in the memory cell array 100 is the same as that shown in FIGS. 2 to 4, the description thereof in this embodiment is omitted.

FIG. 13 illustrates a cross-sectional structure along the y direction of the resistance element of the nonvolatile semiconductor memory of the present embodiment. The cross-sectional structure along the x direction of the present embodiment is the same as the structure shown in FIGS.
As shown in FIG. 13, the resistance layer 30 of the resistance element of the present embodiment has a plurality of second portions 32A and 32B. More specifically, the structure of the resistance layer 30 includes, in addition to the two first portions 31A and 31B at one end and the other end of the resistance layer 30, another first portion between the first portions 31A and 31B at both ends. 31C is provided, and second parts 32A and 32B are provided between these three first parts 31A, 31B, and 31C, respectively. That is, in this example, the resistance layer 30 includes two second portions 32A and 32B.

  Of the plurality of first portions 31A, 31B, and 31C included in the resistance layer 30, the second insulating film 40 is formed on the first portion 31C except for the first portions 31A and 31B connected to the contact layers 50A and 50B, respectively. A conductive layer 50C is provided via the. The conductive layer 50C is made of the same material as the control gate electrode 5A and the contact layers 50A and 50B.

  The conductive layer 50C is a dummy layer that does not function electrically and is separated from the contact layers 50A and 50B when the second portions 32A and 32B are formed in the manufacturing process described in the first embodiment. Hereinafter, a conductive layer having no electrical function, such as the conductive layer 50C, is referred to as a dummy layer 50C. The plurality of second portions 32A and 32B are formed in a self-aligned manner with respect to the contact layers 50A and 50B and the dummy layer 50C.

  As shown in FIG. 14, the resistance layer 30 may include three or more second portions 32A, 32B, 32C, and 32D. In this case, since the formation process of the second portions 32A to 32D is performed simultaneously with the formation process (separation of the conductive layers) of the contact layers 50A and 50B, the first portions 31C, 31D, and 31E and the first portions 31C and 31D. , 31E also increases the number of dummy layers 50C.

In the present embodiment, the resistance layer 30 includes a plurality of second portions 32A to 32D having a film thickness T1 that is smaller than the film thickness T1 of the first portions 31A to 31E. A resistance value higher than that of the resistance element of the first embodiment can be obtained.
Further, as in the present embodiment, the resistance value of the resistance element can be reduced by increasing or decreasing the number of the second portions 32A and 32B or changing the size of the second portions 32A to 32D in the y direction. It can be adjusted to a predetermined resistance value for ensuring stable operation of the memory.

  Furthermore, in the resistance element of the present embodiment, the manufacturing method is substantially the same as the manufacturing process described in the first embodiment, and a plurality of second portions 32A to 32D are formed in the resistance layer 30. However, only the number of locations to be etched increases, and the formation process can be executed at a time by the manufacturing process shown in FIG. 12 of the first embodiment. Further, in the present embodiment, it is only necessary to change the mask pattern in the resistance element formation region, that is, to change the number or size of the opening pattern at the portion where the resistance layer 30 is etched. There is no need to redesign the mask so that the layout of the mask pattern is greatly changed with the change.

  Therefore, according to the nonvolatile semiconductor memory of the second embodiment of the present invention, the chip size of the nonvolatile semiconductor memory can be reduced as in the first embodiment. In addition, according to the nonvolatile semiconductor memory of the second embodiment of the present invention, the operation of the nonvolatile semiconductor memory can be stabilized. Furthermore, the production efficiency of the nonvolatile semiconductor memory can be improved.

(3) Third embodiment
A nonvolatile semiconductor memory according to the third embodiment of the present invention will be described with reference to FIG. The same members as those of the nonvolatile semiconductor memory according to the first and second embodiments are denoted by the same reference numerals, and detailed description will be given as necessary. Also, since the structure in the memory cell array 100 is the same as that shown in FIGS. 2 to 4, the detailed description of this modification is omitted.

FIG. 15 illustrates a cross-sectional structure along the y direction of the resistance element of the nonvolatile semiconductor memory of the present embodiment. The cross-sectional structure along the x direction of the present embodiment is the same as the structure shown in FIGS.
In the resistance element of the present embodiment, the first portions 31A and 31B included in the resistance layer 30 are only provided immediately below the contact layers 50A and 50B, and the entire portion between the two first portions 31A and 31B is the second portion. 32A.

  As a result, the resistance value of the resistance element of the present embodiment is higher than the resistance value of the resistance element described in the first and second embodiments.

  Therefore, as in this embodiment, in the resistance layer 30 made of the same material as the floating gate electrode, the first portions 31A and 32B are provided at both ends thereof, and the entire portion between the two first portions 31A and 31B is provided. By setting the second portion 32A as the second portion 32A and increasing the dimension in the y direction of the second portion 32A, the resistance value of the resistance element can be improved.

  In addition, in this process, in the step shown in FIG. 12, the resist mask 90B is patterned so as to remove the conductive layer on the insulating film 40 other than the portion to be the contact layer, and the contact layers 50A and 50B are formed. A part of the resistance layer 30 may be etched to form a second portion 32A having a thickness T2 that is smaller than the thickness T1 of the first portions 31A and 31B. Therefore, the manufacturing process is not increased and complicated, and there is no need to redesign the mask with a large layout change.

  Therefore, according to the third embodiment of the present invention, the chip size of the nonvolatile semiconductor memory can be reduced as in the first and second embodiments. Moreover, according to the third embodiment of the present invention, the production efficiency of the nonvolatile semiconductor memory can be improved as in the second embodiment.

(4) Modification
A nonvolatile semiconductor memory according to a modification of the embodiment of the present invention will be described with reference to FIG. The same members as those in the nonvolatile semiconductor memory according to the first to third embodiments are denoted by the same reference numerals, and detailed description will be given as necessary. Also, since the structure in the memory cell array 100 is the same as that shown in FIGS. 2 to 4, the detailed description of this modification is omitted.

  FIG. 16 shows a resistance element according to a modification of the embodiment of the present invention.

  As shown in FIG. 16, the resistance layer 30 of the resistance element may be provided on the insulating film 20 having a thickness larger than the thickness of the gate insulating film (tunnel insulating film) 2A of the memory cell transistor.

  In the resistance element shown in FIG. 16, the resistance layer 30 is provided between the semiconductor substrate 1 and the resistance layer 30 as compared with the case where the resistance layer 30 is provided on the semiconductor substrate 1 through the thin insulating film 20 formed simultaneously with the gate insulating film. Can reduce the parasitic capacitance.

  In this modification, after the insulating film 20 is formed in the semiconductor substrate 1 in a process different from the formation of the gate insulating film 2, the first polysilicon film 3 that becomes the floating gate electrode and the resistance layer is formed in the memory. They are simultaneously formed on the gate insulating film 2 in the cell array 100 and on the insulating film 20 in the resistance element region 200. In the subsequent process, the memory cell transistor and the resistance element are formed using the same process as described above.

  As described above, according to the modification of the embodiment of the present invention, the chip size of the nonvolatile semiconductor memory can be reduced as in the first to third embodiments of the present invention. Further, according to the modification of the embodiment of the present invention, the operation of the nonvolatile semiconductor memory can be stabilized by reducing the parasitic capacitance.

3. Other
According to the embodiment of the present invention, the chip size of the nonvolatile semiconductor memory can be reduced.

  The example of the present invention is not limited to the above-described embodiment, and can be embodied by modifying each component without departing from the gist thereof. Various inventions can be configured by appropriately combining a plurality of constituent elements disclosed in the above-described embodiments. For example, some constituent elements may be deleted from all the constituent elements disclosed in the above-described embodiments, or constituent elements of different embodiments may be appropriately combined.

The figure which shows the whole structure of fresh memory. The top view which shows the structure of a memory cell array. Sectional drawing which follows the III-III line | wire of FIG. Sectional drawing which follows the IV-IV line | wire of FIG. The top view which shows the structure of the resistive element which concerns on 1st Embodiment. Sectional drawing which follows the VI-VI line of FIG. Sectional drawing which follows the VII-VII line of FIG. Sectional drawing which follows the VIII-VIII line of FIG. Sectional drawing which shows 1 process of the manufacturing process of 1st Embodiment. Sectional drawing which shows 1 process of the manufacturing process of 1st Embodiment. Sectional drawing which shows 1 process of the manufacturing process of 1st Embodiment. Sectional drawing which shows 1 process of the manufacturing process of 1st Embodiment. Sectional drawing which shows the structure of the resistive element which concerns on 2nd Embodiment. Sectional drawing which shows the structure of the resistive element which concerns on 2nd Embodiment. Sectional drawing which shows the structure of the resistive element which concerns on 3rd Embodiment. Sectional drawing which shows the structure of the resistive element which concerns on a modification.

Explanation of symbols

  1: Semiconductor substrate, 2A: Tunnel insulating film, 2B: Gate insulating film, 3A: Floating gate electrode, 4A, 4B: Inter-gate insulating film, 5A: Control gate electrode, 2B: Gate insulating film, 3B, 5B: Gate electrode 8: Element isolation insulating film, 10A, 10B, 11: Interlayer insulating film, 2, 20: First insulating film, 30: Resistance layer, 31A to 31E: First part, 32A to 32D: Second part, 40, 40C: second insulating film, 50A, 50B: contact layer, 50C; dummy layer.

Claims (5)

A non-volatile semiconductor memory comprising a memory cell transistor having a stacked gate structure composed of a floating gate electrode and a control gate electrode and a resistance element,
The resistance element is
A first insulating film provided on the semiconductor substrate;
A resistance layer made of the same material as the floating gate electrode and provided on the first insulating film;
A second insulating film having two openings provided on the resistance layer;
A contact layer that is made of the same material as the control gate electrode and is provided on one end and on the other end of the resistance layer through the opening of the second insulating film,
The resistance layer is
At least two first parts;
A non-volatile semiconductor memory comprising: at least one second portion having a thickness smaller than that of the first portion.   2. The nonvolatile semiconductor memory according to claim 1, wherein the first portion is provided at one end and the other end in the resistance layer, and the first portion is connected to the contact layer. An interlayer insulating film covering the resistance layer and the contact layer;
The nonvolatile semiconductor memory according to claim 1, wherein an upper surface of the second portion of the resistance layer is in contact with the interlayer insulating film.   4. The nonvolatile semiconductor memory according to claim 1, wherein a film thickness of the first insulating film is larger than a film thickness of a gate insulating film of the memory cell transistor. 5. A method for manufacturing a nonvolatile semiconductor memory comprising a memory cell transistor having a stacked gate structure composed of a floating gate electrode and a control gate electrode and a resistance element,
Forming a resistance layer made of the same material as the floating gate electrode on the first insulating film on the surface of the semiconductor substrate in the resistance element region;
Forming a second insulating film having two openings on the resistance layer;
Forming a conductive layer made of the same material as the control gate electrode on the second insulating film;
The conductive layer is separated by etching to form two contact layers connected to the resistance layer through the opening of the second insulating film, and at the same time, the contact layer on which the resistance layer is formed And a step of forming at least two first portions and forming at least one second portion thinned by the etching in a self-aligning manner with respect to the non-volatile property. Manufacturing method of semiconductor memory.

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