JP2010087158A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a configuration for preventing cracks from being generated by heat treatment when using an SOG film as an element separation insulation film. <P>SOLUTION: A gate insulation film 4, a polycrystalline silicon film 5, an insulation film for processing, and then a trench 1a are formed on a silicon substrate 1. A silicon oxide film 8 is formed in the trench 1a, and a coating film made of polysilazane is filled to middle height of the polycrystalline silicon film 5. After forming a silicon nitride film 9 for preventing cracks, the coating film is formed further. Although the coating film is converted to silicon oxide films 2, 10 by heat treatment, cracks may be generated in the silicon oxide film 10 at an upper layer by thermal shrinkage stress, which can be prevented by the silicon nitride film 9. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a semiconductor device having a configuration using a coating type oxide film as an element isolation insulating film.

  In a NAND flash memory device, for example, which is one of semiconductor devices, the processing dimensions are being made finer in order to increase the storage capacity. An STI (Shallow Trench Isolation) structure in which a trench is formed in a semiconductor substrate and an insulating film is embedded is formed as an element isolation structure between adjacent memory cells. For example, in the technique disclosed in Patent Document 1, a gate insulating film is formed on a semiconductor substrate, a first conductive layer is formed thereon, and the first conductive layer, the gate insulating film, and the semiconductor substrate are predetermined. A trench is formed along the direction, and an element isolation insulating film is embedded in the trench. In this case, for the purpose of improving the embedding property, a coating film (SOG; spin on glass) such as polysilazane (silazane polymer) is formed, and heat treatment is performed to convert it into a silicon oxide film.

  Subsequently, a second conductive layer is formed on the first conductive layer, and the second conductive layer is separated by etching back the second conductive layer until the element isolation insulating film is exposed. An inter-gate insulating film and a control gate are formed on the isolation insulating film and the second conductive layer.

  However, the formation of the element isolation insulating film disclosed in Patent Document 1 as described above has the following problems. That is, in the heat treatment when the coating film (SOG film) is converted to a silicon oxide film, it occurs when the SOG film contracts due to the step shape between the element formation region of the silicon substrate and the element isolation insulating film portion of the trench. Tensile stress to concentrate. As a result, cracks may occur from the surface of the SOG film. In addition, the crack generated in the step portion may reach the bottom in the trench regardless of the pattern by receiving tensile stress due to contraction. As a result, in some cases, the crack enters into the silicon substrate and is cleaved, and further develops into a crack that breaks the element formation region.

These cracks cause problems such as an electrical short circuit between the silicon substrate and the gate electrode when the inter-electrode insulating film and the polycrystalline silicon film as the control gate electrode are embedded. Become.
JP 2004-186185 A

  An object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing element destruction caused by cracks when a coating type oxide film is used as an element isolation insulating film.

  According to a first aspect of the method for manufacturing a semiconductor device of the present invention, there is provided a step of forming a groove for element isolation on an upper surface of a semiconductor substrate, and element isolation at a predetermined depth below the position of the upper surface opening of the groove in the groove. A step of embedding a coating film for an insulating film, a step of forming a crack prevention film on the upper surface of the coating film, a step of embedding an insulating film in the groove up to the position of the upper surface opening of the groove, and element separation of the coating film It is characterized in that a heat treatment process for converting to an insulating film is sequentially performed.

  According to a second aspect of the semiconductor device manufacturing method of the present invention, a gate insulating film, a first floating gate electrode film, and a processing insulating film are formed on the upper surface of a semiconductor substrate having a memory cell region and a peripheral circuit region. A step of processing the first gate electrode film, the gate insulating film and the semiconductor substrate using the processing insulating film as a mask to form an element isolation groove; and a deposition type on the inner surface of the groove A step of forming an insulating film, a step of embedding a coating film for an element isolation insulating film in a predetermined depth below the upper surface opening position of the groove in the groove, and forming a crack prevention film on the upper surface of the coating film A step of embedding the coating film in the groove up to the upper surface opening position of the groove, a step of performing a heat treatment for converting the coating film into an element isolation insulating film, and removing the processing insulating film to form the first On the top surface of the electrode film Forming an interelectrode insulating film and a second electrode film; and processing the second electrode film, the interelectrode insulating film, and the first electrode film in a direction perpendicular to the element isolation groove. It is characterized in that the step of forming the gate electrode is sequentially performed.

  According to the method for manufacturing a semiconductor device of the present invention, when a coating-type oxide film is used as the element isolation insulating film, it is possible to prevent element destruction due to crack generation.

  Hereinafter, an embodiment in which the present invention is applied to a NAND flash memory device will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones.

First, the configuration of the NAND flash memory device of this embodiment will be described.
FIG. 1 is an equivalent circuit diagram showing a part of a memory cell array formed in a memory cell region of a NAND flash memory device.
The memory cell array of the NAND flash memory device includes two selection gate transistors Trs1 and Trs2, and a plurality (for example, 8: 2 raised to the nth power (n: 8), for example, between the selection gate transistors Trs1 and Trs2. Are positive cell numbers)) memory cell transistors Trm, and NAND cell units (memory units) SU are formed in a matrix. In the NAND cell unit SU, a plurality of memory cell transistors Trm are formed by sharing adjacent source / drain regions.

  The memory cell transistors Trm arranged in the X direction (corresponding to the word line direction and the gate width direction) in FIG. 1 are commonly connected by a word line (control gate line) WL. Further, the selection gate transistors Trs1 arranged in the X direction in FIG. 1 are commonly connected by a selection gate line SGL1, and the selection gate transistors Trs2 are commonly connected by a selection gate line SGL2. A bit line contact CB is connected to the drain region of the select gate transistor Trs1. The bit line contact CB is connected to a bit line BL extending in the Y direction (corresponding to the gate length direction and the bit line direction) orthogonal to the X direction in FIG. The select gate transistor Trs2 is connected to a source line SL extending in the X direction in FIG. 1 through a source region.

  2A and 2B are plan views showing a layout pattern of a part of the transistors and memory cell regions of the peripheral circuit. In FIG. 2B, a plurality of element isolation insulating films 2 adopting an STI (shallow trench isolation) structure are formed on a silicon substrate 1 as a semiconductor substrate at a predetermined interval along the Y direction in FIG. The active region 3 is formed separately in the X direction in FIG. Word lines WL of the memory cell transistors are formed at predetermined intervals along the X direction in FIG. 2 orthogonal to the active region 3. A selection gate line SGL1 of a pair of selection gate transistors is formed along the X direction in FIG. Bit line contacts CB are formed in the active region 3 between the pair of select gate lines SGL1. The gate electrode MG of the memory cell transistor that is the first gate electrode is on the active region 3 that intersects the word line WL, and the selection gate that is the second gate electrode is on the active region 3 that intersects the selection gate line SGL1. A gate electrode SG of the transistor is formed.

  FIG. 2A is a plan view showing a layout pattern of transistors in the peripheral circuit region. On the silicon substrate 1, an element isolation insulating film 2a adopting an STI structure is formed so as to surround a rectangular active region 3a, and is formed separately from active regions of other transistors. A gate electrode PG is formed so as to cross over the active region 3a and to span the element isolation insulating film STI2a. A gate contact CP is formed on the upper surface of the gate electrode PG.

  FIG. 3 is a diagram schematically showing three-dimensionally by cutting out a region including the gate electrode MG portion of the memory cell transistor surrounded by a two-dot chain line represented by S in FIG. The element isolation insulating film 2 described above is embedded in the trench 1a formed in the surface layer portion of the silicon substrate 1, thereby forming the element forming region 3 in a band shape. A word line WL is formed so as to cross the element forming region 3 at a right angle, and a gate electrode MG is formed at the intersection.

  In the gate electrode MG, a gate insulating film 4 is formed on the surface of the element forming region 3 of the silicon substrate 1, and a polycrystalline silicon film 5 serving as a first gate electrode film is formed on the upper surface thereof. The polycrystalline silicon film 5 is formed in a rectangular shape having the width dimension of the element formation region 3 and the length dimension of the word line WL. An interelectrode insulating film 6 made of an ONO (oxide-nitride-oxide) film or the like is formed on the upper surface of the polycrystalline silicon film 5, and a polycrystalline silicon film 7 serving as a second gate electrode film is formed on the upper surface. Yes. The polycrystalline silicon film 7 functions as the word line WL, and is formed so as to connect the adjacent gate electrodes MG with the STI 2 therebetween.

  The upper surface of the element formation region 3 is formed so as to be exposed at a portion where the gate electrode MG is not formed, and an impurity diffusion gap region serving as a source / drain region is formed. Although the state shown in the drawing is shown in the middle of the manufacturing process, in reality, this part is also formed in a state of being embedded with an interlayer insulating film.

  The element isolation insulating film 2 is a kind of SOG (spin on glass) film which is a coating type silicon oxide film. For example, a solution of perhydrogenated polysilazane (silazane polymer) is applied to form a coating film. By heat treatment, impurities are removed and converted into a silicon oxide film. The element isolation insulating film 2 is buried with a silicon oxide film 8 formed on the inner wall surface of the trench 1a interposed therebetween. The silicon oxide film 8 is formed in a liner shape by LP-CVD (low pressure chemical vapor deposition).

  The element isolation insulating film 2 is formed at different heights in a portion adjacent to the gate electrode MG and a portion adjacent to the source / drain region. In a portion adjacent to the source / drain region, it is formed at a height substantially the same as or slightly lower than the upper surface of the element forming region 3. Further, in the portion adjacent to the gate electrode MG, the element isolation insulating film 2 is formed to an intermediate height of the polycrystalline silicon film 5. A silicon nitride film 9 as a crack preventing film is formed on the upper surface. The silicon nitride film 9 is also formed on the side wall portion of the polycrystalline silicon film 5 on the element isolation insulating film 2.

  Further, a silicon oxide film 10 formed by converting from a coating film such as a polysilazane film is formed on the upper surface of the silicon nitride film 9 so as to be buried to the same height as the upper surface of the polycrystalline silicon film 5. Interelectrode insulating film 6 and polycrystalline silicon film 7 are formed so as to extend over the upper surface of silicon oxide film 10 and the upper surface of polycrystalline silicon film 5.

  3 shows a configuration in which the silicon nitride film 9 as a crack preventing film and the silicon oxide film 10 formed from the coating film remain. The silicon nitride film 9 effectively functions as a crack prevention film when the coating film is embedded in a wide trench in the peripheral circuit region mainly in the manufacturing process described below.

  Next, the manufacturing process will be described with reference to FIGS. 4 to 10 schematically show portions cut along cutting lines AA and BB in FIGS. 2A and 2B, respectively. A portion obtained by cutting the gate electrode PG portion and the gate electrode MG portion of the memory cell transistor in the direction of the word line WL is shown.

  First, as shown in FIG. 4, a gate insulating film 4 is formed on a silicon substrate 1 with a predetermined film thickness, and then a floating gate electrode film in a memory cell transistor portion, and a polycrystal that becomes a lower electrode in a peripheral circuit portion. A silicon film 5 is formed. Thereafter, a silicon nitride film 11 serving as a hard mask material is deposited on the upper surface of the polycrystalline silicon film 5.

  Next, as shown in FIG. 5, the resist is patterned by lithography, the silicon nitride film 11 is processed to form a hard mask, and the polycrystalline silicon film 5, the gate insulating film 4 and the silicon are formed using this as a mask. The substrate 1 is processed by RIE (reactive ion etching) to form trenches (grooves) 1a so that the depth from the surface of the silicon substrate 1 becomes a predetermined depth. Next, an HTO (high temperature oxide) film is formed as a silicon oxide film 8 on the inner wall surface of the trench 1a by LP-CVD.

  Subsequently, as shown in FIG. 6, a polysilazane solution is applied to form a SOG film 12 as a coating film to a predetermined depth in the trench 1a, for example, to a depth of 10 nm or more from the upper surface of the polycrystalline silicon film 5. Form. At this time, the SOG film 12 may be adjusted to a predetermined height by adjusting the amount of the polysilazane solution applied in advance. Alternatively, the SOG film 12 is formed so as to fill the trench 1a and cover the silicon nitride film 11, and then perform CMP ( It can also be adjusted to a predetermined height by an etch back process after flattening by a chemical mechanical polishing method. Thereafter, a low temperature heat treatment is performed to convert the SOG film 12 into a silicon oxide film. Here, for example, weak heat treatment at about 250 ° C. is performed.

  Subsequently, as shown in FIG. 7, a silicon nitride film 9 as a crack preventing film is formed on the entire surface with a film thickness of about 20 nm by LP-CVD. The reason why the silicon nitride film 9 is used as the crack prevention film is that the film is relatively hard and can prevent cracks generated by heat treatment of the SOG film from proceeding.

  Next, as shown in FIG. 8, an SOG film 13 as a coating film is formed on the upper surface of the silicon nitride film 9 using polysilazane similar to the SOG film 12 described above. The SOG film 13 is formed at a thickness of, for example, about 300 nm in order to secure a film thickness that becomes a cutting allowance necessary for subsequent CMP processing. As a result, the SOG film 13 is filled in the portion where the element isolation insulating film 2 between the polycrystalline silicon films 5 to be the gate electrodes MG is formed at a low height, and the upper surface portion of the polycrystalline silicon film 5 is also formed. An SOG film 13 is formed so as to be covered. Since there is a step between the polycrystalline silicon film 5 and the element isolation insulating film 2 as described above, the SOG film 13 is also unevenly formed.

  The upper SOG film 13 is formed because it is difficult in the process to carry out the processing step with the recess remaining, and the processing step is preferably performed with a flat surface. Because. Therefore, after this purpose is achieved, even when the SOG film 13 is converted to the silicon oxide film 10, it may not necessarily be necessary in terms of structure, and may be finally removed.

  Subsequently, in order to convert the SOG films 12 and 13 into the silicon oxide films 2 and 10, heat treatment is performed in an oxidizing atmosphere of about 400 to 500 ° C. At this time, since the SOG film 13 is exposed to the first heat treatment, a large thermal contraction occurs on the surface, and stress concentration tends to occur particularly in a portion where a step is generated. For this reason, as shown in FIG. 9, the crack K may generate | occur | produce in the part which has the surface level | step difference. In this case, the generated crack K progresses downward from the upper surface of the SOG film 13, but since the silicon nitride film 9 is formed in the lower layer portion thereof, the progress of the crack K can be prevented here. . As a result, even if the heat treatment step for converting the SOG films 13 and 12 into the silicon oxide films 10 and 2 is performed and the crack K is generated on the surface, it is possible to prevent the formation of the element from being hindered.

  Thereafter, as shown in FIG. 10, the silicon oxide film 10 is dropped by performing an etch back process on the entire surface by the RIE method. The depth of dropping is such that the height of the upper surface of the silicon oxide film 10 is substantially the same as the upper surface of the polycrystalline silicon film 5. In addition, in FIG. 10, it has shown as an example in case the crack K mentioned above does not exist.

  Thereafter, from the state of the above configuration, the inter-electrode insulating film 6 and the polycrystalline silicon film 7 to be the second gate electrode film are laminated and gate processed, and along the word line WL as shown in FIG. The polycrystalline silicon film 7, the interelectrode insulating film 6, the polycrystalline silicon film 5, the silicon oxide film 10, the silicon nitride film 9, and the silicon oxide film 2 are etched by the RIE method so as to obtain the shape.

  In the transistor in the memory cell region shown in FIG. 3, silicon oxide film 10 converted from silicon nitride film 9 and polysilazane film 13 remains as a trace in a portion adjacent to gate electrode MG. On the other hand, in the transistor of the peripheral circuit, the silicon oxide film 10 and the silicon nitride film 9 are lost by the etch back process during the gate processing.

  Thereafter, in order to form source / drain regions in the element formation region 3 where the silicon substrate 1 is exposed between the gate electrodes MG, impurities are introduced by a method such as ion implantation to form an impurity diffusion region. . Further, an interlayer insulating film is buried between the gate electrodes MG, and contact formation, wiring layers, and the like are formed to form a NAND flash memory device. In addition, the polycrystalline silicon film 7 can employ a configuration in which the upper portion is silicided to reduce resistance.

  According to the above-described embodiment, the following effects can be obtained. In the prior art, in the processing step of filling the groove 1a formed in the silicon substrate 1 with an SOG film such as a polysilazane film, cracks due to stress concentration at the step between the element formation region 3 and the element isolation insulating film 2 are generated. Enlarging and causing defects at various sites. For this reason, in the present embodiment, by sandwiching a relatively hard film such as the silicon nitride film 9 in the SOG film, even when a crack K occurs, it can be prevented from extending and reaching the silicon substrate 1. Further, since this crack K is removed in the subsequent etch-back process, although it occurs as a result in the middle of the manufacturing process, it does not remain in the element structure in the end.

  Further, it has been clarified that the use of the silicon nitride film 9 as a crack prevention film as described above significantly improves the process when it is not provided. More specifically, the defect caused by the occurrence of cracks could be reduced to about 1/10.

(Other embodiments)
The present invention is not limited to the above embodiment, and can be modified or expanded as follows.
The silicon nitride film 9 is used as the crack prevention film. However, when the silicon oxide film is formed by converting the SOG film by heat treatment, the silicon nitride film 9 should be used if it has a film quality that can prevent the progress of cracks. For example, a polycrystalline silicon film can also be used.

  In the above-described embodiment, the case where the silicon nitride film 9 remains in the memory cell transistor portion has been described as an example. However, the present invention is not limited to this, and the silicon nitride film 9 as a crack prevention film is removed in a subsequent process. It can also be applied to

As the interelectrode insulating film, a non-nitride-oxide-nitride-oxide-nitride (NONON) film other than the ONO film, or other high dielectric constant materials can be used.
In addition to the NAND flash memory device, the present invention can also be applied to a NOR type memory device or a memory device such as an SRAM. Further, the present invention is applied to all semiconductor devices having an STI structure and an SOG film embedded therein. be able to.

1 is an equivalent circuit diagram showing a part of a memory cell array of a NAND flash memory device according to an embodiment of the present invention; (A) is a schematic plan view showing a layout pattern of transistors in the peripheral circuit region, (b) is a schematic plan view showing a partial layout pattern of the memory cell region. Schematic diagram three-dimensionally showing the portion surrounded by S in FIG. FIG. 2 is a schematic longitudinal sectional view (No. 1) at one stage of the manufacturing process, where (a) is a portion indicated by a cutting line AA in FIG. 2 (a), and (b) is a cutting line B in FIG. 2 (b). -B part Schematic longitudinal section at one stage of the manufacturing process (2) Schematic longitudinal section at one stage of the manufacturing process (Part 3) Schematic longitudinal section at one stage of the manufacturing process (Part 4) Schematic longitudinal section at one stage of the manufacturing process (Part 5) Schematic longitudinal section at one stage of the manufacturing process (Part 6) Schematic longitudinal section at one stage of the manufacturing process (Part 7)

Explanation of symbols

  In the drawings, 1 is a silicon substrate (semiconductor substrate), 2 is a silicon oxide film (element isolation insulating film), 4 is a gate insulating film, 5 is a polycrystalline silicon film (first electrode film), and 6 is an interelectrode insulating film. 7 is a polycrystalline silicon film (second electrode film), 9 is a silicon nitride film (crack prevention film), 10 is a silicon oxide film, 11 is a silicon nitride film (insulating film for processing), and 12 is a polysilazane film (coating). Membrane).

Claims (5)

Forming a groove for element isolation on the upper surface of the semiconductor substrate;
Embedding a coating film for an element isolation insulating film in the groove at a predetermined depth below the position of the upper surface opening of the groove;
Forming a crack prevention film on the upper surface of the coating film;
Embedding an insulating film in the groove up to the upper surface opening position of the groove;
And a step of performing a heat treatment for converting the coating film into an element isolation insulating film. Forming a gate insulating film, a first gate electrode film and a processing insulating film on an upper surface of a semiconductor substrate having a memory cell region and a peripheral circuit region;
Processing the first gate electrode film, the gate insulating film, and the semiconductor substrate by using the processing insulating film as a mask to form an element isolation groove;
Forming a deposition type insulating film on the inner surface of the groove;
Embedding a coating film for an element isolation insulating film in the groove at a predetermined depth below the position of the upper surface opening of the groove;
Forming a crack prevention film on the upper surface of the coating film;
Embedding the coating film in the groove up to the opening position of the upper surface of the groove;
Performing a heat treatment to convert the coating film into an element isolation insulating film;
Removing the processing insulating film and forming an interelectrode insulating film and a second electrode film on an upper surface of the first electrode film;
The step of processing the second electrode film, the interelectrode insulating film, and the first electrode film in a direction orthogonal to the element isolation groove to form a gate electrode is sequentially performed. A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 1 or 2,
The method for manufacturing a semiconductor device, wherein the crack preventing film uses a film having a strength sufficient to withstand the strain stress of the coating film in the heat treatment step. In the manufacturing method of the semiconductor device according to claim 3,
A method of manufacturing a semiconductor device, wherein the crack prevention film uses a silicon nitride film. In the manufacturing method of the semiconductor device according to claim 1,
The method for manufacturing a semiconductor device, wherein the coating film is a polysilazane film.

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