JP2010085178A - Ic tester - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an IC tester capable of shortening a time for data update of a timing memory by updating of a skew adjusting value. <P>SOLUTION: In this invention, an IC tester is improved, wherein an address is given to the timing memory, and a timing of a signal to be given to a test object is adjusted by timing data output from the timing memory, and the test object is tested. This device is equipped with an updating data generation part wherein the timing data in the timing memory are read, and a present skew adjusting value is subtracted, and an update skew adjusting value is added and stored in the timing memory. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an IC tester in which an address is given to a timing memory, the timing of a signal to be tested is adjusted based on timing data output from the timing memory, and a test of the test target is performed. The present invention relates to an IC tester that can shorten the time for updating data in a timing memory.

  The IC tester gives a test signal to an object to be tested (hereinafter referred to as DUT), for example, IC, LSI, etc., compares the output of the DUT with an expected value, and determines pass / fail. The test signal is generated by adjusting the timing of the edge signal and inputting the edge signal to the set terminal or the reset terminal of the SR flip-flop. Such an apparatus is described in, for example, Patent Document 1 below.

JP-A-8-293765

  Hereinafter, a description will be given with reference to FIG. In FIG. 2, the address generator 1 generates an address. A CPU I / F (interface) 2 inputs and outputs an address and timing data from a CPU (not shown). The skew register 3 stores a skew adjustment value. A multiplexer (hereinafter referred to as MUX) 4 selects an address from the address generator 1 and an address from the CPU I / F 2. The adder 5 adds the timing data from the CPU I / F 2 and the skew adjustment value of the skew register 3. The timing memory 6 receives the address selected by the MUX 4, the timing data from the adder 5 is written, and the timing data is read. The edge signal generator 7 receives the timing data from the timing memory 6, adjusts the timing based on the timing data, and outputs an edge signal. The formatter 8 receives the edge signal from the edge signal generator 7, determines the rising edge and the falling edge based on the edge signal, and outputs a test signal.

  The operation of such an apparatus will be described below. First, the MUX 4 selects the CPU I / F2. Then, a CPU (not shown) inputs to the timing memory 6 via the CPU I / F 2 and MUX 4 while changing the address. Then, the CPU outputs the timing data while changing the timing data in conjunction with the change of the address via the CPU I / F 2. The adder 5 adds the timing data from the CPU I / F 2 and the skew adjustment value of the skew register 3 and outputs the result to the timing memory 6. As a result, the timing data with the skew adjustment value added to the timing memory 6 is stored for each address.

  Next, the MUX 4 selects the address generator 1. Then, the address generator 1 outputs to the timing memory 6 via the MUX 4 while changing the address. Corresponding to the input address, the timing memory 6 outputs timing data to the edge signal generator 7. Then, the edge signal generator 7 adjusts the timing using a counter or a programmable delay line (not shown) based on the timing data, and outputs an edge signal to the formatter 8. The formatter 8 inputs an edge signal to a set terminal or a reset terminal of an SR flip-flop (not shown), determines rising and falling, and outputs a test signal to a DUT (not shown).

  In such a device, skew correction between signals output to the DUT is performed, and when the skew adjustment value changes, the skew adjustment value is stored again in the skew register 3, and the CPU outputs the address and timing data. Thus, all data contents of the timing memory 6 had to be rewritten. Therefore, since the CPU has to calculate timing data based on a test program or the like, it takes time to update the data.

  SUMMARY OF THE INVENTION An object of the present invention is to realize an IC tester that can shorten the time for updating the data in the timing memory by updating the skew adjustment value.

In order to achieve such a problem, the invention according to claim 1 of the present invention is:
In an IC tester that performs timing adjustment of a signal to be tested by performing timing adjustment on a signal to be tested by an address given to the timing memory and timing data output from the timing memory,
An update data generation unit for reading the timing data of the timing memory, subtracting the current skew adjustment value, adding the update skew adjustment value, and storing it in the timing memory is provided.
Invention of Claim 2 is invention of Claim 1, Comprising:
A first skew register that stores a current skew adjustment value and gives the update data generation unit;
A second skew register is provided, which stores an update skew adjustment value and gives it to the update data generation unit.
Invention of Claim 3 is invention of Claim 1 or 2, Comprising:
An update address generator for sequentially giving addresses to the timing memory is provided.

  According to the present invention, the update data generation unit reads the data in the timing memory, subtracts the current skew adjustment value, adds the update skew adjustment value, and stores it in the timing memory, thereby shortening the data update time. Can do.

  Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. Here, the same components as those in FIG.

  In FIG. 1, an update address generator 9 generates addresses in ascending or descending order. The MUX 10 selects one of the address generator 1, the update address generator 9, and the CPU I / F 2 and gives an address to the timing memory 6. The first skew register 11 stores the current skew adjustment value. The second skew register 12 stores an updated skew adjustment value. The update data generation unit 13 reads the timing data of the timing memory 6, subtracts the current skew adjustment value of the skew register 11, adds the update skew adjustment value of the skew register 12, and stores it in the timing memory 6. The MUX 14 selects the CPU I / F 2 and the update data generation unit 13 and supplies timing data to the timing memory 6.

  The operation of such an apparatus will be described below. First, the MUXs 10 and 14 select the CPU I / F2. Then, a CPU (not shown) inputs to the timing memory 6 via the CPU I / F 2 and the MUX 10 while changing the address. Then, the CPU outputs the timing data to the timing memory 6 via the CPU I / F 2 and the MUX 14 while changing the timing data in conjunction with the change of the address. Thereby, timing data is stored in the timing memory 6 for each address.

  Then, the MUX 10 selects the update address generator 9 and the MUX 14 selects the update data generator 13. Here, since there is no current skew adjustment value in the skew register 11, “0” is stored, and the skew register 12 stores the skew adjustment value that is initially set as the updated skew adjustment value. Then, the update address generator 9 outputs the address to the timing memory 6 via the MUX 10 while changing the address in ascending or descending order. The update data generation unit 13 reads the timing data from the timing memory 6, and since the current skew adjustment value is “0”, the update skew adjustment value of the skew register 12 is added to the timing memory 6 as timing data. Store. As a result, the timing data with the skew adjustment value added to the timing memory 6 is stored for each address.

  Next, the MUX 10 selects the address generator 1. Then, the address generator 1 outputs to the timing memory 6 via the MUX 10 while changing the address. Corresponding to the input address, the timing memory 6 outputs timing data to the edge signal generator 7. Then, the edge signal generator 7 adjusts the timing using a counter or a programmable delay line (not shown) based on the timing data, and outputs an edge signal to the formatter 8. The formatter 8 inputs an edge signal to a set terminal or a reset terminal of an SR flip-flop (not shown), determines rising and falling, and outputs a test signal to a DUT (not shown).

  Then, when skew adjustment of the IC tester is performed and the skew adjustment value is changed, the current skew adjustment value is stored in the skew register 11, and the skew register 12 stores the new skew adjustment value as an updated skew adjustment value. . The MUX 10 selects the update address generator 9, and the MUX 14 selects the update data generator 13. Then, the update address generator 9 outputs the address to the timing memory 6 via the MUX 10 while changing the address in ascending or descending order. The update data generation unit 13 reads the timing data from the timing memory 6, subtracts the current skew adjustment value of the skew register 11, and adds the update skew adjustment value of the skew register 12 to the timing memory 6 as timing data. Store in the memory 6. As a result, the timing data changed to the new skew adjustment value is stored in the timing memory 6 for each address.

  As described above, the update data generation unit 13 reads the data in the timing memory 6, subtracts the current skew adjustment value of the skew register 11, adds the update skew adjustment value of the skew register 12, and stores it in the timing memory 6. Therefore, the data update time can be shortened.

  The present invention is not limited to this, and the configuration in which the update address generation unit 9 is provided separately from the address generation unit 1 is shown. However, the update address generation unit 9 may be the same, and the update address generation unit 9 is not necessarily in ascending order or descending order. Even if it is not changed, any configuration can be used as long as it can be given to all addresses.

  In addition, the update data generation unit 13 subtracts the current skew adjustment value of the skew register 11 from the data from the timing memory 6 and then adds the update skew adjustment value of the skew register 12 as well as the timing. The difference between the current skew adjustment value and the updated skew adjustment value may be added or subtracted from the data from the memory 6. That is, the update data generation unit 13 may be configured to subtract the current skew adjustment value and add the update skew adjustment value.

  In addition, once the timing data is stored in the timing memory 6 from the CPU I / F 2, the skew adjustment value is added by the update data generation unit 13. However, as shown in FIG. 2, the skew adjustment is performed by the adder. A configuration may be used in which values are added and stored. Alternatively, the timing data may be given from the CPU I / F 2 to the update data generation unit 13, and the update data generation unit 13 may add the first skew adjustment value and store it in the timing memory 6.

  Although the configuration in which the MUXs 10 and 14 are provided is shown, the configuration in which the MUXs 10 and 14 are not provided may be used if there is no problem on the signal line.

It is the block diagram which showed one Example of this invention. It is the figure which showed the structure of the conventional IC tester.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Address generation part 6 Timing memory 7 Edge signal generator 8 Formatter 9 Update address generation part 11, 12 Skew register 13 Update data generation part

Claims (3)

In an IC tester that performs timing adjustment of a signal to be tested by performing timing adjustment on a signal to be tested by an address given to the timing memory and timing data output from the timing memory,
An IC tester comprising: an update data generation unit that reads timing data from the timing memory, subtracts a current skew adjustment value, adds an update skew adjustment value, and stores the result in a timing memory. A first skew register that stores a current skew adjustment value and gives the update data generation unit;
2. The IC tester according to claim 1, further comprising a second skew register that stores an update skew adjustment value and gives the update skew adjustment value to the update data generation unit.   3. The IC tester according to claim 1, further comprising an update address generator for sequentially giving addresses to the timing memory.

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