JP2010081690A - Synchronous rectification start control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the malfunction of a converter itself or a circuit on its subsequent stage and prevent the deterioration of used parts and their breakdown, by structuring it so that its output voltage may not drop or that undershoot may not occur at start of an insulated switching DC-DC converter. <P>SOLUTION: A control circuit for synchronous rectification controls the ON/OFF of the synchronous rectifier FET of the secondary rectification circuit of the insulated switching DC-DC converter. The control circuit includes a driver 14, which drives the synchronous rectifier FET, and a synchronous rectification soft start circuit 16, which supplies a start slope voltage, where the voltage rises gradually, as an operation source for the driver after start of the main switching part 10. The gate voltage of the synchronous rectifier FET is gradually raised by the start slope voltage after start of the main switching part, thereby gradually lowering the ON resistance of the synchronous rectifier FET to softly start synchronous rectification. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a control circuit for controlling on / off of a synchronous rectification FET of a secondary side synchronous rectification circuit of an isolated switching DC-DC converter. More specifically, the present invention relates to a synchronous rectification circuit when a main switching unit of a converter is started. The present invention relates to a start control circuit for synchronous rectification in which a soft start is applied to suppress excessive power extraction from an output.

  In recent years, as one technique for improving the efficiency of a switching power supply, loss is reduced by using a rectifier circuit on the secondary side of the transformer as a synchronous rectifier. Synchronous rectification uses a switching element (usually FET: a field effect transistor) instead of a rectifying diode as a rectifying element, and is turned on when it should be conductive as a rectifying element. This is a rectification method in which the switch element is controlled so that it is turned off when it should be. A switching power supply employing a synchronous rectification method is described in, for example, Patent Document 1.

  In the prior art, the synchronous rectification operation is started simultaneously with the start of the isolated switching DC-DC converter (the switching start of the main switching unit). Therefore, the ON state of the synchronous rectification FET continues, whereby the synchronous rectification FET absorbs excessive current from the output side, and an abnormal drop in output voltage and undershoot occur. Then, there is a possibility that the isolated switching DC-DC converter itself or the circuit device at the subsequent stage may malfunction, and there is a risk of deterioration or damage of used parts including the FET.

JP 2003-189622 A

  The problem to be solved by the present invention is to prevent the output voltage drop and undershoot from occurring at the start of the isolated switching DC-DC converter, thereby preventing the malfunction of the converter itself and the subsequent circuit. It is to prevent deterioration and damage.

  The present invention relates to a control circuit for controlling on / off of a synchronous rectification FET of a secondary side synchronous rectification circuit of an isolated switching DC-DC converter, a driver for driving the synchronous rectification FET, and an isolation switching DC-DC converter. A synchronous rectification soft start circuit that supplies a start slope voltage that gradually increases as an operating power supply of the driver after the main switching unit is activated is provided, and the gate voltage of the synchronous rectification FET is gradually increased by the start slope voltage after the main switching unit is activated. The synchronous rectification start control circuit is characterized in that the on-resistance of the synchronous rectification FET is gradually lowered to soft start the synchronous rectification.

  For example, the synchronous rectification includes an OR gate that obtains a logical sum of the output voltage of the secondary winding of the transformer of the isolated switching DC-DC converter and a pulse width modulation signal that controls switching of the main switching unit. The driver that drives the FET is an inverter driver that inverts the logic of the input and output. By supplying the output of the OR gate to the driver, the synchronous rectification FET is turned off when there is a secondary winding voltage. It is preferable to reduce the pulse width of synchronous rectification by ringing the secondary winding voltage when the switching unit is activated.

  The synchronous rectification start control circuit according to the present invention delays the timing at which the synchronous rectification FET is turned on with respect to the start of the isolated switching DC-DC converter (when the switching of the main switching unit starts), and at the time of synchronous rectification start, Since the soft start is applied to the synchronous rectification FET, the output voltage does not drop and undershoot does not occur when the converter is started up. Therefore, malfunction of the converter itself and subsequent circuits can be prevented, and deterioration and damage of used parts can be prevented. it can.

  FIG. 1 is a circuit diagram showing an example of an isolated switching DC-DC converter to which the present invention is applied. The converter body has a configuration in which a main switching unit 10 including a switching element (not shown) is disposed on the primary side of the transformer T, and a synchronous rectifier circuit 12 is disposed on the secondary side. The DC input is switched by the switch element of the main switching unit 10. The secondary side of the transformer T is center tap type windings N21 and N22, which reach the output terminal (+) through the choke coil L from the center tap, and the other ends of both secondary windings N21 and N22 are synchronized. They are commonly connected through rectifying FETs (indicated by reference numerals Q1 and Q2) and connected to an output terminal (GND).

  The secondary side synchronous rectification circuit 12 is controlled so that the synchronous rectification FET is turned on when it should be conductive as a rectifying element, and the synchronous rectification FET is turned off when it should be non-conductive, as in the prior art. Thereby, a DC output is obtained at the output terminal.

  Each synchronous rectification FET is driven by a driver (inverter / driver) 14, and a synchronous rectification soft start circuit 16 that supplies a start slope voltage to an operation power source of the driver 14 is provided. The synchronous rectification soft start circuit 16 creates a start slope voltage from which the voltage gradually increases (ramp waveform) after the main switching unit 10 is started up from the power supply voltage Vcc. Synchronous rectification starts after the main switching unit 10 is activated (transition from the cut-off state to the synchronous rectification state), and at that time, the gate voltage of the synchronous rectification FET is gradually increased by the driver 14 to thereby turn on the synchronous rectification FET. Decrease gradually and soft start.

  In the present embodiment, the first OR gate 18 that takes the logical sum of the output voltage of the secondary windings N21 and N22 of the transformer T and the pulse width modulation (PWM) signal that controls the switching operation of the main switching unit 10 is used. And the output of the first OR gate 18 is supplied to the driver 14. Also at the start of synchronous rectification, the synchronous rectification FET is turned off when the secondary winding voltage is present, and the pulse width of the synchronous rectification is narrowed by ringing of the secondary winding voltage at the start of the main switching unit so that the soft start is applied. Fulfills the function of

  Furthermore, in this embodiment, a second OR gate 20 is inserted between the first OR gate 18 and the driver 14. In the second OR gate 20, one input is the output of the first OR gate 18, the other input is the On / Off signal of synchronous rectification, and the logical sum output thereof is the input of the driver 14. Connecting. The output of the second OR gate 20 is positively fed back to the On / Off signal input side of the synchronous rectification via the resistor R. The second OR gate 20 functions so as to receive the synchronous rectification Off signal only when the secondary side winding voltage is present when the synchronous rectification is stopped.

  FIG. 2 shows the timing (A) and operation waveform (B) when the converter is started, and FIG. 3 shows the timing (A) and operation waveform (B) when the converter is stopped.

  The switching operation of the main switching unit 10 is controlled by a soft start slope, and a normal operation state is reached after a soft start period from the start of main switching. During the soft start period, the pulse width of the switch element gradually increases. As the main switching unit 10 is activated, the synchronous rectification soft start circuit 16 uses the power supply voltage Vcc to create a start slope voltage that gradually increases. By using this start slope voltage as the operating voltage of the driver 14, the driver 14 gradually increases the gate voltage of the synchronous rectification FET. Then, the on-resistance of the synchronous rectification FET gradually decreases and the synchronous rectification soft-starts. When the synchronous rectification is soft-started, the output voltage gradually increases, and after a period of synchronous rectification soft-start, the output is stabilized.

  When the converter is activated, ringing occurs in the secondary winding voltage of the transformer T as the oscillation of the main switching unit 10 starts. An appropriate threshold value is set for the ringing (indicated by a broken line in FIG. 2B), and in the first OR gate 18, the synchronous rectification FET is in a period during which the ringing generated in the secondary winding is higher than the threshold value. It is controlled to be in an off state, and thereby the pulse width of synchronous rectification is narrowed. This effect also contributes to the soft start of synchronous rectification.

  Even when the converter is stopped, the switching operation of the main switching unit 10 is controlled by the soft start slope, the pulse width gradually decreases, and the main switching stops. Although the synchronous rectification is stopped by the synchronous rectification Off signal, the synchronous rectification FET is alternately turned off when the winding voltage is present by the second OR gate 20 in this embodiment. If the synchronous rectification FETs of both secondary windings are simultaneously turned off by the bridge type synchronous rectification, the choke coil L and the synchronous rectification FET form a booster circuit from the output side, and an excessive voltage is applied to the synchronous rectification FET. Although there is a fear, in the present embodiment, this can be prevented and deterioration / breakage of the parts used can be prevented.

The circuit diagram which shows an example of the insulation type switching DC-DC converter to which this invention is applied. Explanatory drawing which shows the timing at the time of converter starting, and an operation waveform. Explanatory drawing which shows the timing and operation waveform at the time of a converter stop.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Main switching part 12 Synchronous rectification circuit 14 Driver 16 Synchronous rectification soft start circuit 18 1st OR gate 20 2nd OR gate Q1, Q2 Synchronous rectification FET

Claims (2)

In a control circuit for controlling on / off of a synchronous rectification FET of a secondary side synchronous rectification circuit of an isolated switching DC-DC converter,
A driver for driving the synchronous rectification FET, and a synchronous rectification soft start circuit for supplying a start slope voltage that gradually increases as an operation power source of the driver after activation of a main switching unit of the isolated switching DC-DC converter; The synchronous rectification FET is soft-started by gradually decreasing the on-resistance of the synchronous rectification FET by gradually increasing the gate voltage of the synchronous rectification FET by the start slope voltage after the main switching unit is activated. Synchronous rectification start control circuit.   An OR gate that takes the logical sum of the output voltage of the secondary winding of the transformer of the isolated switching DC-DC converter and the pulse width modulation signal that controls the switching of the main switching unit is provided to drive the synchronous rectification FET The driver is an inverter driver that inverts the input / output logic, and supplies the OR gate output to the driver to turn off the synchronous rectification FET when there is a secondary winding voltage, and at the time of starting the main switching unit 2. The start control circuit for synchronous rectification according to claim 1, wherein the pulse width of synchronous rectification is narrowed by ringing of the secondary winding voltage.

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