JP2010081578A - Pwm pulse generation device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a PWM pulse generation device capable of securing a high S/N by use of a digital circuit that works with a low clock frequency. <P>SOLUTION: The PWM pulse generation device converts an analogue amplitude conversion signal M into a digital signal by an analog-digital conversion device 11, and obtains a pulse signal that is of pulse-width modulated by a pulse modulation unit 13. The PWM pulse generation device is provided with an analogue delay device 20 for controlling delay time with a digital signal. As a result, a delay time of 0/16 to 15/16 times the digital resolution is further added to the digital pulse, thus making it possible to divide the pulse resolution into 16 times and to obtain an equivalent resolution with 1/16 frequency clock. At this time, variations in the characteristics of a circuit element that constitutes the analogue delay device 20 can be corrected by providing a conversion table 14. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a pulse generator used for a switching power supply, and more particularly to a PWM pulse generator suitable for a switching power supply in a power supply voltage modulation type high frequency power amplifier.

In the case of a transmitter for analog wireless communication, a high-frequency power modulation amplification device of a power supply voltage modulation method has been conventionally used for the final-stage high-frequency power amplification unit.
In this power supply voltage modulation method, the power supply voltage supplied to the active element of the amplification stage is changed by an amplitude modulation signal such as an audio signal so that amplitude modulation can be obtained. Since a transistor is used as an element, this is a modulation method that was previously called a collector modulation method.

By the way, this power supply voltage modulation type high frequency power modulation amplification apparatus requires a power supply apparatus in which the DC output voltage can be variably controlled by the amplitude modulation signal. Conventionally, this power supply apparatus has a PWM (pulse width modulation). ) Many switching power supply circuits are used.
An example of a power supply voltage modulation type high frequency power modulation amplifier using the PWM switching power supply circuit will be described with reference to FIG.
This example is an example of a power supply voltage modulation type high frequency power modulation amplifying apparatus in a wireless transmission device operating with an AC power supply. For this reason, as shown in the figure, for example, power is supplied from a 100 V AC power supply AC such as a general distribution system. It comes to be supplied.

The alternating current supplied from the alternating current power source AC is converted into a desired voltage by the transformer T, rectified by the diode D to become a pulsating current, and smoothed by a smoothing circuit (not shown). It operates as a direct current power source DC having a desired voltage E, whereby direct current of voltage E is supplied to the source electrode of the field effect transistor FET.
On the other hand, the amplitude modulation signal M such as an audio signal is supplied to the PWM pulse generation unit PS, whereby the PWM pulse signal X having a desired switching period, for example, 5 μs period (switching frequency 200 kHz) is applied to the field effect via the FET driver DR. Applied to the gate electrode of the transistor FET.

As a result, the field effect transistor FET is switching-controlled by the PWM pulse signal X, and the direct current of the voltage E is periodically interrupted. As a result, it is determined by the ratio (duty ratio) of the ON period and the OFF period of the voltage E. The average value voltage is output from the drain electrode as the pulse voltage Y, and as a result, the function as a PWM switching variable voltage circuit is obtained.
Thereafter, the pulse voltage Y is processed by a low-pass filter LF having a desired frequency characteristic, for example, a cutoff frequency lower than the above-mentioned 200 KHz and higher than the upper limit of the audio signal frequency band. The amplitude-modulated power supply voltage Z whose amplitude is changed is input to the power supply terminal of the power amplifier PA.

At this time, the power amplifying unit PA constitutes a final-stage high-frequency power amplifying unit of the wireless transmission device, and a carrier wave C having a desired frequency is supplied to its input.
Therefore, the power amplifier PA operates according to the power supply voltage modulation method, and amplitude-modulates and power-amplifies the input carrier wave C so that an amplitude-modulated wave CP having a desired power is supplied to the antenna. An amplitude-modulated radio wave is transmitted from the transmission device.

By the way, in the case of a transmitter in which the amplitude modulation is obtained by varying the power supply voltage of the final stage amplifier as described above, the power supply voltage is changed from a voltage almost close to 0 V to a considerably high voltage, for example, 50 V described above. It is necessary to vary continuously and without distortion. For this purpose, high accuracy is required for the PWM pulse generator PS.
At this time, an analog circuit is conventionally used as the PWM pulse generation unit PS, but in recent years, it has become possible to configure a digital circuit using an IC such as an FPGA (Field Progeammable Gate Arrey) as hardware. ing.
Next, the PWM pulse generation unit PS by this digital circuit will be described with reference to FIG.

As shown in FIG. 7, the PWM pulse generation unit PS by this digital circuit includes an A / D (analog / digital modulator) 1, a frequency divider 2, and a pulse converter 3.
First, the A / D 1 functions to convert the analog amplitude modulation signal M into a 10-bit digital signal every sampling period (conversion period).
The sampling period at this time is given by a 200 kHz clock, and therefore a 10-bit digital signal is obtained every 5 μs which is the inverse of 200 kHz.
The frequency divider 2 receives a clock CLK having a frequency of 204.8 MHz, divides it by 1024 (1/1024), and supplies a 200 kHz clock to the A / D 1.

The pulse converter 3 operates to generate a pulse 1024 times at intervals of 5 ns in a period of 5 ns in synchronization with the clock CLK of 204.8 MHz. At this time, the 10-bit digital signal input from the A / D 1 Whether or not to actually generate a pulse is determined in accordance with the numerical value (digital value) of the amplitude modulation signal MD.
That is, when the digital value is 1, a pulse is generated only once every 1024 times for a period of 5 μs, twice when the digital value is 2,..., 1023 every 1024 times when the digital value is 1023. A pulse is generated such as times. Therefore, when the digital value is 0, no pulse is generated once in 1024 times, and when the digital value is 1024, all pulses are generated 1024 times.

As a result, when the state of the pulse output from the pulse converter 3 every sampling period of A / D1 by the clock of 200 kHz, that is, every 5 μs, the pulse synchronized with the clock CLK of 204.8 MHz included therein is checked. The number always corresponds to the amplitude of the amplitude modulation signal M. Therefore, the PWM pulse signal X can be obtained from the pulse converter 3 in a cycle of 5 μs by the clock of 200 kHz, and the PWM pulse generation unit PS can be obtained by a digital circuit. It can be configured.
In addition, as a prior art regarding the PWM switching power supply circuit by control of such a pulse duty ratio, the indication of patent document 1 can be mentioned, for example.

JP-A-11-161217

The above prior art does not take into consideration that a circuit that operates with a clock having a high frequency is required as a digital circuit, and there is a problem in an increase in device cost, heat generation amount, and power consumption.
When the PWM pulse signal is generated by a digital circuit, the pulse width changes from continuous to discrete. The minimum value of the change unit at this time is the minimum value of the amplitude conversion change level, which is called resolution.
The resolution in the digital circuit is sampling noise, and the noise level in the case of amplitude modulation is determined. In this case, generally, −60 dB or more is desirable.

In the case of the above prior art, the PWM pulse signal X has a period of a 200 kHz clock. In this case, the period of the PWM pulse signal X is 5 μs, and the S / N of amplitude modulation transmission is secured at least 60 dB as described above. In order to do that, -60 dB = 1.0 × 10 ⁻³ ,
5 μs × 1.0 × 10 ⁻³ = 5 ns
Since a resolution of 5 ns or less is required, as described above, a digital circuit that operates with the clock CLK having a frequency of 204.8 MHz is used as the pulse modulator 3, and as a result, the apparatus cost, the heat generation amount, and the power consumption are reduced. There will be a problem with the increase.

  An object of the present invention is to provide a PWM pulse generation device capable of ensuring a high S / N ratio by a digital circuit having a low clock frequency.

  An object of the present invention is to provide a PWM pulse generation apparatus in which a digital amplitude modulation signal is input to a pulse conversion means comprising a digital circuit, and a pulse width modulated pulse signal is obtained from the pulse conversion means. The delay time is controlled by some bits of the analog delay means, and the pulse signal modulated by the pulse width modulation, the pulse signal output from the pulse conversion means, and the pulse signal output from the analog delay means This is accomplished by providing an OR circuit means to which both of the signals are input, and obtaining the pulse width modulated pulse signal from the OR circuit means.

  At this time, a conversion table for inputting a part of the bits in the digital amplitude modulation signal is further provided, and the data of a part of the bits in the digital amplitude modulation signal input to the analog delay means is converted into the conversion table. The above-described object is achieved even when the analog delay means is input after being processed by a table, and further, a test signal generating means for supplying a test signal to the input of the conversion table, and the pulse width modulation. The analog-digital conversion means to which the pulse signal is inputted and the level values obtained from the analog-digital conversion means corresponding to the respective level values of the test signal are represented by the vertical axis. Recording means for storing a table as an axis and the data in the table are rearranged to obtain the conversion table as a correction conversion table. And a rearranging means for the recording data to be set in the table, it may be inaccuracy is suppressed due to variations of the circuit element characteristic of the analog delay means.

According to the present invention, a PWM pulse generation device having a high S / N can be obtained using a digital circuit having a low clock frequency, so that heat generation and power consumption can be reduced, and variations in delay time due to analog delay means can be suppressed. Therefore, a highly accurate PWM pulse generation device can be provided at low cost.
In addition, as a result of such a high-resolution pulse being generated by a low-frequency clock, according to the present invention, a high S / N amplitude modulation transmitter can be provided at low cost.

1 is a block configuration diagram showing a first embodiment of a PWM pulse generating device according to the present invention. It is a block block diagram which shows 2nd Embodiment of the PWM pulse generation apparatus which concerns on this invention. It is a block block diagram for demonstrating the operation | movement of 2nd Embodiment based on this invention. It is explanatory drawing which shows an example of the table in 2nd Embodiment of the PWM pulse generation apparatus which concerns on this invention. It is explanatory drawing which shows another example of the table in 2nd Embodiment of the PWM pulse generation apparatus which concerns on this invention. It is a block block diagram which shows an example of the high frequency electric power modulation amplification apparatus of a power supply voltage modulation system. It is a block block diagram of the PWM pulse generation apparatus by a prior art.

In the present invention, an analog delay means is used in combination with a digital circuit for generating a pulse to further increase the resolution. Therefore, in one embodiment of the present invention, as shown in FIG. PS is composed of a digital circuit 10 and an analog delay device 20.
At this time, the analog delay unit 20 controls the delay time in four steps of 4 bits. For this reason, simultaneously with the generation of the pulse by the digital circuit 10, the 4-bit information is transmitted to the analog delay unit 20 and further the digital resolution is added to the digital pulse. The delay time of 0/16 to 15/16 is added.

As a result, the resolution of the pulse can be made 16 times finer, and an equivalent resolution can be secured with a clock of 1/16 frequency.
At this time, a conversion table is provided at the input of the analog delay device 20 so that variations in characteristics of circuit elements such as resistors and capacitors that determine the time constant of the analog delay device 20 can be corrected.

In the embodiment of FIG. 1, first, the digital circuit 10 is basically the same as the digital circuit in the prior art described in FIG. 7, and includes an A / D 11, a frequency divider 12, and a pulse converter 13. Yes.
However, at this time, the frequency divider 12 inputs a clock CLK having a frequency of 12.8 MHz, divides it by 64 (1/64), and a 200 kHz clock is supplied to the A / D 11. The pulse converter 13 operates with a clock CLK having a frequency of 12.8 MHz, and only 6 bits of the 10-bit digital signal output from the A / D 11 are input, and the remaining 4-bit digital signal is This is different from the prior art in that it is output from the digital circuit 10 to the outside and supplied to the analog delay device 20.

On the other hand, the analog delay device 20 includes a resistor 21, four capacitors 22, 23, 24, 25, four FETs 26, 27, 28, 29, and an OR circuit 30.
First, the resistor 21 and the capacitors 22, 23, 24, and 25 constitute an RC-type delay unit.
Next, the FETs 26, 27, 28 and 29 are ON / OFF controlled in accordance with a 4-bit digital signal supplied from the A / D 11 of the digital circuit 10, and the delay time by the RC type delay means described above is 16 ways. , And operates as a switching element for causing the delay means to function as a variable delay means, and sequentially gives a desired delay to the pulse signal by the 6-bit digital signal supplied from the pulse converter 13 of the digital circuit 10. Work.

The OR circuit 30 receives both a pulse signal of a 6-bit digital signal supplied from the pulse converter 13 of the digital circuit 10 and a pulse signal delayed by the variable delay means described above. It works to output as X.
Therefore, the operation of the PWM pulse generator PS according to the embodiment of the present invention shown in FIG. 1 will be described below.

The pulse converter 13 of the digital circuit 10 performs an operation of generating pulses at an interval of 0.078125 μs (5 μs / 64) 64 times in a 5 μs period in synchronization with the clock CLK of 12.8 MHz. Whether or not to actually generate a pulse is determined in accordance with the numerical value (digital value) of the 6-bit digital amplitude modulation signal MD input from D11.
That is, in this case, when the digital value for 6 bits is 1, a pulse is generated only once in 64 times for a period of 5 μs, twice when the digital value is 2, and so on. In some cases, pulses are generated 63 times in 64 times, and 64 times when the digital value is 64.

As a result, when the state of the pulse output from the pulse converter 13 is seen every sampling period of A / D1 by the clock of 200 kHz, that is, every 5 μs, the pulse synchronized with the clock CLK of 12.8 MHz included therein. Always corresponds to the amplitude of the amplitude modulation signal M.
In this way, a pulse signal corresponding to a 6-bit digital value is obtained from the pulse converter 13 in a cycle of 5 μs and input to the variable delay means of the analog delay device 20.

The FETs 26 to 29 of the variable delay means are turned ON / OFF every 5 μs in 16 different patterns by a 4-bit digital value.
Accordingly, the capacitors 22 to 25 are also connected to the common potential point (ground) every 5 μs in 16 different combinations, and as a result, 16 different capacitances are connected to the resistor 21. Thus, the variable delay means adds 16 different delay times according to the 4-bit digital value.

Here, by selecting the resistance value of the resistor 21 and the capacitance values of each of the four capacitors 22 to 25 as appropriate as shown in the figure, for example, the delay time is changed from 0 μs to 0.0732 μs ((5 μs / 64) × (15/16)) can be set to 16 delay times that are equally spaced.
Hereinafter, for the sake of explanation, the pulse signal supplied from the pulse converter 13 with a period of 5 μs is referred to as a pulse signal XA, and after being delayed by variable delay means formed of a resistor 21 and capacitors 22 to 25. This pulse signal is a pulse signal XB.

Then, the pulse signal XB becomes a delayed signal of 0 μs to 0.0732 μs with respect to one pulse signal XA.
The pulse signal XB is input to the OR circuit 30 and output to the same line as the pulse signal XA.
As a result, the OR circuit 30 changes the pulse signal XA to 16 pulse delay signals XB (0 μs to 0.0732 μs) followed by the pulse signal X.

Here, regarding the pulse signal XB, as described above, the pulse signal XA immediately before it and a signal obtained by delaying it with a resolution of 0 μs to 0.0732 μs are obtained.
Therefore, regarding the pulse signal X, each of the 64 pulses output at a period of 5 μs is a signal to which 16 delays are added, and this is 1024 (64 × 16) in 5 μs. It can be seen that the resolution is about 5 ns (4.88 ns) as a result.

At this time, since the clock CLK of the pulse converter 13 has a frequency of 12.8 MHz, the PWM pulse generation unit PS is configured using a digital circuit having a clock frequency lower than that in the case of the prior art.
Specifically, in the prior art of FIG. 7, a digital circuit using a clock CLK having a frequency of 204.8 MHz is required as the pulse converter 3 in order to obtain a desired resolution. Thus, it can be seen that the pulse converter 13 can be configured by a digital circuit that operates with a clock CLK having a frequency of 12.8 MHz.

  Therefore, according to this embodiment, it is possible to configure a PWM pulse generator that can generate a pulse signal with high resolution without using a digital circuit with a high clock frequency. As a result, PWM pulse generation with low heat generation and low power consumption can be configured. Can be provided at low cost, and further contribute to energy saving.

  By the way, in this case, the delay time by the variable delay means of the analog delay device 20 is equidistant between 16 delay times from 0 μs to 0.0732 μs ((5 μs / 64) × (15/16)). For this purpose, the circuit elements constituting the variable delay means, that is, the resistors 21 and the capacitors 22 to 25, each have a resistance value as specified. Must have a capacitance value.

However, circuit elements such as resistors and capacitors generally have low accuracy with respect to specifications. In particular, in the case of general-purpose products, the actual error is that the tolerance for the specification values reaches several percent to several tens of percent.
This is because in the case of such a circuit element, it is extremely difficult to maintain the accuracy in the manufacturing process. Therefore, a high-precision element can only be a custom-made product or a selected product. It must be an extremely expensive element.

Here, FIG. 2 shows a second embodiment of the present invention. In the figure, reference numeral 14 denotes a conversion table, and other configurations are the same as those of the embodiment (first embodiment) of FIG. Therefore, the second embodiment corresponds to the addition of the conversion table 14 to the first embodiment of FIG.
In this conversion table 14, a correction conversion table is set in advance, whereby the desired data rearrangement correction is performed on the 4-bit data input from the A / D 11, and the corrected 4-bit data is converted into an analog delay. By supplying the four FETs 26 to 29 of the device 20 and switching the delay time to 16 ways, the desired delay characteristics can be obtained even if the characteristics of the resistors 21 and the capacitors 22 to 25 vary. As a result, even if general-purpose products are used as the resistor 21 and the capacitors 22 to 25, desired accuracy can be easily obtained.

For this purpose, as described above, it is necessary to set the correction conversion table in the conversion table 14 in advance. This correction conversion table is composed of the resistor 21 and the capacitor 22 provided in the analog delay device 20. It must be set according to the delay time characteristic obtained by each of ˜25.
Next, the procedure for setting the correction conversion table will be described with reference to FIG.
In this case, first, as shown in the figure, a desired test signal, that is, 16 4-bit test signals T each representing a digital value from 0 to 15 are sequentially generated to generate a pulse converter 13 and a conversion table 14. To supply.
At this time, in the conversion table 14, for example, a table in which the input and the output are equal is set as the initial value of the correction conversion table.

At this time, the pulse signal X output from the OR circuit 30 is supplied to the A / D 32 via the LPF 31 for removing unnecessary components, and the obtained digital values are recorded as a table by the recording processing 33.
In the table recorded at this time, each level value of the test signal T is shown as an input on the horizontal axis, and a level value obtained from the A / D 32 corresponding to each level value of the test signal T is shown as an output on the vertical axis. Therefore, when the resistance 21 and the capacitors 22 to 25 of the analog delay device 20 have resistance values and capacitance values as specified, the relationship between the input and output of the table is a straight line with a constant slope. It becomes a characteristic.

For example, in this case, since the correction conversion table is set to the above-described initial value, the relationship between the horizontal axis and the vertical axis of the table is as shown in FIG. The characteristic becomes one-to-one.
However, when the resistor 21 and the capacitors 22 to 25 do not have the resistance value and the capacitance value as specified, for example, the characteristics shown as “before improvement” in FIG. Since the characteristics are far from “ideal”, the desired accuracy cannot be expected.

Therefore, in this case, the recording data rearrangement process 34 is executed so that the characteristic “before improvement” approaches the characteristic indicated as “ideal” so that the characteristic indicated as “after improvement” in FIG. A table in which input and output data are switched is set, and this is set in the conversion table 14 as a correction conversion table.
As a result, a delay time approximated with considerable accuracy can be obtained with respect to the “ideal” characteristic. Therefore, even if general-purpose products are used as the resistor 21 and the capacitors 22 to 25, a desired accuracy can be easily obtained. Can be made.

A specific example of the recording data rearrangement process 34 at this time will be described with reference to FIG.
In FIG. 5, the horizontal axis represents the address value of the data represented by a 4-bit digital signal, and the vertical axis represents the electrostatic capacitance shown in the same manner as the resistor 21 of the indicated resistance value corresponding to this address value. The delay time given by the value capacitors 22 to 25 is taken as a table, so that the “ideal” characteristic is a straight line as shown.
However, here, there is a variation in the characteristics of the parts. For example, the capacitance value of the capacitor 22 is increased by 30% from 100 pF to 130 pF as shown in the figure. As a result, the “before correction” characteristic is changed from the “ideal” characteristic shown in the figure. That is, it is assumed that the recording data rearrangement process 34 has changed to the characteristics before execution.

Therefore, in this case, if the data is rearranged by the recording data rearrangement process 34 as shown as the corrected address value to obtain the “after correction” characteristic, the resistors 21 and Even if general-purpose products are used as the capacitors 22 to 25, desired accuracy can be easily obtained.
The setting of the correction conversion table for the conversion table 14 of the PWM pulse generation unit PS at this time should normally be executed before the use of the high-frequency power modulation amplification apparatus to which the PWM pulse generation unit PS is applied. However, it goes without saying that it may be executed as needed.

  Here, the above embodiment is described as an example for explanation, and therefore it is needless to say that the present invention can be implemented without being limited to the clock frequency and the numerical value of the circuit element in the above embodiment. Absent.

11: A / D (analog / digital converter)
12: Divider (1/64)
13: Pulse converter 14: Conversion table 21: Resistance (resistance constituting delay means)
22-25: Capacitor (capacitor constituting delay means)
26-29: FET (switching element for making delay means variable delay means)
30: OR circuit 31: LPF (low pass filter)
32: A / D (analog / digital converter)

Claims (3)

In a PWM pulse generation device in which a digital amplitude modulation signal is input to pulse conversion means composed of a digital circuit, and a pulse signal subjected to pulse width modulation is obtained from the pulse conversion means.
An analog delay means in which a delay time is controlled by some bits in the digital amplitude modulation signal, and the pulse signal modulated by the pulse width is input;
An OR circuit means for inputting both a pulse signal output from the pulse conversion means and a pulse signal output from the analog delay means;
A PWM pulse generation device characterized in that the pulse width modulated pulse signal is obtained from the OR circuit means. The PWM pulse generation device according to claim 1,
Providing a conversion table into which some of the bits in the digital amplitude modulation signal are input;
The PWM is characterized in that data of a part of the bits in the digital amplitude modulation signal input to the analog delay means is processed by the conversion table and then input to the analog delay means. Pulse generator. The PWM pulse generation device according to claim 2,
Test signal generating means for supplying a test signal to the input of the conversion table;
Analog-to-digital conversion means to which the pulse width modulated pulse signal is input;
Recording means for storing a table with each level value of the test signal as a horizontal axis and a level value obtained from the analog-digital conversion means corresponding to each level value of the test signal as a vertical axis;
Reordering the data of the table, and comprising a reordering means for recording data set in the conversion table as a correction conversion table,
A PWM pulse generation device configured to suppress a decrease in accuracy due to variations in circuit element characteristics of the analog delay means.

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