JP2010080725A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology capable of improving a manufacture yield of a semiconductor device. <P>SOLUTION: The semiconductor device includes: first and second semiconductor chip areas 2<SB>1</SB>and 2<SB>2</SB>provided inside a wafer 1; first element areas 5<SB>1</SB>and 5<SB>2</SB>provided inside the first and second semiconductor chip areas 2<SB>1</SB>and 2<SB>2</SB>and having a transistor formed thereon, respectively; a dicing area 3A provided between the first and the second semiconductor chips 5<SB>1</SB>and 5<SB>2</SB>; an alignment area 35 formed inside the dicing area 3A in which alignment marks are formed; and concave portion forming areas 7<SB>1</SB>and 7<SB>2</SB>provided between first element areas 5<SB>1</SB>and 5<SB>2</SB>and the alignment area 35 and having concave portions 9<SB>1</SB>and 9<SB>2</SB>, respectively, wherein, each of the concave portions 9<SB>1</SB>and 9<SB>2</SB>protrudes in a direction vertical to the surface of the wafer 1 and has a top end higher than the surface of the wafer 1 and lower than the top end of a gate electrode 12 of the transistor. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a structure near the boundary between a semiconductor chip area and a dicing area.

  Semiconductor devices such as semiconductor memories and semiconductor integrated circuits are mounted on various electronic devices.

Usually, a plurality of the same semiconductor devices are formed in one wafer. Then, the wafer is diced and cut out as independent semiconductor chips. For this reason, in addition to a region for forming a semiconductor device (hereinafter referred to as a semiconductor chip area), a region reserved for dicing (hereinafter referred to as a dicing area) is provided in the wafer. In the dicing area, alignment marks and TEG (Test Element Group) for preventing misalignment between the manufacturing mask and the wafer are also arranged. The alignment mark is made of, for example, SiO ₂ , and the alignment between the mask and the wafer is recognized by an optical signal due to the difference in light reflection between the mark and the wafer (for example, Si).

  In recent years, with the high integration of semiconductor devices, a multilayer wiring technique in which a plurality of wiring layers including metal wirings and interlayer insulating films covering the metal wirings are stacked is employed.

In a semiconductor device employing a multilayer wiring technique, the surface after the formation of metal wiring and an interlayer insulating film is flattened using a (Chemical Mechanical Polish) method.
In the planarization process by the CMP method, dishing in which the interlayer insulating film is excessively ground becomes a problem. Since the dishing area is a recess (dent), the wiring material remains in the recess, causing a short circuit between the wirings. In addition to this, in the multilayer wiring technique, the upper wiring layer is affected by dishing generated in the lower layer. In this case, a depression that is larger than the dishing that occurs in the lower wiring layer occurs in the upper wiring layer. Therefore, the higher the wiring layer, the greater the probability of occurrence of a short circuit between wirings. As a result, the manufacturing yield of the semiconductor device is reduced.

  Since the occurrence of dishing tends to depend on the coverage of the wiring pattern on the wafer, dishing is likely to occur in a region where no wiring pattern such as a gate electrode is provided. For this reason, the occurrence of dishing is suppressed by disposing a dummy pattern in a semiconductor chip area or a portion where no alignment mark is provided in the dicing area (see, for example, Patent Document 1).

  However, as described above, since the alignment between the mask and the wafer is adjusted based on the optical principle, the wiring pattern cannot be arranged at the location where the alignment mark is provided in the dicing area.

By increasing the dicing area, it is possible to suppress the influence of the residue of the wiring material. However, in this case, it becomes difficult to miniaturize the semiconductor chip, and the number of semiconductor chips that can be formed on one wafer is reduced. Decrease.
JP-A-10-335333

  The present invention proposes a technique for improving the manufacturing yield of semiconductor devices.

  A semiconductor device according to an example of the present invention is provided in a wafer, in the wafer, in each of first and second semiconductor chip areas, and in each of the first and second semiconductor chips, and a transistor is formed. A first element region; a dicing area provided between the first and second semiconductor chips; an alignment region provided in the dicing area and formed with an alignment mark; the first element region and the alignment region; A convex portion forming region having a convex portion protruding in a direction perpendicular to the wafer surface, and an upper end of the convex portion is at a position higher than the wafer surface, and It is in the position below the upper end of a gate electrode.

  A semiconductor device according to an example of the present invention includes a semiconductor substrate, an element region provided in the semiconductor substrate in which a transistor having a multilayer wiring structure is formed, and an end portion of the semiconductor substrate and the element region. A convex portion provided in the region and projecting in a direction perpendicular to the surface of the semiconductor substrate, and an upper end of the convex portion is higher than the surface of the semiconductor substrate and is equal to or lower than an upper end of the gate electrode of the transistor. It is in the position of.

  According to the example of the present invention, the manufacturing yield of the semiconductor device can be improved.

  The best mode for carrying out an example of the present invention will be described below in detail with reference to the drawings.

1. Embodiment
(1) Basic configuration
The basic configuration of the embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 shows a plan view of the wafer 1. FIG. 2 schematically shows a cross section taken along the line AA in FIG. 1, and FIG. 3 schematically shows a cross section taken along the line BB in FIG. FIG. 1 shows a plan view of the entire wafer 1 and a plan view in which a part of the wafer 1 is extracted.

One wafer 1 (for example, a silicon substrate) is provided with a plurality of semiconductor chip areas 2 ₁ , 2 ₂ , 2 ₃ , 2 ₄ .

In the semiconductor chip areas 2 ₁ , 2 ₂ , 2 ₃ , 2 ₄ , element regions 5 ₁ , 5 ₂ , 5 ₃ , 5 ₄ in which a plurality of elements are formed are provided. In the element regions 5 ₁ , 5 ₂ , 5 ₃ , 5 ₄ , elements such as MIS (Metal-Insulator-Semiconductor) transistors, memory cells or resistance elements, and interlayer insulating films covering these elements are formed. However, the illustration and detailed description are omitted here.

To the semiconductor chip areas ₂ 1 in the wafer _1, 2 _2, 2 3, _{2 4} and independent chip, the semiconductor chip areas ₂ 1 dicing area 3A, 3B are adjacent in the x or y direction, _{2 2} , 2 ₃ , 2 ₄ . The wafer 1 is cut along the dicing areas 3A and 3B, and the semiconductor chip areas 2 ₁ , 2 ₂ , 2 ₃ and 2 ₄ become, for example, one semiconductor chip having a multilayer wiring structure.

An alignment region 30 is provided in the dicing area 3A extending in the y direction. An alignment mark 35 for preventing misalignment between a mask (not shown) and the wafer 1 is provided in the alignment region 30. The width in the x direction of the dicing area 3A is, for example, about 70 μm to 80 μm. In the dicing area 3B extending in the x direction, the width of the area 3B in the y direction is, for example, the same width as the width of the dicing area 3A in the x direction. However, the width in the y direction of the dicing area 3B may be different from the width in the x direction of the dicing area 3A.
In the dicing areas 3A and 3B, for example, a TEG (Test Element Group) (not shown) is also provided.

In the embodiment of the present invention, between the alignment region 30 in the dicing area 3A and the element regions 5 ₁ , 5 ₂ , 5 ₃ , 5 _{4 in the} semiconductor chip areas 2 ₁ , 2 ₂ , 2 ₃ , 2 ₄ . , Convex portion forming regions 7 ₁ , 7 ₂ , 7 ₃ , and 7 ₄ are provided. The convex portion formation regions 7 ₁ , 7 ₂ , 7 ₃ , 7 ₄ are included in, for example, the semiconductor chip areas 2 ₁ , 2 ₂ , 2 ₃ , 2 ₄ , and the element regions 5 ₁ , 5 ₂ , 5 ₃ , 5 are included. ₄ is surrounded.

As shown in FIG. 2 and 3, the projection forming region _{7 1,} 7 2, _{7 3,} the protrusions _{9 1,} 9 2, _{9 3} is provided which projects in a direction perpendicular to the wafer 1 surface ing. Therefore, the upper ends of the convex portions 9 ₁ , 9 ₂ , 9 _{3 of} the convex portion forming regions 7 ₁ , 7 ₂ , 7 ₃ , 7 ₄ are the surfaces of the wafer 1 in the element regions 5 ₁ , 5 ₂ , 5 ₃ , 5 ₄ . In a higher position.
For example, misalignment between the mask and the wafer is prevented by using an optical method, so that a dummy pattern cannot be disposed on the alignment mark 35. For this reason, in the dicing areas 3A and 3B, for example, the coverage in regions where dummy patterns cannot be arranged, such as regions in the alignment region 30 or TEG, is reduced, and the interlayer insulating film above the alignment mark 35 is reduced. Dishing may occur. The generated dishing has an adverse effect on the upper interlayer insulating film, and a recess having a larger scale than that of the dishing is formed in the upper interlayer insulating film. When this recess expands not only in the dicing areas 3A and 3B but also in the element regions 5 ₁ , 5 ₂ , 5 ₃ and 5 ₄ , if wiring material remains in the recess, a short circuit between the interconnects of the semiconductor device to be manufactured. Cause.

In an embodiment of the present invention, between the alignment region 30 and the element region ₅ 1, _{5 2} of the wafer 1, the protrusions ₉ 1, ₉ projection forming region ₇ 1 with _{2, 7 2} provided. Thus, dishing dicing area 3A, when generated in the interlayer insulating film in the 3B also, the dishing, element regions 5 ₁ than projection forming region 7 _1, 7 _2, from entering the 5 ₂ side, Can be suppressed.

  Further, in the embodiment of the present invention, the scale (size) of the dishing that occurs can be reduced. As a result, the scale (size) of the recess generated in the upper interlayer insulating film due to dishing can be reduced.

Thus, it is possible to prevent the large dishing, recess, such as extending to the element region 5 _1, 5 in ₂ occurs, thereby preventing the short circuit between wires of a semiconductor device.
Therefore, according to the embodiment of the present invention, the manufacturing yield of the semiconductor device can be improved.

As shown in FIG. 1, even in the dicing area 3A, there are places where alignment marks (alignment regions) are not provided, such as between the two semiconductor chip areas 2 ₃ and 2 ₄ . In this way, even in the semiconductor chip areas 2 ₃ and 2 ₄ that are not adjacent to the alignment mark, the convex portion forming region 9 ₃ is surrounded so as to surround the element regions 5 ₃ and 5 ₄ in the semiconductor chip areas 2 ₃ and 2 ₄ . , the may be provided with 9 _4, of course.

  In the following, each embodiment will be described by taking the alignment region 30 in which the alignment mark 35 is formed as an example of the region in the dicing areas 3A and 3B where the dummy pattern cannot be arranged, but the present invention is not limited to this. Of course, the region where the dummy pattern in the dicing area cannot be arranged may be, for example, a region provided with TEG instead of the alignment region 30.

(2) First embodiment
(A) Structure
The first embodiment of the present invention will be described with reference to FIGS.

FIG. 4 is a cross-sectional structure diagram schematically showing a cross section corresponding to the line CC in FIG. FIG. 4 shows a part of two semiconductor chip areas 2 ₁ and 2 ₂ and a dicing area 3A provided between the two areas 2 ₁ and 2 ₂ .

The element regions 5 ₁ and 5 ₂ of the semiconductor chip areas 2 ₁ and 2 ₂ in the wafer 1 are composed of an element isolation region provided with an element isolation insulating film 20 and an active region surrounded by the element isolation region. Yes.
The element region ₅ 1, _{5 2} in the active region, the element such as a MIS transistor Tr, a resistor 15 is formed.

The MIS transistor Tr is disposed in an active region partitioned by an element isolation insulating film 20 (element isolation region) formed in the wafer 1. The MIS transistor Tr has a gate electrode 12 on an active region (channel region) between two impurity diffusion layers 13 (hereinafter referred to as source / drain diffusion layers) as source / drain. A gate insulating film 12 is interposed between the gate electrode 12 and the channel region. For example, an insulating layer as a mask layer 93 is provided on the gate electrode 12. However, the present invention is not limited to this, and a structure in which the mask layer 93 is not provided over the gate electrode 12 may be employed.
The resistance element 15 is, for example, a diffusion layer resistance element including a diffusion layer 15 formed in the wafer 1.

Further, in the element region ₅ 1, _{5 2,} the dummy layer 19A is provided. The dummy layer 19A does not have an electrical function and is formed on the element isolation insulating film 20, for example. In this manner, by providing the element region 5 _1, 5 in ₂ as a pattern of the dummy layer 19, the coverage of the device region 5 _1, 5 in ₂ is suppressed.

In FIG. 4, only one MIS transistor Tr and one resistance element 15 are shown, but this is for simplification of description, and semiconductor chip areas 2 ₁ and 2 ₂ (element region 5). ₁ , 5 ₂ ) The formed elements are not limited to these elements.

A dicing area 3A is provided between the two element regions 5 ₁ and 5 ₂ . An alignment region 30 in which alignment marks 35 are formed is provided in the dicing area 3A. The alignment mark 35 is composed of, for example, an insulating film 35 embedded in the wafer 1.

  A first interlayer insulating film 41 is formed on the surface of the wafer 1. For example, a contact plug CP1 is embedded in the first interlayer insulating film 41, and the contact plug CP1 is connected to the source / drain diffusion layer 13 of the MIS transistor Tr and the resistance element 15. The contact plug CP1 is made of a refractory metal such as tungsten (W) or molybdenum (Mo).

  A second interlayer insulating film 42 is formed on the first interlayer insulating film 41. A first metal wiring M0 is provided in the second interlayer insulating film. The first metal wiring M0 is made of, for example, aluminum (Al) or copper (Cu).

  Further, a plurality of interlayer insulating films 43 to 46 and a plurality of metal wirings M1, M2 are stacked on the first and second interlayer insulating films 41, 42. The second metal wiring M1 is formed in the fourth interlayer insulating film 44 and is connected to the first metal wiring M0 via the first via contact V1 embedded in the third wiring layer 43. The third metal wiring M2 is formed in the sixth interlayer insulating film 46, and is connected to the second metal wiring M1 via the second via contact V2 embedded in the fifth interlayer insulating film 45. On the sixth interlayer insulating film 46, for example, a protective resin film (not shown) is formed.

The sixth interlayer insulating film 46 functions as, for example, a passivation film. The second and third metal wirings M1, M2 are made of, for example, Al or Cu. The first and second via contacts V1, V2 are made of, for example, W or Mo. The via contacts V1 and V2 may be connected to the metal wirings M1 and M2 through a barrier metal (for example, titanium (Ti) / titanium nitride (Ti)) formed in the contact hole. Of course.
Thus, in the semiconductor chip areas 2 ₁ and 2 ₂ formed in the wafer 1, for example, a semiconductor device using a multilayer wiring technique is provided.

In the first embodiment of the present invention, the semiconductor chip area ₂ 1, _second element region ₅ 1 in the _2, between _{5 2} and the alignment region 30 of the dicing area 3A, projection forming region ₇ 1, 7 ₂ is provided. In the convex portion forming regions 7 ₁ and 7 ₂ , convex portions 9 ₁ and 9 ₂ protruding in a direction perpendicular to the surface of the wafer 1 are formed. The protrusions 9 ₁ , 9 ₂ are, for example, protrusions cut out from the wafer 1, and the upper ends of the protrusions 9 ₁ , 9 ₂ are lower than the upper ends of the gate electrodes 12 of the MIS transistor Tr (semiconductor, for example) On the substrate side). Further, the convex portion forming region ₇ 1, _{7 2} (the protrusions ₉ 1, _{9 2),} for example, as shown in FIG. 1, it surrounds the periphery of the element region ₅ 1, _{5 2.}

The convex portion formation regions 7 ₁ and 7 ₂ are included in, for example, the semiconductor chip areas 2 ₁ and 2 ₂ . In this case, when the chip the wafer along the dicing area 3A, the structure of the semiconductor chip is a convex portion 9 _1, 9 ₂ are provided at an end of the semiconductor chip structure. However, the convex portion forming regions 7 ₁ and 7 ₂ may be included in the dicing area 3A, and the convex portions 9 ₁ and 9 ₂ may be separated from the semiconductor chip when the wafer is diced.

By providing the convex portions 9 ₁ and 9 ₂ as in this embodiment, the coverage in the vicinity of the dicing area 3A can be improved. Therefore, when the planarization process by the CMP method is performed, the size of the dishing Z generated at the upper end of the interlayer insulating film 41 in the alignment region 30 where the dummy pattern cannot be arranged can be reduced in the dicing areas 3A and 3B.

Thus, in the vicinity of the region can not be a dummy pattern, such as the alignment area 30, by providing the protrusions 9 _1, 9 _2, it is possible to reduce the scale of dishing Z generated in the lowermost layer of the interlayer insulating film 41 upper The scale of the depression Z ′ generated in the upper interlayer insulating films 42 to 46 due to the dishing Z can also be reduced. As a result of this, it is possible to suppress the large depression in the generation that enters the element region 5 _1, 5 _2.

Therefore, in the element region 5 _1, 5 _2, dishing Z moiety and the wiring material in the recesses Z 'in due to the dishing in the dicing area 3A can be prevented from remaining, short circuit between the conductive wiring layers residue wiring material It is possible to prevent the occurrence of wiring defects such as those in the formed semiconductor device.

  Therefore, according to the first embodiment of the present invention, the manufacturing yield of the semiconductor device can be improved.

(B) Manufacturing method
A method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. Here, each step will be described using a cross section corresponding to line CC in FIG.

First, as shown in FIG. 5, a resist is applied on the wafer 1. By photolithography, a resist predetermined patterning is performed on the resist mask 90 is formed on the wafer 1 between the element region 5 _1, 5 ₂ and the alignment region 30. Using this resist mask 90 as a mask, the wafer 1 is etched by, for example, RIE (Reactive Ion Etching).
As a result, convex portions 9 ₁ and 9 ₂ projecting in a direction perpendicular to the surface of the wafer (semiconductor substrate) 1 are formed in the convex portion forming regions 7 ₁ and 7 _{2 of} the wafer 1.

  Next, as shown in FIG. 6, a groove is formed in the alignment region 30 in the dicing area 3A, and an alignment mark 35 made of an insulating film is embedded in the groove.

In the element region 5 _1, 5 _2, grooves are formed in the element isolation region, a groove formed, the element isolation insulating film 20 is formed. Thus, the active area is divided into element regions ₅ 1, _{5 2.} Then, a predetermined region in the element region ₅ 1, _{5 2,} MIS transistor Tr, a resistor 15, elements such as a memory cell (not shown), CVD (Chemical Vapor Deposition) method thin film deposition techniques such as photo It is formed using a lithography technique, an RIE method, or the like.

For example, in the manufacturing process of the MIS transistor Tr, first, the gate insulating film 11 is formed on the surface of the active region (wafer 1) by using, for example, a thermal oxidation method. Next, a polysilicon film, for example, is deposited on the gate insulating film 11 using the CVD method. Further, a mask layer (for example, a silicon nitride film) 93 is formed on the polysilicon film. Then, the mask layer 93 is patterned by a photolithography technique, and the polysilicon film is processed by the RIE method based on the transferred pattern. As a result, a gate electrode 12 having a predetermined pattern is formed. Then, using the formed gate electrode 12 (mask layer 93) as a mask, the source / drain diffusion layer 13 is formed in the wafer 1 using an ion implantation method.
The resistance element 15 is manufactured by forming the diffusion layer 15 in an active region of a predetermined size, for example, by ion implantation of a predetermined dose.
The dummy layer 19A is formed on the element isolation insulating film 20 in the same process as the gate electrode of the MIS transistor Tr, for example.
After the plurality of elements constituting the semiconductor device are formed on the wafer, the first interlayer insulating film 41 is formed on the wafer 1 by using, for example, a CVD method. At this time, in the regions 5 ₁ , 5 ₂ , 7 ₁ , 7 ₂ provided with the gate electrode 12, the dummy layer 19 A, and the convex portions 9 ₁ , 9 ₂ , these regions 5 ₁ , 5 ₂ , 7 ₁ , 7 _{2 The} upper surface of the interlayer insulating film 41 above is raised more than the upper surface of the interlayer insulating film 41 above the region where the pattern is not provided (for example, the alignment region 30).

Incidentally, the upper end of the convex portion ₉ 1, _{9 2} is at a position lower than the upper end of the gate electrode 12, than the wafer (semiconductor substrate) 1 surface of the element region ₅ 1, _{5 2,} at a higher position.

Subsequently, as shown in FIG. 7, the upper surface of the interlayer insulating film 41 is planarized by CMP using the mask layer 93 on the gate electrode 12 as a stopper. As in the present embodiment, the region ₇ 1, ₇ by provided in _2, the coverage of the alignment region 30 near between the protrusions ₉ 1, _{9 2} element region ₅ 1, _{5 2} and the alignment region 30 Will rise.
As a result, the occurrence of large-scale dishing Z on the upper surface of the interlayer insulating film 41 can be suppressed. That is, even if dishing occurs in the interlayer insulating film 41 in the alignment region 30 (dicing areas 3A and 3B), the dishing Z extends over the convex portion forming regions 7 ₁ and 7 ₂ and the element regions 5 ₁ and 5 _2. It can be prevented from spreading inside.

  Note that the mask layer 93 on the gate electrode 12 may be removed and the gate electrode 12 may be silicided after planarizing the upper surface of the interlayer insulating film 41 by CMP.

  Then, as shown in FIG. 8, the second interlayer insulating film 42 is formed on the first interlayer insulating film 41 by using, for example, a CVD method. The first and second interlayer insulating films 41 and 42 are patterned by using a photolithography technique. Based on the formed pattern, the interlayer insulating films 41 and 42 are etched by the RIE method, and contact holes and wiring grooves are formed at predetermined positions in the interlayer insulating films 41 and 42. Then, the contact plug CP1 and the first metal wiring M0 are embedded in the formed contact hole and wiring trench using the damascene method. At the upper end of the second interlayer insulating film 42, a recess Z ′ is generated due to the dishing Z.

As mentioned above, dishing in planarizing step for the first interlayer insulating film 41 (see FIG. 7), by which the convex portions 9 _1, 9 ₂ are provided, which occurs in the alignment region 30 above the interlayer insulating film 41 the top surface The scale of Z becomes smaller.

Therefore, as shown in FIG. 9, also recessed second interlayer insulating film 42 the top surface is due to the lower layer of dishing Z, scale generated recess Z ', such as entering the device region 5 _1, 5 in ₂ It will not be large.

Thereafter, as shown in FIG. 4, a plurality of metal wirings M1, M2, via contacts V1, V2, and interlayer insulating films 43 to 46 are sequentially formed by a process substantially similar to the process shown in FIG. At this time, since the scale of the dishing Z generated in the lower interlayer insulating film 41 is small, the depression Z ′ generated on the upper surfaces of the interlayer insulating films 43 to 46 is also reduced by the influence of dishing, and the generated depression Z ′ Entering into the areas 5 ₁ and 5 ₂ . Therefore, in the wiring layer is used interlayer insulating film 43 to 46, residues of the wiring material in the recesses Z '(not shown) that does not adversely affect the element region 5 _1, 5 within _2, wire It is possible to prevent the occurrence of a short circuit between the wirings due to the residue of the material.
Through the above steps, a semiconductor device having a multilayer wiring structure is manufactured in each of the plurality of semiconductor chip areas 2 ₁ to 2 ₄ in the wafer 1.

In the first embodiment of the present invention, the semiconductor chip area ₂ 1, _second element region ₅ 1 in the _2, between _{5 2} and the alignment region 30 of the dicing area 3A, projection forming region ₇ 1, 7 ₂ are formed, and the convex portions 9 ₁ and 9 ₂ projecting in the direction perpendicular to the surface of the wafer 1 are formed in the convex portion forming regions 7 ₁ and 7 ₂ . The upper ends of the convex portions 9 ₁ and 9 ₂ are higher than the surface of the wafer (semiconductor substrate) 1 and lower than the upper end of the gate electrode 12.
As in the present embodiment, by disposing the convex portions 9 ₁ and 9 ₂ in the regions 7 ₁ and 7 ₂ adjacent to the alignment region 30 where the dummy pattern cannot be formed, the coverage in the vicinity of the alignment region 30 is reduced. Can be reduced. Therefore, the scale (size) of the dishing Z generated on the upper surface of the first interlayer insulating film 41 formed in the lowermost layer of the stacked interlayer insulating films can be reduced.

In this way, the dishing Z on the upper surface of the lowermost interlayer insulating film 41 can be reduced, so that the size of the recess Z ′ caused by dishing generated in the upper interlayer insulating films 42 to 46 than the lowermost interlayer insulating film 41 is also increased. Can be small. Therefore, depression due to dishing Z and dishing Z 'is, can be suppressed from entering the device regions 5 _1, 5 _2.

Therefore, due to the dishing, the interlayer insulating film 42 to 46 upper surface, since the depression as entering from the dicing area 3A to the element region 5 _1, 5 in ₂ is not generated, with reference to FIGS. 8 and 9 as described, the wiring material remains in the dishing Z and depressions Z 'in the wiring defective semiconductor device formed in the element region 5 _1, 5 in ₂ (e.g., short circuit between wires) does not cause.
Therefore, according to the first embodiment of the present invention, the manufacturing yield of the semiconductor device can be improved.

(C) Supplementary examples
In the first embodiment of the present invention, interlayer insulation is provided by a structure in which convex portions 9 ₁ and 9 ₂ are provided in the regions 7 ₁ and 7 ₂ between the element regions 5 ₁ and 5 ₂ and the alignment region 30. The technique for suppressing the dishing generated in the film 41 and the depression caused by the dishing from expanding into the semiconductor chip area (element regions 5 ₁ and 5 ₂ ) has been described.

However, it is also possible to completely suppress dishing occurring on the alignment region 30 by optimizing the width of the convex portions 9 ₁ and 9 _{2 in} the x direction and the interval between the _two convex portions 9 ₁ and 9 _2. It is. In this case, as shown in FIG. 10, element regions 5 _1, 5 ₂ and the alignment region 30 above the interlayer insulating film 41 upper end is flat, depression due to dishing in the interlayer insulating film 42 to 46 which is formed on the upper layer Will no longer occur.

  Even in this case, in the present embodiment, it is possible to prevent a short circuit between wirings due to dishing. Therefore, according to the first embodiment of the present invention, the manufacturing yield of the semiconductor device can be improved.

  In the above example, the mask layer 93 is left on the gate electrode 12 of the transistor even after the planarization treatment of the upper surface of the interlayer insulating film 41 shown in FIG.

When the mask layer 93 on the gate electrode 12 is also regarded as a part of the wiring pattern (gate) and the gate electrode 12 and the mask layer 93 are formed as one stacked body, for example, in the process shown in FIG. (Mask layer / gate electrode) If the upper end is higher than the upper ends of the protrusions 9 ₁ and 9 ₂ in the protrusion formation regions 7 ₁ and 7 ₂ , the upper surface of the interlayer insulating film 41 is covered with the mask layer 93 as a stopper. Can be flattened. Thus, the protrusions 9 _1, 9 ₃ upper end, a position higher than the interface of the mask layer 93 and the gate electrode 12, or may be in the same position as the interface.

(3) Second embodiment
A second embodiment of the present invention will be described with reference to FIGS. In the present embodiment, the same members as those in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and description thereof will be given as necessary.

(A) Structure
The structure of the semiconductor device according to the second embodiment of the present invention will be described with reference to FIG. FIG. 11 is a cross-sectional structure diagram schematically showing a cross section corresponding to the line CC in FIG.

In the first embodiment, the convex portions 9 ₁ and 9 ₂ provided in the convex portion forming regions 7 ₁ and 7 ₂ are formed by cutting the wafer 1. However, the protrusions 9 ₁ and 9 ₂ only need to protrude in the direction perpendicular to the surface of the semiconductor substrate, and the constituent members of the protrusions 9 ₁ and 9 ₂ are not limited.
For example, as shown in FIG. 11, the convex portions 9 ₁ and 9 ₂ may be composed of insulating films 14B and 93 and a conductive film 19B.

  The semiconductor device includes, for example, a high withstand voltage MIS transistor having a threshold voltage of 20 V to 30 V and a low withstand voltage MIS transistor having a threshold voltage lower than that of the high withstand voltage MIS transistor (for example, the transistor in FIG. 4). Tr).

  The film thickness of the gate insulating film 14A of the high voltage transistor HTr is larger than the film thickness of the gate insulating film of the low voltage transistor in order to ensure a sufficiently large gate breakdown voltage. Therefore, the gate insulating film 14A of the high breakdown voltage MIS transistor HTr is formed in a separate process from the gate insulating film of the low breakdown voltage MIS transistor. However, the gate electrode 12 of the high voltage MIS transistor HTr is formed in the same process as the gate electrode of the low voltage MIS transistor.

Insulating film 11B constituting the protrusions 9 _1, 9 _2, for example, is formed simultaneously with the gate insulating film of the low-breakdown-voltage MIS transistors constituting the semiconductor device. Further, the protrusions ₉ 1, _{9 2} of the present embodiment, the conductive film 19B on the insulating film 11B is formed, for example, at the same time as the gate electrode 12 of the low-breakdown-voltage MIS transistor Tr. However, the conductive film 19B is a dummy layer having no electrical function. Hereinafter, the conductive layer 19B is referred to as a dummy layer 19B. An insulating layer 93 formed simultaneously with the mask layer is also disposed on the dummy layer 19B.

Thus, the convex portions 9 ₁ and 9 ₂ described in the present embodiment have substantially the same structure as the gate electrode of the low breakdown voltage MIS transistor Tr.

As in the present embodiment, the insulating layer 14B and the conductive layer 19B and the protrusions 9 _{1 consists,} 9 be _two, as in the first embodiment can not be a dummy pattern alignment region 30 near the The coverage rate can be improved, and an increase in the size of dishing that occurs in the alignment region 30 is suppressed. In the present embodiment, since dishing generated in the lower layer of the interlayer insulating film 41 is reduced, the interlayer insulating film 42 to 46 the upper surface of the upper layer, depression large as extending to the element region 5 _1, 5 within ₂ is formed Can be prevented. Thus, wiring material remaining in the depression generated in the interlayer insulating film 42 to 46 is, because it will not enter the device region 5 _1, 5 _2, short circuit between wires of the semiconductor device does not occur due to the residue of the wiring material.

  Therefore, also in the second embodiment of the present invention, the manufacturing yield of the semiconductor device can be improved.

(B) Manufacturing Method Hereinafter, the manufacturing process of the semiconductor device according to the second embodiment of the present invention will be described with reference to FIGS. 12 and 13 are process diagrams showing a cross section corresponding to the line CC in FIG. 1 as in FIG.

First, as shown in FIG. 12, of the element region 5 _1, 5 _2, region forming the high withstand voltage MIS transistors (hereinafter, the high voltage region hereinafter) wafer 1 the top surface of the is etched recesses in the wafer 1 U is formed. At this time, the alignment region 30 and the convex portion formation regions 7 ₁ and 7 ₂ are covered with a resist (not shown) so as not to be etched. Subsequently, the gate insulating film 14 of the high breakdown voltage MIS transistor is formed using, for example, a thermal oxidation method or a CVD method.

  Next, a resist mask 95A is formed in the high breakdown voltage region (concave portion) using, for example, a photolithography technique.

  In addition, it is preferable to form the concave portion U in the high breakdown voltage region so that the upper end of the gate insulating film 14 in the high breakdown voltage region and the surface of the wafer 1 in the region other than the high breakdown voltage region substantially coincide.

Subsequently, as shown in FIG. 13, the insulating film in the region where other elements such as the convex portion forming regions 7 ₁ and 7 ₂ and the low breakdown voltage MIS transistor are formed is formed by using, for example, wet etching or RIE method. The insulating film 14A remains only in the high breakdown voltage region.

Thereafter, in step similar to the step shown in FIG. 6 of the first embodiment, a plurality of elements constituting the alignment mark 35 and the semiconductor device, formed respectively in the alignment region 30 and the element region 5 _1, 5 in ₂ Is done.

In this step, simultaneously with the formation of the gate insulating film of the low breakdown voltage MIS transistor shown in FIG. 6, the insulating film 11B is formed on the surface of the wafer 1 in the convex portion forming regions 7 ₁ and 7 ₂ . A dummy layer 19B is formed simultaneously with the formation of the gate electrode of the low withstand voltage MIS transistor Tr on the insulating film 11B formed in the convex formation regions 7 ₁ and 7 ₂ . A mask layer 93 is formed on the dummy layer 19B in order to process the convex portions 9 ₁ and 9 ₂ into a predetermined shape. Further, the gate electrode 14A of the high breakdown voltage MIS transistor HTr is simultaneously formed using the same material as the dummy layer 19B.
As described above, the convex portions 9 ₁ and 9 ₂ including the insulating films 14B and 93 and the dummy layer (conductive layer) 19B are formed in the convex portion forming regions 7 ₁ and 7 ₂ . Since the convex portions 9 ₁ and 9 ₂ of this embodiment are formed simultaneously with the gate electrode of the low breakdown voltage transistor, the position of the upper end of the gate electrode and the position of the upper end of the convex portions 9 ₁ and 9 ₂ are the same.
After the protrusions 9 ₁ and 9 ₂ and the elements are formed, an interlayer insulating film 41 is formed on the wafer 1.

  Thereafter, the interlayer insulating films 42 to 46 and the wiring layers M0 to M2 are sequentially formed by using the steps shown in FIGS. 7 to 9 and the steps similar to those shown in FIG. 4 according to the present embodiment. A semiconductor device is completed.

As described above, in the present embodiment, the protrusions ₉ 1, _{9 2} is formed on the convex portion forming region ₇ 1, _{7 2,} protrusions ₉ 1, _{9 2} in the present embodiment, the insulating film 14B, 93 And a conductive layer (dummy layer) 19B.

In this embodiment, the region ₇ 1, _{7 2} of between alignment region 30 of the semiconductor chip areas ₂ 1, _second element region ₅ 1 in the _{2, 5 2} and the dicing area 3A, the protrusions ₉ 1, by placing the 9 _2, improves the alignment region 30 near the coverage, it is possible to reduce the scale of dishing generated in the interlayer insulating film 41. As a result, the scale of the depressions in the upper interlayer insulating films 42 to 46 generated under the influence of dishing can be reduced. That is, in the present embodiment, a large depression that enters the element regions 5 ₁ and 5 ₂ does not occur, and a residue of the wiring material in the depression is formed in the semiconductor device formed in the element regions 5 ₁ and 5 ₂ . In addition, wiring defects such as a short circuit between wirings are not caused.

  Therefore, also in the semiconductor device according to the second embodiment of the present invention, the manufacturing yield of the semiconductor device can be improved as in the first embodiment.

In the present embodiment, the convex portions 9 ₁ , 9 ₂ including the conductive layer and the insulating layer have been described. However, the present invention is not limited to this, and the convex portions 9 ₁ , 9 _{2 having} a single layer structure of the conductive layer. Or, for example, the convex portions 9 ₁ and 9 _{2 made} of an insulating film formed simultaneously with the element isolation insulating film 20 may be used.

2. Modified example
A modification of the embodiment of the present invention will be described with reference to FIGS.

In the first and second embodiments, the convex portion forming region ₇ 1, _{7 2} provided at the end of the semiconductor chip area 21, the element region ₅ 1, _{5 2} around the convex portion formation region _71, a semiconductor device having enclosed structure by 7 _2, has been described.

  First, a modification of the embodiment of the present invention will be described with reference to FIGS. 14 and 15. FIG. 14 is a plan view showing the structure of the present modification, and FIG. 15 shows a cross section corresponding to the line DD in FIG.

However, it is only necessary to reduce the scale (size) of dishing generated in the interlayer insulating film by providing the convex portions 9 ₁ and 9 ₂ , and the convex portion forming regions 7 ₁ and 7 ₂ are arranged in the semiconductor chip area 2. It is not limited to the ends of ₁ and 2 ₂ .

For example, as shown in FIGS. 14 and 15, first element regions 5A ₁ and 5A ₂ and second element regions 5B ₁ and 5B ₂ are provided in the semiconductor chip areas 21 and 22, and the protrusion forming regions 7 ₁ and 5B are provided. 7 ₂ may be provided between the first element region _5A 1, 5A ₂ and the second element region _5B 1, 5B _2. In the example shown in FIG. 14, the structure of the semiconductor chip areas 2 ₁ and 2 ₂ is such that the convex portion forming regions 7 ₁ and 7 ₂ surround the first element regions 5A ₁ and 5A ₂ , and further, the second element region 5B. ₁ and 5B ₂ surround the convex portion forming regions 7 ₁ and 7 ₂ . However, the layout of the element regions 5A ₁ , 5A ₂ , 5B ₁ , 5B ₂ and the convex portion forming regions 7 ₁ , 7 ₂ is not limited to the example shown in FIG.

In the example shown in FIG. 15, MIS transistors are provided in the first element regions 5A ₁ and 5A ₂ , and, for example, a guard ring GR is provided in the second element regions 5B ₁ and 5B ₂ . In the second element regions 5B ₁ and 5B ₂ , for example, a region where a member less important than the memory cell or its control element is formed, such as a guard ring GR, or a dummy element that does not function as an element is formed. This is the area that has been However, it goes without saying that the second element region may be a region where an element having a function with respect to the semiconductor device such as a resistance element is formed.

In addition, a modified example different from FIGS. 14 and 15 will be described with reference to FIG.
The convex portion formation regions 7 ₁ and 7 ₂ (convex portions 9 ₁ and 9 ₂ ) are provided between the region where the dummy pattern cannot be arranged and the element regions 5 ₁ and 5 ₂ , as in the alignment region 30. What is necessary is just to improve the coverage in the vicinity of the region where it cannot be arranged.

Thus, for example, as shown in FIG. 16, the convex portion forming region 7 _1, 7 _2, are only provided on one end and the other end of the alignment region 30 and adjoining element region 5 _1, 5 ₂ in the x-direction May be.

In this case, the y-direction of the one end and the other end of the element region ₅ 1, _{5 2} (semiconductor chip areas ₂ 1, _{2 2),} becomes better without providing a projection forming region, the semiconductor chip area ₂ 1, _{2 2} The size can be reduced.

As described above, also in the present modification, as in the first and second embodiments, the size (size) of dishing can be reduced, and the element region can be reduced by the dishing and the wiring material remaining in the depression resulting therefrom. 5 _1, the semiconductor device formed on 5 ₂ can be prevented from short circuit between the conductive wiring layers is caused.

  Therefore, according to the semiconductor device of the modification of the embodiment of the present invention, the manufacturing yield of the semiconductor device can be improved.

3. Application examples
An application example of the embodiment of the present invention will be described with reference to FIGS. In addition, about the same member as 1st and 2nd embodiment, the same code | symbol is attached | subjected and description is abbreviate | omitted.
FIG. 19 shows an entire configuration of a semiconductor chip which is an application example of the embodiment of the present invention. 17 and 18 schematically show cross-sectional structures along the x and y directions of the semiconductor chip 20 to which the embodiment of the present invention is applied.

In the example shown in FIGS. 17 to 19, the semiconductor chip 20 is a memory chip, element region 5 ₁ includes a memory cell array 100, for example, a row decoder and a sense amplifier, peripheral circuits such as control circuits are formed And a peripheral circuit region 120.

  The memory cell array 100 has, for example, a NAND flash memory configuration. In this case, a plurality of NAND cell units are provided in the memory cell array 100, and FIG. 17 shows one NAND cell unit. One NAND cell unit includes a plurality of memory cells MC whose current paths are connected in series in the y direction, and select transistors STD and STS provided at one end and the other end of the series connected memory cells MC. The

  The memory cell MC is, for example, a stack gate MIS transistor having a floating gate electrode 16 and a control gate electrode 18.

The floating gate electrode 16 is disposed on a gate insulating film (tunnel insulating film) 11A on the surface of the semiconductor substrate (wafer) 1. The floating gate electrode 16 functions as a charge storage layer that holds electrons (data).
A control gate electrode 18 is disposed on the floating gate electrode 16 via an interelectrode insulating film 17. The control gate electrode 18 extends in the x direction and is shared by a plurality of memory cells MC adjacent in the x direction. The control gate electrode 18 functions as a word line.

  For example, the upper portion of the control gate electrode 18 is silicided. The silicide process is performed after the mask layer on the formed gate electrode 18 is used as a stopper and the upper surface of the interlayer insulating film 41 is flattened, and then the mask layer on the control gate electrode 18 is peeled off. Therefore, in this case, the mask layer is not left on the control gate electrode 18.

  The memory cells MC adjacent in the y direction share the source / drain diffusion layer 13A, and their current paths are connected in series.

  The structure of the memory cell MC is not limited to the stack gate structure, but may be a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) structure.

  Since the select transistors STD and STS are formed at the same time as the memory cell MC, they have substantially the same structure as the memory cell MC. However, the gate electrode 12 of the select transistors STD and STS is an interelectrode insulating film in which a conductive layer formed simultaneously with the floating gate electrode 16 and a conductive layer formed simultaneously with the control gate electrode 18 are interposed between the conductive layers. It is connected via the opening formed in. The gate electrodes 12 of the select transistors STD and STS function as select gate lines.

  The select transistors STD and STS share one source / drain diffusion layer 13A with the adjacent memory cell MC, and their current path is connected in series to the current path of the memory cell MC.

  The source / drain diffusion layer 13S of the source side select transistor STS in the NAND cell unit is connected to the source line SL (first metal wiring) via the source line contact SC. The source / drain diffusion layer 13D of the drain side select transistor STD in the NAND cell unit is connected to the bit line BL (second metal wiring) via the bit line contact BC and the first metal wiring.

The peripheral circuit region 120 is provided with high breakdown voltage / low breakdown voltage MIS transistors HTr, Tr. Since the gate electrodes 12 of these MIS transistors HTr and Tr are also formed at the same time as the memory cell MC, they have the same stacked structure as the select transistors STD and STS.
The source / drain diffusion layers 13 and the gate electrodes 12 of the MIS transistors HTr and Tr are connected to the metal wirings M0 to M2 via the contact plug CP1.

  When the control gate electrode of the memory cell is silicided, the upper ends of the gate electrodes 12 of the selection transistor and the MIS transistor are also silicided. Therefore, the mask layer does not remain at the upper ends of the gate electrodes 12 of the selection transistor and the MIS transistor.

  In addition, as a resistance element provided in the memory chip 20, instead of the diffusion layer resistance element described in the first and second embodiments, a resistance having a conductive layer formed simultaneously with the floating gate electrode 16 as a resistor 16R. An element may be used. In such a resistance element, the conductive layer 18C formed at the same time as the control gate electrode functions as a contact, and is connected to the resistor 16R through an opening formed in the insulating film 17. The resistor (resistive element) 16R is connected to the metal wirings M0 to M2 via the conductive layer 18C and the contact plug CP2.

The projection forming region 7 ₁ so as to surround the element region 5 ₁ is provided between the end portion and the element region 5 ₁ of the memory chip 20. The projection forming region 7 _1, the protrusions 9 ₁ is provided. As shown in FIGS. 18 and 19, the protrusions 9 ₁ mentioned in this application example is a protrusion which is cut out from a semiconductor substrate (wafer) 1, the protrusions 9 ₁ of the memory cell MC stack It may be a stacked body composed of a conductive layer and an insulating layer having the same structure as the gate structures 16 and 18 or the gate structures 11 and 12 of the low breakdown voltage MIS transistor Tr.

In this application example, the protrusions 9 ₁ upper is positioned lower than the stacked gate electrodes 16 and 18 the upper end of the memory cell MC. The upper end of the convex portion 9 ₁ is at a higher position than the semiconductor substrate 1 (the memory cell formation region) surface. Note that in FIG. 18, the upper end of the convex portion 9 _1, for example, in a higher position than the upper end of the high-voltage / low-voltage MIS transistors HTr, an element isolation insulating film partitioning the region for forming the Tr.

As described in the first and second embodiment, by providing the protrusions 9 _1, the semiconductor device in the manufacturing process of (memory chip), dishing of scale (size) generated in the lower layer of the interlayer insulating film 41 And the size of the recesses in the upper interlayer insulating films 42 to 46 due to dishing can be reduced. Therefore, never recess large entering to the element region 5 ₁ occurs, wiring material remaining in the depressions, an adverse effect on the element formed in the memory cell array 100 and the peripheral circuit region 120 is Absent.

  Therefore, as in the application example of the present embodiment, it is possible to provide the memory chip 20 in which the short circuit between the wirings due to the residue of the wiring material does not occur.

  Therefore, according to the embodiment of the present invention, the manufacturing yield of a semiconductor device (for example, a memory chip) as in the application example of the embodiment of the present invention can be improved.

  In this application example, the semiconductor chip serving as a memory chip has been described as an example. However, the present invention is not limited thereto, and a semiconductor chip in which another semiconductor integrated circuit such as a logic circuit is formed may be used. Of course. Of course, the same effect can be obtained even in a semiconductor chip to which a modification of the embodiment of the present invention is applied.

4). Other
The example of the present invention can improve the manufacturing yield of the semiconductor device.

  The example of the present invention is not limited to the above-described embodiment, and can be embodied by modifying each component without departing from the gist thereof. Various inventions can be configured by appropriately combining a plurality of constituent elements disclosed in the above-described embodiments. For example, some constituent elements may be deleted from all the constituent elements disclosed in the above-described embodiments, or constituent elements of different embodiments may be appropriately combined.

1 is a plan view for explaining a basic configuration of a semiconductor device according to an embodiment of the present invention. Sectional drawing in alignment with the AA of FIG. Sectional drawing which follows the BB line of FIG. FIG. 3 is a cross-sectional view schematically showing the structure of the semiconductor device according to the first embodiment. The figure which shows 1 process of the manufacturing process of the semiconductor device which concerns on 1st Embodiment. The figure which shows 1 process of the manufacturing process of the semiconductor device which concerns on 1st Embodiment. The figure which shows 1 process of the manufacturing process of the semiconductor device which concerns on 1st Embodiment. The figure which shows 1 process of the manufacturing process of the semiconductor device which concerns on 1st Embodiment. The figure which shows 1 process of the manufacturing process of the semiconductor device which concerns on 1st Embodiment. The figure for demonstrating the supplementary example of 1st Embodiment. Sectional drawing which shows the structure of the semiconductor device which concerns on 2nd Embodiment typically. The figure which shows 1 process of the manufacturing process of the semiconductor device which concerns on 2nd Embodiment. The figure which shows 1 process of the manufacturing process of the semiconductor device which concerns on 2nd Embodiment. The top view for demonstrating the modification of embodiment. The figure which shows typically the cross section which follows the DD line | wire of FIG. The top view for demonstrating the modification of embodiment of this invention. The layout figure for demonstrating the example of application of embodiment of this invention. Sectional drawing for demonstrating the application example of embodiment of this invention. Sectional drawing for demonstrating the application example of embodiment of this invention.

Explanation of symbols

1: Wafer, 2 _{1 to} 2 ₄ : Semiconductor chip area, 3A, 3B: Dicing area, 30: Alignment area, 35: Alignment mark, 5 ₁ , 5 ₂ : Element area, 71, 72: Projection forming area, 9 _{1 to} 9 ₂ : convex portion, 11, 11A, 14A: gate insulating film, 12: gate electrode, 13: source / drain diffusion layer, 15: diffusion layer, 16: floating gate electrode, 16R: resistance layer, 17: gate Interlayer insulating film, 18: control gate electrode (word line), 14A, 19A, 19B: dummy layer, CP: contact plug, V1 to V2: via contact, 20: element isolation insulating film, M0 to M2: wiring layer, 41 ˜42: interlayer insulating film, 90, 95A: resist mask, 93: mask layer.

Claims (5)

A wafer,
Provided in the wafer, first and second semiconductor chip areas;
A first element region provided in each of the first and second semiconductor chips and in which a transistor is formed;
A dicing area provided between the first and second semiconductor chips;
An alignment region provided in the dicing area and where an alignment mark is formed;
A protrusion forming region provided between the first element region and the alignment region and having a protrusion protruding in a direction perpendicular to the wafer surface;
Comprising
The upper end of the convex portion is at a position higher than the wafer surface, and is at a position below the upper end of the gate electrode of the transistor.
A semiconductor device.   The semiconductor device according to claim 1, wherein the convex portion forming region is provided in the first and second semiconductor chip areas.   3. The semiconductor device according to claim 1, wherein the convex portion forming region is provided so as to surround the first element region. 4.   4. The device according to claim 1, further comprising: a second element region provided between the convex portion forming region and the dicing region and included in each of the first and second semiconductor chip areas. The semiconductor device according to any one of the above. A semiconductor substrate;
An element region provided in the semiconductor substrate, in which a transistor having a multilayer wiring structure is formed;
A convex portion provided in a region between the end portion of the semiconductor substrate and the element region, and projecting in a direction perpendicular to the surface of the semiconductor substrate;
The semiconductor device according to claim 1, wherein an upper end of the convex portion is at a position higher than a surface of the semiconductor substrate and is not higher than an upper end of the gate electrode of the transistor.

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