JP2010080709A - Forming method of silicon oxide film and manufacturing method of non-volatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a silicon oxide film acting as a low-temperature and superior insulating film. <P>SOLUTION: Trenches 1a and 1b are formed on a silicon substrate 1, and a coating film is formed by applying a coating agent wherein polymer including silazane bond is solved in an organic solvent. A polymer film is formed by vaporizing the organic solvent contained in the coating film. The polymer film is irradiated with ultraviolet rays at the temperature of 90°C or below, and the polymer film is soaked in purified water or water solution of the temperature of not lower than 50°C and lower than 80°C, to convert into a silicon oxide film 3. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for forming a silicon oxide film using a coating film and a method for manufacturing a nonvolatile semiconductor memory device.

  2. Description of the Related Art Semiconductor devices are actively being miniaturized for the purpose of improving performance such as improvement in element operation speed or low power consumption due to high integration and suppressing manufacturing cost. Although miniaturization of transistors and wiring is important for miniaturization of semiconductor devices, the difficulty of forming an element isolation region that insulates elements is increasing rapidly with miniaturization. This is because, with the miniaturization of devices such as transistors, the space between devices is naturally miniaturized, and embedding an insulating film having good insulating characteristics in the fine space itself has become more difficult with miniaturization. Because.

  In addition, along with the miniaturization of devices, wiring and barrier metals diffuse into metals (low oxidation resistance) such as copper (Cu), tantalum (Ta), ruthenium (Ru), or silicon (Si) in the thermal process. Metals that have not been used in semiconductor processes in the past, such as metals that are easy to do, are now being used.

  Further, in a transistor, a metal such as hafnium (Hf) or zirconium (Zr) is used for the gate insulating film, and an acid resistance such as cobalt silicide (CoSi), nickel silicide (NiSi), platinum silicide (PtSi) is used for the gate electrode. Metals with low chemical properties or metals that easily diffuse into silicon in the thermal process are beginning to be used, and it is important to promote low-temperature processing in the process of forming an inter-element insulating region. Yes.

As a technique for filling a fine space using an STI (shallow trench isolation) structure as an element isolation insulating film of a nonvolatile semiconductor memory device, for example, as disclosed in Patent Document 1, an SOG (spin on glass) technique is adopted. However, in the SOG film, heat treatment in an oxidizing atmosphere containing water vapor is indispensable in order to remove impurities in the film and adsorbed water in the film at the stage when the film is formed. However, as described above, heat treatment in an oxidizing atmosphere containing water vapor is difficult with the miniaturization of elements, and further lowering of the temperature is required, and it is difficult to form a high-quality insulating film in a narrow space. It has become very difficult.
JP 2004-179614 A

  An object of the present invention is to provide a method for forming a silicon oxide film which is a good insulating film at a low temperature and a method for manufacturing a nonvolatile semiconductor memory device using the method.

  One aspect of the method for forming a silicon oxide film of the present invention includes a step of applying a coating agent in which a polymer having a silazane bond is dissolved in an organic solvent on a substrate to form a coating film, and the organic included in the coating film A step of vaporizing a solvent to form a polymer film; a step of irradiating the polymer film with ultraviolet light at a temperature of 90 ° C. or lower; and a pure water having a temperature of 50 ° C. or higher and lower than 80 ° C. And a step of converting into a silicon oxide film by dipping in an aqueous solution.

  One aspect of a method for manufacturing a nonvolatile semiconductor memory device according to the present invention is a method for manufacturing a nonvolatile semiconductor memory device in which a memory cell transistor and a peripheral circuit transistor are formed on a semiconductor substrate. Forming a first element isolation groove corresponding to the cell transistor and a second element isolation groove corresponding to the transistor of the peripheral circuit; and silazane coupling in the first and second element isolation grooves. A step of forming a coating film by applying a coating agent in which a polymer having an organic solvent is dissolved, a step of forming a polymer film by vaporizing the organic solvent contained in the coating film, and a temperature of 90 ° C. or less on the polymer film Irradiating ultraviolet rays at a temperature of 5 ° C., and immersing the polymer film irradiated with the ultraviolet rays in pure water or an aqueous solution having a temperature of 50 ° C. or more and less than 80 ° C. By sequentially executing the step of converting the silicon oxide film I has a feature where the forming buried the silicon oxide film on the first and second element isolation groove.

  According to the present invention, a silicon oxide film which is a good insulating film can be formed at a low temperature.

(First embodiment)
A first embodiment in the case where the present invention is applied to a NAND flash memory device which is one of nonvolatile semiconductor memory devices will be described below with reference to FIGS. The drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones.

  FIG. 1 is a cross-sectional view along the direction in which the word line WL of the memory cell transistor is formed at the boundary portion extending from the end of the memory cell region to the peripheral circuit region. Memory cell transistors are formed in the memory cell region, and peripheral circuit transistors are formed in the peripheral circuit region. Moreover, these FIG. 1 has shown the state in the middle stage of the wiring process which is one stage of a manufacturing process.

  In FIG. 1, trenches 1a and 1b which are shallow in the memory cell region and deeply formed in other portions are provided in a surface layer portion of a silicon substrate 1 which is a semiconductor substrate. In each of these trenches 1a and 1b, a thin silicon oxide film 2 formed by an ALD (atomic layer deposition) method is formed on the inner surface, and a silicon oxide film 3 to be described later is embedded therein. These silicon oxide films 2 and 3 constitute an element isolation insulating film having a shallow trench isolation (STI) structure.

  A plurality of active regions 4 which are element formation regions of the silicon substrate 1 are separated and formed by the silicon oxide films 2 and 3 serving as element isolation insulating films. A silicon thermal oxynitride film 5 serving as a gate insulating film is formed on the upper surface of the active region 4 to a thickness of 8 nm, and a gate electrode MG of a memory cell transistor and a gate electrode PG of a peripheral circuit transistor are formed thereon. . A dummy gate electrode DG is formed at the boundary between the gate electrode MG of the memory cell transistor and the gate electrode PG of the transistor in the peripheral circuit region.

  Each of the gate electrodes MG, DG, and PG is formed by forming a phosphorus (P) -doped polycrystalline silicon film 6 having a thickness of 50 nm to be a floating gate electrode from below, and ONO (oxide-nitride-oxide) as an interelectrode insulating film The film 7 and the phosphorus (P) -doped polycrystalline silicon films 8 and 9 to be the control gate electrode film are laminated. The polycrystalline silicon films 8 and 9 formed on the ONO film 7 are formed as word lines connecting the gate electrodes MG of the memory cell transistor and the gate electrodes PG of the peripheral circuit transistors. Instead of the ONO film 7, a NONON (nitride-oxide-nitride-oxide-nitride) film can be used.

  The gate electrode PG of the transistor in the peripheral circuit is in a state in which the opening 7a is formed in the ONO film 7 and the polycrystalline silicon films 6 and 8 positioned above and below are electrically connected through the opening 7a. Is formed. In the figure, an ONO film 7 and a polycrystalline silicon film 8 extending from another gate electrode (not shown) are formed on the upper surface of the silicon oxide film 3 buried in the wide trench 1b formed in the peripheral circuit region. , 9 are formed.

  A silicon oxide film 10 is formed as an inter-layer dielectric (ILD) so as to cover the upper surface portion of the polycrystalline silicon film 9. A contact 11 is formed so as to penetrate the silicon oxide film 10 at the end of the polycrystalline silicon film 9 to be a word line or on the upper surface of the polycrystalline silicon film 9 formed on the silicon oxide film 3. A wiring layer 12 connected to the contact 11 is formed on the upper surface of the silicon oxide film 10. In addition to this configuration, a silicon oxide film as an interlayer insulating film and a wiring layer are further formed in an upper layer.

  In the above configuration, the silicon oxide film 3 embedded in the trenches 1a and 1b is formed by applying a coating agent in which a polymer having a silazane bond (perhydrogenated silazane) is dissolved in an organic solvent on the upper surface of the silicon substrate 1. The coated film (perhydrogenated silazane film) is formed, the organic solvent contained in the coated film is evaporated, and various processes described later are performed under low temperature conditions. As a result, a high-quality silicon oxide film 3 is formed by low-temperature processing. In this configuration, heat treatment in a high-temperature oxidizing atmosphere for converting the polymer film into a silicon oxide film is not required, so that there is little shift in threshold voltage in electrical characteristics and off-leakage current is also reduced. Can be obtained.

  Next, with reference to FIGS. 2 to 5, and various characteristics will be described with reference to FIGS. 6 to 9, focusing on the process of forming the silicon oxide film 3 at a low temperature in the manufacturing process having the above configuration. 2 to 5 show schematic configurations in the manufacturing process of the portion corresponding to FIG. In this embodiment, the NAND flash memory device is applied to the silicon oxide film 3 serving as an element isolation insulating film having an STI structure. After the polysilazane film is irradiated with ultraviolet (UV), hot water treatment is performed. This is an example of realizing an element isolation insulating film in which a high-quality insulating film with few impurities is embedded by performing cure by SPM (sulfuric acid / hydrogen peroxide mixture) treatment and subsequently performing steam oxidation.

  First, as shown in FIG. 2, a silicon thermal oxynitride film 5 to be a tunnel oxide film is formed on the upper surface of the silicon substrate 1 with a film thickness of 8 nm. Subsequently, a phosphorus (P) -doped polycrystalline silicon film 6 to be a floating gate electrode is formed with a film thickness of 50 nm. Further, a silicon nitride film 13 serving as a stopper material in a polishing process by a CMP (chemical mechanical polishing) method is formed on the upper surface with a film thickness of 60 nm.

  Next, the silicon nitride film 13, the polycrystalline silicon film 6, the silicon thermal oxynitride film 5, and the silicon substrate 1 are sequentially etched by a known lithography technique and reactive ion etching (RIE) method, The trenches 1a and 1b having a predetermined depth are formed.

Next, on the entire surface of the silicon substrate 1, that is, the upper surface of the silicon nitride film 13 on the silicon substrate 1 and the inner wall surfaces and bottom surfaces of the trenches 1a and 1b, a film forming temperature is 450 ° C. ) And oxygen (O ₂ ) to form a silicon oxide film 2 with a film thickness of 12 nm by the ALD method.

Subsequently, as shown in FIG. 3, the polysilazane film 14 is spin-coated at a flat portion of the silicon substrate 1 so as to have a film thickness of 600 nm to completely fill the trenches 1a and 1b. The polysilazane film 14 is formed as follows. Perhydrogenated silazane (perhydrosilazane) polymer [(SiH ₂ NH) _n ] having an average molecular weight of 1500 to 5500 is dispersed in xylene, dibutyl ether or the like to produce a perhydrogenated silazane polymer solution, and the perhydrogenation is performed. A silazane polymer (perhydrogenated polysilazane) solution is applied to the surface of the silicon substrate 1 by spin coating. The conditions of the spin coating method are, for example, a rotation speed of the silicon substrate 1 of 1000 rpm, a rotation time of 30 seconds, and a dropping amount of the perhydrogenated silazane polymer solution of 2 cc.

  Next, the silicon substrate 1 on which the polysilazane film 14 as a coating film is formed is heated to 150 ° C. on a hot plate and baked in an inert gas atmosphere for 3 minutes, thereby removing the solvent in the perhydrogenated silazane polymer solution. The polysilazane film 14 is converted into a polymer film by volatilization. In this state, in the film, carbon (C) or hydrocarbon (CH) derived from the solvent is present as impurities of several atomic percent to several tens of atomic percent, and nitrogen (N) derived from the polymer of polysilazane remains several tens atomic percent. is doing.

  Next, the polysilazane film 14 converted into a polymer film is irradiated with ultraviolet light (UV) having a wavelength of 150 nm to 300 nm. By irradiation with ultraviolet light, the silicon-nitrogen (Si-N) bond in the polysilazane film 14 is dissociated and the polysilazane film 14 changes to an active state. At this time, the wavelength of the ultraviolet light that is substantially equal to the energy of the silicon-oxygen (Si-O) bond is 142 nm. Therefore, the polysilazane film 14 is formed by conversion without using ultraviolet light longer than that. This is not preferable because ultraviolet irradiation damage remains in the silicon oxide film 3 to be formed. On the other hand, it was found that when the wavelength of ultraviolet light is longer than 300 nm, the oxidation of polysilazane described below hardly occurs. Note that room temperature is desired as the temperature at which the ultraviolet light is irradiated, and it is preferable to cool the substrate on which the polysilazane film 14 is formed. This is because the temperature at the time of ultraviolet light irradiation is high, for example, when it exceeds 90 ° C., sublimation of low molecular components from polysilazane occurs, and the mechanical strength of polysilazane is lowered, which is likely to cause film cracks.

Next, as shown in FIG. 4, the polysilazane film 14 is oxidized by being immersed in pure water maintained at a temperature of 50 ° C. or higher and lower than 80 ° C. for 30 minutes. In the oxidation process in pure water, water (H ₂ O) is infiltrated into the polysilazane film 14 to oxidize dangling bonds of silicon (Si) and silicon-hydrogen (Si—H) bonds to form silicon hydroxide (SiOH). ) And ammonia generated by dissociation of the silicon-nitrogen (Si-N) bond is discharged out of the film, thereby densifying the film. Thus, in this treatment, it is important that the solution contains water (H ₂ O) at a temperature of 50 ° C. or higher, and an acidic aqueous solution can be used instead of pure water.

This reaction depends on the solution temperature, and each time the solution temperature decreases by 10 ° C., the efficiency of diffusion and reaction decreases by about a half, so if the solution temperature is less than 50 ° C. This is insufficient for modifying the polysilazane film 14. It should be noted that before introducing water (H ₂ O) into the film, heating in, for example, water vapor at a high temperature of 100 ° C. or higher means that residual impurities such as carbon (C) and nitrogen (N) are thermally diffused in the film. However, it is not preferable because pile-up is promoted at the interface of the silicon substrate 1 to promote the formation of fixed charges. Also, the use of pure water at 80 ° C. or higher is not preferable because uniform reaction is inhibited by boiling of pure water. Therefore, the temperature of pure water is preferably set in the range of 60 ° C to 70 ° C. The immersion time is preferably in the range of 10 minutes to 30 minutes.

  6 and 7 show a polysilazane film (as UV (indicated by a broken line in the figure)) immediately after the ultraviolet irradiation, and a polysilazane film (UV + 25 ° C. Wash (indicated by a thin solid line in the figure)) washed at room temperature (25 ° C.) after the ultraviolet irradiation. Temperature) desorption gas analysis for each of polysilazane films (UV + 60 ° C. Boil, UV + 70 ° C. Boil (indicated by a one-dot chain line and a thick solid line in the figure)) immersed in warm water (60 ° C., 70 ° C.) after ultraviolet irradiation The result of having performed (TDS; thermal desorption spectroscopy) is shown.

As a result, in the polysilazane film immersed in warm water (60 ° C., 70 ° C.) after ultraviolet irradiation, the TDS peak changes greatly, and the release peak value of water (H ₂ O) absorbed in the film released at 400 ° C. or lower. On the contrary, the release peak value due to silicon hydroxide (SiOH) observed at 400 ° C. or higher is increased, and the total release amount of water (H ₂ O (m / z = 18)) is also small. I understand. Moreover, this reaction is mainly dependent on the temperature of warm water, and it turns out that there is almost no effect at temperature lower than 50 degreeC. This is because, as described above, the diffusion of water (H ₂ O) in the polysilazane film and the oxidation reaction strongly depend on the hot water temperature. That is, the step of immersing in warm water of 50 ° C. or higher is a polysilazane oxidation step and not a water absorption step. In TDS, since measurement is started after sufficient evacuation before measurement, water (H ₂ O) that is simply adsorbed on the surface and easily separated during evacuation is not measured. Thus, the polysilazane film is converted into the silicon oxide film 3 containing about 1 at% nitrogen (N).

Next, the polysilazane film treated with warm water after ultraviolet irradiation is immersed in SPM (mixed solution of sulfuric acid and hydrogen peroxide) at 100 ° C. or higher, preferably 120 ° C. or higher and 200 ° C. or lower for 15 minutes. Since the SPM temperature reaches 100 ° C. or higher, dangling bonds or silicon-hydrogen (Si—H) bonds of water (H ₂ O) and silicon (Si) that have penetrated into the polysilazane film 14 that has been treated with hot water after the ultraviolet irradiation. Oxidation due to the reaction is promoted, and the absorption of ammonia into the acidic SPM is also promoted. A SPM temperature higher than 200 ° C. is not preferable because the polysilazane film may be dissolved.

In this reaction, a chemical solution of 100 ° C. or higher is preferable to promote the reaction, but it is important that the chemical solution contains moisture. This is because in the case of a chemical solution that does not contain moisture, silicon hydroxide (SiOH) taken into the polysilazane film 14 in the previous warm water process is dissociated and water (H ₂ O) is released again. In the case of SPM, water is generated by the dissociation of hydrogen peroxide, which is suitable for this application. After this treatment, the polysilazane film 14 changes to a silicon oxide film 3 containing about 0.5 at% nitrogen (N). However, since the ultraviolet light hardly reaches the inside of the trench 1a portion in the gate electrode MG portion of the memory cell transistor having a narrow width such as the trench 1a, the embedded polysilazane is shown in FIG. The film 14 is still close to the state after baking. As a comparative example, a sample not subjected to SPM processing was also created.

  Next, the silicon oxide film 3 is densified by heat treatment in a water vapor atmosphere, and the polysilazane film 14 in the trench 1a in the memory cell region is converted into the silicon oxide film 3. Nitrogen (N) of about 0.5 at% remains in the silicon oxide film 3, and this nitrogen (N) is not strongly bonded to silicon (Si) due to the influence of ultraviolet irradiation, so that it is easy to move. Therefore, after nitrogen (N) which is easy to liberate by introducing water vapor at 300 ° C. or less, preferably 250 ° C. or less at which diffusion of nitrogen (N) can be suppressed is oxidized, the temperature is continuously raised to 500 ° C. in water vapor. Heat treatment. Through the above processing, the nitrogen concentration in the silicon oxide film 3 is reduced to 0.1 at% or less, and the silicon oxide film 3 itself is densified by the heat treatment. In addition, in order to compare with the prior art, a sample in the case where the water vapor oxidation was suddenly performed without performing the ultraviolet irradiation and the wet treatment was prepared and the data was measured.

  FIG. 8 shows the results of examining the steam introduction temperature dependence of steam oxidation. This FIG. 8 shows the formation of a polysilazane film on a p-type silicon substrate, and the introduction of ultraviolet rays (with UV) / warm water + water vapor introduction temperature at 500 ° C. steam oxidation after SPM treatment under various conditions. It is the result of measuring the shift of voltage. Thereby, the fixed charge due to the impurities caused by polysilazane is evaluated. When the impurities in the polysilazane diffuse to the surface of the p-type silicon substrate during the heat treatment, the charge is fixed, so that the condition that the flat band voltage shift is large is that there are many movable impurities. Moreover, the case where ultraviolet irradiation is not performed (without UV) was also shown as a comparative example.

  From this result, when ultraviolet irradiation is performed (with UV), the flat band voltage shift depends on the water vapor introduction temperature, and when the water vapor introduction temperature is low, the fixed charge is compared with the case where ultraviolet irradiation is not performed (without UV). However, when the water vapor introduction temperature is high, it is understood that the deterioration is worse than the case where ultraviolet irradiation is not performed.

  This is because the irradiation with ultraviolet rays causes the silazane bond to break and the nitrogen atom (N) is released, so that nitrogen (N) is more easily removed by oxidation than a normal polysilazane film, but easily during heat treatment. This is because it is in a state of being easily diffused. From the above results, it is understood that the steam introduction temperature during steam oxidation is 300 ° C. or less, preferably 250 ° C. or less.

  FIG. 9 shows a spectrum of infrared absorption in a Fourier transform infrared spectrophotometer (FTIR) measurement at each stage of the manufacturing process. According to this result, the polysilazane film is almost oxidized in warm water, the silicon-oxygen (Si-O) peak intensity is almost the same after the SPM treatment, and the oxidation reaction is almost completed at the end of the SPM treatment. You can see that

Next, as shown in FIG. 5, after the silicon oxide film 3 is densified by nitrogen (N ₂ ) annealing at 875 ° C., the silicon oxide films 3 and 2 are polished by the CMP method using the silicon nitride film 13 as a stopper. Then, it remains only in the trenches 1a and 1b. Subsequently, the silicon oxide film 3 remaining in the trenches 1a and 1b is etched back to a desired height by a known lithography technique and reactive ion etching (RIE) method. Next, the silicon nitride film 13 is removed in hot phosphoric acid. Thereby, an element isolation insulating film is formed.

  Thereafter, as shown in FIG. 1, an ONO film 7 serving as an interelectrode insulating film and a phosphorus (P) -doped polycrystalline silicon film 8 serving as a control gate electrode are formed. Next, a slit communicating with the phosphorus (P) -doped polycrystalline silicon film 6 in the peripheral circuit through the phosphorus (P) -doped polycrystalline silicon film 8 and the ONO film 7 by a known lithography technique and reactive ion etching (RIE) method. A shaped opening 7a is formed. Subsequently, a phosphorus (P) -doped polycrystalline silicon film 9 is formed on the entire surface of the silicon substrate 1, and phosphorus (P) -doped polycrystalline silicon films 9, 8 are formed by a known lithography technique and reactive ion etching (RIE) method. , And the ONO film 7 and the phosphorous (P) doped polycrystalline silicon film 6 are sequentially processed to separate the control gate electrode and the floating gate electrode. In the subsequent steps, a silicon oxide film 10 as an interlayer insulating film is formed, and contacts 11 and wirings 12 are formed. However, details are omitted here.

  The case where the silicon oxide film 3 is formed as described above and the case where the oxidation is performed only by steam oxidation for comparison, the dependence of the off-leakage current (Ioff) on the peripheral circuit on the gate width (W). The measured results are shown in Table 1 below.

  From the results shown in Table 1, it can be seen that when the gate width W is 1 μm or less, the off-leakage current Ioff is greatly increased in the case of the prior art as compared with the present embodiment. This is because as the width (= W) of the active area (AA) becomes narrower, the deterioration occurs, and the influence is remarkable in the N-channel transistor. Therefore, positive fixed charges are applied to the element isolation insulating film of the STI structure. This is because the threshold voltage Vt of the transistor is lowered in the active region (AA) in the vicinity of the element isolation insulating film. Even when the SPM process is not performed, the off-leakage current Ioff of the transistor is improved by the sequence of this embodiment, but a better result is obtained by combining with the SPM process. That is, it is because the impurities that are the source of fixed charges can be efficiently removed by a combination of ultraviolet irradiation / warm water treatment / SPM treatment at a low temperature of 200 ° C. or less where impurity diffusion cannot occur. On the other hand, it can be seen that even if a washing step at room temperature without an oxidizing effect such as hot water is added after ultraviolet irradiation, there is no impurity removal effect, and therefore no improvement in transistor characteristics can be obtained.

  In this embodiment, an example in which the present invention is applied to a NAND flash memory device has been described. However, the present invention is not limited to this, and an element having an STI structure such as a charge trap memory, a DRAM (dynamic random access memory), a logic device, or the like. Application to an isolation insulating film is possible, and it is possible to embed an element isolation insulating film with a small fixed charge in a trench without impairing the good embedding property of a coating type polysilazane film. Miniaturization becomes possible.

(Second Embodiment)
FIGS. 10 to 13 show a second embodiment of the present invention, in which a polysilazane film is used for embedding between wirings in a resistance change type memory device (ReRAM) having a two-layer structure to convert to a silicon oxide film. An example is shown. In this embodiment, when the polysilazane film is converted into a silicon oxide film, it can be basically formed at a temperature of 200 ° C. or lower, so that the memory cell is not degraded without deteriorating the diode characteristics of the peripheral circuit and the cell portion. There is an advantage that it is possible to stack the layers. Hereinafter, the manufacturing process will be schematically described focusing on the process of converting the polysilazane film into a silicon oxide film.

  10 to 13 show cross sections when the memory cell region of the resistance change type memory device is cut in each of the orthogonal bit line direction and the word line direction. The drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones.

  First, in FIG. 10, a transistor 22 serving as a peripheral circuit of a resistance change memory device on a silicon substrate 21, an element isolation insulating film 23 formed by embedding a silicon oxide film in a trench 21a, an interlayer insulating film 24, a contact plug 25, 26, 27, the first wiring layer 28, and the second wiring layer 29 are formed by a known semiconductor manufacturing technique.

  Next, as shown in FIG. 11, a tungsten film 30 to be a word line of the memory element is formed with a film thickness of 200 nm. Subsequently, the GeSbxTey film 31 serving as a resistance change element has a thickness of 10 nm, the tantalum oxide film 32 serving as a heater is 2 nm thick, the tungsten nitride film 33 serving as an upper electrode and barrier metal is 10 nm thick, and n + / n serving as a pin diode. A − / p + amorphous silicon laminated film 34 is formed with a film thickness of 50 nm / 100 nm / 50 nm, a tungsten nitride film 35 serving as a barrier metal is formed with a film thickness of 10 nm, and a tungsten film 36 serving as a polishing stopper by CMP is formed with a film thickness of 50 nm. To do.

  Subsequently, a tungsten film 36, a tungsten nitride film 35, an amorphous silicon laminated film 34, a tungsten nitride film 33, a tantalum oxide film 32, and a GeSbxTey film 31 formed by a known lithography technique and reactive ion etching (RIE) technique. The tungsten film 30 is collectively processed into a strip shape.

  Next, as shown in FIG. 12, a silicon nitride film 37 having a film thickness of 3 nm is formed between the laminated films that have been collectively processed by the ALD method. Subsequently, a silicon oxide film 38 made of polysilazane is formed. Here, the method of forming the silicon oxide film 38 is the same as that of the first embodiment. That is, a polysilazane film is spin-coated, baked at 150 ° C., and then irradiated with ultraviolet light having a wavelength of 172 nm. Thereafter, the first wet process is performed in warm water at 60 to 70 ° C. for 30 minutes, and then the second wet process is performed in SPM for 20 minutes to convert the polysilazane film into the silicon oxide film 38. To do.

  Next, the silicon oxide film 38 is planarized by a known CMP technique using the tungsten film 36 as a stopper. Thereafter, the tungsten film 39 serving as the first bit line is formed with a thickness of 100 nm, the tungsten nitride film 40 serving as the barrier metal is formed with a thickness of 10 nm, and the p + / n− / n + amorphous silicon laminated film 41 is formed with a thickness of 50 nm / 100 nm. / 50 nm, tungsten nitride film 42 serving as a barrier metal / lower electrode with a film thickness of 10 nm, tantalum oxide film 43 serving as a heater with a film thickness of 2 nm, GeSbxTey film 44 serving as a resistance change element with a film thickness of 10 nm, and a stopper during CMP processing A tungsten film 45 is formed with a film thickness of 50 nm. Further, the laminated films 39 to 45 are collectively processed by a known lithography technique and reactive ion etching (RIE) technique, and the laminated films 39 to 36 embedded between the silicon oxide film 38 and the silicon oxide film 38 are collectively processed. To do.

  Next, as shown in FIG. 13, the silicon nitride film 46 and the polysilazane film by the ALD method are applied to the side walls facing between the laminated films 31 to 36 and 39 to 45 which are collectively processed, as in the first layer. The silicon oxide film 47 is formed by performing the same process as described above. The polysilazane film is converted into the silicon oxide film 47 by sequentially performing ultraviolet irradiation, first wet treatment, and second wet treatment after coating. Thereafter, the silicon oxide film 47 is planarized by a known CMP technique.

  Next, a tungsten film 48 to be a second word line is formed and buried between the tungsten film 48, the silicon oxide film 47, and the silicon oxide film 47 by a known lithography technique and reactive ion etching (RIE) technique. The laminated films 40 to 45 are collectively processed. Next, a silicon nitride film 49 and a polysilazane film are applied between the laminated films 40 to 45 and the tungsten film 48 which are collectively processed in the same manner as the first and second layers, and the same processing as described above is performed. The silicon oxide film 50 is formed and buried. The polysilazane film is converted into the silicon oxide film 50 by sequentially performing ultraviolet irradiation, first wet treatment, and second wet treatment after coating. Thereafter, the silicon oxide film 50 is planarized by a known CMP technique.

  Next, the n + / n− / p + amorphous silicon multilayer film 34 and the p + / n− / n + amorphous silicon multilayer film 41 are crystallized and impurities are activated using RTP (Rapid Thermal Processing) technology. . As described above, a resistance variable memory cell in which two layers are stacked is formed. Thereafter, the interlayer insulating film 51 is formed, and the aluminum wiring 52 and the passivation film 53 are formed, whereby the resistance change memory device is completed.

  In this embodiment, a GST (GeSbxTey) film is used as a resistance change material. However, a chalcogenide-based GST (GeSbxTey), nitrogen (N) whose resistance state changes due to Joule heat generated by a voltage applied to both ends. A material such as doped GST, oxygen (O) doped GST, GeSb, or InGexTey can be used.

Further, although tantalum oxide is used as the heater material, niobium oxide, titania or the like can be used, and a heater can be omitted. Further, although not chalcogenide, NiO, CuO, HfO ₂ , ZrO ₂ , PrxCa 1 -xMnO ₃ , SrTiO ₃ , FeO doped with a metal such as TiO ₂ , NiO, or Ti whose resistance value changes depending on the voltage applied to both ends. It is also possible to use a metal oxide variable resistance material such as.

In this embodiment, tungsten nitride is used as the electrode material. However, the material does not impair the variable resistance by reacting with the heater material, for example, titanium nitride, titanium nitride aluminum, tantalum nitride, titanium nitride silicide, tantalum carbide, titanium silicide. Tungsten silicide, cobalt silicide, nickel silicide, cobalt silicide, nickel platinum silicide, platinum, ruthenium, platinum rhodium, iridium, or the like can be used.
In addition to a semiconductor such as silicon or germanium, a pn junction of a metal oxide semiconductor such as NiO, TiO, CuO, or InZnO, or a Schottky diode using a metal and semiconductor Schottky junction can be used as a diode material. It is.

  Table 2 shows the order of the diodes in the case where the structure in the present embodiment is adopted and the case where the polysilazane film corresponding to the prior art is converted into a silicon oxide film by steam oxidation at 600 ° C. and used as an interlayer insulating film. The result of comparing the direction current / reverse off-leakage current and the write current / erase current is shown.

  From the above results, in the structure of this embodiment, the process of forming the silicon oxide film can be performed at a low temperature, so that the impurity profile of the diode is not easily broken, and the rectification characteristics of the diode are greatly improved. It can be seen that the cell can be realized.

  As described above, since the erase current can be reduced in the structure of this embodiment, there is an advantage that it is possible to create a resistance change type memory device particularly suitable for mobile use in which power consumption is desired to be suppressed.

(Third embodiment)
FIGS. 14 to 17 show a third embodiment of the present invention. In this embodiment, the present invention is applied to a process for forming an insulating film necessary for forming a thin film transistor (TFT) of a liquid crystal display device. An example is shown.

  In a liquid crystal display device, it is required to form an insulating film at a low temperature in order to form a TFT on a glass substrate. Usually, a plasma CVD (chemical vapor deposition) method has been used. First, it is difficult to handle large-area liquid crystals, it is difficult to ensure film thickness uniformity, and since a vacuum system is required, the device tends to become huge, and second, plasma TFTs are easily damaged. There was a problem.

In this respect, in this embodiment, since a relatively good quality silicon oxide film can be formed without using plasma, there is an advantage that a good TFT can be realized by a simple manufacturing process.
In this embodiment, a configuration in which the method is applied to a silicon oxide film of a semiconductor device applied to a TFT liquid crystal will be described.

  First, as shown in FIG. 14, a first polysilazane film 62 is formed by coating a perhydrogenated polysilazane solution with a thickness of 200 nm on the entire surface of a glass substrate 61 as a substrate. The method for forming the perhydrogenated polysilazane solution is the same as the method shown in the first embodiment. Next, the glass substrate 61 is heated to 150 ° C. in an oven to volatilize the solvent in the perhydrogenated polysilazane coating film. Subsequently, the polysilazane film 62 is irradiated with ultraviolet light having a wavelength in the range of 150 nm to 190 nm. The Si—N bond in the polysilazane film 62 is dissociated by ultraviolet light irradiation, and the polysilazane film 62 changes to an active state.

Next, as a first wet process, the polysilazane film 62 is oxidized by being immersed in pure water maintained at a temperature of 70 ° C. to 80 ° C. for 10 minutes. Specifically, water (H ₂ O) is infiltrated into the polysilazane film 62 to oxidize dangling bonds and Si—H bonds of silicon (Si) and to remove ammonia generated by dissociation of Si—N bonds outside the film. To discharge.

  Subsequently, as a second wet process, the polysilazane film 62 subjected to warm water treatment after ultraviolet irradiation is immersed in SPM (sulfuric acid / hydrogen peroxide solution) for 15 minutes to suppress the metal diffusion from the glass substrate to the polysilazane film. Into a silicon oxide film 63 for the purpose.

  Next, an amorphous silicon film is deposited to a thickness of 200 nm on the entire upper surface of the silicon oxide film 63 of the glass substrate 61 and patterned by photolithography. Subsequently, the polycrystalline silicon film 64 is formed by crystallizing the amorphous silicon film by laser annealing.

  Next, a perhydrogenated polysilazane to be a gate oxide film is applied to the polycrystalline silicon film 64 by, for example, an ink jet method to form a second polysilazane film, and a wavelength of 150 nm to 190 nm is formed similarly to the first polysilazane film. The silicon oxide film 65 is formed by performing ultraviolet light irradiation in the range, the first wet treatment step, and the second wet treatment step. Furthermore, the glass substrate 61 is introduced into a furnace at 200 ° C., water vapor is introduced at 200 ° C., and oxidation treatment is performed for 30 minutes. Thereafter, the temperature is continuously raised to 400 ° C. in water vapor and oxidized at 400 ° C. for 10 minutes. As a result, a high-purity film containing only about 0.3 at% nitrogen (N) is formed in the silicon oxide film 65 serving as a gate insulating film.

  Next, a material for the gate electrode film is formed on the upper surface of the silicon oxide film 65 and patterning is performed to form the gate electrode film 66. Subsequently, diffusion layers 64a and 64b serving as source / drain are formed in the polycrystalline silicon film 64 by ion implantation and activation treatment. Next, a coating film of a third polysilazane solution is formed on the entire upper surface of the glass substrate 61 at 400 nm, and irradiation with ultraviolet light having a wavelength in the range of 150 nm to 190 nm is performed as in the case of the first and second polysilazane films described above. The silicon oxide film 67 is formed as an interlayer insulating film by performing the first wet processing step and the second wet processing step.

  Next, a contact hole is formed in the silicon oxide film 67 to form a contact hole communicating with the gate electrode 68 of the transistor and the diffusion layers 64a and 64b. Subsequently, an aluminum film is formed so as to fill the contact hole. Subsequently, the aluminum film is processed by a known lithography technique and etching technique to form contact plugs 68, 69, 70 and wirings, thereby forming TFT liquid crystal TFT transistors.

  Results of measurement of impurity distribution in the perhydrogenated polysilazane film (Coat + Bake) in the above embodiment and the silicon oxide film (UV + Boil + SPM) converted by the formation method of the present embodiment by SIMS (secondary ion mass spectroscopy) Are shown in FIGS. 16 and 17. 16 shows the concentration distribution of carbon (C), and FIG. 17 shows the concentration distribution of nitrogen (N). From this result, in the process of forming the silicon oxide film, nitrogen (N) is uniformly converted into oxygen (O) in the film despite the fact that almost no high-temperature heat treatment process is used, and carbon (C) It can be seen that the number is also decreasing. The peak appearing at the substrate interface is a peak due to SIMS measurement and not an actual peak.

  According to the present embodiment, a relatively good quality silicon oxide film can be formed at a low temperature below 150 ° C., the baking temperature of the perhydrogenated polysilazane film. Wo can be formed, whereby the characteristics of the TFT can be improved.

Table 3 shows the residual carbon (C) concentration in the silicon oxide film formed by the method of this embodiment and the threshold voltage of the transistor. Here, for comparison,
(A) When using an oxide film formed by plasma CVD of TEOS (tetra-ethoxysilane) raw material,
(B) In the case of using a perhydrogenated polysilazane that can be modified to a silicon oxide film at a low temperature (300 ° C. or lower) by adding an amine as a low-temperature oxidation catalyst, the residual carbon (C) concentration in the oxide film and 120 of the gate oxide film are used. TDDB (time dependent dielectric breakdown) [year], which is a time-dependent dielectric film breakdown at 0 ° C., and a threshold voltage of a transistor formed using these oxide films are shown.

  As described above, according to the insulating film forming method according to the present embodiment, the perhydrogenated polysilazane is compared with less residual carbon at a low temperature without introducing an amine in which carbon (C) is likely to remain in the film as an impurity. It can be modified to a silicon oxide film with good quality. As a result, the carbon-derived fixed charge on the threshold voltage of the transistor can be minimized. In addition, since there is only a low-temperature process, it is possible to minimize the diffusion of metals such as sodium from the glass substrate 61, so that it is possible to improve the reliability of the gate oxide film (longer TDDB). is there. That is, according to the method for forming a silicon oxide film according to the present embodiment, a high-quality silicon oxide film having a higher purity than that of plasma CVD in which carbon tends to remain in the film can be formed at a lower temperature.

  The present invention is not limited to the application examples shown in the embodiments, and a high-quality silicon oxide film with few impurities is formed at a low temperature using a perhydrogenated polysilazane film, or a silicon oxide film with excellent embeddability is formed. Application to applications formed at low temperatures is possible.

Schematic sectional view showing a first embodiment of the present invention Schematic sectional view corresponding to FIG. 1 shown in one stage of the manufacturing process (No. 1) Schematic sectional view corresponding to FIG. 1 shown in one stage of the manufacturing process (No. 2) Schematic sectional view corresponding to FIG. 1 shown in one stage of the manufacturing process (No. 3) Schematic sectional view corresponding to FIG. 1 shown in one stage of the manufacturing process (No. 4) Results of thermal desorption gas analysis (TDS) of silicon oxide film under various conditions (intensity distribution when the TDS temperature is plotted on the horizontal axis) Results of thermal desorption gas analysis (TDS) of silicon oxide film under various conditions (peak value data when the Boil temperature is plotted on the horizontal axis) The figure which shows the result of having measured the steam introduction temperature dependence of steam oxidation as a shift of the flat band voltage of a capacitor The figure which shows the spectrum of the infrared absorption in the Fourier-transform infrared spectrophotometer (FTIR) measurement in each step of a manufacturing process Typical sectional drawing at the time of cut | disconnecting in the planar direction which shows the 2nd Embodiment of this invention and is mutually orthogonal at the stage of a manufacturing process (the 1) Schematic cross-sectional view when cutting in plane directions perpendicular to each other in one stage of the manufacturing process (Part 2) Schematic cross-sectional view when cutting in plane directions orthogonal to each other in one stage of the manufacturing process (No. 3) Schematic cross-sectional view when cutting in plane directions perpendicular to each other in one stage of the manufacturing process (No. 4) Typical sectional drawing in the stage of a manufacturing process which shows the 3rd Embodiment of this invention (the 1) Schematic cross-sectional view at one stage of the manufacturing process (Part 2) The figure which shows the result of having measured the carbon distribution in a silicon oxide film and a perhydrogenated polysilazane film | membrane by SIMS The figure which shows the result of having measured the nitrogen distribution in a silicon oxide film and a perhydrogenated polysilazane film | membrane by SIMS

Explanation of symbols

  In the drawings, 1 is a silicon substrate (semiconductor substrate), 3 is a silicon oxide film, 5 is a silicon thermal oxynitride film, 6 is a polycrystalline silicon film, 7 is an ONO film, 8 and 9 are polycrystalline silicon films, and 14 is an excess film. Hydrogenated polysilazane film (polymer film), 21 is a silicon substrate (semiconductor substrate), 22 is a transistor, 23 is an element isolation insulating film, 38, 47 and 50 are silicon oxide films, 61 is a glass substrate (substrate), and 62 is a polymer Films 63, 65, and 67 are silicon oxide films.

Claims (5)

Applying a coating agent in which a polymer having a silazane bond is dissolved in an organic solvent on a substrate to form a coating film;
Vaporizing the organic solvent contained in the coating film to form a polymer film;
Irradiating the polymer film with ultraviolet rays at a temperature of 90 ° C. or lower;
And a step of converting the polymer film irradiated with ultraviolet rays into a silicon oxide film by immersing the polymer film in pure water or an aqueous solution having a temperature of 50 ° C. or higher and lower than 80 ° C. The method for forming a silicon oxide film according to claim 1,
The method for forming a silicon oxide film, wherein the polymer film has a wavelength of ultraviolet light irradiated at a temperature of 90 ° C. or lower in a range of 150 nm to 300 nm. The method for forming a silicon oxide film according to claim 1,
Following the step of converting the polymer film into a silicon oxide film,
A method for forming a silicon oxide film, comprising performing an oxidation process in a steam atmosphere at 300 ° C. or lower. The method for forming a silicon oxide film according to claim 1,
In the step of converting the polymer film into a silicon oxide film,
A step of immersing the polymer film irradiated with ultraviolet rays in pure water or an aqueous solution having a temperature of 50 ° C. or higher and lower than 80 ° C. followed by a step of immersing in a chemical solution containing water of 100 ° C. or higher is performed. Forming a silicon oxide film. A method for manufacturing a nonvolatile semiconductor memory device, in which a memory cell transistor and a peripheral circuit transistor are formed on a semiconductor substrate,
Forming a first element isolation groove corresponding to the memory cell transistor and a second element isolation groove corresponding to the peripheral circuit transistor in the semiconductor substrate;
Applying a coating agent in which a polymer having a silazane bond is dissolved in an organic solvent in the first and second element isolation grooves to form a coating film;
Vaporizing the organic solvent contained in the coating film to form a polymer film;
Irradiating the polymer film with ultraviolet rays at a temperature of 90 ° C. or lower;
The first and second elements are sequentially performed by performing a step of converting the polymer film irradiated with ultraviolet rays into a silicon oxide film by immersing the polymer film in pure water or an aqueous solution having a temperature of 50 ° C. or higher and lower than 80 ° C. A method of manufacturing a nonvolatile semiconductor memory device, wherein the silicon oxide film is embedded in an isolation trench.

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