JP2010080633A - Semiconductor device, wafer structure, and method for manufacturing the semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a method for manufacturing the semiconductor device which can enhance heat dissipation efficiency and can prevent yield reduction and reliability. <P>SOLUTION: This semiconductor device includes: a silicon substrate 101 with a recess part DP1 formed at the back thereof; a p-type semiconductor layer 103 grown on the back and on a top face on the opposite side in the silicon substrate 101; and a MOSFET including a source electrode 108s and a drain electrode 108d, which are formed separately upward or sideward of the p-type semiconductor layer 103. In the p-type semiconductor layer 103, at least one of a lattice constant and a coefficient of thermal expansion differs from that of the silicon substrate 101. The recess part DP1 is formed in a region involving at least a region sandwiched between the source electrode 108s and the drain electrode 108d when viewed from a thickness direction of the silicon substrate 101. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device, a wafer structure, and a method for manufacturing the semiconductor device, and more particularly to a semiconductor device using a group III nitride semiconductor, a wafer structure, and a method for manufacturing the semiconductor device.

_{Conventionally, Al x In y Ga 1-} x-y As u P v N 1-u-v ( however, 0 ≦ x ≦ 1,0 ≦ y ≦ 1, x + y ≦ 1,0 ≦ u ≦ 1,0 ≦ v An electronic device such as a field effect transistor using a nitride compound semiconductor represented by ≦ 1, u + v <1), for example, a GaN compound semiconductor, can operate stably even in a high temperature environment close to 400 ° C. Is attracting attention as a solid device.

  However, unlike silicon (Si) or gallium arsenide (GaAs), it is difficult for a GaN-based compound semiconductor to produce a single crystal substrate having a relatively large diameter. Therefore, in recent years, for example, a GaN-based compound semiconductor layer is epitaxially grown on a substrate made of a material such as silicon carbide (SiC), sapphire, ZnO, or Si (hereinafter referred to as a support substrate), and a laminate formed thereby. A technique for manufacturing an electronic device using a substrate is used. In particular, a substrate made of Si is widely used as a support substrate for an electronic device using a GaN-based compound semiconductor layer because a substrate having a relatively large diameter can be obtained at a low cost.

  However, Si and GaN have very large differences in lattice constants and thermal expansion coefficients. For this reason, when the GaN layer is directly epitaxially grown on the Si substrate, a relatively large tensile strain is inherent in the GaN layer. This tensile strain becomes a factor that causes problems such as generation of concave warpage and deterioration of crystallinity in the entire Si substrate on which the GaN layer is epitaxially grown. Further, if the inherent tensile strain is large, a crack may be generated in the GaN layer. Therefore, conventionally, a buffer layer as a strain relaxation layer is provided between the Si substrate and the GaN layer to reduce the inherent tensile strain (for example, see Patent Document 1 or 2 shown below).

JP 2003-59948 A JP 2007-88426 A

  By the way, in recent years, a power supply device has been developed using an electronic device using an epitaxially grown GaN-based compound semiconductor layer as an active layer for reasons such as being capable of stable operation at high temperatures and capable of high-speed operation. The technology to produce is drawing attention. Here, as one of the important factors in manufacturing a power supply device using an electronic device, there is an increase in the withstand voltage of the electronic device.

  However, a Si substrate that is easy to use in terms of lattice constant and cost has a lower resistance than, for example, a sapphire substrate. For this reason, in order to increase the withstand voltage of an electronic device using a Si substrate, it is necessary to increase the total thickness of the epitaxial layers formed on the Si substrate to alleviate electric field concentration. However, when the total thickness of the epitaxial layer is increased, the rigidity of the entire epitaxial layer is increased, which causes a problem that the tensile strain inherent in the laminated substrate composed of the Si substrate and the epitaxial layer increases.

  On the other hand, in an electronic device, since an element generates heat during operation, it is necessary to prevent the element temperature from excessively rising by efficiently releasing this heat to the outside. Therefore, conventionally, after the wafer process is completed, the substrate of the wafer is polished and thinned to reduce the thermal resistance of the device and improve the heat dissipation efficiency.

  However, in a semiconductor wafer obtained by epitaxially growing a GaN-based compound semiconductor layer on a Si substrate, the inherent tensile strain is large as described above. For this reason, when the substrate is thinly polished, the balance of stress between the epitaxial layer and the Si substrate is lost, which may cause a problem that a crack occurs in the wafer. Such a problem is a factor that greatly lowers the yield and reliability of the device after singulation, and needs to be solved.

  As described above, in an electronic device manufactured using a multilayer substrate in which a GaN-based compound semiconductor layer is epitaxially grown on a Si substrate, there is a trade-off between prevention of cracks due to tensile strain inherent in the multilayer substrate and improvement of heat dissipation efficiency. Therefore, the conventional technique has a problem that it is difficult to make both compatible.

  In addition, such a problem is not limited to the Si substrate, but a substrate made of a material having a lattice constant and / or a thermal expansion coefficient different from that of the layer to be epitaxially grown, such as SiC, sapphire, or ZnO (hereinafter referred to as a heterogeneous substrate) is used. Even in this case, the problem occurs in the same manner.

  Therefore, the present invention has been made in view of the above problems, and is a semiconductor device using a heterogeneous substrate and a method for manufacturing the semiconductor device, which improves heat dissipation efficiency and prevents a decrease in yield and reliability. An object of the present invention is to provide a semiconductor device, a wafer structure, and a method for manufacturing the semiconductor device.

  In order to achieve such an object, a semiconductor device according to the present invention includes a support substrate having a recess formed on the back surface, a compound semiconductor layer grown on the top surface of the support substrate opposite to the back surface, and the compound semiconductor. A semiconductor element including two electrodes formed above or laterally apart from each other, wherein the compound semiconductor layer has at least one of a lattice constant and a thermal expansion coefficient with respect to the support substrate. In other words, the recess is formed in a region including at least a region sandwiched between the two electrodes when viewed from the thickness direction of the support substrate.

  The semiconductor device according to the present invention described above is characterized in that the concave portion has a depth of 80% or more with respect to the thickness in the thickness direction of the portion where the singulated surface is formed in the support substrate.

  The semiconductor device according to the present invention described above includes a lead frame provided on the lower surface of the support substrate and having a convex portion that fits into the concave portion.

  The semiconductor device according to the present invention described above is characterized in that the semiconductor element includes at least one of MOSFET, HEMT, and SBD.

  The semiconductor device according to the present invention described above is characterized in that the compound semiconductor layer contains at least one of GaN, AlGaN, BAlGaN, InGaN, GaAs, InP, and SeGe.

  In addition, the wafer structure according to the present invention includes an element formation region in which one or more semiconductor elements each including a compound semiconductor layer and two electrodes formed apart from each other above or on the side of the compound semiconductor layer are formed. And an element isolation region disposed between the element formation regions, wherein the element formation is formed on a surface of the element formation region opposite to the element formation surface on which the semiconductor element is formed. A recess is formed in a region including at least a region sandwiched between the two electrodes when viewed from above.

  The above-described wafer structure according to the present invention is characterized in that the concave portion is formed other than under the element isolation region.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, wherein a semiconductor substrate is divided into pieces by cutting a support substrate including a plurality of element formation regions and element isolation regions partitioning each element formation region at the element isolation regions. A method of manufacturing a semiconductor device, comprising: a step of dividing a semiconductor device, wherein the compound semiconductor layer grown on the upper surface of the support substrate and two electrodes formed on or apart from the compound semiconductor layer are spaced apart from each other An element forming step of forming a semiconductor element including the element in the element forming region and a region other than under the element isolation region on the back surface of the support substrate between at least the two electrodes when viewed from the thickness direction of the support substrate. A recess forming step of forming a recess containing the region formed.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, wherein a semiconductor substrate is divided into pieces by cutting a support substrate including a plurality of element formation regions and element isolation regions partitioning each element formation region at the element isolation regions. A method for manufacturing a semiconductor device, comprising: a step of forming a concave portion in a region other than under the element isolation region on the back surface of the support substrate; and a step of growing on the upper surface of the support substrate. Forming a semiconductor element in the element formation region, the semiconductor element including a compound semiconductor layer and two electrodes formed on or above the side of the compound semiconductor layer so as to be spaced apart from each other, the two electrodes comprising: The support substrate is formed in a region included in the recess as viewed from the thickness direction of the support substrate.

  The depth of the concave portion according to the present invention is 80% or more of the thickness in the thickness direction of the portion where the individualized surface is formed on the support substrate.

  According to the present invention, since the recess for thinning the support substrate is formed under the region between the two electrodes functioning as the channel formation region in the compound semiconductor layer, the heat generated in the channel formation region during operation is supported by the support substrate. It is possible to efficiently dissipate heat from the back surface. In addition, since the thickness of the support substrate is secured in the region where the recess is not formed, it is possible to prevent the balance of stress between the compound semiconductor layer that is an epitaxial layer and the support substrate that is a different substrate from being lost. As a result, it is possible to realize a semiconductor device and a method for manufacturing the semiconductor device that can improve heat dissipation efficiency and prevent a decrease in yield and reliability.

  Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings. In the following description, each drawing only schematically shows the shape, size, and positional relationship to the extent that the contents of the present invention can be understood. Therefore, the present invention is illustrated in each drawing. It is not limited to only the shape, size, and positional relationship. Moreover, in each figure, a part of hatching in a cross section is abbreviate | omitted for clarification of a structure. Furthermore, the numerical values exemplified below are merely preferred examples of the present invention, and therefore the present invention is not limited to the illustrated numerical values.

<Embodiment 1>
Hereinafter, the semiconductor device 100 according to the first embodiment of the present invention will be described in detail with reference to the drawings.

(Constitution)
FIG. 1A is a top view showing a schematic configuration of a wafer 1 before the semiconductor device 100 according to the present embodiment is singulated, and FIG. 1B is a state before the singulation formed on the wafer 1 shown in FIG. 1A. 4 is an enlarged view of one schematic configuration of a plurality of semiconductor devices 100. FIG. FIG. 2 is a schematic diagram showing the layer structure of the AA ′ cross section in FIG. 1B. FIG. 3 is a cross-sectional view of the semiconductor device 100 separated into chips and mounted on the lead frame 120. 3 shows a cross section corresponding to FIG.

  As shown in FIG. 1A, a plurality of semiconductor devices 100 are formed on a wafer 1 in a two-dimensional array using a wafer process technique. Each semiconductor device 100 includes an element formation region AR1 in which a semiconductor element such as a MOSFET included therein is formed, and an element isolation region FR1 that electrically isolates the adjacent element formation region AR1.

  Further, as shown in FIG. 1B, in the wafer 1, in the element isolation region FR1 between the element formation regions AR1 that are adjacent vertically or horizontally, a scribe region SR that becomes a cut portion when each semiconductor device 100 is separated into pieces. Is set. In the present embodiment, each semiconductor device 100 is divided into chips by cutting the scribe region SR along a predetermined dicing line DL using, for example, a dicing blade or a laser cutter.

  In the present embodiment, as an example, the width of the element isolation region FR1 is about 300 μm, and the width of the scribe region SR is about 50 to 100 μm. The length of the element formation region AR1 in the longitudinal direction (for example, the channel length direction of the element to be formed) is about 7 mm, and the length in the short direction is about 3.5 mm. However, it is not limited to this. For example, the scribe region SR may be the same region as the element isolation region FR1. In addition, the width removed by dicing, that is, the width of the dicing blade, the spot diameter of the laser cutter, and the like do not have to be the same width as the scribe region SR, but may be smaller than the scribe region SR.

  Further, a silicon substrate 101 (see FIG. 2), which will be described later, is engraved from the back surface of the substrate (the surface opposite to the element formation surface) in at least the region below the channel formation region CR1, which is the drive portion of the semiconductor device 100. There is a recess DP1 formed. That is, in the present embodiment, at least the silicon substrate 101 below the channel formation region CR1 is thinner than the silicon substrate 101 in the scribe region SR that is a cut portion at the time of singulation. The channel formation region CR <b> 1 that is a driving portion of the semiconductor device 100 is a portion that generates heat during the operation of the semiconductor device 100. Therefore, the silicon substrate 101 under the channel formation region CR1 is thinned as in this embodiment. As a result, the thermal resistance of the silicon substrate 101 in the thinned portion can be reduced, so that the heat generated in the channel formation region CR1 can be efficiently radiated from the back surface of the substrate through the silicon substrate 101. It becomes.

  The recess DP1 does not necessarily have to be formed in the entire region under the channel formation region CR1, and if it is also formed in a part under the channel formation region CR1, the heat dissipation effect of the heat generated in the channel formation region CR1. It is possible to improve.

  Here, the number of semiconductor elements (MOSFET 100A in this description) formed in one element formation region AR1 is not limited to one. For example, as shown in FIG. 1B, a plurality of source electrodes 108s connected in a comb shape connected to a common source electrode pad PS and a plurality of drain electrodes connected in a comb shape connected to a common drain electrode pad PD. A plurality of MOSFETs connected in parallel may be formed in one element formation region AR1 by facing each other so as to mesh with 108d. In this case, a gate connected to a common or independent gate electrode pad PG is formed between the source and drain of each MOSFET. Note that the width in the longitudinal direction of each pad (PS, PD, PG) can be, for example, about 200 μm.

  When a plurality of semiconductor elements are formed in one element formation region AR1 as described above, for example, a region formed by connecting the outside of the channel formation region of the semiconductor element arranged at the outermost position among the plurality of arranged semiconductor elements is 1 It is preferable to consider the two channel forming regions and form the recess DP1 under the channel forming region. In the following, for simplicity of explanation, the semiconductor device 100 in which one MOSFET 100A is formed is taken as an example.

  As shown in FIG. 2, the layer structure of each element formation region AR1 includes, for example, a p-type semiconductor layer 103 that functions as a channel layer during operation and a heterojunction interface on a buffer layer 102 formed on a silicon substrate 101. The gate insulating film 106 on the p-type semiconductor layer 103 constituting a MOS (Metal Oxide Semiconductor) structure, and a carrier traveling layer 104 and a carrier supply layer 105 that generate a two-dimensional electron gas that can be used as carriers by forming. And a gate electrode 107, and a source electrode 108s and a drain electrode 108d formed in two regions sandwiching the gate electrode 107, whereby one MOSFET 100A is formed in each element formation region AR1.

  A trench TR1 is formed between the adjacent semiconductor devices 100, that is, in the element isolation region FR1, as a structure for electrically isolating the MOSFET 100A. The trench TR1 reaches, for example, the upper layer of the silicon substrate 101. Further, in the element formation region AR1 where the MOSFET 100A is formed, an interlayer insulating film 109 extending to the inside of the trench TR1 of the element isolation region FR1 is formed. In the interlayer insulating film 109, openings for exposing the gate electrode 107, the source electrode 108s, and the drain electrode 108d are formed, and each electrode (107, 108s, and 108d) extends from the opening to a part on the interlayer insulating film 109. Is formed on the interlayer insulating film 109 to form a metal layer 110. Further, a passivation film 111 for protecting the underlying MOSFET 100A and the like is formed on the interlayer insulating film 109 on which the metal layer 110 is formed.

  In the semiconductor device 100 having the above configuration, the region functioning as the channel formation region CR1 is mainly located below the region sandwiched between the source electrode 108s and the drain electrode 108d of the MOSFET 100A as shown in FIG. The p-type semiconductor layer 103, the carrier traveling layer 104 and / or the carrier supply layer 105. In other words, this region is a region where a current path from the source electrode 108 s to the drain electrode 108 d is formed, and is a drive portion of the semiconductor device 100. Therefore, in the present embodiment, the concave portion DP1 for thinning the silicon substrate 101 is formed in a region including at least a region sandwiched between the source electrode 108s and the drain electrode 108d when viewed from the thickness direction of the silicon substrate 101.

  However, since the recess DP1 for thinning the silicon substrate 101 is enlarged from the bottom of the recess toward the opening of the recess as shown in the drawing, the recess can be easily formed. Further, it is not formed at least in a portion removed during dicing. This is because, for example, to support a cutting portion to which a dicing blade or the like is pressed during dicing, to ensure rigidity or resistance of the wafer 1 against stress such as vibration or heat generated during dicing, In order to secure a bonding surface (back surface of the wafer 1) with the dicing sheet DS to which 1 is fixed. Note that the cut portion that is removed during dicing does not become a committed region on the wafer 1 due to factors such as positional deviation of the wafer 1 on the dicing table, positional deviation of the dicing blade, or optical axis deviation of the laser cutter. Therefore, in the present embodiment, the scribe region SR is set wider than the portion to be cut, so that the concave portion DP1 is not formed in the scribe region SR. Thereby, even when the cut portion is slightly deviated from the planned cut portion, it is possible to prevent the cut portion from reaching the recess DP1 and the rigidity of the wafer 1 and the adhesiveness to the dicing tape from being lowered.

  As described above, the wafer 1 before being singulated according to the present embodiment includes the groove-shaped recess DP1 for thinning the silicon substrate 101 under the active region (channel formation region CR1) of the semiconductor device 100. At the time of singulation, the scribe region SR set outside the recess DP1 and outside the MOSFET 100A is cut. As a result, the separated semiconductor device 100 has a configuration in which the thick silicon substrate 101 remains in the outer peripheral portion and the silicon substrate 101 is thinned under the active region (channel formation region CR1). As a result, it is possible to reduce the balance of stress balance between the epitaxial layer p-type semiconductor layer 103, the carrier traveling layer 104 and / or the carrier supply layer 105, and the silicon substrate 101, which is a heterogeneous substrate. It is possible to prevent the yield and reliability of the semiconductor device 100 from deteriorating due to cracks or the like in the semiconductor device 100.

  As shown in FIG. 3, a lead frame 120 made of metal such as copper (Cu) is bonded to the back surface of the semiconductor device 100 separated into chips by solder or the like. The semiconductor device 100 to which the lead frame 120 is bonded is molded with a resin 130 after necessary wiring is applied. The lead frame 120 includes a protruding convex portion 121, and is bonded to the back surface of the semiconductor device 100 so that the convex portion 121 fits into the concave portion DP1. The lead frame 120 also functions as a heat sink. Therefore, in the present embodiment, a heat sink is provided directly below the thinned silicon substrate 101 under the channel formation region CR1, which is a heat generating portion of the semiconductor device 100, and the thermal resistance can be greatly reduced.

  In the above description, various substrates such as a sapphire substrate, a SiC substrate, and a ZnO substrate can be applied to the support substrate in addition to the silicon (111) substrate 101 described above. Further, the buffer layer 102 on the silicon substrate 101 is a layer for buffering the interaction due to the characteristic difference between the p-type semiconductor layer 103 grown on the upper layer and the silicon substrate 101 and improving the bonding strength between them. For such a buffer layer 102, an AlN (aluminum nitride) layer having a thickness of, for example, about 50 nm is formed on the silicon substrate 101, and a GaN layer having a thickness of, for example, about 5 to 100 nm is formed on the AlN (aluminum nitride) layer. It can be formed by stacking, for example, about 20 to 80 layers of a laminated film composed of an AlN layer of about 1 to 10 nm. However, the present invention is not limited to this structure, and various modifications may be made depending on the material of the semiconductor layer (p-type semiconductor layer 103 in this embodiment) formed over the buffer layer 102.

The p-type semiconductor layer 103 on the buffer layer 102 is, for example, a semiconductor layer containing p-type impurities, and includes the channel formation region CR1 in which a channel is formed during operation as described above. Such a p-type semiconductor layer 103 is formed on a silicon substrate 101 used as a support substrate, for example, a group III nitride semiconductor such as GaN, AlGaN, BAlGaN, or InGaN, or a compound semiconductor such as GaAs, InP, or SeGe. On the other hand, it can be formed using various semiconductors having at least one of a lattice constant and a thermal expansion coefficient different. In this embodiment, a case where a p-type semiconductor layer is formed using a GaN layer is taken as an example. In this embodiment, the case where magnesium (Mg) is used as a p-type impurity is taken as an example, and the concentration (Mg concentration) is set to about 1 × 10 ¹⁷ / cm ^3, for example.

  The carrier running layer 104 and the carrier supply layer 105 on the p-type semiconductor layer 103 are layers that form a so-called HEMT structure, and as described above, the upper layer of the carrier running layer 104 that is in the vicinity of the interface by forming a heterojunction interface. A two-dimensional electron gas that can be used as a carrier during operation is generated. In this embodiment, for example, an undoped GaN (hereinafter referred to as un-GaN) layer is used as the carrier traveling layer 104, and an undoped AlGaN (hereinafter referred to as un-AlGaN) layer is used as the carrier supply layer 105. However, the present invention is not limited to these, and various compound semiconductor laminated films capable of generating a two-dimensional electron gas by forming a heterojunction interface can be applied.

  A part of the HEMT structure on the p-type semiconductor layer 103 (a part of the carrier traveling layer 104 and the carrier supply layer 105) is removed, and the gate insulating film 106 and the gate electrode are formed on the p-type semiconductor layer 103 in the removed part. 107 is formed. With this configuration, MOSFET 100A according to the present embodiment has a MOS structure including p-type semiconductor layer 103, gate insulating film 106, and gate electrode 107. In this embodiment, for example, a silicon oxide film is used as the gate insulating film 106, and a metal film having a stacked structure in which, for example, an aluminum (Al) film is sandwiched from upper and lower layers by a titanium (Ti) film is used as the gate electrode 107. However, the present invention is not limited to this, and the semiconductor element incorporated in the semiconductor device 100 may be, for example, a MIS (Metal Insulator Semiconductor) FET. Therefore, various insulating films and conductor films can be used for the gate insulating film 106 and the gate electrode 107.

  On the carrier supply layer 105, as described above, the source electrode 108s and the drain electrode 108d that are paired with two regions sandwiching the gate electrode 107 are formed. In the present embodiment, for the source electrode 108s and the drain electrode 108d, for example, a metal film having a laminated structure including a lower Ti film and an upper Al film can be used. However, the present invention is not limited to this, and for example, various conductors capable of ohmic contact with the lower carrier supply layer 105 can be used.

  The interlayer insulating film 109 covering the semiconductor element can be formed using an insulating film such as a silicon oxide film. Furthermore, the metal layer 110 on the interlayer insulating film 109 and in the contact hole thereof can be formed using, for example, a metal film having a laminated structure of a Ti film and an Al film. Furthermore, the passivation film 111 covering these can be formed using an insulating film such as a silicon nitride film.

  The recess DP1 under the channel formation region CR1 is formed on the back surface of the silicon substrate 101 by using a double-side lithography apparatus to transfer the opening shape of the recess DP1 after the wafer process for forming the MOSFET 100A is completed. Next, the back surface of the silicon substrate 101 on which the mask film is formed is formed by performing dry etching using an ICP (Inductively Coupled Plasma) apparatus or the like. The depth of the recess DP1 can be determined from, for example, the allowable thermal resistance and the ease of processing. In the present embodiment, for example, the thickness of the silicon substrate 101 remaining under the channel formation region CR1 is set to about 100 μm. Thereby, both reduction in thermal resistance and ease of processing can be achieved. Usually, in the case of a GaN-based compound semiconductor field effect transistor having a breakdown voltage of 1000 V or more, a GaN layer is often epitaxially grown on a Si substrate having a thickness of about 1 mm. Therefore, the etching depth in this case is approximately 900 μm. However, it is not limited to this. For example, even in a recess having a depth of 60% or more of the thickness of the silicon substrate 101, the effect of reducing the thermal resistance is recognized to some extent, but by forming the recess DP1 having a depth of 80% or more, the thermal resistance is sufficiently reduced. It is possible to achieve both reduction and ease of processing. A trench TR1 for separating elements between adjacent semiconductor devices 100 in the wafer 1 is formed in a portion of the outer peripheral portion of each semiconductor device 100 where substrate etching is not performed.

  Heretofore, for simplification of explanation, the case where each semiconductor device 100 includes one MOSFET 100A has been described as an example. However, in order to increase the amount of current flowing through the semiconductor device 100 in practice, for example, FIG. As shown in FIG. 2, it is common to use a metal layer on the wafer 1 so that one semiconductor device is provided with a plurality of semiconductor elements connected in parallel. A cross-sectional view in this case is shown in FIG. As shown in FIG. 4, in the semiconductor device 150 in which a plurality of MOSFETs 100A (semiconductor elements) are formed, for example, a region formed by connecting the outside of the channel formation region CR1 of the MOSFET 100A arranged on the outermost side among the plurality of MOSFETs 100A arranged. Is regarded as one channel formation region CR11, and a recess DP1 is formed under the channel formation region CR11.

(Production method)
Next, a method for manufacturing the semiconductor device 100 according to the present embodiment will be described in detail.

  In this manufacturing method, first, as shown in FIG. 5A, a buffer layer 102A is formed on a silicon substrate 101, and a p-GaN layer 103A, an un-GaN layer 104A, and an un-AlGaN layer 105A are formed thereon. Are sequentially formed.

Specifically, first, for example, in a state where the silicon substrate 101 is installed in a chamber of a MOCVD (Metal Organic Chemical Deposition) apparatus, for example, trimethylaluminum (TMA) and ammonia (NH ₃ ) are respectively formed on the silicon substrate 101. For example, the introduction is performed at a flow rate of about 100 μmol / min and about 12 liter / min. Thereby, an AlN layer having a film thickness of, for example, about 100 nm is epitaxially grown on the silicon substrate 101. Next, for example, trimethylgallium (TMG) and ammonia are introduced onto the grown AlN layer at a flow rate of, for example, about 58 μmol / min and about 12 liter / min, respectively, thereby epitaxially growing a GaN layer having a thickness of, for example, about 200 nm. Subsequently, by introducing TMA and ammonia, for example, on the GaN layer at the same flow rate as described above, an AlN layer having a thickness of, for example, about 20 nm is epitaxially grown. Thereafter, a laminated film composed of a GaN layer having a film thickness of about 200 nm and an AlN layer having a film thickness of about 20 nm is stacked, for example, about 8 layers, so that the total film thickness from the lowermost AlN layer is, for example, about 1860 nm. A buffer layer 102 having a structure is formed on the silicon substrate 101.

Subsequently, for example, biscyclopentadienyl magnesium (Bis (Cyclopentadienyl) Magnesium: CP2Mg) is introduced onto the buffer layer 102 in addition to TMG and ammonia. Thereby, a GaN layer (p-GaN layer) 103A doped with Mg as a p-type impurity is epitaxially grown on the buffer layer 102A. The film thickness of the p-GaN layer 103A can be about 500 nm, for example. In addition, the flow rates of TMG and ammonia at this time can be set to, for example, about 19 μmol / min and about 12 liter / min, respectively. Furthermore, the flow rate of CP2Mg can be set such that the Mg concentration in the grown p-GaN layer 103A is about 1 × 10 ¹⁷ / cm ^3, for example. However, the Mg concentration is a result of measurement by, for example, secondary ion mass spectrometry (SIMS).

Subsequently, for example, TMG and ammonia are introduced onto the p-GaN layer 103A at a flow rate of, for example, about 19 μmol / min and about 12 liter / min, thereby epitaxially growing the un-GaN layer 104A having a thickness of, for example, about 100 nm. To do. Subsequently, for example, TMA, TMG, and ammonia are introduced onto the un-GaN layer 104A at a flow rate of, for example, about 125 μmol / min, about 19 μmol / min, and about 12 liter / min, so that the film thickness is about 20 nm, for example. The un-AlGaN layer 105A is epitaxially grown. The composition of the un-AlGaN layer 105A can be, for example, Al _0.25 Ga _0.75 N. In addition, the growth temperature of each layer (buffer layer 102A, p-GaN layer 103A, un-GaN layer 104A, and un-AlGaN layer 105A) in the above process can be set to about 1050 ° C., for example.

  When the laminated film including the buffer layer 102, the p-GaN layer 103A, the un-GaN layer 104A, and the un-AlGaN layer 105A is formed on the silicon substrate 101 as described above, then, for example, a photolithography technique and an etching technique. As shown in FIG. 5B, a part of the un-AlGaN layer 105A and the un-GaN layer 104A in the element formation region AR1 is removed, and a part of the lower p-GaN layer 103A is exposed. Let Specifically, for example, a CVD method is used to form a silicon oxide film having a film thickness of, for example, about 300 nm on the un-AlGaN layer 105A, and then, for example, photolithography is used to form an un- on the silicon oxide film. A photoresist to which the removal pattern of the AlGaN layer 105A and the un-GaN layer 104A is transferred is formed. Subsequently, the removal pattern is formed on the silicon oxide film by processing the silicon oxide film by wet etching using buffered hydrofluoric acid (BHF) or dry etching using fluorine-based gas while using the photoresist as a mask. Transcript. Thus, a silicon oxide film M1 having an opening ap1 as a removal pattern is formed. Subsequently, after removing the photoresist, the un-AlGaN layer 105A and the un-GaN layer 104A are sequentially etched by dry etching using, for example, a chlorine-based gas, using the silicon oxide film M1 having the opening ap1 as a mask. Thus, the un-AlGaN layer 105A and the un-GaN layer 104A under the opening ap1 are removed, and the upper surface of the p-GaN layer 103A in this portion is exposed. At this time, it is preferable to completely remove the un-GaN layer 104 </ b> A under the opening ap <b> 1 by performing an over-etching process. In this step, the un-GaN layer 104A and the un-AlGaN layer 105A located in a region not used as a semiconductor element may be removed.

  Next, after the silicon oxide film M1 used as a mask is removed, for example, by using a photolithography technique and an etching technique, as shown in FIG. A trench TR1 is formed. Specifically, for example, by using a process similar to the process described with reference to FIG. 5B, the opening ap2 for forming the trench TR1 is formed on the un-AlGaN layer 105A and the exposed p-GaN layer 103A. A silicon oxide film M2 is formed. The film thickness of the silicon oxide film M2 can be about 1000 nm, for example. Subsequently, using the silicon oxide film M2 as a mask, the un-AlGaN layer 105A and the un-AlGaN layer 105A and un- are formed by dry etching such as RIE (Reactive Ion Etching) or ICP-RIE (Inductive Coupled Plasma-RIE) using a chlorine-based gas, for example. By sequentially etching the GaN layer 104A, the p-GaN layer 103A, the buffer layer 102A, and the upper layer portion of the silicon substrate 101, the trench TR1 that electrically isolates the semiconductor elements from each other is formed in the scribe region SR. In the above-described embodiment, the trench TR1 is formed after the step of exposing the p-GaN layer 103A. However, the step of exposing the p-GaN layer 103A may be performed after the formation of the trench TR1.

  Next, after removing the silicon oxide film M2 used as a mask, a film thickness of about 60 nm, for example, covers the entire top surface of the silicon substrate 101 on which each of the above layers is formed by using, for example, a CVD (Chemical Vapor Deposition) method. A gate insulating film 106 made of a silicon oxide film is formed. Subsequently, by processing the silicon oxide film using a photolithography technique and an etching technique, at least a part of the gate insulating film 106 on the carrier supply layer 105 is removed as shown in FIG. Then, an opening ap3 for contact with the source electrode 108s and the drain electrode 108d is formed.

  Next, by using, for example, a lift-off method, as shown in FIG. 6B, the source electrode 108s and the drain electrode that are in ohmic contact with the carrier supply layer 105 exposed through the opening ap3 of the gate insulating film 106 are formed. 108d is formed. Specifically, for example, by using a photolithography technique, the photoresist R1 having the opening ap4 including the opening ap3 in the formation region of the source electrode 108s and the drain electrode 108d is formed. Subsequently, Ti and Al are sequentially deposited on the photoresist R1 and the carrier supply layer 105 exposed by the opening ap4 by using, for example, a sputtering method or a vacuum evaporation method. As a result, a metal film 1008 made of a laminated film of a Ti film and an Al film is formed on the photoresist R1, and a source electrode 108s and a drain electrode 108d are formed on the carrier supply layer 105 exposed through the opening ap4. The The film thicknesses of the Ti film and the Al film can be set to, for example, about 25 nm and about 300 nm, respectively. Subsequently, the metal film 1008 on the photoresist R1 is removed by lift-off by removing the photoresist R1 using a stripping solution such as acetone. Thereafter, for example, annealing at 600 ° C. is performed for about 10 minutes, so that the source-side carrier supply layer 105 and the source electrode 108s and the drain-side carrier supply layer 105 and the drain electrode 108d are brought into ohmic contact with each other.

  Next, a gate electrode 107 is formed on the gate insulating film 106 as shown in FIG. 7A by using, for example, a lift-off method. Specifically, for example, by using a photolithography technique, a photoresist R2 having an opening ap5 in the formation region of the gate electrode 107 on the gate insulating film 106 is formed. Subsequently, Ti, Al, and Ti are sequentially deposited on the photoresist R2 and the gate insulating film 106 exposed by the opening ap5 by using, for example, a sputtering method or a vacuum evaporation method. As a result, a metal film 1007 made of a laminated film of a Ti film, an Al film, and a Ti film is formed on the photoresist R2, and a gate electrode 107 is formed on the gate insulating film 106 exposed through the opening ap5. . The film thicknesses of the lower Ti film, the Al film, and the upper Ti film can be set to, for example, about 25 nm, about 300 nm, and about 25 nm, respectively. Subsequently, the metal film 1007 on the photoresist R2 is removed by lift-off by removing the photoresist R2 using a stripping solution such as acetone.

  The above steps are performed on the compound semiconductor layer (at least one of the p-type semiconductor layer 103, the carrier traveling layer 104, and the carrier supply layer 105) grown on the upper surface of the wafer 1 and above (on the side of) the compound semiconductor layer. This corresponds to an element formation step in which a semiconductor element (MOSFET 100A) including two electrodes (source electrode 108s and drain electrode 108d) formed apart from each other is formed in the element formation region AR1.

  When the semiconductor element including the MOSFET 100A is formed as described above, the film thickness is, for example, 3000 nm, covering the entire upper surface of the silicon substrate 101 on which each of the above layers is formed by depositing silicon oxide using, for example, a CVD method. An interlayer insulating film 109 is formed to a certain extent. Subsequently, by using, for example, a photolithography technique and an etching technique, contact holes that expose portions of the source electrode 108s, the drain electrode 108d, and the gate electrode 107 are formed in the interlayer insulating film 109, and then, for example, a sputtering method or a vacuum is used. By using the vapor deposition method, as shown in FIG. 7B, the metal layer 110 including the upper layer wiring on the interlayer insulating film 109 and the contact extension in the contact hole is formed. Note that the interlayer insulating film 109 and the metal layer 110 are not limited to one layer, and a plurality of layers may be formed.

  Next, a passivation film 111 having a thickness of, for example, about 800 nm is formed on the interlayer insulating film 109 and the metal layer 110 as shown in FIG. To do.

  Next, for example, a photolithography technique is used to form a photoresist having an opening in a portion where the recess DP1 under the channel formation region CR1 is to be formed. Subsequently, by using the formed photoresist as a mask and performing dry etching using, for example, an ICP apparatus, a recess DP1 is formed on the back surface of the silicon substrate 101 as shown in FIG. Forming step). As described above, the depth of the recess DP1 is determined from the allowable thermal resistance and the ease of processing. Therefore, in this embodiment, the thickness of the silicon substrate 101 is about 1 mm, and the remaining thickness of the substrate under the channel formation region CR1 is about 100 μm, for example. Therefore, the depth for engraving the silicon substrate 101 is about 900 μm. As a result of this step, the wafer 1 shown in FIGS. 1A to 2 is manufactured. Next, for bonding to the lead frame 120, a nickel (Ni) film having a thickness of about 100 nm and a film thickness of about 500 nm are formed on the entire back surface of the silicon substrate 101 by sputtering or vapor deposition. A back electrode composed of a gold (Au) film is formed.

  Next, for example, a dicing sheet DS having an adhesive surface is attached to the back surface of the silicon substrate 101 on which the recess DP1 is formed, and this is fixed on a dicing table, and then, as shown in FIG. The SR is cut using, for example, a dicing blade DB (dividing step). At this time, the silicon substrate 101 is cut from the upper surface side. As a result, the wafer 1 shown in FIGS. 1A to 2 is separated into individual semiconductor devices 100. In the present embodiment, the semiconductor device 100 is divided into pieces using the dicing blade DB as described above, but the present invention is not limited to this, and the semiconductor device 100 is stealth cut using a laser cutter, for example. May be singulated. As a result, the separated semiconductor device 100 remains the thick silicon substrate 101 at the outer peripheral portion, and only the silicon substrate 101 under the channel forming region CR1 that is the heat generating portion is thinned. Thereby, since the balance of stress between the p-type semiconductor layer 103 and the silicon substrate 101 formed by epitaxial growth is not lost, it is possible to avoid the occurrence of cracks in the wafer 1, and as a result, the yield and reliability of the semiconductor device 100 can be avoided. Can be prevented from deteriorating.

  Further, as shown in FIG. 3, the semiconductor device 100 separated into chips is bonded to the lead frame 120 with solder or the like, and after necessary wiring is formed, it is molded with a resin 130. At this time, the lead frame 120 is bonded to the back surface of the semiconductor device 100 so that the convex portion 121 fits into the concave portion DP1 of the semiconductor device 100. Further, the lead frame 120 may be bonded to the back surface of the wafer 1 before the semiconductor device 100 is singulated. In this case, as shown in FIG. 10, a dicing blade DB or the like in a state where an integrated lead frame in which a plurality of lead frames 120 are arranged is bonded to the back surface of the silicon substrate 101 in the same manner as the arrangement of the semiconductor devices 100 on the wafer 1. The semiconductor device 100 is divided into pieces using

  By manufacturing the semiconductor device 100 using the processes as described above, the semiconductor device 100 including the lead frame 120 as shown in FIG. 3 is manufactured. In this semiconductor device 100, since the convex portion 121 of the lead frame 120 functioning as a heat sink is fitted in the concave portion DP1 on the back surface of the silicon substrate 101, as described above, the heat generated in the channel forming region CR1 during driving is generated. It is possible to dissipate heat efficiently.

  As described above, according to the present embodiment, the source electrode 108s functioning as the channel formation region CR1 in the p-type semiconductor layer 103 (which may include the carrier traveling layer 104 or the carrier supply layer 105) that is a compound semiconductor layer and Since the recess DP1 for thinning the silicon substrate 101 as the support substrate is formed under the region sandwiched between the drain electrodes 108d, heat generated in the channel formation region CR1 during operation can be efficiently radiated from the back surface of the silicon substrate 101. Is possible. Further, since the thickness of the silicon substrate 101 is secured in the region where the recess DP1 is not formed, the stress balance between the p-type semiconductor layer 103 which is an epitaxial layer and the silicon substrate 101 which is a different substrate is lost. Can be prevented. Thereby, it is possible to realize the semiconductor device 100 capable of improving the heat dissipation efficiency and preventing the yield and the reliability from being lowered.

  In the above-described embodiment, the concave portion DP1 is formed on the back surface of the silicon substrate 101 after the completion of the wafer process for forming the semiconductor element (MOSFET 100A). However, the present invention is not limited to this, and for example, the silicon substrate 101 Immediately after the epitaxial growth of a film such as the p-type semiconductor layer 103 (see FIG. 5A), the recess DP1 is formed on the back surface of the silicon substrate 101, and the channel formation region CR1 of the MOSFET 100A is disposed immediately above the recess DP1. As described above, it may be configured to perform subsequent wafer processing. Further, the semiconductor device 100 may be manufactured using the silicon substrate 101 in which the concave portion DP1 is formed in advance.

  In the first embodiment described above, the lead frame 120 having a surface opposite to the surface to be bonded to the silicon substrate 101 (this is the back surface) is the same plane, so-called flush. Exemplified case. By using the lead frame 120 having the same back surface side in this way, it is possible to increase the contact surface between the heat dissipation plate provided under the lead frame 120 and the lead frame 120, so that the heat dissipation efficiency can be improved. it can. Furthermore, the effect that the pick-up property of the semiconductor device 100 to which the lead frame 120 is attached can be improved. However, the present invention is not limited to this. For example, as shown in FIG. 11, a lead frame 120A having a recess 122 similar to the recess DP1 formed on the back surface of the silicon substrate 101 on the back surface side may be used. The lead frames 120 and 120A as described above can be formed by, for example, pressing or etching.

<Embodiment 2>
Next, the semiconductor device 200 according to the second embodiment of the present invention will be described in detail with reference to the drawings. Note that in this embodiment, the semiconductor device 200 in which one or more HEMTs 200A are formed as semiconductor elements is taken as an example. In the following description, the same components as those in Embodiment 1 of the present invention are denoted by the same reference numerals, and detailed description thereof is omitted.

(Constitution)
In the present embodiment, the schematic configuration from above of the wafer 2 before the semiconductor device 200 is singulated is the same as the schematic configuration shown in FIGS. 1A and 1B, and here, the details are given by quoting this. The detailed explanation is omitted. FIG. 12 is a schematic diagram showing the layer structure of the wafer 2 according to the present embodiment. FIG. 12 shows a layer structure of a cross section corresponding to the cross section AA ′ in FIG. 1B.

  As is clear from comparison between FIG. 12 and FIG. 2, the HEMT 200A formed in each element formation region AR1 in the present embodiment has the same configuration as the MOSFET 100A according to the first embodiment of the present invention, and the carrier traveling layer 204. In addition, the carrier supply layer 205 is not removed in the formation region of the gate electrode 207. Further, the gate insulating film 106 in the MOSFET 100A is omitted, and the gate electrode 107 is replaced with a gate electrode 207 that is in Schottky contact with the carrier supply layer 205. Other configurations are the same as those of the first embodiment of the present invention, and thus the same reference numerals are given and detailed description thereof is omitted.

  Further, the recess DP2 in the present embodiment is formed by engraving the silicon substrate 101 from the back side of the substrate in a region below the channel formation region CR2 which is a driving portion of the semiconductor device 200 and is a heat generating portion. As a result, as in the first embodiment of the present invention, the thermal resistance of the silicon substrate 101 in the thinned portion can be reduced, so that the region under the region sandwiched between the source electrode 108s and the drain electrode 108d can be reduced. Heat generated in the channel formation region CR2 can be efficiently radiated from the back surface of the substrate through the silicon substrate 101.

  The gate electrode 207 is formed on the carrier supply layer 205 as described above, and is in Schottky contact therewith. In this embodiment, the gate electrode 207 can be a metal film having a stacked structure including, for example, a lower nickel (Ni) film and an upper gold (Au) film. However, the present invention is not limited to this, and for example, various conductors capable of making Schottky contact with the lower carrier supply layer 205 can be used.

  Since the carrier travel layer 204 and the carrier supply layer 205 can be formed using the same material as that of the carrier travel layer 104 and the carrier supply layer 105 in the first embodiment of the present invention, a detailed description will be given here. Omitted.

(Production method)
Next, a method for manufacturing the semiconductor device 200 according to the present embodiment will be described in detail with reference to the drawings. FIG. 13A to FIG. 13C are process diagrams showing a method for manufacturing the semiconductor device 200 according to the present embodiment. In the following description, the same steps as those of the first embodiment of the present invention will be simplified by quoting them.

  In this manufacturing method, first, the buffer layer 102A and the p-GaN layer 103A are formed on the silicon substrate 101 by using the same process as that described with reference to FIG. 5A in the first embodiment of the present invention. Then, an un-GaN layer 104A and an un-AlGaN layer 105A are sequentially formed.

  Next, by using the same process as that described with reference to FIG. 5C in the first embodiment of the present invention, as shown in FIG. 13A, element isolation is performed between the element formation regions AR1. A trench TR1 is formed. As a result of this step, the buffer layer 102A, the p-GaN layer 103A, the un-GaN layer 104A, and the un-AlGaN layer 105A in the element formation region AR1 are converted into the buffer layer 102, the p-type semiconductor layer 103, the carrier traveling layer 204, and While being shaped into the carrier supply layer 205, the element formation regions AR1 are separated from each other.

  Next, after removing the silicon oxide film M22 used as a mask, a step similar to the lift-off step described with reference to FIG. 6A in the first embodiment of the present invention is used, so that FIG. As shown in FIG. 5, the source electrode 108s and the drain electrode 108d that are in ohmic contact with the carrier supply layer 205 are formed. Note that the metal film 1008 on the photoresist R21 is removed by lift-off by removing the photoresist R21 used as a mask using a stripping solution such as acetone, and the source electrode 108s and the drain formed in the opening ap21. The electrode 108d remains.

  Next, by using, for example, a lift-off method, a gate electrode 207 is formed in a region sandwiched between the source electrode 108s and the drain electrode 108d on the carrier supply layer 205 as illustrated in FIG. Specifically, for example, by using a photolithography technique, a photoresist R22 having an opening ap22 is formed on a region sandwiched between the source electrode 108s and the drain electrode 108d. Subsequently, Ni and Au are sequentially deposited on the photoresist R22 and the carrier supply layer 205 exposed by the opening ap22 by using, for example, a sputtering method or a vacuum evaporation method. As a result, a metal film 2007 made of a laminated film of a Ni film and an Au film is formed on the photoresist R22, and a gate electrode 207 that forms a Schottky junction with the carrier supply layer 205 exposed through the opening ap22. It is formed. The film thicknesses of the Ni film and the Au film can be set to, for example, about 100 nm and about 200 nm, respectively. Note that by removing the photoresist R22 used as a mask using a stripping solution such as acetone, the metal film 2007 on the photoresist R22 is removed by lift-off, and the gate electrode 207 formed in the opening ap22 remains. . Moreover, the process up to the above corresponds to the element forming process.

  Thereafter, by using the same process as that described with reference to FIGS. 7B to 8A in the first embodiment of the present invention, the interlayer insulating film 109, the metal layer 110, and the passivation film 111 are sequentially formed. Then, by using a process similar to the process described with reference to FIG. 8B in the first embodiment, the recess DP2 carved from the back surface of the silicon substrate 101 is formed at least under the channel formation region CR2. (Recess forming step).

  Thereafter, by using a process similar to that described with reference to FIG. 9 in the first embodiment, the wafer 2 (see FIG. 12) on which the respective layers are formed is separated into individual semiconductor devices 200 (see FIG. 12). Individualization step).

  As described above, according to the present embodiment, the source electrode 108s functioning as the channel formation region CR2 in the p-type semiconductor layer 103 (which may include the carrier traveling layer 204 or the carrier supply layer 205) that is a compound semiconductor layer and Since the recess DP2 for thinning the silicon substrate 101 as the support substrate is formed under the region sandwiched between the drain electrodes 108d, heat generated in the channel formation region CR2 during operation can be efficiently radiated from the back surface of the silicon substrate 101. Is possible. Further, since the thickness of the silicon substrate 101 is secured in the region where the recess DP2 is not formed, the stress balance between the p-type semiconductor layer 103 which is an epitaxial layer and the silicon substrate 101 which is a different substrate is lost. Can be prevented. Thereby, the semiconductor device 200 capable of improving the heat dissipation efficiency and preventing the yield and the reliability from being lowered can be realized.

<Embodiment 3>
Next, the semiconductor device 300 according to the third embodiment of the present invention will be described in detail with reference to the drawings. Note that in this embodiment, a semiconductor device 300 in which one or more SBDs 300A are formed as semiconductor elements is described as an example. In the following description, the same components as those in the first or second embodiment of the present invention are denoted by the same reference numerals, and detailed description thereof is omitted.

(Constitution)
In the present embodiment, the schematic configuration from above of the wafer 3 before the semiconductor device 300 is singulated is the same as the schematic configuration shown in FIGS. 1A and 1B, and therefore, this is referred to here for details. The detailed explanation is omitted. FIG. 14 is a schematic diagram showing the layer structure of the wafer 3 according to the present embodiment. FIG. 14 shows a layer structure of a cross section corresponding to the cross section AA ′ in FIG. 1B.

  As is apparent from a comparison between FIG. 14, FIG. 2 and FIG. 12, in the present embodiment, the SBD 300A formed in each element formation region AR1 has the same configuration as the HEMT 200A according to the second embodiment of the present invention. The gate electrode 207 on the carrier supply layer 205 is omitted, and the source electrode 108s and the drain electrode 108d on the carrier supply layer 205 are replaced with the cathode electrode 308c and the anode electrode 308a, respectively. Since other configurations are the same as those of the first or second embodiment of the present invention, the same reference numerals are given and detailed description thereof is omitted.

  Furthermore, the recess DP3 in the present embodiment is formed by carving the silicon substrate 101 from the back surface of the substrate in the region under the channel formation region CR3 that is a driving portion of the semiconductor device 300 and is a heat generating portion. As a result, as in the first or second embodiment of the present invention, the thermal resistance of the silicon substrate 101 in the thinned portion can be reduced, so that the region sandwiched between the anode electrode 308a and the cathode electrode 308c. Heat generated in the lower channel formation region CR3 can be efficiently radiated from the back surface of the substrate through the silicon substrate 101.

  The cathode electrode 308 c is an electrode made of a metal film that is in ohmic contact with the carrier supply layer 205. In this embodiment, for example, a metal film having a laminated structure including a lower Ti film and an upper Al film is used. However, the present invention is not limited to this, and various conductors that can make ohmic contact with the lower carrier supply layer 205 can be used.

  The anode electrode 308 a is an electrode made of a metal film that is in Schottky contact with the carrier supply layer 205. In this embodiment, for example, a metal film having a laminated structure including a lower Ni film and an upper Al film is used. However, the present invention is not limited to this, and various conductors capable of making Schottky contact with the lower carrier supply layer 205 can be used.

(Production method)
Next, a method for manufacturing the semiconductor device 300 according to the present embodiment will be described in detail with reference to the drawings. FIG. 15A and FIG. 15B are process diagrams showing a method for manufacturing the semiconductor device 300 according to the present embodiment. In the following description, the same steps as those in the first or second embodiment of the present invention will be simplified by quoting them.

  In this manufacturing method, first, the buffer layer 102A and the p-GaN layer 103A are formed on the silicon substrate 101 by using the same process as that described with reference to FIG. 5A in the first embodiment of the present invention. Then, an un-GaN layer 104A and an un-AlGaN layer 105A are sequentially formed.

  Next, as shown in FIG. 13 (a) in the second embodiment of the present invention by using the same process as that described with reference to FIG. 5 (c) in the first embodiment of the present invention, A trench TR1 for element isolation is formed between the element formation regions AR1. As a result of this step, the buffer layer 102A, the p-GaN layer 103A, the un-GaN layer 104A, and the un-AlGaN layer 105A in the element formation region AR1 are converted into the buffer layer 102, the p-type semiconductor layer 103, the carrier traveling layer 204, and While being shaped into the carrier supply layer 205, the element formation regions AR1 are separated from each other.

  Next, by using a process similar to the lift-off process described with reference to FIG. 6A in the first embodiment of the present invention, as shown in FIG. A cathode electrode 308c is formed in ohmic contact therewith. Note that the metal film 3008 on the photoresist R31 is removed by lift-off by removing the photoresist R31 used as a mask using a stripping solution such as acetone, and the cathode electrode 308c formed in the opening ap31 remains. .

  Next, by using a process similar to the lift-off process described with reference to FIG. 13C in the second embodiment of the present invention, as shown in FIG. An anode electrode 308a that is in Schottky contact is formed. Note that by removing the photoresist R32 used as a mask using a stripping solution such as acetone, the metal film 3018 on the photoresist R32 is removed by lift-off, and the anode electrode 308a formed in the opening ap32 remains. . Note that the steps described above correspond to an element formation step.

  Thereafter, by using the same process as that described with reference to FIGS. 5B to 6A in the first embodiment of the present invention, the interlayer insulating film 109, the metal layer 110, and the passivation film 111 are sequentially formed. Then, by using a process similar to the process described with reference to FIG. 8B in the first embodiment, the recessed part DP3 carved from the back surface of the silicon substrate 101 is formed at least under the channel formation region CR3. (Recess forming step).

  Thereafter, by using a process similar to that described with reference to FIG. 9 in the first embodiment, the wafer 3 (see FIG. 14) on which each of the layers is formed is divided into individual semiconductor devices 300 (see FIG. 14). Individualization step).

  As described above, according to the present embodiment, the anode electrode 308a functioning as the channel formation region CR3 in the p-type semiconductor layer 103 (which may include the carrier traveling layer 204 or the carrier supply layer 205) that is a compound semiconductor layer and Since the concave portion DP3 for thinning the silicon substrate 101 as the support substrate is formed under the region sandwiched between the cathode electrodes 308c, heat generated in the channel formation region CR3 during operation can be efficiently radiated from the back surface of the silicon substrate 101. Is possible. In addition, since the thickness of the silicon substrate 101 is secured in the region where the recess DP3 is not formed, the stress balance between the p-type semiconductor layer 103 which is an epitaxial layer and the silicon substrate 101 which is a different substrate is lost. Can be prevented. Accordingly, it is possible to realize the semiconductor device 300 that can improve the heat dissipation efficiency and prevent the yield and the reliability from being lowered.

  In each of the above embodiments, the semiconductor electronic device is an electronic device exemplified by an element such as a MOSFET, HEMT, SBD or the like as the semiconductor element. However, the present invention is not limited to this, and is not limited to this. The present invention can be applied to various semiconductor element electronic devices such as type) transistors and pn junction diodes. In the first embodiment of the present invention, a recess type MOSFET using an AlGaN / GaN structure as the breakdown voltage maintaining layer has been described as an example. However, the present invention is not limited to this, and the breakdown voltage maintaining layer includes n− The present invention can also be applied to other types of MOSFETs such as a recess type MOSFET using a GaN epitaxial layer, a planar type MOSFET having a breakdown voltage maintaining layer formed by ion implantation, and a vertical trench MOSFET.

  Further, the above embodiment is merely an example for carrying out the present invention, and the present invention is not limited to these, and various modifications according to specifications and the like are within the scope of the present invention. It is obvious from the above description that various other embodiments are possible within the scope of the present invention.

It is a top view which shows schematic structure of the wafer before dividing the semiconductor device by Embodiment 1 of this invention into pieces. FIG. 1B is an enlarged view of an enlarged schematic configuration of one of a plurality of semiconductor devices formed on the wafer shown in FIG. 1A before singulation. It is a schematic diagram which shows the layer structure of the A-A 'cross section in FIG. 1B. It is sectional drawing of what mounted the semiconductor device separated into the chip | tip by Embodiment 1 of this invention on the lead frame. It is a schematic diagram which shows the cross-sectional structure of a wafer at the time of forming several semiconductor element in one element formation area in Embodiment 1 of this invention. FIG. 6 is a process diagram (part 1) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention; FIG. 7 is a process diagram (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention; FIG. 6 is a process diagram (part 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention; FIG. 6 is a process diagram (part 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention; FIG. 6 is a process diagram (No. 5) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention; It is a process diagram which shows the other manufacturing method of the semiconductor device by Embodiment 1 of this invention. FIG. 6 is a cross-sectional view showing a modification of the lead frame according to Embodiment 1 of the present invention. It is a schematic diagram which shows the layer structure of the wafer by Embodiment 2 of this invention. It is a process diagram which shows the manufacturing method of the semiconductor device by Embodiment 2 of this invention. It is a schematic diagram which shows the layer structure of the wafer by Embodiment 3 of this invention. It is a process diagram which shows the manufacturing method of the semiconductor device by Embodiment 3 of this invention.

Explanation of symbols

1, 2, 3 Wafer 100, 150, 200, 300 Semiconductor device 100A MOSFET
101 silicon substrate 102, 102A buffer layer 103 p-type semiconductor layer 104, 204 carrier traveling layer 105, 205 carrier supply layer 106 gate insulating film 107, 207 gate electrode 108d drain electrode 108s source electrode 109 interlayer insulating film 110 metal layer 111 passivation film 120 Lead frame 121 Convex 130 Resin 200A HEMT
300A SBD
308a Anode electrode 308c Cathode electrode AR1 Element formation region CR1, CR2, CR3, CR11 Channel formation region DP1, DP2, DP3 Recess FR1 Element isolation region SR Scribe region

Claims (10)

A support substrate having a recess formed on the back surface;
A semiconductor element comprising: a compound semiconductor layer grown on an upper surface opposite to the back surface of the support substrate; and two electrodes formed on or apart from the compound semiconductor layer and spaced apart from each other;
With
The compound semiconductor layer is different from the support substrate in at least one of a lattice constant and a thermal expansion coefficient,
The recess is formed in a region including at least a region sandwiched between the two electrodes when viewed from the thickness direction of the support substrate.   2. The semiconductor device according to claim 1, wherein the recess has a depth of 80% or more with respect to a thickness in a thickness direction of a portion of the support substrate where the singulated surface is formed.   The semiconductor device according to claim 1, further comprising a lead frame provided on a lower surface of the support substrate and having a convex portion that fits into the concave portion.   The semiconductor device according to claim 1, wherein the semiconductor element includes at least one of a MOSFET, a HEMT, and an SBD.   5. The semiconductor device according to claim 1, wherein the compound semiconductor layer includes at least one of GaN, AlGaN, BAlGaN, InGaN, GaAs, InP, and SeGe. An element formation region in which one or more semiconductor elements each including a compound semiconductor layer and two electrodes formed on or above the side of the compound semiconductor layer are spaced apart from each other is disposed between the element formation region An element isolation region, and a wafer structure comprising:
A concave portion is formed on a surface of the element formation region opposite to the element formation surface on which the semiconductor element is formed, in a region including at least the region sandwiched between the two electrodes when viewed from the element formation surface. A wafer structure characterized by comprising:   The wafer structure according to claim 6, wherein the concave portion is formed in a region other than under the element isolation region. A method of manufacturing a semiconductor device, comprising a singulation step of dividing a semiconductor device into pieces by cutting a support substrate including a plurality of element formation regions and element isolation regions partitioning each element formation region at the element isolation regions. Because
An element forming step of forming in the element forming region a semiconductor element including a compound semiconductor layer grown on the upper surface of the support substrate and two electrodes formed on or above the compound semiconductor layer and spaced apart from each other When,
A recess forming step of forming a recess including at least a region sandwiched between the two electrodes when viewed from the thickness direction of the support substrate, in a region other than under the element isolation region on the back surface of the support substrate;
A method for manufacturing a semiconductor device, comprising: A method of manufacturing a semiconductor device, comprising a singulation step of dividing a semiconductor device into pieces by cutting a support substrate including a plurality of element formation regions and element isolation regions partitioning each element formation region at the element isolation regions. Because
A recess forming step of forming a recess in a region other than under the element isolation region on the back surface of the support substrate;
An element forming step of forming in the element forming region a semiconductor element including a compound semiconductor layer grown on the upper surface of the support substrate and two electrodes formed on or above the compound semiconductor layer and spaced apart from each other When,
Including
The method for manufacturing a semiconductor device, wherein the two electrodes are formed in a region included in the recess as viewed from the thickness direction of the support substrate.   10. The method of manufacturing a semiconductor device according to claim 8, wherein a depth of the concave portion is 80% or more of a thickness in a thickness direction of a portion of the support substrate where the singulated surface is formed.

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