JP2010080491A - Structure for mounting electronic component - Google Patents

Structure for mounting electronic component Download PDF

Info

Publication number
JP2010080491A
JP2010080491A JP2008244040A JP2008244040A JP2010080491A JP 2010080491 A JP2010080491 A JP 2010080491A JP 2008244040 A JP2008244040 A JP 2008244040A JP 2008244040 A JP2008244040 A JP 2008244040A JP 2010080491 A JP2010080491 A JP 2010080491A
Authority
JP
Japan
Prior art keywords
electronic component
base resin
substrate
electrode
conductive film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2008244040A
Other languages
Japanese (ja)
Other versions
JP4888462B2 (en
JP2010080491A5 (en
Inventor
Nobuaki Hashimoto
伸晃 橋元
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2008244040A priority Critical patent/JP4888462B2/en
Priority to US12/561,526 priority patent/US8497432B2/en
Publication of JP2010080491A publication Critical patent/JP2010080491A/en
Publication of JP2010080491A5 publication Critical patent/JP2010080491A5/ja
Application granted granted Critical
Publication of JP4888462B2 publication Critical patent/JP4888462B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H05K3/305—Affixing by adhesive
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/325—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02311—Additive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02313—Subtractive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02373—Layout of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02377—Fan-in arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0239—Material of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/033—Manufacturing methods by local deposition of the material of the bonding area
    • H01L2224/0331—Manufacturing methods by local deposition of the material of the bonding area in liquid form
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/033—Manufacturing methods by local deposition of the material of the bonding area
    • H01L2224/0331—Manufacturing methods by local deposition of the material of the bonding area in liquid form
    • H01L2224/0332—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/035—Manufacturing methods by chemical or physical modification of a pre-existing or pre-deposited material
    • H01L2224/03515—Curing and solidification, e.g. of a photosensitive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/03618—Manufacturing methods by patterning a pre-deposited material with selective exposure, development and removal of a photosensitive material, e.g. of a photosensitive conductive resin
    • H01L2224/0362—Photolithography
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/038—Post-treatment of the bonding area
    • H01L2224/0383—Reworking, e.g. shaping
    • H01L2224/03831—Reworking, e.g. shaping involving a chemical process, e.g. etching the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/0519—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/0519—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H01L2224/05191—The principal constituent being an elastomer, e.g. silicones, isoprene, neoprene
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05551—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/0558—Plural external layers being stacked
    • H01L2224/05582—Two-layer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05664—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05671—Chromium [Cr] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05684—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/0569—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/0569—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H01L2224/05691—The principal constituent being an elastomer, e.g. silicones, isoprene, neoprene
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • H01L2224/06155—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/065—Material
    • H01L2224/06505—Bonding areas having different materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/0805—Shape
    • H01L2224/08057—Shape in side view
    • H01L2224/08058—Shape in side view being non uniform along the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/08225—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/08238—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bonding area connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H01L2224/0905—Shape
    • H01L2224/09051—Bonding areas having different shapes
    • H01L2224/09055—Bonding areas having different shapes of their bonding interfaces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
    • H01L2224/2731—Manufacturing methods by local deposition of the material of the layer connector in liquid form
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
    • H01L2224/2731—Manufacturing methods by local deposition of the material of the layer connector in liquid form
    • H01L2224/2732—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/275—Manufacturing methods by chemical or physical modification of a pre-existing or pre-deposited material
    • H01L2224/27515—Curing and solidification, e.g. of a photosensitive layer material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/276—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/2761—Physical or chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/278—Post-treatment of the layer connector
    • H01L2224/2782—Applying permanent coating, e.g. in-situ coating
    • H01L2224/27825—Plating, e.g. electroplating, electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/278—Post-treatment of the layer connector
    • H01L2224/2783—Reworking, e.g. shaping
    • H01L2224/27831—Reworking, e.g. shaping involving a chemical process, e.g. etching the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29005—Structure
    • H01L2224/29008—Layer connector integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29011—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29012—Shape in top view
    • H01L2224/29013—Shape in top view being rectangular or square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29016—Shape in side view
    • H01L2224/29017—Shape in side view being non uniform along the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2902—Disposition
    • H01L2224/29023—Disposition the whole layer connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29075—Plural core members
    • H01L2224/2908—Plural core members being stacked
    • H01L2224/29082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/29124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H01L2224/29191—The principal constituent being an elastomer, e.g. silicones, isoprene, neoprene
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/2954—Coating
    • H01L2224/2956—Disposition
    • H01L2224/29563—Only on parts of the surface of the core, i.e. partial coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/2954—Coating
    • H01L2224/2957—Single coating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/2954—Coating
    • H01L2224/29575—Plural coating layers
    • H01L2224/2958—Plural coating layers being stacked
    • H01L2224/29582—Two-layer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/2954—Coating
    • H01L2224/29599—Material
    • H01L2224/296—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/29624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/2954—Coating
    • H01L2224/29599—Material
    • H01L2224/296—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/2954—Coating
    • H01L2224/29599—Material
    • H01L2224/296—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/2954—Coating
    • H01L2224/29599—Material
    • H01L2224/296—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/2954—Coating
    • H01L2224/29599—Material
    • H01L2224/296—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/29664—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/2954—Coating
    • H01L2224/29599—Material
    • H01L2224/296—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/29666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/2954—Coating
    • H01L2224/29599—Material
    • H01L2224/296—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/29671—Chromium [Cr] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/2954—Coating
    • H01L2224/29599—Material
    • H01L2224/296—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/29684—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H01L2224/301—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H01L2224/301—Disposition
    • H01L2224/3012—Layout
    • H01L2224/3015—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/30154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • H01L2224/30155—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H01L2224/305—Material
    • H01L2224/30505—Layer connectors having different materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H01L2224/32058—Shape in side view being non uniform along the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32238—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/3305—Shape
    • H01L2224/33051—Layer connectors having different shapes
    • H01L2224/33055—Layer connectors having different shapes of their bonding interfaces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8019—Arrangement of the bonding areas prior to mounting
    • H01L2224/80194—Lateral distribution of the bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/802—Applying energy for connecting
    • H01L2224/80201—Compression bonding
    • H01L2224/80203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8038—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/80385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8038—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/80399—Material
    • H01L2224/804—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/80417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/80424—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8038—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/80399—Material
    • H01L2224/804—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/80438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/80444—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8038—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/80399—Material
    • H01L2224/804—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/80438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/80447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8038—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/80399—Material
    • H01L2224/80486—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2224/80488—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/8085—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/8085—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/80855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/80862—Heat curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/8085—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/8088—Hardening the adhesive by cooling, e.g. for thermoplastics or hot-melt adhesives
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/809—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding with the bonding area not providing any mechanical bonding
    • H01L2224/80901—Pressing a bonding area against another bonding area by means of a further bonding area or connector
    • H01L2224/80902—Pressing a bonding area against another bonding area by means of a further bonding area or connector by means of a further bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83193—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding
    • H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/83424—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83444—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/83486—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2224/83488—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862—Heat curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/8388—Hardening the adhesive by cooling, e.g. for thermoplastics or hot-melt adhesives
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/839—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector with the layer connector not providing any mechanical bonding
    • H01L2224/83901—Pressing the layer connector against the bonding areas by means of another connector
    • H01L2224/83902—Pressing the layer connector against the bonding areas by means of another connector by means of another layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0367—Metallic bump or raised conductor not used as solder bump
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0382—Continuously deformed conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/091—Locally and permanently deformed areas including dielectric material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10977—Encapsulated connections
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Metallurgy (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a structure for mounting an electronic component, which improves a bonding strength between a bump electrode and a substrate-side terminal, improves the reliability of a conductive connection state and allows easy manufacture. <P>SOLUTION: The bump electrode 12 includes base resin 13 arranged on an active face 121a of the electronic component 121 and a conductive film 14 which covers part of a surface of base resin 13, exposes a remaining part and performs conduction to an electrode terminal 16 installed on the active face 121a. Base resin 13 includes an opening 13b surrounding a plurality of electrode terminals 16, a connection 13A whose one end is connected to the electrode terminal 16 and on which part of the conductive film 14 pulled out to the surface is disposed and an adhesion part 13a which is formed in a region except for the opening 13b and the connection 13A and is bonded to a substrate. The base resin 13 is elastically deformed in the connection 13A. Thus, the adhesion part 13a is bonded to the substrate, and the conductive film 14 and the terminal on the substrate are kept in a connection state. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、電子部品の実装構造に関する。   The present invention relates to an electronic component mounting structure.

従来、各種の電子機器に搭載される回路基板や液晶表示装置などにおいては、半導体ＩＣなどの電子部品を基板上に実装する技術が用いられている。例えば液晶表示装置には、液晶パネルを駆動するための液晶駆動用ＩＣチップが実装される。この液晶駆動用ＩＣチップは、液晶パネルを構成するガラス基板に直接実装される場合もあり、また、液晶パネルに実装されるフレキシブル基板（ＦＰＣ）上に実装される場合もある。前者による実装構造はＣＯＧ（Chip On Glass）構造と呼ばれ、後者はＣＯＦ(Chip On FPC)構造と呼ばれている。なお、これら実装構造以外にも、例えばガラエポ基板などにＩＣチップを実装するＣＯＢ（Chip On board）構造も知られている。   2. Description of the Related Art Conventionally, in circuit boards and liquid crystal display devices mounted on various electronic devices, a technique for mounting an electronic component such as a semiconductor IC on the substrate is used. For example, a liquid crystal driving IC chip for driving a liquid crystal panel is mounted on the liquid crystal display device. The liquid crystal driving IC chip may be directly mounted on a glass substrate constituting the liquid crystal panel, or may be mounted on a flexible substrate (FPC) mounted on the liquid crystal panel. The former mounting structure is called a COG (Chip On Glass) structure, and the latter is called a COF (Chip On FPC) structure. In addition to these mounting structures, for example, a COB (Chip On board) structure in which an IC chip is mounted on a glass epoxy substrate or the like is also known.

このような実装構造に用いられる基板には、配線パターンに接続するランド（端子）が形成されており、一方、電子部品には、電気的接続を得るためのバンプ電極が形成されている。そして、ランドにバンプ電極を接続させた状態で、基板上に電子部品を実装することにより、電子部品の実装構造が形成されている。   On the substrate used in such a mounting structure, lands (terminals) connected to the wiring pattern are formed, while on the electronic component, bump electrodes for obtaining electrical connection are formed. And the mounting structure of an electronic component is formed by mounting an electronic component on a board | substrate in the state which connected the bump electrode to the land.

ところで、上記の実装構造においては、基板上に電子部品がより強固にかつ確実に接続していることが望まれている。特に、ランドやバンプ電極がそれぞれ複数ずつあり、複数のランド−バンプ電極間をそれぞれ接続させる場合には、全てのランド−バンプ電極間が良好に接続していることが、信頼性を確保するうえで重要となっている。
ところが、一般にランドやバンプ電極は金属によって形成されており、したがって接合時に合わせずれが生じたり、あるいはランドやバンプ電極の位置精度が悪いことによってこれらの間で位置ずれが生じた場合に、これらランドとバンプ電極との間で十分な接合強度が得られず、接触不良（導電不良）を起こしてしまうおそれがあった。
また、基板やＩＣなどの電子部品の反りや、ランドとバンプ電極などの形成高さのばらつきによって、ランドとバンプ電極間の距離が一定でなくなり、これらランドとバンプ電極との間で十分な接合強度が得られず、接触不良（導電不良）を起こしてしまうおそれがあった。 By the way, in the mounting structure described above, it is desired that the electronic components are more firmly and securely connected on the substrate. In particular, when there are a plurality of lands and bump electrodes, and a plurality of lands and bump electrodes are connected to each other, all the lands and bump electrodes are connected well to ensure reliability. It has become important.
However, in general, lands and bump electrodes are made of metal. Therefore, when a misalignment occurs at the time of joining, or when a misalignment occurs between them due to poor position accuracy of the land or bump electrode, these lands and bump electrodes are formed. Insufficient bonding strength is obtained between the bump electrode and the bump electrode, which may cause a contact failure (conductivity failure).
In addition, the distance between the land and the bump electrode is not constant due to warpage of electronic parts such as a substrate and IC, and variations in the formation height of the land and the bump electrode, and sufficient bonding between the land and the bump electrode is possible. The strength could not be obtained, and there was a risk of causing poor contact (conductive failure).

このような不都合を防止するため、従来、台形状断面を有する導体パターンを有し、この導体パターン上に金属導電層を形成するとともに、この金属導電層の表面に多数の凹凸を付与したプリント配線板が提供されている（例えば、特許文献１参照）。
このプリント配線板によれば、金属導電層表面の凹凸によるアンカー効果により、部品実装時に圧力がかかっても、部品（電子部品）の接続電極が基板の電極上を滑ったり、ずれ落ちて傾いたりしないため、実装歩留まりが向上するとされている。
特開２００２−２６１４０７号公報 Conventionally, in order to prevent such inconvenience, a printed wiring having a conductor pattern having a trapezoidal cross section, forming a metal conductive layer on the conductor pattern, and providing a number of irregularities on the surface of the metal conductive layer A plate is provided (see, for example, Patent Document 1).
According to this printed wiring board, due to the anchor effect due to the irregularities on the surface of the metal conductive layer, even when pressure is applied during component mounting, the connection electrode of the component (electronic component) slips on the electrode of the board, or falls and tilts. Therefore, the mounting yield is said to be improved.
JP 2002-261407 A

しかしながら、上記したプリント配線板にあっては、金属導電層表面の凹凸によるアンカー効果により、この金属導電層上に配置される接続電極（バンプ電極）が滑り落ちたりずれ落ちて傾いたりしないようになっているものの、これらの間の接合強度を高め、さらには複数の電極間での接合強度をも高める構造とはなっていない。したがって、接合時に合わせずれが生じたり、電極間（ランドとバンプ電極との間）の位置精度が悪いことに起因してこれらの間で位置ずれが生じた場合には、これら電極間で十分な接合強度が得られず、依然として接触不良（導電不良）を起こしてしまうおそれがある。また、接続電極（バンプ電極）が金属でできていたため、接続電極は接続時に塑性変形を起こし、前記のようにランドとバンプ電極間の距離が一定でなくなった場合に弾性変形による距離変化の吸収能力が低いため、これら電極間で十分な接合強度が得られず、依然として接触不良（導電不良）を起こしてしまうおそれもある。
さらに、このような金属導電層を有するプリント配線板と接続電極を有する部品との接合構造（実装構造）においては、プリント配線板に部品を実装し固定するためにアンダーフィル材などの接着材が必要となっており、これが実装に要するコストの低減化を妨げる一因となっている。 However, in the above-described printed wiring board, the connection electrode (bump electrode) disposed on the metal conductive layer is prevented from slipping or slipping off and tilting due to the anchor effect due to the unevenness on the surface of the metal conductive layer. However, it does not have a structure that increases the bonding strength between them, and further increases the bonding strength between a plurality of electrodes. Therefore, if misalignment occurs at the time of joining or misalignment occurs between the electrodes due to poor positional accuracy between the electrodes (between the land and the bump electrode), it is sufficient between these electrodes. There is a possibility that the bonding strength cannot be obtained and contact failure (conductivity failure) may still occur. In addition, since the connection electrode (bump electrode) is made of metal, the connection electrode undergoes plastic deformation at the time of connection, and when the distance between the land and the bump electrode is not constant as described above, the distance change due to elastic deformation is absorbed. Since the capability is low, sufficient bonding strength between these electrodes cannot be obtained, and there is a possibility that contact failure (conductivity failure) may still occur.
Furthermore, in such a joint structure (mounting structure) between a printed wiring board having a metal conductive layer and a component having a connection electrode, an adhesive such as an underfill material is used to mount and fix the component on the printed wiring board. This is necessary, and this is one factor that hinders cost reduction for mounting.

本発明はこのような事情に鑑みてなされたもので、その目的とするところは、バンプ電極と基板側端子との間の接合強度を高めて導電接続状態の信頼性を向上し、容易に製造することのできる電子部品の実装構造を提供することにある。   The present invention has been made in view of such circumstances, and its object is to increase the bonding strength between the bump electrode and the substrate-side terminal, improve the reliability of the conductive connection state, and easily manufacture It is an object of the present invention to provide an electronic component mounting structure that can be used.

本発明の電子部品の実装構造は、上記課題を解決するために、複数のバンプ電極を有する電子部品を、複数の端子を有する基板上に実装してなる電子部品の実装構造であって、前記バンプ電極は、前記電子部品の能動面に設けられた下地樹脂と、該下地樹脂の表面の一部を覆い残部を露出させるとともに前記能動面に設けられた電極端子に導通する導電膜と、を有してなり、前記下地樹脂は、複数の前記電極端子を取り囲む第１の開口部と、前記電極端子に一端を接続されるとともに前記表面に引き出された前記導電膜の一部が配置された接続部と、前記第１の開口部および前記接続部以外の領域に形成され、前記基板と接着された接着部と、を有し、前記接続部において前記下地樹脂が弾性変形していることで前記接着部が前記基板に接着され、前記導電膜と前記基板上の前記端子とが接続状態に保持されていることを特徴とする。   In order to solve the above problems, an electronic component mounting structure according to the present invention is an electronic component mounting structure in which an electronic component having a plurality of bump electrodes is mounted on a substrate having a plurality of terminals. The bump electrode includes a base resin provided on the active surface of the electronic component, and a conductive film that covers a part of the surface of the base resin, exposes the remaining portion, and is electrically connected to the electrode terminal provided on the active surface. The base resin has a first opening that surrounds the plurality of electrode terminals, and one end connected to the electrode terminals and a part of the conductive film drawn to the surface. A connecting portion, and an adhesive portion formed in a region other than the first opening and the connecting portion, and bonded to the substrate, wherein the base resin is elastically deformed in the connecting portion. The bonding part is bonded to the substrate It is, to the conductive layer and the terminal of the substrate is equal to or held in the connected state.

本発明によれば、下地樹脂に、電子部品の能動面に設けられた複数の電極端子を取り囲む第１の開口部が設けられており、複数の電極端子の周囲に存在する下地樹脂によって各電極端子に水分が侵入するのを防ぐことができる。したがって、電極端子と導電膜との接続部分におけるマイグレーションの発生などを防止することができ、接続信頼性を向上させることができる。
また、接続部において下地樹脂が弾性変形していることで接着部が基板に接着され、導電膜と基板上の端子とが接続状態に保持されているので、バンプ電極と基板側の端子との接続状態が確保され、これによっても導電接続の信頼性が向上する。 According to the present invention, the base resin is provided with the first openings surrounding the plurality of electrode terminals provided on the active surface of the electronic component, and each electrode is formed by the base resin existing around the plurality of electrode terminals. It is possible to prevent moisture from entering the terminal. Therefore, it is possible to prevent the occurrence of migration at the connection portion between the electrode terminal and the conductive film, and to improve the connection reliability.
In addition, since the base resin is elastically deformed in the connection portion, the adhesion portion is bonded to the substrate, and the conductive film and the terminal on the substrate are held in a connected state. A connection state is ensured, which also improves the reliability of the conductive connection.

また、前記下地樹脂には、前記能動面を露出させる第２の開口部が形成されており、前記導電膜が前記第１の開口部から前記下地樹脂上を経由して前記第２の開口部内に延びていることが好ましい。
本発明によれば、導電膜が、下地樹脂の第１の開口部から第２の開口部内に延びていることにより、第１の開口部および第２の開口部間の下地樹脂とその上の導電膜とによってバンプ電極が形成される。このようなバンプ電極は、基板側の端子に対して実装開始時には点接触し、実装達成後には面接触することになる。これにより、安定した電気的な接続を達成することができる。 In addition, the base resin has a second opening that exposes the active surface, and the conductive film passes through the base resin from the first opening to the inside of the second opening. It is preferable to extend.
According to the present invention, since the conductive film extends from the first opening of the base resin into the second opening, the base resin between the first opening and the second opening and the top thereof A bump electrode is formed by the conductive film. Such a bump electrode makes point contact with the terminal on the substrate side at the start of mounting, and makes surface contact after the mounting is achieved. Thereby, a stable electrical connection can be achieved.

また、前記基板と前記電子部品とは、前記下地樹脂の前記接着部の前記基板に対する接着力により、前記バンプ電極が前記端子に導電接触している状態が保持されていることが好ましい。
本発明によれば、基板と電子部品との間にアンダーフィル材などの接着材を配する必要がなくなる。したがって、アンダーフィル材などの接着材に要する材料コストが低減され、また、このような接着材を配する工程も不要になって生産コストが低減されることにより、実装コストの低減化が図られる。 Further, it is preferable that the substrate and the electronic component are held in a state in which the bump electrode is in conductive contact with the terminal by an adhesive force of the bonding portion of the base resin to the substrate.
According to the present invention, it is not necessary to arrange an adhesive such as an underfill material between the substrate and the electronic component. Accordingly, the material cost required for an adhesive such as an underfill material is reduced, and the process of arranging such an adhesive is not required, and the production cost is reduced, thereby reducing the mounting cost. .

また、前記下地樹脂の少なくとも一部に、横断面を略半円形状、略半楕円形状、または略台形状とする凸条部が形成され、前記導電膜は、前記下地樹脂の前記横断面方向に沿って前記表面の一部に帯状に設けられていることが好ましい。
本発明によれば、下地樹脂の表面に間隔をおいて導電膜を設けることにより、複数のバンプ電極を形成することができ、製造が容易である。また、下地樹脂の一部に凸条部を形成することで、安定した電気的な接続を達成できるバンプ電極とすることができる。 Further, at least a part of the base resin is provided with a ridge having a substantially semicircular shape, a semi-elliptical shape, or a substantially trapezoidal cross section, and the conductive film is formed in the cross sectional direction of the base resin. It is preferable that it is provided in a part of the surface along the band.
According to the present invention, a plurality of bump electrodes can be formed by providing a conductive film with an interval on the surface of the base resin, and manufacturing is easy. Moreover, it can be set as the bump electrode which can achieve the stable electrical connection by forming a protruding item | line part in a part of base resin.

また、前記電子部品が、半導体素子であることが好ましい。
本発明によれば、電子部品として半導体素子を適用した場合、半導体素子をその下地樹脂を介して基板に接続することができるので、半導体素子への応力伝達を抑制することができる。 The electronic component is preferably a semiconductor element.
According to the present invention, when a semiconductor element is applied as an electronic component, the semiconductor element can be connected to the substrate via the base resin, and therefore, stress transmission to the semiconductor element can be suppressed.

以下、本発明の電子部品の実装構造を詳しく説明する。
図１は本発明に係る電子部品の実装構造を適用した液晶表示装置を示す模式図である。まず、図１を用いて本発明に係る電子部品の実装構造の適用例を説明する。
図１において符号１００は液晶表示装置であり、この液晶表示装置１００は、液晶パネル１１０と、電子部品（液晶駆動用ＩＣチップ）１２１とを有して構成されている。なお、この液晶表示装置１００には、図示しないものの、偏光板、反射シート、バックライト等の付帯部材が、必要に応じて適宜設けられるものとする。 The electronic component mounting structure of the present invention will be described in detail below.
FIG. 1 is a schematic view showing a liquid crystal display device to which an electronic component mounting structure according to the present invention is applied. First, an application example of the electronic component mounting structure according to the present invention will be described with reference to FIG.
In FIG. 1, reference numeral 100 denotes a liquid crystal display device. The liquid crystal display device 100 includes a liquid crystal panel 110 and an electronic component (IC chip for liquid crystal drive) 121. Although not shown, the liquid crystal display device 100 is appropriately provided with incidental members such as a polarizing plate, a reflective sheet, and a backlight as necessary.

液晶パネル１１０は、ガラスや合成樹脂からなる基板１１１及び１１２を備えて構成されたものである。基板１１１と基板１１２とは、相互に対向配置され、図示しないシール材などによって相互に貼り合わされている。基板１１１と基板１１２の間には、電気光学物質である液晶（図示せず）が封入されている。基板１１１の表面１１１Ａ上には、ＩＴＯ（Indium Tin Oxide）などの透明導電材料からなる電極１１１ａが形成され、基板１１２の内面上には前記電極１１１ａに対向配置される電極１１２ａが形成されている。   The liquid crystal panel 110 includes substrates 111 and 112 made of glass or synthetic resin. The substrate 111 and the substrate 112 are arranged to face each other and are bonded to each other by a seal material (not shown). A liquid crystal (not shown) that is an electro-optical material is sealed between the substrate 111 and the substrate 112. An electrode 111a made of a transparent conductive material such as ITO (Indium Tin Oxide) is formed on the surface 111A of the substrate 111, and an electrode 112a disposed opposite to the electrode 111a is formed on the inner surface of the substrate 112. .

電極１１１ａは、同じ材質で一体に形成された配線１１１ｂに接続されて、基板１１１に設けられた基板張出部１１１Ｔの内面上に引き出されている。基板張出部１１１Ｔは、基板１１１の端部において基板１１２の外形よりも外側に張り出された部分である。配線１１１ｂの一端側は、端子１１１ｂｘとなっている。電極１１２ａも、同じ材質で一体に形成された配線１１２ｂに接続されて、図示しない上下導通部を介して基板１１１上の配線１１１ｃに導電接続されている。この配線１１１ｃも、ＩＴＯで形成されている。配線１１１ｃは基板張出部１１１Ｔ上に引き出され、その一端側は端子１１１ｃｘとなっている。基板張出部１１１Ｔの端縁近傍には入力配線１１１ｄが形成されており、その一端側は端子１１１ｄｘとなっている。該端子１１１ｄｘは、前記端子１１１ｂｘ及び１１１ｃｘと対向配置されている。また、入力配線１１１ｄの他端側は、入力端子１１１ｄｙとなっている。   The electrode 111a is connected to the wiring 111b integrally formed of the same material, and is drawn out on the inner surface of the substrate extension portion 111T provided on the substrate 111. The substrate overhanging portion 111T is a portion that protrudes outward from the outer shape of the substrate 112 at the end of the substrate 111. One end of the wiring 111b is a terminal 111bx. The electrode 112a is also connected to the wiring 112b integrally formed of the same material, and is conductively connected to the wiring 111c on the substrate 111 through a vertical conduction portion (not shown). The wiring 111c is also formed of ITO. The wiring 111c is drawn out on the substrate overhanging portion 111T, and one end thereof is a terminal 111cx. An input wiring 111d is formed in the vicinity of the edge of the substrate overhanging portion 111T, and one end thereof is a terminal 111dx. The terminal 111dx is disposed opposite to the terminals 111bx and 111cx. The other end of the input wiring 111d is an input terminal 111dy.

基板張出部１１１Ｔ上には、ＮＣＰ（Non-Conductive Paste）やＮＣＦ（Non-Conductive Film）を介在させることなく、本発明に係る電子部品１２１が直接実装されている。
この電子部品１２１は、例えば液晶パネル１１０を駆動する液晶駆動用ＩＣチップである。電子部品１２１の下面には、本発明に係る多数のバンプ電極（図示せず）が形成されており、これらのバンプ電極は、基板張出部１１１Ｔ上の端子１１１ｂｘ，１１１ｃｘ，１１１ｄｘにそれぞれ導電接続されている。これにより、基板１１１上に電子部品１２１が実装されてなる、本発明の実装構造が形成されている。 The electronic component 121 according to the present invention is directly mounted on the substrate extension 111T without interposing NCP (Non-Conductive Paste) or NCF (Non-Conductive Film).
The electronic component 121 is, for example, a liquid crystal driving IC chip that drives the liquid crystal panel 110. A large number of bump electrodes (not shown) according to the present invention are formed on the lower surface of the electronic component 121, and these bump electrodes are conductively connected to the terminals 111bx, 111cx, and 111dx on the substrate extension portion 111T, respectively. Has been. Thereby, the mounting structure of the present invention in which the electronic component 121 is mounted on the substrate 111 is formed.

また、基板張出部１１１Ｔ上の入力端子１１１ｄｙの配列領域には、異方性導電膜１２４を介してフレキシブル配線基板１２３が実装されている。入力端子１１１ｄｙは、フレキシブル配線基板１２３に設けられた、それぞれに対応する配線（図示せず）に導電接続されている。そして、このフレキシブル配線基板１２３を介して外部から制御信号、映像信号、電源電位などが、入力端子１１１ｄｙに供給されるようになっている。入力端子１１１ｄｙに供給された制御信号、映像信号、電源電位などは、電子部品１２１に入力され、ここで液晶駆動用の駆動信号が生成されて液晶パネル１１０に供給されるようになっている。フレキシブル基板は、ポリイミドや液晶ポリマー等可撓性を有する有機基板であり、その基板上に銅やアルミニウムで回路パターンおよび端子が形成されていることが多く好ましいが、必ずしもその限りではない。端子部には表面に金メッキが施されていると接続抵抗が安定するので、なお良い。   In addition, a flexible wiring substrate 123 is mounted on the array region of the input terminals 111dy on the substrate extension 111T via an anisotropic conductive film 124. The input terminal 111 dy is conductively connected to wiring (not shown) corresponding to each of the input terminals 111 dy provided on the flexible wiring board 123. A control signal, a video signal, a power supply potential, and the like are supplied to the input terminal 111dy from the outside via the flexible wiring board 123. A control signal, a video signal, a power supply potential, and the like supplied to the input terminal 111dy are input to the electronic component 121, where a drive signal for driving the liquid crystal is generated and supplied to the liquid crystal panel 110. The flexible substrate is a flexible organic substrate such as polyimide or liquid crystal polymer, and a circuit pattern and a terminal are often formed of copper or aluminum on the substrate, but it is not necessarily limited thereto. It is even better if the surface of the terminal portion is gold-plated because the connection resistance is stabilized.

以上のように構成された液晶表示装置１００によれば、電子部品１２１を介して電極１１１ａと電極１１２ａとの間に適宜の電圧が印加されることにより、両電極１１１ａ，１１２ａが対向配置される部分に構成される各画素毎に独立して光を変調させることができ、これによって液晶パネル１１０の表示領域に所望の画像を形成することができる。   According to the liquid crystal display device 100 configured as described above, when an appropriate voltage is applied between the electrode 111a and the electrode 112a via the electronic component 121, the both electrodes 111a and 112a are arranged to face each other. The light can be modulated independently for each pixel included in the portion, whereby a desired image can be formed in the display area of the liquid crystal panel 110.

次に、前記液晶表示装置１００に適用された、本発明の電子部品の実装構造の実施形態について詳述する。
まず、本実施形態の電子部品の構造について述べる。図２（ａ）は電子部品１２１の能動面１２１ａ側の斜視図、図２（ｂ）は図２（ａ）におけるＡ−Ａ線矢視断面図である。図３（ａ）は実装構造の要部を拡大して示す斜視図、図３（ｂ）は（ａ）におけるＢ−Ｂ線矢視断面図であって、同図において、符号１１Ｐは基板１１１上に設けられた配線パターン、すなわち、配線１１１ｂ、１１１ｃ、１１１ｄのいずれかを表しており、符号１１はこれら配線に設けられた端子、すなわち、前記した端子１１１ｂｘ、１１１ｃｘ，１１１ｄｘのいずれかを表している。なお、本実施形態では、端子１１は比較的膜厚が厚く、したがって高く形成されており、また、その横断面が略台形状になっている。 Next, an embodiment of the electronic component mounting structure of the present invention applied to the liquid crystal display device 100 will be described in detail.
First, the structure of the electronic component of this embodiment will be described. 2A is a perspective view of the electronic component 121 on the active surface 121a side, and FIG. 2B is a cross-sectional view taken along line AA in FIG. 2A. 3A is an enlarged perspective view showing the main part of the mounting structure, and FIG. 3B is a cross-sectional view taken along the line BB in FIG. 3A. In FIG. The wiring pattern provided above, that is, one of the wirings 111b, 111c, and 111d is represented, and reference numeral 11 represents a terminal provided on these wirings, that is, one of the terminals 111bx, 111cx, and 111dx described above. ing. In the present embodiment, the terminal 11 has a relatively large film thickness and is therefore formed high, and its cross section is substantially trapezoidal.

図２（ａ），（ｂ）に示すように、電子部品１２１には、基板１１１の各端子１１（１１１ｂｘ，１１１ｃｘ，１１１ｄｘ）にそれぞれ導電接続される多数のバンプ電極１２が形成されている。バンプ電極１２は、電子部品１２１の能動面１２１ａに設けられた下地樹脂１３と、該下地樹脂１３の表面の一部を覆い残部を露出させた導電膜１４と、からなるものである。   As shown in FIGS. 2A and 2B, the electronic component 121 is formed with a large number of bump electrodes 12 that are conductively connected to the terminals 11 (111bx, 111cx, 111dx) of the substrate 111, respectively. The bump electrode 12 includes a base resin 13 provided on the active surface 121a of the electronic component 121, and a conductive film 14 that covers a part of the surface of the base resin 13 and exposes the remainder.

下地樹脂１３は、電極端子１６に対応する箇所を除いて、能動面１２１ａ全体を略覆った状態で設けられている。すなわち、下地樹脂１３は、電子部品１２１の矩形の能動面１２１ａ上において四角錐台状または四角板状に形成されている。本実施形態の下地樹脂１３には、電子部品１２１の能動面１２１ａに設けられた複数の電極端子１６をそれぞれ取り囲むようして２つの開口部（第１の開口部）１３ｂ，１３ｂが形成されており、これら各開口部１３ｂ，１３ｂに沿って能動面１２１ａ上の全ての電極端子１６を露出させている。より具体的には、電子部品１２１の能動面１２１ａには、複数の電極端子１６からなる端子列１６Ａが、電子部品１２１の両側の長辺１２１ｂによってそれぞれ２列並列に配置されており、これら各端子列１６Ａ，１６Ａに対応すべく開口部１３ｂ、１３ｂがそれぞれ形成されている。   The base resin 13 is provided so as to substantially cover the entire active surface 121a except for the portions corresponding to the electrode terminals 16. That is, the base resin 13 is formed in a quadrangular pyramid shape or a square plate shape on the rectangular active surface 121 a of the electronic component 121. In the base resin 13 of the present embodiment, two openings (first openings) 13b and 13b are formed so as to surround the plurality of electrode terminals 16 provided on the active surface 121a of the electronic component 121, respectively. In addition, all the electrode terminals 16 on the active surface 121a are exposed along these openings 13b and 13b. More specifically, on the active surface 121a of the electronic component 121, a terminal row 16A composed of a plurality of electrode terminals 16 is arranged in two rows in parallel by the long sides 121b on both sides of the electronic component 121. Openings 13b and 13b are formed to correspond to the terminal rows 16A and 16A, respectively.

図２（ａ）に示すように、一つの開口部１３ｂ内には端子列１６Ａを構成する複数の電極端子１６が配置されている。これら複数の電極端子１６に共通する開口部１３ｂを形成すべく下地樹脂１３がパターニングされている。なお、端子列１６Ａを構成する電極端子１６の数については適宜設定し、図２（ａ）では数を省略しているが、実際には約２０００個の電極端子１６が配置されている。   As shown in FIG. 2A, a plurality of electrode terminals 16 constituting a terminal row 16A are arranged in one opening 13b. The base resin 13 is patterned to form an opening 13b common to the plurality of electrode terminals 16. Note that the number of electrode terminals 16 constituting the terminal row 16A is set as appropriate, and the number is omitted in FIG. 2A, but in practice, approximately 2000 electrode terminals 16 are arranged.

これら各開口部１３ｂ内で露出する複数の電極端子１６には、それぞれ帯状の導電膜１４の端部１４ａが接合（導通）している。一方、導電膜１４の端部１４ａとは反対側の端部１４ｂは、下地樹脂１３上に引き出されて下地樹脂１３の表面の一部を覆った状態で設けられている。ここで、下地樹脂１３は、開口部１３ｂ，１３ｂ同士の間においてその横断面が略台形状の凸条部（面内の方向に長手の突起部）となるように形成されており、この横断面方向に沿って帯状に導電膜１４が設けられている。また、凸条部の長さ方向に導電膜１４が複数配列されている。   The end portions 14a of the strip-shaped conductive film 14 are joined (conducted) to the plurality of electrode terminals 16 exposed in the openings 13b. On the other hand, the end portion 14 b opposite to the end portion 14 a of the conductive film 14 is provided in a state where it is drawn on the base resin 13 and covers a part of the surface of the base resin 13. Here, the base resin 13 is formed such that the cross section between the openings 13b, 13b is a substantially trapezoidal convex strip (protrusion that is long in the in-plane direction). A conductive film 14 is provided in a strip shape along the surface direction. A plurality of conductive films 14 are arranged in the length direction of the ridges.

このような構成のバンプ電極１２にあっては、図２（ａ），（ｂ）において下地樹脂１３の導電膜１４によって覆われている部分が基板１１１側の各端子１１と接続する接続部１３Ａとなり、この接続部１３Ａ上の導電膜１４の一部が電極として実質的に機能する部分となっている。   In the bump electrode 12 having such a configuration, a connecting portion 13A in which a portion of the base resin 13 covered with the conductive film 14 in FIGS. 2A and 2B is connected to each terminal 11 on the substrate 111 side. Thus, a part of the conductive film 14 on the connection portion 13A is a portion that substantially functions as an electrode.

導電膜１４は、図２（ｂ）に示すように、電子部品１２１の表面部において絶縁膜１５の開口部１５ａ内に露出した電極端子１６に接続・導通し、下地樹脂１３上に引き回されたものである。このような導電膜１４は、その内側に位置する下地樹脂１３とともに、それぞれが独立して、本発明におけるバンプ電極１２として機能するようになっている。   As shown in FIG. 2B, the conductive film 14 is connected and conducted to the electrode terminal 16 exposed in the opening 15 a of the insulating film 15 on the surface portion of the electronic component 121, and is drawn around the base resin 13. It is a thing. Such a conductive film 14 functions independently as the bump electrode 12 in the present invention, together with the base resin 13 located inside thereof.

また、本実施形態では、さらに下地樹脂１３の導電膜１４に覆われることなく露出している部分の一部が基板１１１へと接着される接着部１３ａとなっている。具体的には、下地樹脂１３の開口部１３ｂ，１３ｂおよび接続部１３Ａ以外の領域が接着部１３ａとされている。   Further, in the present embodiment, a part of the exposed portion of the base resin 13 that is not covered by the conductive film 14 is an adhesive portion 13 a that is bonded to the substrate 111. Specifically, the region other than the openings 13b and 13b and the connecting portion 13A of the base resin 13 is the bonding portion 13a.

このような構成の電子部品１２１は、図３（ａ），（ｂ）に示すように、多数のバンプ電極１２が、基板１１１の各端子１１（１１１ｂｘ，１１１ｃｘ，１１１ｄｘ）にそれぞれ導電接続されるようにして、基板１１１へと実装されている。このとき、下地樹脂１３の接続部１３Ａにおいて弾性変形していることで接着部１３ａが基板１１１の表面１１１Ａに直接接着され、これによって電子部品１２１の基板１１１に対する実装状態が確保されている。   In the electronic component 121 having such a configuration, as shown in FIGS. 3A and 3B, a large number of bump electrodes 12 are conductively connected to the terminals 11 (111bx, 111cx, 111dx) of the substrate 111, respectively. In this way, it is mounted on the substrate 111. At this time, the bonding portion 13a is directly bonded to the surface 111A of the substrate 111 by being elastically deformed at the connection portion 13A of the base resin 13, thereby ensuring the mounting state of the electronic component 121 on the substrate 111.

下地樹脂１３は、電子部品１２１を基板１１１に実装した際、この電子部品１２１が基板１１１に対して加圧され圧着されつつ、加熱されることにより、接着性を発揮する、熱接着性を有する絶縁性のものである。具体的には、ポリイミド樹脂やＢＣＢ（ベンゾシクロブテン）、液晶ポリマー、各種の熱可塑性樹脂等が用いられ、さらには、熱可塑性成分を有する感光性絶縁樹脂や熱硬化性絶縁樹脂も使用可能である。
また、下地樹脂１３は基板１１１に接着する機能を有する熱硬化性樹脂でも、光硬化性樹脂あるいはそれらを組み合わせた樹脂でも構わない。 When the electronic component 121 is mounted on the substrate 111, the base resin 13 has thermal adhesiveness that exhibits adhesiveness when the electronic component 121 is heated while being pressed against the substrate 111. Insulating. Specifically, polyimide resin, BCB (benzocyclobutene), liquid crystal polymer, various thermoplastic resins, and the like are used. Furthermore, photosensitive insulating resins and thermosetting insulating resins having a thermoplastic component can also be used. is there.
Further, the base resin 13 may be a thermosetting resin having a function of adhering to the substrate 111, a photo-curing resin, or a resin combining them.

すなわち、ポリイミド等の熱硬化性樹脂（熱可塑性成分を含有させておく）の場合、バンプ電極１２の形成時において下地樹脂１３を全硬化させることなく半硬化状態にとどめるように加熱処理し、その後、電子部品１２１を実装した際、その一部を基板１１１に当接させこれに圧着させた状態で加熱し、全硬化させる。すると、半硬化状態で接着性を有していた下地樹脂１３は、加圧加熱されて硬化する過程で基板１１１に接着し、そのまま硬化することでこの接着状態を保持するようになる。下地樹脂が光硬化性樹脂の場合は、光を照射するなど下地樹脂が基板に接着する機能を発現させるような工程とする。   That is, in the case of a thermosetting resin such as polyimide (containing a thermoplastic component), heat treatment is performed so that the base resin 13 remains in a semi-cured state without being completely cured when the bump electrode 12 is formed, and then When the electronic component 121 is mounted, a part of the electronic component 121 is brought into contact with the substrate 111 and heated in a pressure-bonded state to be completely cured. Then, the base resin 13 having adhesiveness in the semi-cured state adheres to the substrate 111 in the process of being heated under pressure and cured, and is retained as it is by being cured as it is. In the case where the base resin is a photo-curable resin, the process is such that the base resin exhibits a function of adhering to the substrate, such as light irradiation.

また、熱可塑性樹脂（必要に応じて熱硬化成分を含有させておいてもよい）の場合、バンプ電極１２の形成時に下地樹脂１３を全硬化させておく。次に、電子部品１２１を実装した際、その一部を基板１１１に当接させこれに圧着させた状態で加熱する。すると、下地樹脂１３は一部溶融し軟化することで接着性を発揮するようになる。   In the case of a thermoplastic resin (a thermosetting component may be included as necessary), the base resin 13 is fully cured when the bump electrode 12 is formed. Next, when the electronic component 121 is mounted, a part of the electronic component 121 is brought into contact with the substrate 111 and heated in a state where it is pressure-bonded thereto. Then, the base resin 13 is partly melted and softened to exhibit adhesiveness.

その後、冷却することで下地樹脂１３を再度硬化させる。これによって下地樹脂１３は、溶融・軟化し、さらに冷却され硬化する過程で基板１１１に接着し、そのまま硬化することでこの接着状態を保持するようになる。   Thereafter, the base resin 13 is cured again by cooling. As a result, the base resin 13 melts and softens, adheres to the substrate 111 in the process of being cooled and cured, and retains this adhesive state by curing as it is.

なお、このように熱可塑性樹脂によって下地樹脂１３を形成した場合、この下地樹脂１３の接着力を用いて電子部品１２１を基板１１１上に実装した後、例えば合わせずれ等の不具合があったとき、再度加熱し下地樹脂１３を軟化させることで、基板１１１から電子部品１２１を容易に取り外すことができる。   When the base resin 13 is formed of the thermoplastic resin in this way, after mounting the electronic component 121 on the substrate 111 using the adhesive force of the base resin 13, for example, when there is a problem such as misalignment, The electronic component 121 can be easily removed from the substrate 111 by heating again to soften the base resin 13.

このような樹脂からなる下地樹脂１３は、公知のリソグラーフィー技術や印刷技術、ディスペンス技術、エッチング技術により、断面視略台形状とする凸条部に形成されている。なお、樹脂の材質（硬度）や凸条部についての細部における形状（高さや幅）等については、端子１１の形状や大きさ等によって適宜に選択・設計される。   The base resin 13 made of such a resin is formed on a convex strip having a substantially trapezoidal shape in cross section by a known lithographic technique, printing technique, dispensing technique, and etching technique. The material (hardness) of the resin and the shape (height and width) in the details of the ridges are appropriately selected and designed according to the shape and size of the terminal 11.

導電膜１４は、Ａｕ、ＴｉＷ、Ｃｕ、Ｃｒ、Ｎｉ、Ｔｉ、Ｗ、ＮｉＶ、Ａｌ、Ｐｄ、鉛フリーハンダ等の金属や合金からなるもので、これら金属（合金）の単層であっても、複数種を積層したものであってもよい。また、このような導電膜１４は、スパッタ法等の公知の成膜法で成膜し、その後帯状にパターニングしたものであってもよく、無電解メッキによって選択的に形成したものであってもよい。または、スパッタ法や無電解メッキによって下地膜を形成し、その後電解メッキによって下地膜上に上層膜を形成し、これら下地膜と上層膜とからなる積層膜により、導電膜１４を形成してもよい。   The conductive film 14 is made of a metal or alloy such as Au, TiW, Cu, Cr, Ni, Ti, W, NiV, Al, Pd, or lead-free solder, and even if it is a single layer of these metals (alloys). A plurality of types may be laminated. Further, such a conductive film 14 may be formed by a known film formation method such as a sputtering method and then patterned into a band shape, or may be formed selectively by electroless plating. Good. Alternatively, a base film may be formed by sputtering or electroless plating, and then an upper layer film may be formed on the base film by electrolytic plating, and the conductive film 14 may be formed by a laminated film including the base film and the upper layer film. Good.

なお、金属（合金）の種類や層構造、膜厚、幅等については、下地樹脂１３の場合と同様に、端子１１の形状や大きさ等によって適宜に選択・設計される。ただし、導電膜１４は、下地樹脂１３（接続部１３Ａ）の弾性変形に伴って導電膜１４自体も弾性変形することから、特に展延性に優れた金（Ａｕ）を用いるのが好ましい。   Note that the type, layer structure, film thickness, width, and the like of the metal (alloy) are appropriately selected and designed according to the shape and size of the terminal 11 as in the case of the base resin 13. However, since the conductive film 14 itself is elastically deformed with the elastic deformation of the base resin 13 (connecting portion 13A), it is preferable to use gold (Au) that is particularly excellent in spreadability.

また、積層膜によって導電膜１４を形成する場合には、その最外層に金を用いるのが好ましい。さらに、導電膜１４の幅については、接合する端子１１の幅よりも十分に広く形成しておくのが好ましい。   Further, when the conductive film 14 is formed of a laminated film, it is preferable to use gold for the outermost layer. Furthermore, the width of the conductive film 14 is preferably formed sufficiently wider than the width of the terminal 11 to be joined.

図４（ａ）は電子部品１２１を基板１１１に実装する前の状態を示す図であり、図３（ｂ）の要部に対応する要部拡大断面図である。なお、下地樹脂１３については、前述したように熱硬化性樹脂の場合には半硬化状態とされ、熱可塑性樹脂の場合には全硬化状態とされ、これによって熱接着性を有する状態とされている。   4A is a view showing a state before the electronic component 121 is mounted on the substrate 111, and is an enlarged cross-sectional view of a main part corresponding to the main part of FIG. 3B. As described above, the base resin 13 is in a semi-cured state in the case of a thermosetting resin, and in a fully cured state in the case of a thermoplastic resin, thereby being in a state having thermal adhesiveness. Yes.

基板１１１と電子部品１２１とは、互いの端子１１とバンプ電極１２とが対向するように位置決めされ、その状態で互いに接合する方向に加圧されることにより、図４（ｂ），（ｃ）に示したようにバンプ電極１２の導電膜１４が端子１１に接合され導電接触させられる。また、この加圧時には、加熱処理も同時に行われる。なお、加熱温度については、下地樹脂１３の種類等に応じて適宜に設定される。   The substrate 111 and the electronic component 121 are positioned so that the terminals 11 and the bump electrodes 12 face each other, and are pressed in a direction in which they are joined to each other, whereby FIGS. As shown in FIG. 5, the conductive film 14 of the bump electrode 12 is joined to the terminal 11 and brought into conductive contact. Further, during this pressurization, heat treatment is also performed at the same time. The heating temperature is appropriately set according to the type of the base resin 13 and the like.

そして、このように導電膜１４と端子１１とが導電接触した状態で、さらにこの加圧力が高められてバンプ電極１２が基板１１１に圧着されることにより、図４（ｄ）に示すように下地樹脂１３の接続部１３Ａがさらに圧縮変形する。すると、下地樹脂１３は、導電膜１４に覆われることなく露出している接着部１３ａの一部が、基板１１１に直接接合（接着）するようになる。   Then, in this state where the conductive film 14 and the terminal 11 are in conductive contact, the applied pressure is further increased and the bump electrode 12 is pressure-bonded to the substrate 111, whereby the base as shown in FIG. The connecting portion 13A of the resin 13 is further compressed and deformed. Then, the base resin 13 is directly bonded (adhered) to the substrate 111 at a part of the bonding portion 13 a exposed without being covered with the conductive film 14.

そして、さらにこの加圧力が高められると、図３（ｂ）に示したようにバンプ電極１２と下地樹脂１３の接着部１３ａとは、そのほぼ全面が基板１１１に直接接合（接着）するようになる。そして、この状態で前述したように下地樹脂１３が硬化（全硬化）させられることにより、この下地樹脂１３の接着部１３ａは基板１１１に対して良好に接着するようになる。   When this pressure is further increased, as shown in FIG. 3B, the bump electrode 12 and the bonding portion 13a of the base resin 13 are bonded (bonded) almost directly to the substrate 111. Become. In this state, as described above, the base resin 13 is cured (fully cured), so that the bonding portion 13 a of the base resin 13 is favorably bonded to the substrate 111.

これにより、電子部品１２１は下地樹脂１３の接着部１３ａの基板１１１に対する接着によって基板１１１に実装され、また、バンプ電極１２の端子１１に対する導電接触状態も、接着部１３ａの接着力によって保持されるようになり、本発明の第１実施形態となる実装構造１０が得られる。   Accordingly, the electronic component 121 is mounted on the substrate 111 by bonding the bonding portion 13a of the base resin 13 to the substrate 111, and the conductive contact state of the bump electrode 12 with respect to the terminal 11 is also maintained by the bonding force of the bonding portion 13a. Thus, the mounting structure 10 according to the first embodiment of the present invention is obtained.

このようにして形成された本発明の第１実施形態となる実装構造１０では、複数の電極端子１６からなる２つの端子列１６Ａに対応する箇所を除いて、電子部品１２１の能動面１２１ａの略全体を覆った状態で下地樹脂１３が形成されている。すなわち、端子列１６Ａを構成する複数の電極端子１６に共通する開口部１３ｂを設けることで、電極端子１６の設計が細密になっても、安定して下地樹脂１３に開口部１３ｂをパターン形成することが可能となる。各電極端子１６ごとに微細な開口部を複数形成する場合、隣り合う開口部同士が干渉しやすくなりパターニングが困難となる。しかしながら、本実施形態によれば、各電極端子１６ごとではなく、複数の電極端子１６ごとに開口部１３ｂを形成することとしたので、独立した開口の数が少なく開口部１３ｂの形成が容易になる。
また、複数の電極端子１６を囲むようにして下地樹脂１３が存在するために、電極端子１６に水分が浸入し難く、電流のリーク（マイグレーション）などに対する信頼性も非常に高いものとなる。
また、下地樹脂１３に各端子列１６Ａ，１６Ａに対応する開口部１３ｂ，１３ｂを設けることによって、導電膜１４によって覆われない部分も広く（大きく）なることから、基板１１１に直接接着する接着部１３ａの面積を増やすことができる。これによって、基板１１１への電子部品１２１の実装強度を高めることができる。 In the mounting structure 10 thus formed according to the first embodiment of the present invention, the active surface 121a of the electronic component 121 is abbreviated except for portions corresponding to the two terminal rows 16A composed of the plurality of electrode terminals 16. A base resin 13 is formed so as to cover the whole. That is, by providing the openings 13b common to the plurality of electrode terminals 16 constituting the terminal row 16A, the openings 13b can be stably patterned in the base resin 13 even if the design of the electrode terminals 16 is fine. It becomes possible. When a plurality of fine openings are formed for each electrode terminal 16, adjacent openings are likely to interfere with each other and patterning becomes difficult. However, according to the present embodiment, since the opening 13b is formed not for each electrode terminal 16 but for each of the plurality of electrode terminals 16, the number of independent openings is small and the formation of the opening 13b is easy. Become.
Further, since the base resin 13 exists so as to surround the plurality of electrode terminals 16, it is difficult for moisture to enter the electrode terminals 16, and the reliability against current leakage (migration) and the like is extremely high.
Further, by providing openings 13b and 13b corresponding to the respective terminal rows 16A and 16A in the base resin 13, a portion not covered by the conductive film 14 is also widened (enlarged). The area of 13a can be increased. Thereby, the mounting strength of the electronic component 121 on the substrate 111 can be increased.

本実施形態の実装構造１０は、電子部品１２１が基板１１１側に相対的に加圧され、これによってバンプ電極１２が端子１１に当接させられ、さらにその状態で加圧されることにより、バンプ電極１２の下地樹脂１３（接続部１３Ａ）がさらに弾性変形（圧縮変形）し、その下地樹脂１３の接着部１３ａのほぼ全面が基板１１１に接着している。これにより、バンプ電極１２はその下地樹脂１３（接続部１３Ａ）の弾性変形によって基板１１１の端子１１に対し弾性復元力（反発力）を生じることから、バンプ電極１２と端子１１との間の接合強度がより高くなり、導電接続状態の信頼性が向上する。   In the mounting structure 10 of the present embodiment, the electronic component 121 is relatively pressed toward the substrate 111, whereby the bump electrode 12 is brought into contact with the terminal 11, and further pressed in that state. The base resin 13 (connecting portion 13A) of the electrode 12 is further elastically deformed (compressed), and almost the entire surface of the bonding portion 13a of the base resin 13 is bonded to the substrate 111. As a result, the bump electrode 12 generates an elastic restoring force (repulsive force) with respect to the terminal 11 of the substrate 111 due to elastic deformation of the base resin 13 (connecting portion 13A), so that the bonding between the bump electrode 12 and the terminal 11 is performed. The strength is higher, and the reliability of the conductive connection state is improved.

また、上述したように、下地樹脂１３の接着部１３ａの基板１１１に対する接着力により、バンプ電極１２が端子１１に導電接触している状態が保持されているので、基板１１１と電子部品１２１との間に、ＮＣＰ等のアンダーフィル材（接着材）を充填する（配する）必要がなくなる。したがって、接着材に要する材料コストが低減され、また、このような接着材を配する工程も不要になって生産コストが低減されることにより、実装コストの低減化を図ることが可能になる。さらに、導電膜１４間に位置する下地樹脂１３の接着部１３ａが基板１１１の表面に直接当接しているので、この接着部１３ａを挟んで隣り合うバンプ電極１２，１２間においては、マイグレーションが絶縁性の下地樹脂１３によって抑制される。   Further, as described above, the state in which the bump electrode 12 is in conductive contact with the terminal 11 is maintained by the adhesive force of the bonding portion 13a of the base resin 13 to the substrate 111. There is no need to fill (arrange) an underfill material (adhesive) such as NCP. Therefore, the material cost required for the adhesive is reduced, and the process of arranging such an adhesive is not required, and the production cost is reduced, so that the mounting cost can be reduced. Further, since the bonding portion 13a of the base resin 13 located between the conductive films 14 is in direct contact with the surface of the substrate 111, migration is insulated between the adjacent bump electrodes 12 and 12 across the bonding portion 13a. It is suppressed by the base resin 13 of the property.

なお、第１実施形態の実装構造１０では、図２（ｂ）に示したように下地樹脂１３の接着部１３ａのほぼ全面が基板１１１に直接接合（接着）するように、電子部品１２１を基板１１１に実装したが、下地樹脂１３の接着力が十分に大きい場合には、図４（ｄ）に示したように、接着部１３ａの一部のみが基板１１１に直接接合（接着）している状態で、下地樹脂１３を全硬化させるようにしてもよい。このようにしても、接着部１３ａの接着力によってバンプ電極１２と端子１１との導電接触状態が良好に保持されるので、基板１１１と電子部品１２１との間にアンダーフィル材（接着材）を充填する（配する）必要がなくなる。   In the mounting structure 10 of the first embodiment, as shown in FIG. 2B, the electronic component 121 is mounted on the substrate so that the substantially entire surface of the bonding portion 13a of the base resin 13 is directly bonded (bonded) to the substrate 111. In the case where the adhesive strength of the base resin 13 is sufficiently large, only a part of the adhesive portion 13a is directly bonded (adhered) to the substrate 111 as shown in FIG. In this state, the base resin 13 may be fully cured. Even in this case, since the conductive contact state between the bump electrode 12 and the terminal 11 is satisfactorily maintained by the adhesive force of the adhesive portion 13a, an underfill material (adhesive) is used between the substrate 111 and the electronic component 121. There is no need to fill (distribute).

次に、本発明の各実施形態について説明する。以下に示す各実施形態の電子部品の実装構造の基本構成は、先の実施形態と略同様であるが、電子部品の構造が一部異なっている。よって、以下の説明では、電子部品の構造について説明し、共通な箇所の説明は省略する。また、説明に用いる図面において、図１〜図４と共通の構成要素には同一の符号を付すものとする。   Next, each embodiment of the present invention will be described. The basic configuration of the electronic component mounting structure of each embodiment described below is substantially the same as that of the previous embodiment, but the structure of the electronic component is partially different. Therefore, in the following description, the structure of the electronic component will be described, and description of common parts will be omitted. In the drawings used for explanation, the same reference numerals are given to the same components as those in FIGS.

（第２実施形態）
以下、本発明の第２実施形態について説明する。図５（ａ）は、第２実施形態における電子部品１３１の能動面１３１ａ側の平面図、図５（ｂ）は（ａ）におけるＤ−Ｄ線矢視断面図である。
本実施形態の電子部品１３１では、下地樹脂１３に開口部１３ｂと開口部（第２の開口部）１３ｃとがそれぞれ２つずつ、計４つの開口部１３ｂ，１３ｂ，１３ｃ，１３ｃが設けられている。つまり、各端子列１６Ａ，１６Ａに対して設けられた開口部１３ｂ，１３ｂの他に、これら各開口部１３ｂ，１３ｂよりも内側でこれらに並行して延びる開口部１３ｃ，１３ｃが設けられている。開口部１３ｃは、開口部１３ｂと略同様の大きさで平面視矩形状とされており、対応する開口部１３ｂの近傍であって、該開口部１３ｂとは所定間隔をおいて形成されている。 (Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described. FIG. 5A is a plan view on the active surface 131a side of the electronic component 131 in the second embodiment, and FIG. 5B is a cross-sectional view taken along line DD in FIG.
In the electronic component 131 of the present embodiment, the base resin 13 is provided with two openings 13b and two openings (second openings) 13c, for a total of four openings 13b, 13b, 13c, and 13c. Yes. That is, in addition to the openings 13b and 13b provided for the terminal rows 16A and 16A, openings 13c and 13c extending in parallel to the inside of the openings 13b and 13b are provided. . The opening 13c is substantially the same size as the opening 13b and has a rectangular shape in plan view, is in the vicinity of the corresponding opening 13b, and is formed at a predetermined interval from the opening 13b. .

先の実施形態同様、各開口部１３ｂ内には複数の電極端子１６が配置されており、これら各電極端子１６にそれぞれ導電膜１４の端部１４ａが接続されている。導電膜１４は、開口部１３ｂから引き出されて下地樹脂１３の表面の一部を覆うとともに、端部１４ａとは反対側となる端部１４ｂが開口部１３ｃ内に挿入されている。そして、この端部１４ｂは、開口部１３ｃ内で露出する能動面１３１ａの一部に接着されている。導電膜１４は、開口部１３ｂから引き出されて下地樹脂１３の表面を経由して開口部１３ｃ内へと延びている。   As in the previous embodiment, a plurality of electrode terminals 16 are arranged in each opening 13b, and an end 14a of the conductive film 14 is connected to each electrode terminal 16 respectively. The conductive film 14 is drawn out from the opening 13b to cover a part of the surface of the base resin 13, and an end 14b opposite to the end 14a is inserted into the opening 13c. And this edge part 14b is adhere | attached on a part of active surface 131a exposed in the opening part 13c. The conductive film 14 is drawn from the opening 13b and extends into the opening 13c via the surface of the base resin 13.

本実施形態では、開口部１３ｂと開口部１３ｃとの間の下地樹脂１３における導電膜１４によって覆われている部分が基板１１１側の端子１１と接続する接続部１３Ａとなり、この接続部１３Ａ上の導電膜１４の一部が電極として実質的に機能する部分となっている。下地樹脂１３の接続部１３Ａはその横断面形状が略台形状となる凸条部とされ、このような下地樹脂１３の接続部１３Ａと、その上を覆っている導電膜１４の一部とによって本実施形態におけるバンプ電極２２が構成される。   In the present embodiment, a portion of the base resin 13 between the opening 13b and the opening 13c that is covered with the conductive film 14 becomes a connection portion 13A that is connected to the terminal 11 on the substrate 111 side. A part of the conductive film 14 functions as an electrode. The connecting portion 13A of the base resin 13 is a ridge having a substantially trapezoidal cross-sectional shape, and the connecting portion 13A of the base resin 13 and a part of the conductive film 14 covering the connecting portion 13A. The bump electrode 22 in this embodiment is configured.

このような構成の電子部品１３１は、バンプ電極２２を構成する下地樹脂１３の接続部１３Ａが弾性変形していることで接着部１３ａが基板１１１に接着され、導電膜１４の一部と基板１１１側の端子１１とが接続状態に保持された状態で基板１１１に実装されている。   In the electronic component 131 having such a configuration, the connecting portion 13A of the base resin 13 constituting the bump electrode 22 is elastically deformed so that the bonding portion 13a is bonded to the substrate 111, and a part of the conductive film 14 and the substrate 111 are bonded. The terminal 11 on the side is mounted on the substrate 111 in a state of being held in a connected state.

このような第２実施形態では、複数の電極端子１６からなる各端子列１６Ａ，１６Ａにそれぞれ対応する箇所と、各端子列１６Ａ，１６Ａを構成する各々の電極端子１６に接続される複数の導電膜１４の端部１４ｂに対応する箇所を除いて、電子部品１３１の能動面１３１ａの略全体を覆った状態で下地樹脂１３が形成されている。このため、先の実施形態と同様の効果が得られるほか、樹脂コア本来の半球に近い凸断面形状の接点とすることができる。具体的には、本実施形態におけるバンプ電極２２によれば、基板１１１の端子１１に対して実装開始時では点接触とされ、実装達成時では面接触とされる。これによって、基板１１１側の端子１１に対して安定した電気的な接続を達成することが可能となる。   In the second embodiment as described above, the portions corresponding to the terminal rows 16A and 16A composed of the plurality of electrode terminals 16, respectively, and the plurality of conductive members connected to the electrode terminals 16 constituting the terminal rows 16A and 16A. The base resin 13 is formed in a state in which substantially the entire active surface 131a of the electronic component 131 is covered except for portions corresponding to the end portions 14b of the film 14. For this reason, the same effect as the previous embodiment can be obtained, and a contact having a convex cross-sectional shape close to the original hemisphere of the resin core can be obtained. Specifically, according to the bump electrode 22 in the present embodiment, point contact is made with respect to the terminal 11 of the substrate 111 when mounting is started, and surface contact is made when mounting is achieved. This makes it possible to achieve stable electrical connection to the terminal 11 on the substrate 111 side.

また、導電膜１４の両端部１４ａ，１４ｂが電子部品１３１の能動面１３１ａに固定された状態となっており、電極端子１６と接続された端部１４ａとは反対側の端部１４ｂが下地樹脂１３上に接着されていた先の実施形態よりも、導電膜１４の電子部品１３１に対する接続強度が高められた構造となっている。   Further, both end portions 14a and 14b of the conductive film 14 are fixed to the active surface 131a of the electronic component 131, and an end portion 14b opposite to the end portion 14a connected to the electrode terminal 16 is a base resin. 13 has a structure in which the connection strength of the conductive film 14 to the electronic component 131 is higher than that of the previous embodiment that is bonded onto the substrate 13.

（第３実施形態）
次に、本発明の第３実施形態について説明する。図６は、第３実施形態における電子部品１４１の能動面１４１ａ側の平面図である。
本実施形態の電子部品１４１では、下地樹脂１３に、電子部品１４１の四辺に沿うようにして枠状に形成された開口部１３ｄが一つ設けられている。この開口部１３ｄは、能動面１４１ａに設けられた全ての電極端子１６に共通する開口部であって、その内側に能動面１４１ａに設けられた全ての電極端子１６が配置されている。これら複数の電極端子１６は、電子部品１４１の各辺に沿ってそれぞれ複数個ずつ配置されており、開口部１３ｄの周方向に沿って一列に配置されている。ここで、下地樹脂１３における開口部１３ｄによって囲まれた部分は、その横断面形状が略台形状となる凸条部とされている。 (Third embodiment)
Next, a third embodiment of the present invention will be described. FIG. 6 is a plan view on the active surface 141a side of the electronic component 141 according to the third embodiment.
In the electronic component 141 of this embodiment, the base resin 13 is provided with one opening 13d formed in a frame shape along the four sides of the electronic component 141. The opening 13d is an opening common to all the electrode terminals 16 provided on the active surface 141a, and all the electrode terminals 16 provided on the active surface 141a are disposed inside thereof. A plurality of these electrode terminals 16 are arranged along each side of the electronic component 141, and are arranged in a line along the circumferential direction of the opening 13d. Here, the portion surrounded by the opening 13d in the base resin 13 is a ridge that has a substantially trapezoidal cross-sectional shape.

導電膜１４は、端部１４ａが電極端子１６にそれぞれ接続されており、端部１４ａとは反対側の端部１４ｂが開口部１３ｄから引き出されて下地樹脂１３の、開口部１３ｄによって囲まれた領域（凸条部）の表面の一部を覆うようにして設けられている。電子部品１４１における全ての導電膜１４は、各々の端部１４ｂを電子部品１４１の中心に向けて設けられている。
そして、下地樹脂１３における導電膜１４によって覆われている部分が基板１１１の端子１１と接続する接続部１３Ａとなり、この接続部１３Ａ上の導電膜１４の一部が電極として実質的に機能する部分となっている。本実施形態におけるバンプ電極２３は、下地樹脂１３の一部である接続部１３Ａと、その上を覆っている導電膜１４の一部とによって構成されている。 The conductive film 14 has an end portion 14a connected to the electrode terminal 16, and an end portion 14b opposite to the end portion 14a is drawn from the opening portion 13d and surrounded by the opening portion 13d of the base resin 13. It is provided so as to cover a part of the surface of the region (projection). All the conductive films 14 in the electronic component 141 are provided with the respective end portions 14 b facing the center of the electronic component 141.
A portion of the base resin 13 covered with the conductive film 14 becomes a connection portion 13A connected to the terminal 11 of the substrate 111, and a portion of the conductive film 14 on the connection portion 13A substantially functions as an electrode. It has become. The bump electrode 23 in the present embodiment is configured by a connection portion 13A that is a part of the base resin 13 and a part of the conductive film 14 that covers the connection part 13A.

電子部品１４１が基板１１１上に実装された状態においては、バンプ電極２３における下地樹脂１３の接続部１３Ａが弾性変形していることで、下地樹脂１３の接続部１３Ａ以外の接着部１３ａが基板１１１の表面１１１Ａに接着され、バンプ電極２３を構成する導電膜１４の一部と基板１１１の端子１１との接続状態が確保されている。   In a state where the electronic component 141 is mounted on the substrate 111, the connecting portion 13 </ b> A of the base resin 13 in the bump electrode 23 is elastically deformed, so that the adhesive portion 13 a other than the connecting portion 13 </ b> A of the base resin 13 is bonded to the substrate 111. A connection state between a part of the conductive film 14 constituting the bump electrode 23 and the terminal 11 of the substrate 111 is secured.

このような第３実施形態では、能動面１４１ａに設けられた全ての電極端子１６に共通する開口部１３ｄが下地樹脂１３にパターン形成されている。この構成によれば、電極端子１６の設計がより細密になったとしても一つの開口部１３ｄで対応することができるので、製造が容易である。つまり、独立した開口部の数が先の実施形態に比べて少なくその大きさが大きいので、下地樹脂１３に開口部１３ｄをパターン形成しやすいという利点がある。   In such a third embodiment, the opening 13 d common to all the electrode terminals 16 provided on the active surface 141 a is patterned in the base resin 13. According to this configuration, even if the design of the electrode terminal 16 becomes finer, it can be handled by the single opening 13d, so that the manufacturing is easy. That is, since the number of independent openings is smaller than that of the previous embodiment and the size thereof is large, there is an advantage that it is easy to form the openings 13 d in the base resin 13.

（変形例）
また、上述した各実施形態における各開口部１３ｂ、１３ｃ、１３ｄ内に配置される複数の電極端子１６が一列に整列配置されていなくてもよく、例えば、図７に示すように、隣り合う電極端子１６同士が一列ではなく互い違い（ジグザグ）に配置されていてもよい。すなわち、各開口部１３ｂ、１３ｃ、１３ｄは、それぞれ複数の電極端子１６ごとに共通して形成されたものであることから、各電極端子１６毎に独立して開口部をパターン形成する場合に比べて電極端子１６の位置ずれにも対応することができるので、製造が容易である。
さらにまた、上述した各実施形態における各開口は、必要に応じ可変することができる。 (Modification)
In addition, the plurality of electrode terminals 16 arranged in the openings 13b, 13c, and 13d in each of the above-described embodiments may not be arranged in a line. For example, as shown in FIG. The terminals 16 may be arranged alternately (zigzag) instead of in a single row. That is, each of the openings 13b, 13c, and 13d is formed in common for each of the plurality of electrode terminals 16, and therefore, compared with the case where the openings are pattern-formed independently for each of the electrode terminals 16. In addition, since it is possible to cope with the positional deviation of the electrode terminal 16, it is easy to manufacture.
Furthermore, each opening in each embodiment described above can be varied as necessary.

以上、添付図面を参照しながら本発明に係る好適な実施形態について説明したが、本発明は係る例に限定されないことは言うまでもなく、上記各実施形態を組み合わせても良い。当業者であれば、特許請求の範囲に記載された技術的思想の範疇内において、各種の変更例または修正例に想到し得ることは明らかであり、それらについても当然に本発明の技術的範囲に属するものと了解される。   The preferred embodiments according to the present invention have been described above with reference to the accompanying drawings. However, it goes without saying that the present invention is not limited to such examples, and the above embodiments may be combined. It is obvious for those skilled in the art that various changes or modifications can be conceived within the scope of the technical idea described in the claims. It is understood that it belongs to.

例えば、基板１１１については、上記したガラスや合成樹脂からなる基板以外に、リジット基板やシリコン基板、薄厚のセラミックス基板など種々のものが使用可能である。さらに、電子部品としては、液晶駆動用ＩＣチップ以外に各種のＩＣや、ダイオード、トランジスター、発光ダイオード、レーザーダイオード、発信子、コンデンサなどの受動部品など前述したような接続電極（バンプ電極）を有する電子部品であればなんでも構わない。   For example, as the substrate 111, various substrates such as a rigid substrate, a silicon substrate, and a thin ceramic substrate can be used in addition to the above-described substrate made of glass or synthetic resin. In addition to the IC chip for driving the liquid crystal, the electronic component has various ICs and connection electrodes (bump electrodes) as described above, such as passive components such as diodes, transistors, light emitting diodes, laser diodes, oscillators and capacitors. Any electronic component can be used.

本発明の電子部品の実装構造が適用される装置としては、前記した液晶表示装置だけではなく、有機エレクトロルミネッセンス装置（有機ＥＬ装置）や、プラズマディスプレイ装置、電気泳動ディスプレイ装置、電子放出素子を用いた装置（Field Emission Display 及び Surface-Conduction Electron-Emitter Display 等）など、各種の電気光学装置や各種の電子モジュールに適用可能である。   As an apparatus to which the electronic component mounting structure of the present invention is applied, not only the above-described liquid crystal display apparatus but also an organic electroluminescence apparatus (organic EL apparatus), a plasma display apparatus, an electrophoretic display apparatus, and an electron-emitting device are used. It can be applied to various electro-optical devices and various electronic modules such as conventional devices (Field Emission Display, Surface-Conduction Electron-Emitter Display, etc.).

本発明が適用された液晶表示装置の構造を模式的に示す概略斜視図。1 is a schematic perspective view schematically showing the structure of a liquid crystal display device to which the present invention is applied. （ａ）電子部品の能動面側の斜視図、（ｂ）は（ａ）における部分断面図。(A) The perspective view by the side of the active surface of an electronic component, (b) is the fragmentary sectional view in (a). （ａ）実装構造の要部を拡大して示す斜視図、（ｂ）は（ａ）における部分断面図。(A) The perspective view which expands and shows the principal part of a mounting structure, (b) is a fragmentary sectional view in (a). （ａ）〜（ｄ）は第１実施形態の実装構造を説明するための図。(A)-(d) is a figure for demonstrating the mounting structure of 1st Embodiment. （ａ）第２実施形態における電子部品の能動面側の平面図、（ｂ）は（ａ）における部分断面図。(A) The top view by the side of the active surface of the electronic component in 2nd Embodiment, (b) is a fragmentary sectional view in (a). 第３実施形態における電子部品の能動面側の平面図。The top view by the side of the active surface of the electronic component in 3rd Embodiment. 端子の配置例を示す図。The figure which shows the example of arrangement | positioning of a terminal.

符号の説明Explanation of symbols

１２…バンプ電極、１２１，１３１，１４１…電子部品、１１…端子、１１１…基板、１２１ａ、１３１ａ，１４１ａ…能動面、１３…下地樹脂、１６…電極端子、１４…導電膜、１４ａ…端部、１４ｂ…端部、１３Ａ…接続部、１３ａ…接着部、１３ｂ、１３ｄ…開口部（第１の開口部）、１３ｃ…開口部（第２の開口部） DESCRIPTION OF SYMBOLS 12 ... Bump electrode, 121, 131, 141 ... Electronic component, 11 ... Terminal, 111 ... Board | substrate, 121a, 131a, 141a ... Active surface, 13 ... Base resin, 16 ... Electrode terminal, 14 ... Conductive film, 14a ... End part , 14b ... end, 13A ... connection part, 13a ... adhesive part, 13b, 13d ... opening (first opening), 13c ... opening (second opening)

Claims (5)

複数のバンプ電極を有する電子部品を、複数の端子を有する基板上に実装してなる電子部品の実装構造であって、
前記バンプ電極は、前記電子部品の能動面に設けられた下地樹脂と、該下地樹脂の表面の一部を覆い残部を露出させるとともに前記能動面に設けられた電極端子に導通する導電膜と、を有してなり、
前記下地樹脂は、複数の前記電極端子を取り囲む第１の開口部と、前記電極端子に一端を接続されるとともに前記表面に引き出された前記導電膜の一部が配置された接続部と、前記第１の開口部および前記接続部以外の領域に形成され、前記基板と接着された接着部と、を有し、前記接続部において前記下地樹脂が弾性変形していることで前記接着部が前記基板に接着され、前記導電膜と前記基板上の前記端子とが接続状態に保持されている
ことを特徴とする電子部品の実装構造。 An electronic component mounting structure in which an electronic component having a plurality of bump electrodes is mounted on a substrate having a plurality of terminals,
The bump electrode includes a base resin provided on the active surface of the electronic component, a conductive film that covers a part of the surface of the base resin, exposes a remaining portion, and is electrically connected to an electrode terminal provided on the active surface; Having
The base resin includes a first opening that surrounds the plurality of electrode terminals, a connection portion in which one end is connected to the electrode terminals and a part of the conductive film drawn to the surface is disposed, An adhesive portion formed in a region other than the first opening and the connection portion and bonded to the substrate, and the base resin is elastically deformed in the connection portion, whereby the adhesive portion is A mounting structure of an electronic component, wherein the electronic component is bonded to a substrate and the conductive film and the terminal on the substrate are held in a connected state. 前記下地樹脂には、前記能動面を露出させる第２の開口部が形成されており、
前記導電膜が前記第１の開口部から前記下地樹脂上を経由して前記第２の開口部内に延びている
ことを特徴とする請求項１記載の電子部品の実装構造。 The base resin has a second opening that exposes the active surface,
2. The electronic component mounting structure according to claim 1, wherein the conductive film extends from the first opening to the second opening through the base resin. 3. 前記基板と前記電子部品とは、前記下地樹脂の前記接着部の前記基板に対する接着力により、前記バンプ電極が前記端子に導電接触している状態が保持されている
ことを特徴とする請求項１または２記載の電子部品の実装構造。 2. The substrate and the electronic component are held in a state in which the bump electrode is in conductive contact with the terminal by an adhesive force of the bonding portion of the base resin to the substrate. Or the mounting structure of the electronic component of 2. 前記下地樹脂の少なくとも一部に、横断面を略半円形状、略半楕円形状、または略台形状とする凸条部が形成され、前記導電膜は、前記下地樹脂の前記横断面方向に沿って前記表面の一部に帯状に設けられている
ことを特徴とする請求項１ないし３のいずれか一項に記載の電子部品の実装構造。 At least a portion of the base resin is provided with a ridge portion having a substantially semicircular shape, a substantially semielliptical shape, or a substantially trapezoidal cross section, and the conductive film extends along the cross sectional direction of the base resin. 4. The electronic component mounting structure according to claim 1, wherein the electronic component mounting structure is provided on a part of the surface in a band shape. 5. 前記電子部品が、半導体素子である
ことを特徴とする請求項１ないし４のいずれか一項に記載の電子部品の実装構造。 The electronic component mounting structure according to claim 1, wherein the electronic component is a semiconductor element.
JP2008244040A 2008-09-24 2008-09-24 Electronic component mounting structure Expired - Fee Related JP4888462B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008244040A JP4888462B2 (en) 2008-09-24 2008-09-24 Electronic component mounting structure
US12/561,526 US8497432B2 (en) 2008-09-24 2009-09-17 Electronic component mounting structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008244040A JP4888462B2 (en) 2008-09-24 2008-09-24 Electronic component mounting structure

Publications (3)

Publication Number Publication Date
JP2010080491A true JP2010080491A (en) 2010-04-08
JP2010080491A5 JP2010080491A5 (en) 2011-05-26
JP4888462B2 JP4888462B2 (en) 2012-02-29

Family

ID=42036467

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008244040A Expired - Fee Related JP4888462B2 (en) 2008-09-24 2008-09-24 Electronic component mounting structure

Country Status (2)

Country Link
US (1) US8497432B2 (en)
JP (1) JP4888462B2 (en)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8118447B2 (en) 2007-12-20 2012-02-21 Altair Engineering, Inc. LED lighting apparatus with swivel connection
US7938562B2 (en) 2008-10-24 2011-05-10 Altair Engineering, Inc. Lighting including integral communication apparatus
US8214084B2 (en) 2008-10-24 2012-07-03 Ilumisys, Inc. Integration of LED lighting with building controls
US8653984B2 (en) 2008-10-24 2014-02-18 Ilumisys, Inc. Integration of LED lighting control with emergency notification systems
US8901823B2 (en) 2008-10-24 2014-12-02 Ilumisys, Inc. Light and light sensor
US8540401B2 (en) 2010-03-26 2013-09-24 Ilumisys, Inc. LED bulb with internal heat dissipating structures
WO2012058556A2 (en) 2010-10-29 2012-05-03 Altair Engineering, Inc. Mechanisms for reducing risk of shock during installation of light tube
US9072171B2 (en) * 2011-08-24 2015-06-30 Ilumisys, Inc. Circuit board mount for LED light
US9271367B2 (en) 2012-07-09 2016-02-23 Ilumisys, Inc. System and method for controlling operation of an LED-based light
KR101984199B1 (en) * 2012-10-08 2019-05-31 삼성디스플레이 주식회사 Display substrate and display apparatus comprising thereof
US9285084B2 (en) 2013-03-14 2016-03-15 Ilumisys, Inc. Diffusers for LED-based lights
US9267650B2 (en) 2013-10-09 2016-02-23 Ilumisys, Inc. Lens for an LED-based light
KR20160111975A (en) 2014-01-22 2016-09-27 일루미시스, 인크. Led-based light with addressed leds
US9510400B2 (en) 2014-05-13 2016-11-29 Ilumisys, Inc. User input systems for an LED-based light
US10161568B2 (en) 2015-06-01 2018-12-25 Ilumisys, Inc. LED-based light with canted outer walls
US20190172775A1 (en) * 2017-12-04 2019-06-06 Canon Components, Inc. Flexible substrate and electronic device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007019409A (en) * 2005-07-11 2007-01-25 Seiko Epson Corp Electronic module
JP2007227828A (en) * 2006-02-27 2007-09-06 Epson Imaging Devices Corp Electrooptic device, manufacturing method thereof, mounting structure, and electronic appliance
JP2008277647A (en) * 2007-05-02 2008-11-13 Epson Imaging Devices Corp Mounting structure and electronic equipment
JP2009049225A (en) * 2007-08-21 2009-03-05 Seiko Epson Corp Mounting structure for electronic component
JP2009099764A (en) * 2007-10-17 2009-05-07 Seiko Epson Corp Mounting structure of electronic component

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0741000B2 (en) 1990-12-27 1995-05-10 三洋電機株式会社 Coffee heater
JPH04235835A (en) 1991-01-18 1992-08-24 Fujitsu Ltd Automatic paper feeding system
US6770547B1 (en) * 1999-10-29 2004-08-03 Renesas Technology Corporation Method for producing a semiconductor device
JP2002261407A (en) 2001-03-05 2002-09-13 Matsushita Electric Ind Co Ltd Printed wiring board, manufacturing method therefor, and method for mounting electronic component
JP2005235829A (en) 2004-02-17 2005-09-02 Seiko Epson Corp Method of manufacturing electronic component, electronic component, method of mounting electronic component, and electronic apparatus
JP3994989B2 (en) 2004-06-14 2007-10-24 セイコーエプソン株式会社 Semiconductor device, circuit board, electro-optical device, and electronic apparatus
JP4224717B2 (en) * 2005-07-11 2009-02-18 セイコーエプソン株式会社 Semiconductor device
JP4235835B2 (en) * 2005-08-08 2009-03-11 セイコーエプソン株式会社 Semiconductor device
JP4296434B2 (en) 2005-09-13 2009-07-15 セイコーエプソン株式会社 Semiconductor device
JP2007081039A (en) * 2005-09-13 2007-03-29 Seiko Epson Corp Semiconductor device
JP4305667B2 (en) * 2005-11-07 2009-07-29 セイコーエプソン株式会社 Semiconductor device
JP5183893B2 (en) * 2006-08-01 2013-04-17 新光電気工業株式会社 WIRING BOARD, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007019409A (en) * 2005-07-11 2007-01-25 Seiko Epson Corp Electronic module
JP2007227828A (en) * 2006-02-27 2007-09-06 Epson Imaging Devices Corp Electrooptic device, manufacturing method thereof, mounting structure, and electronic appliance
JP2008277647A (en) * 2007-05-02 2008-11-13 Epson Imaging Devices Corp Mounting structure and electronic equipment
JP2009049225A (en) * 2007-08-21 2009-03-05 Seiko Epson Corp Mounting structure for electronic component
JP2009099764A (en) * 2007-10-17 2009-05-07 Seiko Epson Corp Mounting structure of electronic component

Also Published As

Publication number Publication date
US20100071946A1 (en) 2010-03-25
JP4888462B2 (en) 2012-02-29
US8497432B2 (en) 2013-07-30

Similar Documents

Publication Publication Date Title
JP4888462B2 (en) Electronic component mounting structure
JP4548459B2 (en) Electronic component mounting structure
JP5008767B2 (en) Substrate module and manufacturing method thereof
KR100707587B1 (en) Method for manufacturing electronic component mounting body and electro-optical device
JP4525734B2 (en) Electronic component mounting structure
JP5125314B2 (en) Electronic equipment
JP4273551B2 (en) Video apparatus and manufacturing method thereof
JP4353289B2 (en) Electronic device and electronic equipment
JP2013030789A (en) Packaging structure and manufacturing method therefor
JP2009099765A (en) Mounting structure of electronic component
JP5169071B2 (en) Electronic component, electronic device, mounting structure for electronic component, and method for manufacturing mounting structure for electronic component
JP5358923B2 (en) Electronic component mounting structure
JP2008112911A (en) Inter-substrate connection structure, inter-substrate connection method, and display device
JP2009105320A (en) Mounting structure of electronic component and manufacturing method thereof
KR20080053593A (en) Display panel and method of fabricatingthe same
JP2012199262A (en) Circuit board, connection structure and method for connecting circuit board
JP5333367B2 (en) Electro-optical device and electronic module
JP4370994B2 (en) Mounting board and display device
JP2010219272A (en) Structure for mounting electronic component and method for mounting electronic component
JP2013135116A (en) Circuit board and connection structure
JP2009049154A (en) Semiconductor device, packaging structure, electrooptical device, and electronic equipment
JP2011146499A (en) Mounting structure for electronic component and method of mounting electric component
JP2013131599A (en) Circuit board, connection structure, and manufacturing method of circuit board
JP2013131598A (en) Electronic component and electronic device
JP2013197270A (en) Semiconductor device and electronic device

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110408

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20110408

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20110408

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20110411

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20110427

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20110816

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110823

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20111024

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20111024

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20111115

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20111128

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20141222

Year of fee payment: 3

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees