JP2010078841A - Liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a counter electrode from becoming highly resistant, and to display an image with wide viewing angle property and high contrast ratio and with excellent display quality. <P>SOLUTION: This liquid crystal display device includes: an array substrate AR comprising pixel electrodes EP arranged on each pixel in a matrix form; a counter substrate CT comprising the counter electrodes opposing to a plurality of pixel electrodes; and a liquid crystal layer LQ which is held between the array substrate and the counter substrate and contains liquid crystal molecules 40 oriented substantially vertical to the substrate main surface when no electric field is formed between the pixel electrodes and the counter electrodes. The counter electrode includes: a first segment and a second segment, which are of stripe type and oppose the pixel electrode in each pixel; a slit SL which is formed between the first and second segments so as to control the orientation of the liquid crystal molecules when the electric field is formed with the pixel electrode; and connections CN which electrically connects the first and second segments in a shading region between the adjoining pixels. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device using a vertical alignment (VA) mode.

  Liquid crystal display devices are utilized in various fields as display devices for OA equipment such as personal computers and televisions, taking advantage of features such as light weight, thinness, and low power consumption. In recent years, liquid crystal display devices are also used as mobile terminal devices such as mobile phones, display devices such as car navigation devices and game machines.

  Liquid crystal display devices are required to improve display quality, such as widening the viewing angle and improving the contrast ratio. In a multi-domain vertical alignment (MVA) mode liquid crystal display device having a plurality of domains having different alignment directions in one pixel, the viewing angle is compensated for by the plurality of domains, and vertical alignment processing is adopted. The liquid crystal molecules in the vicinity of the surface of the alignment film are aligned substantially perpendicular to the main surface of the substrate, and the birefringence of the liquid crystal layer is almost zero, so that sufficient black can be displayed and a high contrast ratio can be obtained (For example, refer to Patent Document 1).

  In the MVA mode liquid crystal display device, according to Patent Document 1 and the like, a technique for forming protrusions, slits, and depressions is known in order to control the alignment of liquid crystal molecules. Among them, the technique of controlling the alignment of liquid crystal molecules by providing a slit in the counter electrode has a feature that a higher contrast ratio can be obtained compared to the case of providing a protrusion.

  In addition, the slit is a dash slit type in which one or a plurality of slits are arranged as small as possible in one pixel, and is connected from the pixel start end to the pixel end so that one pixel is vertically or horizontally divided. There is a line slit type in which a slit is arranged.

In particular, the line slit type is used in a linear polarization mode. The linearly polarized light mode is mainly used for a transmissive panel (TV or the like), and has characteristics of higher contrast and wider viewing angle than the circularly polarized light mode.
JP 2008-197493 A

  The line slit type as described above has the characteristics as described above. However, considering the structure of the counter electrode of the entire screen (active area), the slit extends over the entire active area, so each segment of each counter electrode divided by the slit is active. It is not connected to the top and bottom or left and right edges of the area.

  For this reason, the counter electrode has an electrically high resistance pattern. In particular, a light-transmitting conductive material (for example, a metal oxide such as indium tin oxide) for forming the counter electrode has a higher resistance than a conductive material for wiring such as aluminum. For this reason, in the vicinity of the center of the active area that is relatively far from the feeding point, the counter electrode has a higher resistance than other display modes such as TN, circular polarization mode MVA, and the like. Furthermore, as the screen becomes larger, the resistance of the counter electrode tends to become higher, which is a great concern.

  Such an increase in resistance of the counter electrode is likely to cause deterioration of the drive signal on the counter electrode side, and is also easily affected by the coupling to the potential fluctuation from the array substrate side. As a result, display defects such as flicker, crosstalk, and display unevenness may occur.

  The present invention has been made in view of the above-described problems, and its purpose is to suppress an increase in resistance of the counter electrode, to have a wide viewing angle characteristic and a high contrast ratio, and to display an image with a good display quality. An object of the present invention is to provide a displayable liquid crystal display device.

A liquid crystal display device according to an aspect of the present invention includes:
An array substrate provided with pixel electrodes arranged in each matrix-shaped pixel;
A counter substrate including a counter electrode facing the plurality of pixel electrodes;
A liquid crystal layer that is held between the array substrate and the counter substrate and includes liquid crystal molecules that are aligned substantially perpendicular to the main surface of the substrate when no electric field is formed between the pixel electrode and the counter electrode. When,
With
The counter electrode is configured to control the alignment of the liquid crystal molecules in a state where an electric field is formed between the stripe-shaped first and second segments facing the pixel electrode and the pixel electrode in each pixel. A slit formed between the first segment and the second segment, and a connection portion for electrically connecting the first segment and the second segment in a light shielding region between adjacent pixels. It is characterized by that.

  According to the present invention, it is possible to provide a liquid crystal display device that can suppress an increase in resistance of the counter electrode, has a wide viewing angle characteristic and a high contrast ratio, and can display an image with good display quality.

  A liquid crystal display device according to an embodiment of the present invention will be described below with reference to the drawings. Here, a liquid crystal display device in which at least a part of each pixel is configured as a transmissive display unit that selectively transmits backlight and displays an image will be described as an example.

  As shown in FIGS. 1 and 2, the liquid crystal display device is an active matrix type liquid crystal display device and includes a liquid crystal display panel LPN. The liquid crystal display panel LPN includes a pair of substrates, that is, an array substrate (first substrate) AR, and a counter substrate (second substrate) CT disposed to face the array substrate AR. The liquid crystal display panel LPN includes a liquid crystal layer LQ held between the array substrate AR and the counter substrate CT.

  Such a liquid crystal display panel LPN includes an active area (display area) DSP for displaying an image. The active area DSP is composed of a plurality of pixels PX arranged in an m × n matrix (m and n are positive integers).

  In addition, the liquid crystal display device includes a first optical element OD1 provided on one outer surface of the liquid crystal display panel LPN (that is, a surface opposite to the surface in contact with the liquid crystal layer LQ of the array substrate AR), and the liquid crystal A second optical element OD2 provided on the other outer surface of the display panel LPN (that is, the surface opposite to the surface in contact with the liquid crystal layer LQ of the counter substrate CT) is provided.

  Further, the liquid crystal display device includes a backlight unit BL that illuminates the liquid crystal display panel LPN from the first optical element OD1 side.

  The array substrate AR is formed using an insulating substrate 10 having optical transparency such as a glass plate or a quartz plate. In other words, the array substrate AR has m × n pixel electrodes EP arranged in each pixel PX on one main surface of the insulating substrate 10 (that is, the surface facing the liquid crystal layer LQ) in the active area DSP. N gate lines Y (Y1 to Yn) arranged so as to extend along the row direction of each pixel PX and m pieces arranged respectively so as to extend along the column direction of each pixel PX. Source line X (X1 to Xm), mxn switching elements W arranged in a region including the intersection of the gate line Y and the source line X in each pixel PX, similarly to the gate line Y, in the row direction Auxiliary capacitance lines AY and the like that are arranged so as to extend along the liquid crystal capacitance CLC and that are capacitively coupled to the pixel electrode EP are provided in parallel with the liquid crystal capacitance CLC.

  The gate line Y and the auxiliary capacitance line AY are arranged substantially in parallel and can be formed of the same material. The auxiliary capacitance line AY is disposed so as to face the pixel electrode EP through an insulating film such as the interlayer insulating film 16. The source line X is disposed so as to be substantially orthogonal to the gate line Y and the auxiliary capacitance line AY via the interlayer insulating film 16. These source line X, gate line Y, and auxiliary capacitance line AY are formed of a low-resistance conductive material such as aluminum, molybdenum, tungsten, or titanium.

  Each switching element W is configured by, for example, an n-channel thin film transistor. The switching element W includes a semiconductor layer 12 disposed on the insulating substrate 10. The semiconductor layer 12 can be formed of, for example, polysilicon or amorphous silicon, and is formed of polysilicon here. The semiconductor layer 12 has a source region 12S and a drain region 12D on both sides of the channel region 12C. The semiconductor layer 12 is covered with a gate insulating film 14.

  The gate electrode WG of the switching element W is opposed to the channel region 12C of the semiconductor layer 12 with the gate insulating film 14 interposed therebetween. The gate electrode WG is connected to the gate line Y (or formed integrally with the gate line Y), and is disposed on the gate insulating film 14 together with the gate line Y and the auxiliary capacitance line AY. The gate electrode WG, the gate line Y, and the auxiliary capacitance line AY can be formed in the same process using the same material, for example, and are covered with the interlayer insulating film 16. The gate insulating film 14 and the interlayer insulating film 16 are made of an inorganic material such as a silicon oxide film and a silicon nitride film, for example.

  The source electrode WS and the drain electrode WD of the switching element W are disposed on both sides of the gate electrode WG on the interlayer insulating film 16. That is, the source electrode WS is connected to the source line X (or formed integrally with the source line X), and the semiconductor layer 12 is connected to the source electrode WS through a contact hole that penetrates the gate insulating film 14 and the interlayer insulating film 16. The source region 12S is contacted. The drain electrode WD is connected to the pixel electrode EP (or formed integrally with the pixel electrode EP), and the drain region 12D of the semiconductor layer 12 through a contact hole that penetrates the gate insulating film 14 and the interlayer insulating film 16. Is in contact. The source electrode WS, the drain electrode WD, and the source line X can be formed in the same process using the same material, for example, and are covered with the insulating film 18. The insulating film 18 is made of, for example, an organic material.

  The pixel electrode EP is disposed on the insulating film 18 and is electrically connected to the drain electrode WD through a contact hole formed in the insulating film 18. The pixel electrode EP is formed of a light-transmitting conductive material such as indium tin oxide (ITO) or IZO (indium zinc oxide).

  The surface of the array substrate AR that contacts the liquid crystal layer LQ is covered with the first alignment film 20.

  On the other hand, the counter substrate CT is formed using an insulating substrate 30 having optical transparency such as a glass plate or a quartz plate. That is, the counter substrate CT includes a counter electrode ET and the like on one main surface (that is, a surface facing the liquid crystal layer LQ) of the insulating substrate 30 in the active area DSP.

  The counter electrode ET is disposed so as to face the pixel electrodes EP corresponding to the plurality of pixels PX. The counter electrode ET is made of a light-transmitting conductive material such as ITO.

  The color display type liquid crystal display device includes a color filter layer 34 provided on the inner surface of the liquid crystal display panel LPN corresponding to each pixel PX. In the example shown in FIG. 2, the color filter layer 34 is provided on the counter substrate CT. The color filter layer 34 is formed of a plurality of different colors, for example, colored resins that are colored in three primary colors such as red, blue, and green. The red colored resin, the blue colored resin, and the green colored resin are disposed corresponding to the red pixel PXR, the blue pixel PXB, and the green pixel PXG, respectively.

  In the example of the color display type liquid crystal display device shown in FIG. 2, the color filter layer 34 is disposed on the counter substrate CT side, but may be disposed on the array substrate AR side. In this case, the insulating film 18 in the array substrate AR can be replaced with the color filter layer 34.

  Each pixel PX is partitioned by a black matrix BM. The black matrix BM is formed of a black colored resin or the like, and is disposed so as to face wiring portions such as the gate lines Y, auxiliary capacitance lines AY, source lines X, and switching elements W provided on the array substrate AR. .

  A region where such a black matrix BM is disposed, or a wiring portion such as a gate line Y, an auxiliary capacitance line AY, a source line X, and a switching element W formed of a conductive material that does not transmit light is disposed. This region corresponds to a light shielding region that does not contribute to display in the active area DSP of the transmissive liquid crystal display device.

  In the counter substrate CT, an overcoat layer may be disposed between the color filter layer 34 and the counter electrode ET in order to reduce the influence of the unevenness on the surface of the color filter layer 34.

  The surface in contact with the liquid crystal layer LQ of the counter substrate CT is covered with the second alignment film 36.

  The array substrate AR and the counter substrate CT as described above are arranged so that the first alignment film 20 and the second alignment film 36 face each other. At this time, a spacer (not shown) (for example, a columnar spacer formed integrally with one substrate by a resin material) is disposed between the array substrate AR and the counter substrate CT, whereby a predetermined gap is formed. It is formed. The array substrate AR and the counter substrate CT are bonded together with a sealing material in a state where a predetermined gap is formed.

  The liquid crystal layer LQ is configured by a liquid crystal composition including liquid crystal molecules 40 enclosed in a gap formed between the first alignment film 20 of the array substrate AR and the second alignment film 36 of the counter substrate CT. Yes. The liquid crystal molecules 40 have, for example, negative dielectric anisotropy.

  In the first alignment film 20 and the second alignment film 36, no electric potential difference is formed between the pixel electrode EP and the counter electrode ET, that is, no electric field is formed between the pixel electrode EP and the counter electrode. When there is no electric field, each liquid crystal molecule 40 has a characteristic of being aligned substantially perpendicular to the main surface of the insulating substrate 10 (or array substrate AR) and the main surface of the insulating substrate 30 (or counter substrate CT). . The material for forming the first alignment film 20 and the second alignment film 36 is not particularly limited as long as it is a light-transmitting thin film basically exhibiting vertical alignment.

  In addition, the liquid crystal display device includes at least part of the gate driver YD connected to the n gate lines Y and at least part of the source driver XD connected to the m source lines X. May be. In particular, when the configuration in which the switching element W includes the semiconductor layer 12 made of polysilicon is applied, at least a part of the gate driver YD and the source driver XD can be formed integrally with the array substrate AR. Similarly to the above, it is possible to include a thin film transistor including a polysilicon semiconductor layer.

  The gate driver YD sequentially supplies scanning signals (drive signals) to the n gate lines Y based on control by the controller CNT. Further, the source driver XD supplies a video signal (drive signal) to the m source lines X at a timing when the switching elements W in each row are turned on by the scanning signal based on the control by the controller CNT. Thereby, the pixel electrode EP of each row is set to a pixel potential corresponding to the video signal supplied via the corresponding switching element W.

  Each of the first optical element OD1 and the second optical element OD2 includes at least a polarizing plate. These polarizing plates are disposed, for example, so that their absorption axes are orthogonal to each other. Further, the first optical element OD1 and the second optical element OD2 may include a retardation plate that imparts an appropriate phase difference to the transmitted light.

  In particular, in this embodiment, the first optical element OD1 and the second optical element OD2 are configured to realize a linear polarization mode. That is, the first optical element OD1 is configured to transmit specific linearly polarized light in the backlight light and guide it to the liquid crystal display panel LPN. The second optical element OD2 is configured to transmit specific linearly polarized light out of the transmitted light transmitted through the liquid crystal display panel LPN.

  In this embodiment, the liquid crystal molecules 40 included in the liquid crystal layer LQ have their major axis substantially perpendicular to the main surface of the substrate by the alignment control by the first alignment film 20 and the second alignment film 36 when there is no electric field. It is aligned substantially parallel to the direction (or the normal direction of the liquid crystal display panel LPN). In such a state, the backlight light (linearly polarized light) transmitted through the first optical element OD1 is absorbed by the second optical element OD2 after transmitting through the liquid crystal layer LQ. Therefore, the transmittance of the liquid crystal display panel LPN is the lowest (that is, a black screen is displayed).

  On the other hand, in a state where an electric field is formed between the pixel electrode EP and the counter electrode ET, the liquid crystal molecules 40 having negative dielectric anisotropy are aligned in a direction substantially perpendicular to the electric field. With respect to the electric field inclined with respect to the normal line of the substrate main surface, the liquid crystal molecules 40 are aligned in the direction in which the major axis is substantially parallel or inclined with respect to the substrate main surface.

  In such a state, the backlight light (linearly polarized light) transmitted through the first optical element OD1 is provided with an appropriate phase difference when transmitted through the liquid crystal layer LQ, and then at least partially (perpendicular to the optical axis). In this plane, the linearly polarized light orthogonal to the linearly polarized light transmitted through the first optical element OD1 can pass through the second optical element OD2. Therefore, a white screen is displayed.

  In this way, a normally black mode vertical alignment mode is realized. In particular, by using the linear polarization mode, a higher contrast can be achieved than in the circular polarization mode, and a wider viewing angle is also possible.

  By the way, in this embodiment, the liquid crystal display panel LPN has a multi-domain structure capable of viewing angle compensation. More specifically, the liquid crystal display device includes alignment control means for controlling the alignment of liquid crystal molecules in a state where an electric field is formed between the pixel electrode EP and the counter electrode ET.

  As shown in FIG. 3, this orientation control means is provided on the counter substrate CT side and is configured by a slit SL formed in the counter electrode ET. In FIG. 3, only the configuration necessary for the description is shown. The slit SL faces the pixel electrode EP and is formed in a straight line so as to cross, for example, the approximate center of the pixel PX.

  Further, with respect to the slit SL, the polarization axis of the first optical element OD1 is disposed at 45 degrees, and the polarization axis of the second optical element OD2 is disposed at 135 degrees.

  In the configuration in which such slits SL are provided, the electric field between the pixel electrode EP and the counter electrode ET is formed so as to avoid these slits SL. Therefore, an electric field inclined with respect to the normal line of the substrate main surface PL can be formed between the pixel electrode EP and the counter electrode ET around the slit SL. For this reason, the liquid crystal molecules 40 around the slit SL are aligned in a predetermined direction by such a gradient electric field.

  That is, in the regions adjacent to each other with the slit SL interposed therebetween, electric fields inclined in the opposite directions with respect to the slit SL are formed, so that the liquid crystal molecules 40 of the respective pixels are also aligned in the opposite directions. As a result, the viewing angle can be compensated and the viewing angle can be expanded, and the contrast ratio can be improved by adopting the normally black mode, so that an image with good display quality can be displayed. It becomes.

  Hereinafter, specific configuration examples according to embodiments of the present invention will be described with reference to the drawings. In the drawings, only main parts necessary for explanation are shown.

<< First configuration example >>
FIG. 4 illustrates two pixels PX1 and PX2 adjacent in the column direction V. A pixel electrode EP is disposed in each pixel PX. The pixel PX substantially corresponds to a region that contributes to display, and the space between pixels corresponds to a light shielding region SLD that does not contribute to display. In FIG. 4, a light shielding region SLD is formed between the pixels PX1 and PX2 adjacent in the column direction V.

  The counter electrode ET includes a striped first segment ET1 and second segment ET2 facing the pixel electrode EP in each pixel PX.

  In the example shown in FIG. 4, the first segment ET1 and the second segment ET2 both extend substantially parallel to each other along the column direction V. Further, the first segment ET1 and the second segment ET2 are opposed to the pixel electrode EP not only in the pixel PX1 but also in the pixel PX2.

  Although omitted in FIG. 4, each segment constituting the counter electrode ET extends linearly over the entire active area DSP and faces each pixel electrode EP in a plurality of pixels arranged in the column direction V. Yes. Each segment is disposed across two pixels arranged in the row direction H.

  A slit SL that functions as an orientation control means is formed between the first segment ET1 and the second segment ET2. As a matter of course, the slit SL extends along the column direction V. The slit SL corresponds to a line slit type along the column direction V of the pixel PX1 but connected from the start end to the end.

  Such a slit SL is formed so as to pass through the approximate center of each pixel PX so as to divide each pixel PX into two regions arranged in the row direction H. That is, in FIG. 4, the pixel PX1 is divided into two parts, a right region and a left region, with the slit SL interposed therebetween. In the left region of the pixel PX1, the pixel electrode EP and the first segment ET1 face each other. Further, in the region on the right side of the pixel PX1, the pixel electrode EP and the second segment ET2 face each other. The areas where the pixel electrode EP and the first segment ET1 and the second segment ET2 face each other have, for example, substantially the same area.

  The counter electrode ET having such a configuration includes a connection portion CN that electrically connects the first segment ET1 and the second segment ET2 in the light shielding region SLD between adjacent pixels. That is, the connection portion CN extends along the row direction H so as to connect the first segment ET1 and the second segment ET2 arranged in the row direction H.

  The first segment ET1 and the second segment ET2 may be configured to be electrically connected to each other outside the active area and supplied with a common potential from a common feeding point. It may be a configuration.

  According to such a configuration, an increase in resistance of the counter electrode ET including the first segment ET1 and the second segment ET2 can be suppressed. For this reason, the deterioration (rounding) of the drive signal supplied to the counter electrode is suppressed, and it is difficult to be affected by the potential fluctuation from the pixel electrode EP side, and an image with good display quality can be displayed.

  In particular, even near the center of the active area that is relatively far from the feeding point, the resistance of the counter electrode ET is suppressed, and even if the screen is enlarged, the screen size does not increase significantly. Regardless, the display uniformity can be ensured.

  Further, according to the above-described configuration, the connection portion CN is disposed in the light shielding region SLD between the pixels. Therefore, even if an undesired electric field is formed between the connection portion CN and the pixel electrode EP, The influence on the display can be reduced.

  That is, since the connection portion CN is a part of the counter electrode ET, it has a common potential similarly to the first segment ET1 and the like. For this reason, the connection portion CN creates an electric field between the pixel electrode EP and the electric field for realizing a desired MVA (that is, between the pixel electrode EP and the first segment ET1 and the second segment ET2) during display. May affect the electric field formed.

  Such an electric field caused by the connection portion CN naturally affects the operation of the liquid crystal molecules 40. Such an operation of the liquid crystal molecules 40 is an unnecessary operation in the linearly polarized light mode, which may cause a light leakage and cause a display defect such as a decrease in contrast ratio.

  Therefore, in this embodiment, the connection portion CN is disposed in the light shielding region SLD. Thereby, the region where the liquid crystal molecules 40 perform an undesired operation can be hidden, and the influence on the display can be sufficiently reduced. In this way, the resistance of the counter electrode ET can be lowered while maintaining the MVA characteristics such as a high contrast ratio and a wide viewing angle, and the occurrence of display defects such as flicker, crosstalk, and display unevenness can be suppressed.

<< First Configuration Example-First Embodiment >>
As shown in FIG. 5, the two pixels PX1 and PX2 are adjacent to each other in the column direction V between two adjacent source lines X1 to X2. Each of the gate lines Y extends along the row direction of each pixel PX and is arranged between pixels adjacent in the column direction V. Here, the gate line Y2 is disposed between the pixel PX1 and the pixel PX2. Such a gate line Y is formed of a conductive material that does not transmit light, and forms a light shielding region SLD that does not contribute to display.

  The pixel PX1 is disposed between two adjacent gate lines Y1-Y2. The pixel electrode EP disposed on the pixel PX1 is connected to the source line X1 via a switching element (not shown) disposed near the intersection between the gate line Y1 and the source line X1.

  The counter electrode ET includes a first segment ET1 and a second segment ET2 extending along the column direction V in the pixel PX1. Such a connection portion CN that electrically connects the first segment ET1 and the second segment ET2 is disposed in the light shielding region SLD formed by the gate line Y. In the example shown in FIG. 5, the gate line Y2 faces the connection part CN.

  According to such a first embodiment, the effect as described in the first configuration example can be obtained.

<< First Configuration Example-Second Embodiment >>
As shown in FIG. 6, the two pixels PX1 and PX2 are adjacent to each other in the column direction V between two adjacent source lines X1 to X2. Each of the gate lines Y extends along the row direction of each pixel PX. Here, each gate line Y is disposed so as to pass through the approximate center of the pixel.

  Each of the storage capacitor lines AY extends along the row direction H of each pixel PX and is disposed between pixels adjacent in the column direction V. Here, the auxiliary capacitance line AY2 is disposed between the pixel PX1 and the pixel PX2. The gate line Y1 is disposed between two adjacent auxiliary capacitance lines AY1-AY2. Such an auxiliary capacitance line AY is formed of a conductive material that does not have optical transparency, and forms a light shielding region SLD that does not contribute to display.

  The pixel PX1 is disposed between two adjacent auxiliary capacitance lines AY1 to AY2. The pixel electrode EP disposed in the pixel PX1 is opposed to the gate line Y1, and is connected to the source line X1 via a switching element (not shown) disposed near the intersection of the gate line Y1 and the source line X1. Has been.

  The counter electrode ET includes a first segment ET1 and a second segment ET2 extending along the column direction V in the pixel PX1. Such a connection portion CN that electrically connects the first segment ET1 and the second segment ET2 is disposed in the light shielding region SLD formed by the auxiliary capacitance line AY. In the example shown in FIG. 6, the storage capacitor line AY2 faces the connection portion CN.

  Even in the second embodiment, the effects described in the first configuration example can be obtained.

<< Second configuration example >>
FIG. 7 illustrates two pixels PX1 and PX2 adjacent in the row direction H. A pixel electrode EP is disposed in each pixel PX. The pixel PX substantially corresponds to a region that contributes to display, and the space between pixels corresponds to a light shielding region SLD that does not contribute to display. In FIG. 7, a light shielding region SLD is formed between the pixels PX <b> 1 to PX <b> 2 adjacent in the row direction H.

  The counter electrode ET includes a striped first segment ET1 and second segment ET2 facing the pixel electrode EP in each pixel PX.

  In the example shown in FIG. 7, the first segment ET <b> 1 and the second segment ET <b> 2 both extend substantially parallel to each other along the row direction H. Further, the first segment ET1 and the second segment ET2 are opposed to the pixel electrode EP not only in the pixel PX1 but also in the pixel PX2.

  Although omitted in FIG. 7, each segment constituting the counter electrode ET extends linearly over the entire active area DSP and faces each pixel electrode EP in a plurality of pixels arranged in the row direction H. Yes. Each segment is arranged across two pixels arranged in the column direction V.

  A slit SL that functions as an orientation control means is formed between the first segment ET1 and the second segment ET2. As a matter of course, the slit SL extends along the row direction H. The slit SL corresponds to a line slit type along the row direction H of the pixel PX1 but connected from the start end to the end.

  Such a slit SL is formed so as to pass through the approximate center of each pixel PX so as to divide each pixel PX into two regions arranged in the column direction V. That is, in FIG. 7, the pixel PX1 is divided into two parts, an upper region and a lower region with the slit SL interposed therebetween. In the upper region of the pixel PX1, the pixel electrode EP and the first segment ET1 face each other. In the lower region of the pixel PX1, the pixel electrode EP and the second segment ET2 face each other. The areas where the pixel electrode EP and the first segment ET1 and the second segment ET2 face each other have, for example, substantially the same area.

  The counter electrode ET having such a configuration includes a connection portion CN that electrically connects the first segment ET1 and the second segment ET2 in the light shielding region SLD between adjacent pixels. That is, the connection part CN extends along the column direction V so as to connect the first segment ET1 and the second segment ET2 arranged in the column direction V.

  The first segment ET1 and the second segment ET2 may be configured to be electrically connected to each other outside the active area and supplied with a common potential from a common feeding point. It may be a configuration.

  According to such a configuration, an increase in resistance of the counter electrode ET including the first segment ET1 and the second segment ET2 can be suppressed, and the same effect as in the first configuration example can be obtained.

  Further, according to the configuration described above, since the connection portion CN is disposed in the light shielding region SLD between the pixels, the same effect as the first configuration example can be obtained.

<< Second Configuration Example-Third Embodiment >>
As shown in FIG. 8, the two pixels PX <b> 1 and PX <b> 2 are adjacent to each other in the row direction H between two adjacent gate lines Y <b> 1-Y <b> 2 (or between two adjacent auxiliary capacitance lines). Each of the source lines X extends along the column direction V of each pixel PX and is arranged between pixels adjacent in the row direction H. Here, the source line X2 is disposed between the pixel PX1 and the pixel PX2. Such a source line X is formed of a conductive material that does not have optical transparency, and forms a light shielding region SLD that does not contribute to display.

  The pixel PX1 is disposed between two adjacent source lines X1-X2. The pixel electrode EP disposed on the pixel PX1 is connected to the source line X1 via a switching element (not shown) disposed near the intersection between the gate line Y1 and the source line X1.

  The counter electrode ET includes a first segment ET1 and a second segment ET2 extending along the row direction H in the pixel PX1. The connection portion CN that electrically connects the first segment ET1 and the second segment ET2 is disposed in the light shielding region SLD formed by the source line X. In the example shown in FIG. 8, the source line X2 faces the connection portion CN.

  According to such 3rd Embodiment, the effect as demonstrated in the 2nd structural example is acquired.

  In the first configuration example and the second configuration example described above, it is desirable that the connection portion CN is integrally formed of the same material as the first segment ET1 and the second segment ET2. That is, the connection portion CN is a part of the counter electrode ET, and is disposed on, for example, the color filter layer 34 in the counter substrate CT as in the example illustrated in FIG. Thereby, it is not necessary to add a separate manufacturing process for forming the connection part CN (that is, the productivity is not deteriorated), and an increase in manufacturing cost can be suppressed.

  Note that the connection portion CN may be formed of a conductive material having a resistance lower than that of the metal oxide, separately from the first segment ET1 and the like.

  Further, the wider the width of the connection portion CN (that is, the length orthogonal to the extending direction), the higher the resistance reduction effect can be expected, but the influence on the display and the margin of misalignment between the array substrate AR and the counter substrate CT. In consideration of the above, it is desirable to set the range not exceeding the light shielding region SLD. In other words, the width of the connection portion CN is preferably smaller than the width of the gate line Y, smaller than the width of the auxiliary capacitance line AY, or smaller than the width of the source line X.

  As shown in FIG. 9, the counter electrode ET includes a plurality of segments ETn with respect to the active area DSP. Each segment ET extends in a stripe shape over the entire active area DSP (in the row direction or the column direction), and is arranged side by side in a direction orthogonal to the extending direction EX. These segments ET are connected to each other outside the active area, for example.

  Each segment ET is arranged over a plurality of pixels PXn arranged in the extending direction EX in the active area DSP. Each segment ET is arranged across two pixels arranged in a direction orthogonal to the extending direction EX. Two adjacent segments ET are electrically connected to each other via at least one connection portion CN between pixels arranged in the extending direction EX (that is, a light shielding region) in the active area DSP.

  For example, the connection part CN may be disposed between all the pixels in the active area DSP. Thus, the resistance of the counter electrode ET can be reduced as the number of connections by the connection portion CN increases.

  On the other hand, considering the influence on display when an undesired electric field is formed between the connection part CN and the pixel electrode EP in the vicinity of the connection part CN, the connection part CN is arranged between all the pixels. Instead, it is desirable to arrange with an arbitrary number smaller than the number of pixels.

  In this case, with regard to the arrangement position of the connection portion CN, if the arrangement position is biased, it causes a problem such as display unevenness. Therefore, the connection portion CN is arranged for every two or more pixels according to a certain rule. Is desirable.

  Further, the connection parts CN may be arranged randomly so that the arrangement position is not biased. Thereby, the influence of the connection part CN can be disperse | distributed. For example, in the example shown in FIG. 9, in the active area DSP, the number of connection parts CN arranged per unit block BLK composed of a plurality of pixels (eg, 9 pixels of 3 × 3) is substantially the same (eg, 3). It is said. In addition, adjacent segments in the unit block BLK do not necessarily have to be connected by the connection part CN. In this case, a connection part CN for connecting adjacent segments in another adjacent unit block BLK may be arranged. good.

  According to such a configuration, the potential distribution in the surface of the counter electrode ET can be made uniform, and a good display quality can be obtained.

  As described above, according to this embodiment, a liquid crystal display device that suppresses an increase in resistance of the counter electrode, has a wide viewing angle characteristic, a high contrast ratio, and can display an image with a good display quality. Can be provided.

  That is, the counter electrode controls the alignment of liquid crystal molecules in the state where an electric field is formed between the stripe-shaped first segment and the second segment facing the pixel electrode in each pixel and the pixel electrode. The first segment and the second segment are electrically connected by a connecting portion in a light shielding region between adjacent pixels.

  That is, although the first segment and the second segment are divided through the slits in each pixel, they are electrically connected in the light shielding region between the pixels. For this reason, the resistance increase of the counter electrode including the first segment and the second segment can be suppressed.

  In addition, since the resistance of the counter electrode is reduced, the deterioration of the drive signal on the counter electrode side is suppressed, and the display is less susceptible to potential fluctuations from the pixel electrode side, such as flicker, crosstalk, and display unevenness. Problems can be suppressed, and an image with good display quality can be displayed.

  Furthermore, since the connection portion is arranged in a light-shielding region between the pixels, even if an undesired electric field is formed between the connection portion and the pixel electrode, it is possible to reduce the influence on the display. Become.

  On the other hand, in the state where no electric field is formed between the pixel electrode and the counter electrode, the liquid crystal molecules that are aligned substantially perpendicular to the main surface of the substrate are separated from each other by the slit formed in the counter electrode in each pixel. Is controlled by an electric field formed between the electrode and the counter electrode. At this time, the electric field formed between the pixel electrode and the first segment and the electric field formed between the second segment are inclined in different directions near the slit.

  Since such an inclined electric field can realize the MVA mode, an image having a wide viewing angle characteristic and a high contrast ratio can be displayed.

  In addition, this invention is not limited to the said embodiment itself, In the stage of implementation, it can change and implement a component within the range which does not deviate from the summary. Further, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine suitably the component covering different embodiment.

FIG. 1 is a diagram schematically showing the configuration of an MVA mode liquid crystal display device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view schematically showing the structure of the array substrate and the counter substrate applied to the liquid crystal display device shown in FIG. FIG. 3 is a cross-sectional view schematically showing a configuration example (slit) of the orientation control means in the present embodiment. FIG. 4 is a diagram for explaining a first configuration example for realizing the MVA mode liquid crystal display device of the present invention. FIG. 5 is a diagram for explaining the first embodiment of the MVA mode liquid crystal display device according to the first configuration example. FIG. 6 is a diagram for explaining a second embodiment of the MVA mode liquid crystal display device according to the first configuration example. FIG. 7 is a diagram for explaining a second configuration example for realizing the MVA mode liquid crystal display device of the present invention. FIG. 8 is a diagram for explaining a third embodiment of the MVA mode liquid crystal display device according to the second configuration example. FIG. 9 is a diagram for explaining a configuration example of a counter electrode for realizing the MVA mode liquid crystal display device of the present invention.

Explanation of symbols

LPN ... Liquid crystal display panel BL ... Backlight unit AR ... Array substrate CT ... Opposite substrate LQ ... Liquid crystal layer DSP ... Active area PX ... Pixel SLD ... Shading area EP ... Pixel electrode W ... Switching element Y ... Gate line X ... Source line AY ... Auxiliary capacitance line ET ... Counter electrode SL ... Slit CN ... Connection part ET1 ... First segment ET2 ... Second segment BM ... Black matrix

Claims (11)

An array substrate provided with pixel electrodes arranged in each matrix-shaped pixel;
A counter substrate including a counter electrode facing the plurality of pixel electrodes;
A liquid crystal layer that is held between the array substrate and the counter substrate and includes liquid crystal molecules that are aligned substantially perpendicular to the main surface of the substrate when no electric field is formed between the pixel electrode and the counter electrode. When,
With
The counter electrode is configured to control the alignment of the liquid crystal molecules in a state where an electric field is formed between the stripe-shaped first and second segments facing the pixel electrode and the pixel electrode in each pixel. A slit formed between the first segment and the second segment, and a connection portion for electrically connecting the first segment and the second segment in a light shielding region between adjacent pixels. A liquid crystal display device characterized by the above. The slit extends along the column direction through the approximate center of each pixel so as to divide each pixel into two regions arranged in the row direction,
The liquid crystal display device according to claim 1, wherein the connection portion is disposed in a light shielding region between pixels adjacent in the column direction.   3. The liquid crystal display according to claim 2, wherein the array substrate includes a gate line that extends along a row direction of the pixels and is disposed between pixels adjacent in the column direction and faces the connection portion. apparatus.   3. The liquid crystal according to claim 2, wherein the array substrate includes a storage capacitor line that extends along a row direction of pixels and is disposed between adjacent pixels in a column direction and faces the connection portion. Display device. The slit extends along the row direction through the approximate center of each pixel so as to divide each pixel into two regions arranged in the column direction,
The liquid crystal display device according to claim 1, wherein the connection portion is disposed in a light shielding region between pixels adjacent in the row direction.   6. The liquid crystal display according to claim 5, wherein the array substrate includes a source line that extends along a column direction of pixels and is disposed between pixels adjacent in the row direction and faces the connection portion. apparatus.   The liquid crystal display device according to claim 1, wherein the connection portion is integrally formed of the same material as the first segment and the second segment.   The first segment and the second segment extend in a stripe shape over the entire active area displaying an image, and are electrically connected via the connection portion at least at one position between pixels arranged in the extending direction. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is a liquid crystal display device.   The liquid crystal display device according to claim 8, wherein the connection portion is arranged for each of a plurality of pixels.   9. The liquid crystal display device according to claim 8, wherein in the active area, the number of connection portions arranged per unit block composed of a plurality of pixels is substantially the same.   2. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is a linearly polarized light mode.

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