JP2010074786A - Encoding/decoding system, encoding circuit, decoding circuit, and tag communication device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the capacity of a memory required for encoding/decoding and to flexibly cope with different kinds of encoding/decoding. <P>SOLUTION: A state storage circuit 94 stores present state information in a plurality of transition states determined by a predetermined encoding system. An encoding information storage circuit 96 stores information for which the combination of the state information of one of the plurality of transition states and encoding object information which is information to be encoded and the combination of post-transition state information indicating the state after transition and encoded information which is the information after encoding as an encoding table. A control circuit 92 receives the input of the encoding object information, outputs the encoded information and the post-transition state information corresponding to the combination of the encoding object information and the present state information stored by the state storage circuit 94 on the basis of the encoding table, and stores the post-transition state information in the state storage circuit 94 as the present state information. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an encoding / decoding system, an encoding circuit, a decoding circuit, and a tag communication device.

  In recent years, RFID that stores information in a small wireless chip and communicates at high frequency with a radio frequency identification (RFID) communication device (RFID reader / writer) for reading and writing has been put into practical use as a central technology of ubiquitous computing. Has attracted attention. Currently, various communication standards for RFID are standardized in accordance with applications, and many products based on these communication standards or products based on original communication standards are sold.

As described above, many types of RFID tags are sold. However, communication methods such as frequency bands and modulation methods are often completely different depending on the RFID tag. Moreover, it is necessary to use the RFID properly according to its use, and it is difficult to unify it into one kind of communication standard. Therefore, an RFID communication device that can communicate with RFID tags of a plurality of communication standards is required. As an RFID communication device capable of communicating with a plurality of communication standard RFID tags, for example, an RFID communication device described in Patent Document 1 is known. Since this RFID communication apparatus is configured to transmit data in a plurality of frequency bands and modulation methods, it can communicate with RFIDs of a plurality of communication standards. In addition, this RFID communication apparatus stores a waveform pattern determined for each communication standard of the RFID tag in a memory, and performs encoding using the waveform pattern. In order to specify this waveform pattern, a method of specifying the waveform pattern by specifying the number of waveform repetitions and the number of cycles is adopted.
JP 2007-134941 A

  However, since the above-described RFID communication apparatus adopts a method of specifying a waveform pattern by specifying the number of repetitions and the number of cycles, it may not necessarily be uniquely determined by the input string, or the number of cycles may be variable. . In this case, since the number of patterns increases, there is a problem that it is necessary to increase the capacity of the memory for storing the patterns. Further, in the above RFID communication apparatus, since it is not possible to perform encoding / encoding of a method different from encoding / decoding of a method for specifying the number of repetitions or the number of cycles, a new code is added for each encoding method. There is a problem that it is necessary to provide a configuration for performing the conversion.

  The present invention has been made in view of the above circumstances, and is capable of reducing the amount of memory required for encoding / decoding and encoding / decoding that can flexibly cope with different types of encoding / decoding. An object is to provide a system, an encoding circuit, a decoding circuit, and a tag communication device.

  The present invention encodes a first state storage circuit that stores current state information in a plurality of transition states determined by a specific encoding method, and state information in any one of the plurality of transition states. A code that stores, as an encoding table, information in which a combination of information to be encoded that is information, post-transition state information indicating a state after transition, and a combination of encoded information that is information after encoding is associated An encoded information storage circuit, receiving the input of the encoded information, and corresponding to a combination of the encoding target information and the current state information stored in the first state storage circuit; A first control circuit that outputs post-transition state information based on the encoding table, and stores the post-transition state information as the current state information in the first state storage circuit; An encoding circuit; a second state storage circuit for storing current state information in a plurality of transition states determined by a method for decoding the encoded information encoded by the specific encoding method; Based on a method for decoding the encoded information encoded by the encoding method, a combination of any one of the plurality of transition states and the encoded information, and a state after the transition are indicated. A decoding information storage circuit that stores information associating a combination of post-transition state information and decoding information, which is information after decoding, as a decoding table; receives the input of the encoding information; Outputting the decoding information and the post-transition state corresponding to a combination of information and the current state information stored in the second state storage circuit based on the decoding table; A decoding circuit comprising: a second control circuit that stores post-transition state information as the current state information in the second state storage circuit; is there.

  According to this configuration, the encoding circuit uniquely determines the post-transition state information and the encoding that are uniquely determined by the combination of the state information of any of the plurality of transition states and the encoding target information. Encoding is performed based on an encoding table, which is information that associates a combination with encoding information that is later information. Thereby, the encoding circuit can flexibly cope with different types of encoding by changing the encoding table.

  In addition, the decoding circuit includes post-transition state information indicating a post-transition state and post-decoding information that is uniquely determined by a combination of any one of a plurality of transition states and encoding information. Decoding is performed based on a decoding table, which is information associated with a certain combination of decoding information. Thereby, the decoding circuit can flexibly cope with different types of decoding by changing the decoding table.

  Further, the present invention is an encoding circuit that performs encoding by a specific encoding method, a state storage circuit that stores current state information in a plurality of transition states determined by a specific encoding method, A combination of any state information in the transition state, encoding target information that is information to be encoded, post-transition state information indicating a state after transition, and encoding information that is information after encoding And an encoding information storage circuit that stores information associated with the combination as a coding table, and accepts input of the encoding target information, and the encoding target information and the current storage stored in the state storage circuit The encoding information and the post-transition state information corresponding to the combination with the state information are output based on the encoding table, and the post-transition state information is used as the current state information for the state. A control circuit to be stored in 憶回 path is a coding circuit, characterized in that it comprises a.

  According to this configuration, the encoding circuit uniquely determines the post-transition state information and the encoding that are uniquely determined by the combination of the state information of any of the plurality of transition states and the encoding target information. Encoding is performed based on an encoding table, which is information associated with a combination of encoding information that is later information. Thereby, the encoding circuit can flexibly cope with different types of encoding by changing the encoding table.

  Further, the present invention is a decoding circuit for decoding encoded information encoded by a specific encoding method, and a method for decoding the encoded information encoded by the specific encoding method Among the plurality of transition states based on a state storage circuit that stores current state information in a plurality of transition states defined by and a method for decoding the encoded information encoded by the specific encoding method A decoding table, information that associates a combination of any one of the state information and the encoded information, a post-transition state information indicating a post-transition state, and a combination of decoding information that is information after decoding. A decoding information storage circuit that stores the encoded information, and the decoding information corresponding to a combination of the encoding information and the current state information stored in the state storage circuit; And a control circuit that outputs the post-transition state based on the decryption table and stores the post-transition state information as the current state information in the state storage circuit. Circuit.

  According to this configuration, the decoding circuit includes the post-transition state information indicating the post-transition state and the post-decoding state, which is uniquely determined by a combination of any one of the plurality of transition states and the encoded information. Decoding is performed based on a decoding table, which is information associated with a combination with the decoding information that is the information of the above. Thereby, the decoding circuit can flexibly cope with different types of decoding by changing the decoding table.

  Further, the present invention provides an encoding circuit that encodes transmission data by an encoding method specified by a predetermined communication method, and the encoding circuit encodes the transmission data in a frequency band specified by the communication method. A high-frequency circuit that transmits transmission data to the wireless tag and receives reception data transmitted from the wireless tag corresponding to the transmission data, and the reception data received by the high-frequency circuit corresponds to the encoding method. And a host interface that outputs the received data decoded by the decoding circuit.

  According to this configuration, the encoding circuit encodes transmission data to be transmitted to the wireless tag, and the transmission unit transmits the transmission data encoded by the encoding circuit to the wireless tag. The reception unit receives the reception data transmitted from the wireless tag, and the decoding circuit decodes the reception data received by the reception unit. Thus, since the encoding circuit encodes the transmission data and the decoding circuit decodes the reception data, the transmission unit and the reception unit can be configured to perform only minimum processing of transmission and reception. .

  Further, the present invention includes a plurality of high frequency circuits capable of communicating in frequency bands corresponding to each of a plurality of communication schemes, and the encoded information storage circuit included in the encoding circuit is defined by the plurality of communication schemes. A plurality of the encoding tables defined for each of the plurality of encoding schemes are stored, and the decoding information storage circuit included in the decoding circuit is defined for each of the decoding schemes corresponding to the plurality of encoding schemes. A plurality of the decoded tables stored, and switching any one communication method among the plurality of communication methods to store the encoding table corresponding to the encoding method defined by the selected communication method. Control the encoding circuit to perform encoding, and transmit the transmission data and receive the reception data using the high-frequency circuit capable of communication in the frequency band defined by the communication method. And it controls to perform, a tag communication apparatus further comprising a control unit for controlling the encoding circuit to perform coding by using the coding table corresponding to the communication method.

  As a result, the encoding circuit performs encoding based on the encoding table determined by the encoding method used for encoding among the encoding tables determined by a plurality of types of encoding methods. Encoding can be performed by any one of the encoding methods. In addition, the decoding circuit performs decoding based on a decoding table defined by a method used for decoding among a plurality of decoding tables to be stored, so that any one of a plurality of types of decoding methods is selected. Decoding can be performed by a decoding method.

  According to the present invention, it is possible to reduce the memory capacity required for encoding / decoding and flexibly cope with different types of encoding / decoding.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram showing a configuration of an RFID reader / writer 1 according to an embodiment of the present invention. In FIG. 1, a host interface 11 is an interface for communicating with a host computer (not shown).

  The main controller 12 manages communication with the host computer and control of each unit in the RFID reader / writer 1. The RF circuit control block 13 performs control such as switching on / off of carriers in the RF circuits 40a, 40b,..., 40n, and changing the modulation degree by the electronic volume. The RFID reader / writer 1 according to the present embodiment includes an RF circuit for each frequency band of a carrier used for transmission to an RFID tag.

  The transmission control block 20 generates data to be transmitted by the RF circuits 40a, 40b, ..., 40n. The D / A converter 71 converts the data generated by the transmission control block 20 into an analog signal and outputs an analog signal to the RF circuits 40a, 40b,. The A / D converter 70 converts signals received by the RF circuits 40a, 40b,..., 40n into digital data. The reception control block 30 performs data processing based on digital data output from the A / D converter 70. The RF circuits 40a, 40b, ..., 40n perform wireless communication with an RFID tag (not shown).

  FIG. 2 is a configuration diagram showing the configuration of the transmission control block 20 of FIG. In FIG. 2, the controller 201 controls each unit in the transmission control block 20. The transmission data read control unit 202 reads the transmission data held in the transmission data buffer 203 in the order determined for each communication standard, and outputs the read data to the pattern read control unit 208. The transmission data buffer 203 holds data to be transmitted to the RFID tag.

  A CRC (Cyclic Redundancy Check) generation unit 204 calculates a CRC value used in error detection based on transmission data. The selector 205 selects whether or not to use CRC in accordance with the RFID communication standard.

  The parity generation unit 206 generates parity used for error detection from transmission data. The selector 207 selects whether to use parity according to the RFID communication standard.

  The pattern readout control unit 208 includes an encoding circuit described later. The pattern readout control unit 208 encodes the input transmission data using an encoding circuit. The pattern reading control unit 208 reads a pattern used for encoding encoded transmission data from the pattern buffer 209 in accordance with the RFID communication standard. In the encoding process, logic “0” and logic “1” of encoded transmission data represented by binary values are expressed by a waveform based on a certain rule. The pattern buffer 209 holds a waveform pattern corresponding to logic “0” and a waveform pattern corresponding to logic “1” for each RFID communication standard.

  The pattern generation unit 210 generates a transmission data pattern to be transmitted to the RFID tag from the encoded pattern read from the pattern buffer 209 and the transmission data encoded by the pattern read control unit 208, and sends it to the D / A converter 71 in FIG. Is output.

  FIG. 3 is a configuration diagram showing the configuration of the reception control block 30 of FIG. In FIG. 3, the reception sequence control unit 301 controls each unit in the reception control block 30.

  The sampling unit 303 samples the digital data output from the A / D converter 70 shown in FIG. The carrier detection unit 304 detects a carrier from the sampled data and outputs the result to the reception sequence control unit 301. The carrier detection unit 304 checks whether or not a carrier signal is generated in the communication field before transmission from the RF circuits 40a, 40b,..., 40n. The filter combination block 305 filters the sampled data in order to remove noise and the like.

  FIG. 4 is a configuration diagram showing the configuration of the filter combination block 305 of FIG. In FIG. 4, selectors 351, 352, 353, and 357 select to apply a filter determined according to the RFID communication standard.

  The edge detection filter 354 is a filter that emphasizes high frequency components in the RF input data. The frequency separation filter 355 is a filter that separates RF input data into a plurality of frequency components. The low-pass filter 356 is a filter that extracts a low-frequency component in the RF input data.

  Returning to the description of FIG. The re-sampling unit 306 re-samples the filtered data. The SOF (Start of Frame) detection unit 307 detects the start of a frame received from the RFID tag and outputs the result to the reception sequence control unit 301.

  The SYNC detection unit 308 detects data from the frame received from the RFID tag, and outputs the detection result to the reception sequence control unit 301. An EOF (End of Frame) detection unit 309 detects the end of the frame received from the RFID tag, and outputs the result to the reception sequence control unit 301.

  The code conversion unit 310 decodes the resampled data. Further, the code conversion unit 310 includes a decryption circuit described later. The code conversion unit 310 decodes the decoded data using a decoding circuit. The CRC check unit 311 detects the error by calculating the CRC value of the decoded data, and outputs the result to the reception sequence control unit 301. The parity check unit 312 detects an error based on the parity of the decoded data, and outputs the result to the reception sequence control unit 301.

  The serial-parallel converter 313 converts the decrypted serial data into parallel data and stores it in the reception buffer 314. The reception sequence control unit 301 inputs parallel data stored in the reception buffer 314 to the main controller 12.

  FIG. 5 is a configuration diagram showing the internal configuration of each of the RF circuits 40a, 40b,..., 40n in FIG. In FIG. 5, an oscillation circuit 401 is a circuit that oscillates at a frequency determined for each communication standard. The modulation circuit 402 receives an analog signal output from the D / A converter 71 of FIG. 1 and modulates the carrier oscillated by the oscillation circuit 401.

  In the current RFID communication standard, ASK (Amplitude Shift Keying) or FSK (Frequency Shift Keying) is often used as a modulation method, so that the modulation circuit can change the amplitude modulation parameter and the carrier frequency parameter. 402 is designed.

  The antenna drive circuit 403 outputs the carrier modulated by the modulation circuit 402 from the antenna 404. The antenna 404 wirelessly transmits the modulated carrier to the RFID and receives radio waves wirelessly transmitted from the RFID.

  The filter circuit 405 removes noise from the analog signal received by the antenna 404. The amplifier 406 amplifies the analog signal output from the filter circuit 405.

  Next, an encoding circuit included in the pattern reading control unit 208 will be described. This encoding circuit uses a push-down automaton. Hereinafter, description will be made using an example of encoding called FM0.

  FIG. 6 is a configuration diagram showing the configuration of the encoding circuit. The encoding circuit includes an input circuit 91, a control circuit 92, an output circuit 93, a state storage circuit 94, a temporary storage circuit 95, and an encoded information storage circuit 96.

  The input circuit 91 receives input of information to be encoded. The control circuit 92 is a circuit that performs encoding. The output circuit 93 is a circuit that outputs encoded information. The state storage circuit 94 is a storage circuit that stores information indicating a state at the time of encoding. Further, the state storage circuit 94 stores an initial state “S1”. The temporary storage circuit 95 is a circuit that temporarily stores information received by the input circuit 91. The encoding information storage circuit 96 is a storage circuit that stores an encoding table that is information for specifying an operation related to encoding of the control circuit 92. The encoding information storage circuit 96 stores this encoding table for each encoding method. By switching the encoding table stored in the encoding information storage circuit 96, a plurality of encoding methods can be supported. Note that the main controller 12 controls switching of the encoding table in accordance with the encoding method defined by the communication method used by the RFID reader / writer 1. Thereby, the encoding circuit can perform the encoding specified by the communication method used by the RFID reader / writer 1.

  FIG. 7 is a diagram showing information indicating the current state (hereinafter referred to as the current state) stored in the state storage circuit 94. In the illustrated example, the current state is “S1”.

  FIG. 8 is a diagram showing a confirmation bit number table that defines the number of bits of the input value stored in the temporary storage circuit 95. In the illustrated example, the number of confirmation bits is “1”. This indicates that the temporary storage circuit 95 temporarily stores 1-bit input information, and the control circuit 92 encodes the temporarily stored 1-bit input information.

  FIG. 9 is a diagram showing a coding table stored in the coding information storage circuit 96. The encoding table stores the current state stored in the state storage circuit 94, the input value stored in the temporary storage circuit 95, the output value associated with the current state and the input value, and the transition destination state. .

  In the illustrated example, the line 1601 outputs “0, 1” as an output value when “0” is input when the current state is “S1”, and sets the transition destination state to “S3”. Is shown. The other rows are as shown. Note that the illustrated example shows conditions for performing encoding called FM0. By switching the encoding table stored in the encoding information storage circuit 96 according to the encoding conditions, various encodings can be handled.

  If the output value and the transition destination state associated with the current state stored in the state storage circuit 94 and the input value stored in the temporary storage circuit 95 are not stored in the encoding table, the input value Is a value not assumed in this encoding circuit. For example, the combination of the current state and the input value that is not defined in FIG. 9 is a combination of the input value and the current state that is not assumed in the encoding in FM0. The input circuit 91 does not accept input of unexpected input values.

  Next, the operation of the encoding circuit will be described. As a specific example, description will be made using an example in which an input 4-bit value “0010” is encoded. First, the input circuit 91 receives an input of “0010”. Subsequently, the control circuit 92 reads the initial state value “S1” stored in the state storage circuit 94 and rewrites the current state stored in the state storage circuit 94 to the initial state value “S1”.

  Subsequently, the control circuit 92 reads the input value “0” of the first bit among the inputs received by the input circuit 91 and stores it in the temporary storage circuit 95. Since the confirmation bit number table stored in the temporary storage circuit 95 defines the number of confirmation bits “1”, the input value stored in the temporary storage circuit 95 is 1 bit. Since the number of bits of information stored in the temporary storage circuit 95 is the same as the number of bits specified in the confirmation bit number table, the control circuit 92 reads the input value “0” stored in the temporary storage circuit 95. . Subsequently, since the control circuit 92 reads information from the temporary storage circuit 95, the control circuit 92 erases all the information stored in the temporary storage circuit 95.

  Subsequently, the control circuit 92 reads the current state “S1” from the state storage circuit 94. Subsequently, the control circuit 92 outputs the output value “0, 1” associated with the current state “S1” and the input value “0” from the encoding table stored in the encoding information storage circuit 96, and the transition destination. The state “S3” is read out.

  Subsequently, the control circuit 92 inputs the output value “0, 1” to the output circuit 93. Subsequently, the control circuit 92 rewrites the current state stored in the state storage circuit 94 to the transition destination state “S3”.

  Since the processing of the information stored in the temporary storage circuit 95 is completed, the control circuit 92 reads the input value “0” of the second bit among the inputs received by the input circuit 91 and stores it in the temporary storage circuit 95. Since the number of bits of information stored in the temporary storage circuit 95 is the same as the number of bits specified in the confirmation bit number table, the control circuit 92 reads the input value “0” stored in the temporary storage circuit 95. . Subsequently, since the control circuit 92 reads information from the temporary storage circuit 95, the control circuit 92 erases all the information stored in the temporary storage circuit 95.

  Subsequently, the control circuit 92 reads the current state “S3” from the state storage circuit 94. Subsequently, the control circuit 92 outputs the output value “0, 1” associated with the current state “S3” and the input value “0” from the encoding table stored in the encoding information storage circuit 96, and the transition destination. The state “S3” is read out.

  Subsequently, the control circuit 92 inputs the output value “0, 1” to the output circuit 93. Subsequently, the control circuit 92 rewrites the current state stored in the state storage circuit 94 to the transition destination state “S3”.

  Since the processing of the information stored in the temporary storage circuit 95 is completed, the control circuit 92 reads the input value “1” of the third bit among the inputs received by the input circuit 91 and stores the input value “1” in the temporary storage circuit 95. Since the number of bits of information stored in temporary storage circuit 95 is the same as the number of bits specified in the confirmation bit number table, control circuit 92 reads input value “1” stored in temporary storage circuit 95. . Subsequently, since the control circuit 92 reads information from the temporary storage circuit 95, the control circuit 92 erases all the information stored in the temporary storage circuit 95.

  Subsequently, the control circuit 92 reads the current state “S3” from the state storage circuit 94. Subsequently, the control circuit 92 outputs the output value “0, 0” associated with the current state “S3” and the input value “1” from the encoding table stored in the encoding information storage circuit 96, and the transition destination. The state “S4” is read out.

  Subsequently, the control circuit 92 inputs the output value “0, 0” to the output circuit 93. Subsequently, the control circuit 92 rewrites the current state stored in the state storage circuit 94 to the transition destination state “S4”.

  Since the processing of the information stored in the temporary storage circuit 95 is completed, the control circuit 92 reads the input value “0” of the fourth bit among the inputs received by the input circuit 91 and stores it in the temporary storage circuit 95. Since the number of bits of information stored in the temporary storage circuit 95 is the same as the number of bits specified in the confirmation bit number table, the control circuit 92 reads the input value “0” stored in the temporary storage circuit 95. . Subsequently, since the control circuit 92 reads information from the temporary storage circuit 95, the control circuit 92 erases all the information stored in the temporary storage circuit 95.

  Subsequently, the control circuit 92 reads the current state “S4” from the state storage circuit 94. Subsequently, the control circuit 92 outputs the output value “1, 0” associated with the current state “S4” and the input value “0” from the encoding table stored in the encoding information storage circuit 96, and the transition destination. The state “S2” is read out.

  Subsequently, the control circuit 92 inputs the output value “1, 0” to the output circuit 93. Subsequently, the control circuit 92 rewrites the current state stored in the state storage circuit 94 to the transition destination state “S2”.

  Since the processing of the information stored in the temporary storage circuit 95 is finished and the processing of all the input values received by the input circuit 91 is finished, the control circuit 92 causes the output circuit 93 to output the output value “010100010”. Thereafter, the process ends. As described above, the encoding circuit can output a value “0101010010” obtained by decoding the input value “0010”.

  Next, a decoding circuit included in the code conversion unit 310 will be described. Hereinafter, description will be made using an example in which data encoded by encoding called FM0 is decoded.

  FIG. 10 is a configuration diagram showing the configuration of the decoding circuit. The encoding circuit includes an input circuit 131, a control circuit 132, an output circuit 133, a state storage circuit 134, a temporary storage circuit 135, and a decoded information storage circuit 136.

  The input circuit 131 receives input of information for decoding. The control circuit 132 is a circuit that performs decoding. The output circuit 133 is a circuit that outputs the decrypted information. The state storage circuit 134 is a storage circuit that stores a state at the time of decoding. Further, the state storage circuit 134 stores an initial state “S1”. The temporary storage circuit 135 is a circuit that temporarily stores information received by the input circuit. The decryption information storage circuit 136 is a storage circuit that stores a decryption table that is information for specifying an operation related to decryption by the control circuit 132. The decryption information storage circuit 136 stores this decryption table for each decryption method. By switching the decoding table stored in the decoding information storage circuit 136, a plurality of decoding methods can be supported. Note that the main controller 12 controls switching of the decoding table in accordance with the decoding method defined by the communication method used by the RFID reader / writer 1. Thereby, the decryption circuit can perform decryption defined by the communication method used by the RFID reader / writer 1.

  FIG. 11 is a diagram showing the current state stored in the state storage circuit 134. In the illustrated example, the current state is “S1”.

  FIG. 12 is a diagram showing a confirmation bit number table that defines the number of bits of the input value stored in the temporary storage circuit 135. In the illustrated example, the number of confirmation bits is “2”. This indicates that the temporary storage circuit 135 temporarily stores 2-bit input information, and the control circuit 132 decodes the temporarily stored 2-bit input information.

  FIG. 13 is a diagram showing a decoding table stored in the decoding information storage circuit 136. The decoding table stores the current state stored in the state storage circuit 134, the input value stored in the temporary storage circuit 135, the output value associated with the current state and the input value, and the transition destination state. .

  In the illustrated example, the row 1201 outputs “0” as an output value when “0, 1” is input when the current state is “S1”, and sets the transition destination state to “S3”. Is shown. The other rows are as shown. Note that the illustrated example shows the conditions for decoding the encoded information called FM0 shown in FIG. As in the case of encoding, various types of decoding can be handled by switching the decoding table stored in the decoding information storage circuit 136 according to the decoding conditions.

  If the output value and the transition destination state associated with the current state stored in the state storage circuit 134 and the input value stored in the temporary storage circuit 135 are not stored in the decoding table, the input value Is a value not assumed in this decoding circuit. For example, the combination of the current state and the input value that is not defined in FIG. 9 is a combination of the input value and the current state that is not assumed in the decoding by FM0. The input circuit 131 does not accept an unexpected input value.

  Next, the operation of the decoding circuit will be described. As a specific example, description will be made using an example of decoding 8-bit input data “010100010” encoded by FM0. First, the input circuit 131 receives an input of “010100010”. Subsequently, the control circuit 132 reads the initial state value “S1” stored in the state storage circuit 134 and rewrites the current state stored in the state storage circuit 134 to the initial state value “S1”.

  Subsequently, the control circuit 132 reads the input value “0” of the first bit among the inputs received by the input circuit 131, and stores it in the temporary storage circuit 135. In the confirmation bit number table stored in the temporary storage circuit 135, the number of confirmation bits is “2”, and the input value stored in the temporary storage circuit 135 is 1 bit. Read eye input. The control circuit 132 stores the read second bit input value “1” in the temporary storage circuit 135.

  Since the number of bits of information stored in the temporary storage circuit 135 is the same as the number of bits specified in the confirmation bit number table, the control circuit 132 inputs the input values “0, 1” stored in the temporary storage circuit 135. Is read. Subsequently, since the control circuit 132 reads the information from the temporary storage circuit 135, the control circuit 132 erases all the information stored in the temporary storage circuit 135.

  Subsequently, the control circuit 132 reads the current state “S1” from the state storage circuit 134. Subsequently, the control circuit 132, from the decryption table stored in the decryption information storage circuit 136, the output value “0” associated with the current state “S1” and the input values “0, 1”, and the transition destination The state “S3” is read out.

  Subsequently, the control circuit 132 inputs the output value “0” to the output circuit 133. Subsequently, the control circuit 132 rewrites the current state stored in the state storage circuit 134 to the transition destination state “S3”.

  Since the processing of the information stored in the temporary storage circuit 135 is finished, the control circuit 132 reads the input value “0” of the third bit among the inputs received by the input circuit 131 and stores it in the temporary storage circuit 135. In the confirmation bit number table stored in the temporary storage circuit 135, the number of confirmation bits is “2”, and the input value stored in the temporary storage circuit 135 is 1 bit. Therefore, the control circuit 132 receives 4 bits from the input circuit 131. Read eye input. The control circuit 132 stores the read input value “1” of the fourth bit in the temporary storage circuit 135.

  Since the number of bits of information stored in the temporary storage circuit 135 is the same as the number of bits specified in the confirmation bit number table, the control circuit 132 inputs the input values “0, 1” stored in the temporary storage circuit 135. Is read. Subsequently, since the control circuit 132 reads the information from the temporary storage circuit 135, the control circuit 132 erases all the information stored in the temporary storage circuit 135.

  Subsequently, the control circuit 132 reads the current state “S3” from the state storage circuit 134. Subsequently, the control circuit 132, from the decryption table stored in the decryption information storage circuit 136, the output value “0” associated with the current state “S3” and the input values “0, 1”, and the transition destination The state “S3” is read out.

  Subsequently, the control circuit 132 inputs the output value “0” to the output circuit 133. Subsequently, the control circuit 132 rewrites the current state stored in the state storage circuit 134 to the transition destination state “S3”.

  Since the processing of the information stored in the temporary storage circuit 135 is completed, the control circuit 132 reads the input value “0” of the fifth bit among the inputs received by the input circuit 131 and stores it in the temporary storage circuit 135. In the confirmation bit number table stored in the temporary storage circuit 135, the number of confirmation bits is “2”, and the input value stored in the temporary storage circuit 135 is 1 bit. Therefore, the control circuit 132 receives 6 bits from the input circuit 131. Read eye input. The control circuit 132 stores the read sixth-bit input value “0” in the temporary storage circuit 135.

  Since the number of bits of information stored in the temporary storage circuit 135 is the same as the number of bits specified in the confirmation bit number table, the control circuit 132 inputs the input value “0, 0” stored in the temporary storage circuit 135. Is read. Subsequently, since the control circuit 132 reads the information from the temporary storage circuit 135, the control circuit 132 erases all the information stored in the temporary storage circuit 135.

  Subsequently, the control circuit 132 reads the current state “S3” from the state storage circuit 134. Subsequently, the control circuit 132, from the decoding table stored in the decoding information storage circuit 136, the output value “1” associated with the current state “S3” and the input value “0, 0”, and the transition destination The state “S4” is read out.

  Subsequently, the control circuit 132 inputs the output value “1” to the output circuit 133. Subsequently, the control circuit 132 rewrites the current state stored in the state storage circuit 134 to the transition destination state “S4”.

  Since the processing of the information stored in the temporary storage circuit 135 is completed, the control circuit 132 reads the input value “1” of the seventh bit among the inputs received by the input circuit 131 and stores it in the temporary storage circuit 135. In the confirmation bit number table stored in the temporary storage circuit 135, the number of confirmation bits is “2”, and the input value stored in the temporary storage circuit 135 is 1 bit. Therefore, the control circuit 132 receives 8 bits from the input circuit 131. Read eye input. The control circuit 132 stores the read sixth-bit input value “0” in the temporary storage circuit 135.

  Since the number of bits of information stored in the temporary storage circuit 135 is the same as the number of bits specified in the confirmation bit number table, the control circuit 132 inputs the input value “1, 0” stored in the temporary storage circuit 135. Is read. Subsequently, since the control circuit 132 reads the information from the temporary storage circuit 135, the control circuit 132 erases all the information stored in the temporary storage circuit 135.

  Subsequently, the control circuit 132 reads the current state “S4” from the state storage circuit 134. Subsequently, the control circuit 132, from the decryption table stored in the decryption information storage circuit 136, the output value “0” associated with the current state “S4” and the input value “1, 0”, and the transition destination The state “S2” is read out.

  Subsequently, the control circuit 132 inputs the output value “0” to the output circuit 133. Subsequently, the control circuit 132 rewrites the current state stored in the state storage circuit 134 to the transition destination state “S2”.

  Since the processing of the information stored in the temporary storage circuit 135 is finished and the processing of all input values received by the input circuit 131 is finished, the control circuit 132 causes the output circuit 133 to output the output value “0010”. Thereafter, the process ends. As described above, the decoding circuit can output the value “0010” obtained by decoding the input value “010100010” encoded by FM0.

  Next, the operation of the RFID reader / writer will be described with reference to FIGS. FIG. 14 is a flowchart showing a procedure when the RFID reader / writer of FIG. 1 communicates with the RFID tag. Note that, in the present embodiment, among the processes required when transmitting data to the RFID tag, protocol processing is performed by software, and encoding processing, CRC generation, parity generation, and modulation processing are performed by hardware.

  When the RFID reader / writer 1 communicates with an RFID tag, the main controller 12 first selects one RFID communication standard. Subsequently, the main controller 12 sends information indicating the type of the selected RFID communication standard to the RF circuit control block 13, the controller 201 in the transmission control block 20, and the reception sequence control unit 301 in the reception control block 30. To enter.

  When information indicating the type of RFID communication standard is input from the main controller 12, the controller 201 in the transmission control block 20 transmits information indicating the type of communication standard to the transmission data read control unit 202 and the pattern read control unit 208. Enter.

  In this embodiment, the frame shown in FIG. 15 is used as a basic transmission frame common to all RFID communication standards. The basic transmission frames are arranged in the order of SOF, SYNC, DATA, CRC, and EOF. The SOF is a pattern indicating the start of a basic transmission frame. SYNC is a pattern indicating that data will follow later. DATA is user data. The CRC is a CRC value generated by the CRC generation unit 204 following DATA. EOF is a pattern indicating the end of a frame.

  Some RFID communication standards do not use SYNC or CRC. The transmission data read control unit 202 does not input unused data to the pattern read control unit 208. As a result, the RFID reader / writer 1 of the present embodiment can also cope with the communication standard of the RFID communication standard that does not use SYNC or CRC.

  Subsequently, the transmission data read control unit 202 in the transmission control block 20 reads transmission data stored in the transmission data buffer 203. Subsequently, the transmission data read control unit 202 sequentially outputs the transmission data read according to the order determined by the communication standard to the pattern read control unit 208. At this time, the transmission data read control unit 202 performs CRC generation and / or parity generation from the transmission data according to the RFID communication standard to be used, and outputs the CRC to the pattern read control unit 208.

  For example, when communicating with an RFID tag of a communication standard that uses both CRC and parity, the transmission data read control unit 202 controls the selector 205 so that the selector 205 outputs the output of the CRC generation unit 204, and the parity The selector 207 is controlled so that the output of the generation unit 206 is output by the selector 207, and these outputs are input to the pattern reading control unit 208. At this time, the CRC value is added by the CRC generation unit 204 and the parity information is further added by the parity generation unit 206 to the transmission data read from the transmission data buffer 203 by the transmission data read control unit 202.

  On the other hand, when communicating with an RFID tag of a communication standard that uses only parity, the transmission data read control unit 202 controls the selector 205 so that the selector 205 does not output the output of the CRC generation unit 204, and the parity generation unit The selector 207 is controlled so that the output of 206 is output by the selector 207, and these outputs are input to the pattern reading control unit 208. At this time, parity information is added by the parity generation unit 206 to the transmission data read from the transmission data buffer 203 by the transmission data read control unit 202.

  The pattern readout control unit 208 encodes input transmission data using an encoding circuit. At this time, the main controller 12 switches the encoding table stored in the encoding information storage circuit 96 to an encoding table corresponding to the encoding method defined by the communication method selected by the main controller 12. Thereby, the encoding circuit can perform the encoding specified by the communication method used by the RFID reader / writer 1.

  Subsequently, the pattern reading control unit 208 outputs the encoded transmission data to the pattern generation unit 210 and instructs the pattern buffer 209 to output a waveform pattern corresponding to the RFID communication standard to the pattern generation unit 210. .

  The pattern generation unit 210 encodes the encoded transmission data input from the pattern read control unit 208 based on the waveform pattern input from the pattern buffer 209 to generate a transmission data pattern.

  In the encoding process, regarding the DATA of FIG. 15 of the transmission data expressed in binary logic, a waveform pattern corresponding to logic “0” or a waveform pattern corresponding to logic “1” according to the order of the bit pattern. Are output in sequence. Regarding the SOF, SYNC, and EOF shown in FIG. 15, since the waveform pattern is defined by the communication standard, the waveform pattern is held in the pattern buffer 209. Then, a waveform pattern corresponding to SOF, SYNC, or EOF is output from the pattern buffer 209 to the pattern generation unit 210 during encoding by the pattern generation unit 210.

  As described above, in the present embodiment, a waveform pattern determined for each communication standard is stored in the pattern buffer 209, and is extracted from the pattern buffer 209 for use during encoding. Therefore, when a new communication method with a different waveform pattern is supported, a waveform pattern used in the communication method may be added to the pattern buffer 209, and the new communication method can be flexibly supported.

  When information indicating the type of RFID communication standard selected by the main controller 12 is input from the main controller 12 to the RF circuit control block 13, the RF circuit control block 13 reads the RF circuit corresponding to the communication standard (in the following, , Described as an RF circuit 40a). Further, the RF circuit control block 13 adjusts the modulation degree of the modulation circuit 402 in the RF circuit 40a with the electronic volume so that the modulation degree defined in the communication standard is obtained.

  In this embodiment, since the modulation degree of the modulation circuit 402 can be adjusted, the same RF circuit 40a can be used for communication standards having the same carrier frequency band and different modulation degrees. Therefore, the circuit scale can be reduced as compared with a conventional RFID reader / writer provided with an RF circuit for each RFID communication standard.

  The pattern generation unit 210 in FIG. 2 inputs the generated transmission data pattern to the modulation circuit 402 of the RF circuit 40a corresponding to the RFID communication standard to be used. The modulation circuit 402 modulates the carrier generated by the oscillation circuit 401 with the input transmission data pattern. The modulated transmission signal (hereinafter referred to as a command) is transmitted from the antenna 404 to the RFID tag via the antenna driving circuit 403 (step S601).

  After the antenna 404 transmits a command to the RFID tag, the main controller 12 checks whether or not a response to the command is received from the RFID tag (step S602). When the communication standard of the RFID tag is different from the communication standard used when the command is transmitted by the RFID reader / writer, the RFID tag cannot respond to the command.

  If the RFID tag communication standard is different from the communication standard used when sending a command with the RFID reader / writer, a response is received even if a certain time (time determined by the RFID communication standard) elapses after the command is sent. Cannot be performed (step S602: No). When the response cannot be received, the main controller 12 determines that the RFID tag corresponding to the communication standard does not exist around the communication of the RFID reader / writer 1 (step S603).

  Next, the main controller 12 determines whether or not all communication standard commands supported by the RFID reader / writer 1 have been transmitted. If it is determined that the commands of all communication standards supported by the RFID reader / writer 1 have not been transmitted (step S605: No), the process returns to step S601 to perform a command transmission process of another communication standard. When it is determined that all communication standard commands have been transmitted, the process ends.

  On the other hand, when the main controller 12 determines that the response from the RFID tag has been received within a certain time after the command transmission (step S602: Yes), the main controller 12 recognizes the RFID tag (step S604).

  As described above, in the present embodiment, all communication standard commands supported by the RFID reader / writer 1 are automatically and sequentially transmitted to determine whether or not a response from the RFID tag is received, and the determination result. To determine the communication standard of the RFID tag. Therefore, when a user brings an RFID tag that can be communicated with the RFID reader / writer 1 within the communicable range of the RFID reader / writer 1, the RFID reader / writer 1 automatically recognizes and recognizes the communication standard of the RFID tag. Communication with the RFID tag is performed using the communication standard.

  Hereinafter, a process after receiving a response from the RFID tag will be described. It should be noted that the code detection, code conversion, CRC check, and parity check processes that are performed in the reception process described later are performed by dedicated hardware blocks. Here, the hardware block can be used in all communication standards.

  When the antenna 404 receives an analog reception signal as a response from the RFID tag, the antenna 404 inputs the analog reception signal to the amplifier 406 via the filter circuit 405. The amplifier 406 amplifies the input analog signal and inputs it to the A / D converter 70 shown in FIG.

  The A / D converter 70 converts the input analog reception signal into digital data and inputs the digital data to the sampling unit 303. The sampling unit 303 samples the input digital data at a predetermined interval. The carrier detection unit 304 performs carrier detection using the sampled digital data. Further, the filter combination block 305 and the resampling unit 306 perform code detection using the sampled digital data.

  In the code detection process, the sampled digital data passes through one or more of the three types of filters shown in FIG. 4, and the waveform of the sampled digital data is shaped. Here, the filter to be used is selected when the reception sequence control unit 301 switches the selectors 351, 352, 353, and 357 based on the RFID communication standard information notified from the main controller 12.

  After the filter combination block 305 performs waveform shaping of the digital data, the SOF detector 307 detects the SOF of the digital data. FIG. 16 shows a basic reception frame used in this embodiment. The SOF, SYNC, DATA, CRC, and EOF of the basic reception frame are the same as those in FIG.

  The SOF detector 307 detects the SOF of the digital data. The SOF detector 307 holds the SOF waveform pattern corresponding to each communication standard, compares the waveform pattern with the digital data after waveform shaping, and determines that the pattern that matches the SOF waveform pattern is SOF. To do.

  Subsequently, the SYNC detector 308 detects the SYNC of the digital data. The SYNC detection unit 308 holds a SYNC waveform pattern corresponding to each communication standard, compares the waveform pattern with the digital data after waveform shaping, and determines a pattern that matches the SYNC waveform pattern as SYNC. To do. Note that the SYNC detection process is not performed in a communication standard that does not use SYNC.

  Subsequently, the resampling unit 306 samples the DATA again. In this embodiment, it is possible to pass a plurality of types of filters or to perform sampling a plurality of times. Therefore, it can cope with an arbitrary waveform.

  The code conversion unit 310 decodes the digital data sampled by the resampling unit 306. The decoding process is the reverse of the encoding process performed by the pattern generation unit 210 in FIG. When the code converter 310 processes the digital data in order from the front and detects a waveform pattern corresponding to logic “0” or logic “1”, the code converter 310 sequentially outputs the corresponding logic “0” or logic “1”. Subsequently, the code conversion unit 310 decodes the output value using a decoding circuit. At this time, the main controller 12 switches the decoding table stored in the decoding information storage circuit 136 to a decoding table corresponding to the decoding method defined by the communication method selected by the main controller 12. Thereby, the decryption circuit can perform decryption defined by the communication method used by the RFID reader / writer 1.

  Subsequently, the EOF detection unit 309 detects the EOF of the digital data. When the EOF detection unit 309 detects EOF, the code detection process and the decoding process for the data received from the RFID tag are terminated. Here, the EOF detection unit 309 holds an EOF waveform pattern corresponding to each communication standard, compares the waveform pattern with the digital data after waveform shaping, and finds a pattern that matches the waveform pattern of the EOF. Judged as EOF.

  After the decoding process ends, the CRC check unit 311 confirms the CRC value of the decoded data. Subsequently, the parity check unit 312 confirms the parity of the data for which the CRC value has been confirmed. When the CRC check unit 311 and the parity check unit 312 determine that there is no error in the received data, the serial-parallel conversion unit 313 converts the received data into parallel data. Subsequently, the reception buffer 314 stores the parallel data converted by the serial-parallel conversion unit 313. When the CRC check unit 311 or the parity check unit 312 determines that the received data includes an error, the controller 201 transmits a message requesting retransmission of information to the RFID tag according to the RFID communication standard. Perform the process.

  The data stored in the reception buffer 314 is output to the main controller 12 in FIG. 1 and transmitted to an external host computer via the host interface 11.

  As described above, the encoding circuit can encode the input value according to the conditions defined in the encoding table stored in the encoding information storage circuit 96. Further, the decoding circuit can decode the input value in accordance with the conditions defined in the decoding table stored in the decoding information storage circuit 136. As a result, by changing the encoding table stored in the encoding information storage circuit 96 and the decoding table stored in the decoding information storage circuit 136, encoding and decoding of various conditions can be performed.

  In this embodiment, encoding and decoding are performed by hardware. Compared with the case where encoding and decoding are performed by software, encoding and decoding by hardware has an effect that the processing time is short.

  As mentioned above, although embodiment of this invention was explained in full detail, the concrete structure is not restricted to this embodiment, The design change etc. of the range which does not deviate from the summary of this invention are included.

It is the block diagram which showed the structure of the RFID reader / writer in one Embodiment of this invention. It is the block diagram which showed the structure of the transmission control block in this embodiment. It is the block diagram which showed the structure of the reception control block in this embodiment. It is the block diagram which showed the structure of the filter combination block in this embodiment. It is the block diagram which showed the structure of RF circuit in this embodiment. It is the block diagram which showed the structure of the encoding circuit in this embodiment. It is the schematic which showed the information which shows the present state in this embodiment. It is the schematic which showed the data structure of the confirmation bit number table in this embodiment. It is the schematic which showed the data structure of the encoding table in this embodiment. It is the block diagram which showed the structure of the decoding circuit in this embodiment. It is the schematic which showed the information which shows the present state in this embodiment. It is the schematic which showed the data structure of the confirmation bit number table in this embodiment. It is the schematic which showed the data structure of the decoding table in this embodiment. It is the flowchart which showed the procedure at the time of the RFID reader / writer in this embodiment communicating with an RFID tag. It is the figure which showed the basic transmission frame which the RFID reader / writer in this embodiment uses. It is the figure which showed the basic reception frame which the RFID reader / writer in this embodiment uses.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... RFID reader / writer, 11 ... Host interface, 12 ... Main controller, 13 ... RF circuit control block, 20 ... Transmission control block, 30 ... Reception control block, 40a, 40b , 40n ... RF circuit, 70 ... A / D converter, 71 ... D / A converter, 91, 131 ... input circuit, 92, 132 ... control circuit, 93, 133 ... Output circuit 94, 134 ... state storage circuit, 95, 135 ... temporary storage circuit, 96 ... encoded information storage circuit, 136 ... decoded information storage circuit, 201 ... controller, 202 ... Transmission data read control unit, 203 ... Transmission data buffer, 204 ... CRC generation unit, 205, 207, 351, 352, 353, 357 ... Selector 206: Parity generation unit, 208 ... Pattern read control unit, 209 ... Pattern buffer, 210 ... Pattern generation unit, 301 ... Reception sequence control unit, 303 ... Sampling unit, 304 ..Carrier detection unit, 305... Filter combination block, 306... Re-sampling unit, 307... SOF detection unit, 308... SYNC detection unit, 309. Code conversion unit, 311 ... CRC check unit, 312 ... Parity check unit, 313 ... Serial-parallel conversion unit, 314 ... Receive buffer, 354 ... Edge detection filter, 355 ... Frequency Separation filter, 356... Low pass filter, 401... Oscillation circuit, 402. Antenna driver circuit, 404 ... antenna, 405 ... filter circuit, 406 ... amplifier

Claims (5)

A first state storage circuit for storing current state information in a plurality of transition states determined by a specific encoding method;
A combination of any one of the plurality of transition states, encoding target information that is information to be encoded, post-transition state information indicating a state after transition, and information after encoding An encoded information storage circuit for storing information associated with a combination of encoded information as an encoding table;
The input of the encoded information is received, and the encoded information and the post-transition state information corresponding to a combination of the encoding target information and the current state information stored in the first state storage circuit A first control circuit that outputs based on the encoding table and stores the post-transition state information in the first state storage circuit as the current state information;
An encoding circuit comprising:
A second state storage circuit for storing current state information in a plurality of transition states determined by a method for decoding the encoded information encoded by the specific encoding method;
Based on a method for decoding the encoded information encoded by the specific encoding method, a combination of any one of the plurality of transition states and the encoded information, and a post-transition A decryption information storage circuit that stores, as a decryption table, information that associates a combination of post-transition state information indicating a state with a combination of decryption information that is decrypted information;
Receiving the input of the encoded information, the decoded information and the post-transition state corresponding to a combination of the encoded information and the current state information stored in the second state storage circuit, A second control circuit that outputs based on the decoding table and stores the post-transition state information in the second state storage circuit as the current state information;
A decryption circuit comprising:
An encoding / decoding system comprising: An encoding circuit that performs encoding using a specific encoding method,
A state storage circuit for storing current state information in a plurality of transition states determined by a specific encoding method;
A combination of any one of the plurality of transition states, encoding target information that is information to be encoded, post-transition state information indicating a state after transition, and information after encoding An encoded information storage circuit that stores information associated with a combination with encoded information as an encoding table;
The input of the encoding target information is received, the encoding information and the post-transition state information corresponding to a combination of the encoding target information and the current state information stored in the state storage circuit, A control circuit that outputs based on the encoding table and stores the post-transition state information in the state storage circuit as the current state information;
An encoding circuit comprising: A decoding circuit for decoding encoded information encoded by a specific encoding method,
A state storage circuit for storing current state information in a plurality of transition states determined by a method for decoding the encoded information encoded by the specific encoding method;
Based on a method for decoding the encoded information encoded by the specific encoding method, a combination of any one of the plurality of transition states and the encoded information, and a post-transition A decryption information storage circuit that stores, as a decryption table, information associating post-transition state information indicating a state with a combination of decryption information that is decrypted information;
The decoding table that receives the input of the encoding information and corresponds to the combination of the encoding information and the current state information stored in the state storage circuit, includes the decoding table. And a control circuit for storing the post-transition state information in the state storage circuit as the current state information,
A decoding circuit comprising: The encoding circuit according to claim 2, wherein the transmission data is encoded by an encoding method defined by a predetermined communication method;
A high frequency that transmits the transmission data encoded by the encoding circuit to the wireless tag in a frequency band defined by the communication method, and receives reception data transmitted from the wireless tag correspondingly Circuit,
The decoding circuit according to claim 3, wherein the reception data received by the high-frequency circuit is decoded by a method corresponding to the encoding method;
A host interface for outputting the received data decoded by the decoding circuit;
A tag communication device comprising: Provided with a plurality of high frequency circuits capable of communication in a frequency band corresponding to each of a plurality of communication methods,
The encoding information storage circuit included in the encoding circuit stores a plurality of the encoding tables defined for each of a plurality of encoding methods defined by a plurality of the communication methods,
The decoding information storage circuit included in the decoding circuit stores a plurality of the decoding tables defined for each decoding scheme corresponding to the plurality of encoding schemes,
The encoding circuit is configured to perform encoding using the encoding table corresponding to the encoding method defined by the selected communication method by switching any one of the plurality of communication methods. The encoding table corresponding to the communication method, controlling to transmit transmission data and receive reception data using the high-frequency circuit capable of communicating in the frequency band defined by the communication method. The tag communication device according to claim 4, further comprising: a control unit that controls the encoding circuit so as to perform encoding using a signal.

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