JP2010068077A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To alleviate an efficiency decline in the electric power addition, when the battery voltage falls off or load mismatching occurs at an antenna. <P>SOLUTION: A transmission output Pout of an RF (Radio Frequency) power amplifying circuit 2 is supplied to an antenna through a principal line 31 of a directional coupler 3. A detection voltage of a sub line 32 of the directional coupler 3 is supplied to an input of an RF detection circuit 4. A power detection voltage Vdet of an output of the RF detection circuit 4 is supplied to an invert input (-) of an error amplifier 7. Bias voltages of a bias circuit 24 are supplied to transistors at each stage of an RF multi-stage amplifier. A transmission power level signal Vramp is supplied to a non-invert input (+) of the error amplifier 7. An automatic power control voltage Vapc of an output of the error amplifier 7 is supplied to an input of the bias circuit 24. Then, Vramp and Vdet are supplied to a first and a second input terminals (+) and (-) of control circuits 8 and 9, and the output is supplied to the non-invert input (+) of the amplifier 7. If Vdet becomes lower than Vramp, the output of control circuits 8 and 9 controls the error amplifier 7 to decrease Vapc. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an RF power amplifier and a method for operating the same, and is particularly useful for reducing a decrease in power added efficiency of the power amplifier when a battery voltage is lowered or when a load mismatch occurs at an antenna. Regarding technology.

  There are a plurality of communication methods in mobile communication represented by mobile phones. For example, in Europe, there is W-CDMA, which is a third generation wireless communication system that has recently started service, in addition to GSM and EDGE that have improved the data communication speed of GSM, which are widely used as the second generation wireless communication system. In North America, in addition to DCS and PCS, which are the second generation wireless communication systems, cdma1x, which is the third generation wireless communication system, has become widespread. GSM is an abbreviation for Global System for Mobile Communication. EDGE is an abbreviation for Enhanced Data rate for GSM Evolution. W-CDMA is an abbreviation for Wide-band Code Division Multiple Access. DCS is an abbreviation for Digital Cellar System. PCS is an abbreviation for Personal Communication System. cdma1x is an abbreviation for Code Division Multiple Access 1x.

  The operation of the high-frequency power amplifier of the cellular phone terminal is a saturation operation in the basic mode GSM that uses only phase modulation, and EDGE that uses amplitude modulation along with phase modulation is several dB from the saturation operation point of GSM. This is a linear operation at the operating point where the back-off is taken. In addition, in W-CDMA and cdma-1x that also use amplitude modulation in conjunction with phase modulation, the operation of the high-frequency power amplifier is a linear operation.

  An antenna switch is disposed between the high frequency power amplifier and the antenna in the high frequency circuit portion of the mobile phone terminal that supports GSM and EDGE. The antenna switch executes a function of switching between a TDMA (Time Division Multiple Access) transmission slot and a reception slot.

  On the other hand, another trend related to the configuration of a high-frequency circuit in a mobile phone terminal is the incorporation of an output power detection circuit in a high-frequency power amplifier module having a high-frequency power amplifier. For example, the following Non-Patent Document 1 describes whether a directional coupler for detecting power generated by a power amplifier is integrated in a power amplifier module together with the power amplifier. The main line of the directional coupler is connected between the output of the power amplifier and the antenna, and the sub line of the directional coupler is connected between the terminating resistor and the input of the power level control unit. The directional coupler can detect a detection voltage that is a vector sum of the combined voltage from the traveling wave signal generated by the power amplifier and the combined voltage from the reflected wave signal reflected by the load.

Jelena Madic et al, “Accurate Power Control Technique for Handset PA Modules with Integrated Directional Couplers”, 2003 IEEE RadioFrequency Inquiries. 715-718.

  By using a directional coupler integrated in a power amplifier module as described in Non-Patent Document 1, a combined voltage from a traveling wave signal generated by the power amplifier and a reflected wave reflected by a load The detection voltage of the vector sum with the coupling voltage from the signal can be detected. On the other hand, in order to precisely control the transmission output power of the power amplifier, the transmission output power level is detected, the detected power level signal is compared with the target power level signal, and the closed loop output power control is performed by the power control unit. There is a need. The directional coupler described in Non-Patent Document 1 can be employed for detection of the transmission output power level for power control.

  However, as a result of studies by the present inventors, when the battery voltage of the mobile phone terminal decreases or when load mismatch occurs at the antenna, the detected power level signal becomes lower than the target power level signal. It has been clarified that since the bias voltage of the power amplifier is controlled to be high, saturation of the output of the power amplifier starts faster than usual.

  If saturation of the output of the power amplifier is started faster than usual, the DC current of the power amplifier increases significantly, so that there is a problem that the power added efficiency (PAE) of the power amplifier is significantly reduced. It was said. On the other hand, it has also been clarified that the nonlinear distortion of the transistor is remarkably increased when the saturation of the output of the power amplifier is started faster than usual. In such a state, the power amplifier becomes a non-linear operation, and the output also becomes a saturated switching waveform. Therefore, the non-linear distortion is called a switching spectrum.

  The present invention has been made as a result of the study of the present inventors prior to the present invention as described above.

  Accordingly, an object of the present invention is to mitigate a decrease in power added efficiency of a power amplifier when a battery voltage decreases or when a load mismatch occurs at an antenna.

  Another object of the present invention is to reduce an increase in nonlinear distortion of a transistor when a battery voltage is lowered or when a load mismatch occurs in an antenna.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  A typical one of the inventions disclosed in the present application will be briefly described as follows.

  That is, a typical RF power amplifier of the present invention includes an RF power amplifier circuit (2), a directional coupler (3), an RF detector circuit (4), an error amplifier (7), and a control circuit (8, 9). It has.

  The RF power amplifier circuit (2) generates an RF transmission output signal (Pout) by amplification of the RF transmission input signal (Pin) and supplies it to the antenna through the main line (31) of the directional coupler (3). To do.

  The sub line (32) of the directional coupler (3) is connected to the input of the RF detection circuit (4), and the power detection voltage (Vdet) at the output of the RF detection circuit (4) is the error amplifier (7). ) To the inverting input terminal (−).

  The RF power amplifier circuit (2) includes a multistage amplifier (21, 22, 23) and a bias circuit (24), and the bias is applied to the control input electrode of the transistor in each stage of the multistage amplifier (21, 22, 23). A bias voltage generated from the output of the circuit (24) is supplied.

  A transmission power level signal (Vramp) is supplied to a non-inverting input terminal (+) of the error amplifier (7), and an automatic power control voltage (Vapc) output from the error amplifier (7) is supplied to the bias circuit (24). Supplied to the input.

  The transmission power level signal (Vramp) and the power detection voltage (Vdet) are respectively supplied to the first input terminal (+) and the second input terminal (−) of the control circuit (8, 9), and the control circuit The output of (8, 9) is supplied to the non-inverting input terminal (+) of the error amplifier (7).

  In response to the level of the power detection voltage (Vdet) being lower than the level of the transmission power level signal (Vramp), the output of the control circuit (8, 9) is the automatic power control voltage (Vapc). The error amplifier (7) is controlled so as to reduce the level of (see FIG. 1).

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. That is, it is possible to reduce a decrease in power added efficiency of the power amplifier when the battery voltage decreases or when load mismatch occurs at the antenna.

<Typical embodiment>
First, an outline of a typical embodiment of the invention disclosed in the present application will be described. The reference numerals of the drawings referred to with parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] An RF power amplifier according to a typical embodiment of the present invention includes an RF power amplifier circuit (2), a directional coupler (3), an RF detector circuit (4), an error amplifier (7), a control circuit ( 8, 9).

  The RF power amplifier circuit (2) generates an RF transmission output signal (Pout) by amplifying an RF transmission input signal (Pin) and transmits an antenna via the main line (31) of the directional coupler (3). To supply. The sub line (32) of the directional coupler (3) is connected to the input of the RF detection circuit (4), and the power detection voltage (Vdet) from the output of the RF detection circuit (4) is the error amplifier ( 7) is supplied to the inverting input terminal (−). The RF power amplifier circuit (2) includes a multistage amplifier (21, 22, 23) and a bias circuit (24), and the bias is applied to the control input electrode of the transistor in each stage of the multistage amplifier (21, 22, 23). A bias voltage generated from the output of the circuit (24) is supplied.

  A transmission power level signal (Vramp) is supplied to a non-inverting input terminal (+) of the error amplifier (7), and an automatic power control voltage (Vapc) generated from the output of the error amplifier (7) is supplied to the bias circuit ( 24) input.

  The transmission power level signal (Vramp) is supplied to the first input terminal (+) of the control circuit (8, 9), and the power detection voltage is supplied to the second input terminal (−) of the control circuit (8, 9). (Vdet) is supplied, and the output of the control circuit (8, 9) is supplied to the non-inverting input terminal (+) of the error amplifier (7).

  In response to the level of the power detection voltage (Vdet) being lower than the level of the transmission power level signal (Vramp), the output of the control circuit (8, 9) is the automatic power control voltage (Vapc). The error amplifier (7) is controlled so as to reduce the level of (see FIG. 1).

  According to the embodiment, the power detection voltage (Vdet) is compared with the target transmission power level signal (Vramp) when the battery voltage of the mobile phone terminal decreases or when load mismatch occurs at the antenna. The control circuit (8, 9) prevents the automatic power control voltage (Vapc) from increasing and the automatic power control voltage (Vapc) from increasing, thereby reducing the reduction in power added efficiency of the RF power amplifier.

  According to a preferred embodiment, the sub line (32) of the directional coupler (3) is connected between a terminating resistor (33) and the input of the RF detection circuit (4), and the direction A detection voltage of the sub line (32) of the sexual coupler (3) is supplied to an input terminal of the RF detection circuit (4).

  The control circuit (8, 9) includes a differential amplifier (8) for comparing the level of the transmission power level signal (Vramp) with the level of the power detection voltage (Vdet), and the differential amplifier (8). And an output control circuit (9) for controlling the voltage level of the non-inverting input terminal (+) of the error amplifier (7) in response to the output voltage of the error amplifier.

  An offset voltage (Voffset) set to a predetermined value is generated inside the output control circuit (9), and the output voltage (Pout_DiffAmp) of the differential amplifier (8) is more than the offset voltage (Voffset). When the level is exceeded, the output of the control circuit (8, 9) controls the error amplifier (7) so that the level of the automatic power control voltage (Vapc) decreases (FIG. 2). reference).

  In another preferred embodiment, the output control circuit (9) is a voltage / current converter that converts the output voltage of the differential amplifier (8) into an output current, and is more than the offset voltage (Voffset). When the level of the output voltage (Pout_DiffAmp) of the differential amplifier (8) exceeds, the voltage / current converter (9) starts to flow the output current (Iconv) (see FIG. 2).

  In still another preferred embodiment, the RF power amplifier includes a filter (6) including resistors (R3, R4) for converting the output current (Iconv) of the voltage / current converter (9) into a voltage. In addition.

  The non-inverting input terminal (+) of the error amplifier (7) is supplied with the transmission power level signal (Vramp) and the output voltage of the control circuit (8, 9) via the filter (6). The

  In a more preferred embodiment, the RF power amplifier further comprises an output matching circuit (10).

  The RF transmission output signal (Pout) is supplied to the antenna through the main line (31) of the directional coupler (3) and the output matching circuit (10).

  In an even more preferred embodiment, the RF power amplifier further comprises an input matching circuit (1).

  The RF transmission input signal (Pin) is supplied to the input terminal of the RF power amplifier circuit (2) via the input matching circuit (1).

  In a specific embodiment, the RF power amplifier further comprises a buffer amplifier (5).

  The transmission power level signal (Vramp) is supplied to the non-inverting input terminal (+) of the error amplifier (7) through the buffer amplifier (5).

  In a more specific embodiment, the RF power amplifier is configured to be mountable in a mobile phone terminal, and the multistage amplifiers (21, 22, 23) of the RF power amplifier circuit (2) and the bias circuit ( 24) is configured to be operable with a battery mounted on the mobile phone terminal.

  In an even more specific embodiment, the transistors at each stage of the multistage amplifiers (21, 22, 23) of the RF power amplifier circuit (2) are field effect transistors.

  In a most specific embodiment, the field effect transistor is an LD (Laterally Diffused) type MOS field effect transistor.

  [2] A typical embodiment of another aspect of the present invention includes an RF power amplifier circuit (2), a directional coupler (3), an RF detector circuit (4), an error amplifier (7), a control circuit ( 8 and 9) is a method of operating an RF power amplifier.

  The RF power amplifier circuit (2) generates an RF transmission output signal (Pout) by amplifying an RF transmission input signal (Pin) and transmits an antenna via the main line (31) of the directional coupler (3). To supply.

  The sub line (32) of the directional coupler (3) is connected to the input of the RF detection circuit (4), and the power detection voltage (Vdet) from the output of the RF detection circuit (4) is the error amplifier ( 7) is supplied to the inverting input terminal (−).

  The RF power amplifier circuit (2) includes a multistage amplifier (21, 22, 23) and a bias circuit (24), and the bias is applied to the control input electrode of the transistor in each stage of the multistage amplifier (21, 22, 23). A bias voltage generated from the output of the circuit (24) is supplied.

  A transmission power level signal (Vramp) is supplied to a non-inverting input terminal (+) of the error amplifier (7), and an automatic power control voltage (Vapc) generated from the output of the error amplifier (7) is supplied to the bias circuit ( 24) input.

  The transmission power level signal (Vramp) is supplied to the first input terminal (+) of the control circuit (8, 9), and the power detection voltage is supplied to the second input terminal (−) of the control circuit (8, 9). (Vdet) is supplied, and the output of the control circuit (8, 9) is supplied to the non-inverting input terminal (+) of the error amplifier (7).

  In response to the level of the power detection voltage (Vdet) being lower than the level of the transmission power level signal (Vramp), the output of the control circuit (8, 9) is the automatic power control voltage (Vapc). The error amplifier (7) is controlled so as to reduce the level of (see FIG. 1).

<< Description of Embodiment >>
Next, the embodiment will be described in more detail. In all the drawings for explaining the best mode for carrying out the invention, components having the same functions as those in the above-mentioned drawings are denoted by the same reference numerals, and repeated description thereof is omitted.

<< Configuration of RF power amplifier >>
FIG. 1 is a diagram showing a configuration of a radio frequency (RF) power amplifier according to an embodiment of the present invention.

  That is, the RF power amplifier shown in FIG. 1 includes an input matching circuit 1, an RF power amplifier circuit 2, a directional coupler 3, an RF detector circuit 4, a buffer amplifier 5, a ramp filter 6, an error amplifier 7, a differential amplifier 8, A voltage / current converter 9, an output matching circuit 10, a low-pass filter 11, and an antenna switch / antenna filter 12 are included.

  An RF transmission input signal Pin supplied by an RF analog signal processing semiconductor integrated circuit (RFIC) mounted on a cellular phone terminal is supplied to an input terminal of the input matching circuit 1, and an output signal of the input matching circuit 1 is an RF power amplifier circuit. 2 input terminals. The RF power amplifier circuit 2 includes a first stage amplifier 21, a next stage amplifier 22, a final stage amplifier 23, and a bias circuit 24. The output signal of the input matching circuit 1 is amplified by a multistage amplifier including the first stage amplifier 21, the next stage amplifier 22, and the final stage amplifier 23 of the RF power amplifier circuit 2, and the output signal of the RF power amplifier circuit 2 is directional coupler. 3 is supplied. The power supply voltage supplied to the collector or drain output electrode of each transistor of the first stage amplifier 21, the next stage amplifier 22, and the last stage amplifier 23 included in the RF power amplifier circuit 2 is supplied from a battery (not shown) of a mobile phone terminal. Supplied. A bias voltage supplied to the control input electrode of the base or gate of each transistor of the first stage amplifier 21, the next stage amplifier 22, and the last stage amplifier 23 included in the RF power amplifier circuit 2 is supplied from a bias circuit 24. Furthermore, the voltage level of the bias voltage generated from the bias circuit 24 is controlled by the level of the automatic power control voltage Vapc of the error amplifier 7.

  In the RF power amplifier shown in FIG. 1, each of the first-stage amplifier 21, the next-stage amplifier 22, and the final-stage amplifier 23 included in the RF power amplifier circuit 2 is an LD-type MOS field effect transistor having good high-frequency characteristics. It is configured. LD is an abbreviation for Laterally Diffused.

<< Operation of RF power amplifier >>
The RF power amplifier according to one embodiment of the present invention shown in FIG. 1 operates as follows.

  The output signal of the RF power amplifier circuit 2 is supplied to the directional coupler 3, and the directional coupler 3 is configured in the same manner as the directional coupler described in Non-Patent Document 1. That is, the main line 31 of the directional coupler 3 is connected between the output of the RF power amplifier circuit 2 and the output matching circuit 10, and the sub line 32 of the directional coupler 3 is connected to the termination resistor 33 and the RF detector circuit 4. Connected to the input. The directional coupler 3 can detect the detection voltage of the vector sum of the combined voltage from the traveling wave signal generated by the power amplifier and the combined voltage from the reflected wave signal reflected by the load. The detection voltage generated from the output of the directional coupler 3 is supplied to the input terminal of the RF detection circuit 4, so that the power detection voltage Vdet generated from the output terminal of the RF detection circuit 4 has an error through the resistor R1. It is supplied to the inverting input terminal − of the amplifier 7. The output signal of the RF power amplifier circuit 2 supplied via the main line 31 of the directional coupler 3 is passed through the output matching circuit 10, the low pass filter 11, and the antenna switch / antenna filter 12 as an RF transmission output signal Pout. It is supplied to the antenna (not shown) of the mobile phone terminal.

  A transmission power level signal Vramp is supplied to the non-inverting input terminal + of the buffer amplifier 5 from a baseband signal processing LSI (baseband LSI) mounted on the mobile phone terminal, and a buffer is supplied to the non-inverting input terminal − of the buffer amplifier 5. An output signal of the amplifier 5 is supplied. The output signal of the buffer amplifier 5 is supplied to the non-inverting input terminal + of the error amplifier 7 through the noise reducing ramp filter 6. The noise reducing ramp filter 6 includes two capacitors C2, C3 and three resistors R3, R4, R5. A resistor R2 and a phase compensation capacitor C1 are connected in parallel between the inverting input terminal − and the output terminal of the error amplifier 7.

  The automatic power control voltage Vapc (APC control voltage) of the error amplifier 7 is supplied to the bias circuit 24 of the RF power amplifier circuit 2, and the bias voltage generated from the bias circuit 24 is the first stage amplifier 21 and the next stage of the RF power amplifier circuit 2. The signal is supplied to the control input electrode of the base or gate of each transistor of the amplifier 22 and the final stage amplifier 23. The amplification gains of the first stage amplifier 21, the next stage amplifier 22 and the final stage amplifier 23 of the RF power amplifier circuit 2 are controlled by a bias voltage generated from the bias circuit 24, and this bias voltage is an automatic power control voltage Vapc of the error amplifier 7. Controlled by. The transmission power level signal Vramp supplied from the baseband LSI to the non-inverting input terminal + of the error amplifier 7 through the RFIC, the buffer amplifier 5 and the ramp filter 6 is carried according to the distance between the base station and the mobile phone terminal. It is a signal which shows the level of RF transmission signal transmitted from the power amplifier of a telephone terminal. The closed loop of the buffer amplifier 5, the lamp filter 6, the error amplifier 7, the RF power amplifier circuit 2, the directional coupler 3, and the RF detector circuit 4 of the cellular phone terminal is such that the power detection voltage Vdet matches the transmission power level signal Vramp. The level of the APC control bias voltage Vapc is controlled. Thereby, the level of the RF transmission signal Pout transmitted from the RF power amplifier can be controlled by the transmission power level signal Vramp.

<Saturation prevention circuit>
In order to prevent saturation of the output of the RF power amplifier when the battery voltage of the mobile phone terminal is lowered or when a load mismatch occurs at the antenna according to the embodiment of the present invention, / Current converter 9 is arranged in particular in the RF power amplifier.

  In general, during the normal RF power amplifier operation period, the buffer amplifier 5 described above is set so that the level of the power detection voltage Vdet as the detection power level signal matches the level of the transmission power level signal Vramp as the target power level signal. The level of the APC control bias voltage Vapc is controlled to an appropriate value by the closed loop of the ramp filter 6, the error amplifier 7, the RF power amplifier circuit 2, the directional coupler 3, and the RF detection circuit 4.

  However, as explained at the beginning, when the battery voltage of the mobile phone terminal decreases or when load mismatch occurs at the antenna, the above-described closed loop does not function and is compared with the transmission power level signal Vramp. The inventors have clarified that the power detection voltage Vdet is lowered, the APC control bias voltage Vapc of the bias voltage of the RF power amplifier circuit 2 is controlled to be extremely high, and the output of the RF power amplifier is saturated. It was.

  In order to prevent such output saturation, the differential amplifier 8 and the voltage / current converter 9 are used in particular. That is, the offset voltage Voffset corresponding to the saturation start power level signal is included in the voltage / current converter 9. When the level of the output voltage of the differential amplifier 8 exceeds the level of the offset voltage Voffset of the voltage / current converter 9, the output conversion current Iconv begins to flow through the output of the voltage / current converter 9. When the output conversion current Iconv begins to flow through the output of the voltage / current converter 9, a voltage drop occurs in the resistors R3 and R4 of the ramp filter 6, so that the voltage at the non-inverting input terminal + of the error amplifier 7 is lowered.

  Therefore, when the battery voltage of the mobile phone terminal is lowered or when a load mismatch occurs in the antenna, the differential amplifier is determined from the level of the offset voltage Voffset of the voltage / current converter 9 corresponding to the saturation start power level signal. The level of the output voltage 8 becomes higher, and the conversion current Iconv begins to flow to the output of the voltage / current converter 9, causing a voltage drop in the resistors R 3 and R 4 of the ramp filter 6. As a result, the voltage at the non-inverting input terminal + of the error amplifier 7 is lowered, so that the level of the APC control bias voltage Vapc from the output of the error amplifier 7 is lowered, thereby reducing the saturation of the output of the RF power amplifier circuit 2. can do.

  FIG. 2 is a diagram showing the configuration of the differential amplifier 8 and the voltage / current converter 9 arranged in the RF power amplifier shown in FIG.

  As shown in FIG. 2, the differential amplifier 8 includes a differential amplifier 81 and resistors R11, R12, R13, and R14. The power detection voltage Vdet is supplied to the inverting input terminal − of the differential amplifier 81 through the resistor R11, and the transmission power level signal Vramp is divided by the voltage dividing resistors R12 and R14 and generated by the voltage dividing resistors R12 and R14. The divided voltage is supplied to the non-inverting input terminal + of the differential amplifier 81. The output of the differential amplifier 81 as the output of the differential amplifier 8 is supplied to the inverting input terminal − of the differential amplifier 81 through the resistor R 13 and also to the input terminal of the voltage / current converter 9.

  The voltage / current converter 9 includes N channel MOS transistors Qn1, Qn2, Qn3, Qn4, P channel MOS transistors Qp1, Qp2, Qp3, Qp4, Qp5, Qp6, constant current sources I0, I1, I2, and a resistor R15. , R16 and a phase compensation capacitor C4. P channel MOS transistor Qp1 and constant current source I1 constitute a source follower, while constant current source I2, P channel MOS transistor Qp2 and resistor R15 constitute a source follower including offset voltage Voffset. This offset voltage Voffset is set by a constant current source I2 and a resistor R15. The sources of the N-channel MOS transistors Qn1 and Qn2 are connected to the ground voltage GND through the constant current source I0, and the drains of the N-channel MOS transistors Qn1 and Qn2 are the P-channel MOS transistors Qp2 and Qp3 that constitute the current mirror of the active load. Connected to the drain.

  An output voltage of the differential N-channel MOS transistors Qn1 and Qn2 is generated from a common connection node between the drain of the N-channel MOS transistor Qn1 and the drain of the P-channel MOS transistor Qp2 of the voltage / current converter 9, and the voltage / current conversion transistor Are supplied to the gate input electrodes of P-channel MOS transistors Qp5 and Qp6. P-channel MOS transistors Qp5 and Qp6 functioning as voltage / current conversion transistors flow the conversion current Iout in response to the output voltages of the differential N-channel MOS transistors Qn1 and Qn2. The voltage drop due to the conversion current Iout at the resistor R16 is supplied to the gate input electrode of the N-channel MOS transistor Qn2 via the source follower including the constant voltage source I2, the P-channel MOS transistor Qp2 and the resistor R15 and including the offset voltage Voffset. Is done.

  If the output voltage of the differential amplifier 8 is Pout_DiffAmp and the source-gate voltage of the P-channel MOS transistor Qp1 is Vsg p1, the voltage Vgn1 of the gate input electrode of the N-channel MOS transistor Qn1 is given by the following equation.

Vgn1 = Pout_DiffAmp + Vsg p1 (1 formula)
On the other hand, if the source-gate voltage of the P channel MOS transistor Qp2 is Vsg p2, the voltage Vgn2 of the gate input electrode of the N channel MOS transistor Qn2 is given by the following equation.

Vgn2 = R16 · Iout + Voffset + Vsg p2 (2 formulas)
Since the P channel MOS transistor Qp5, the resistor R16, the constant current source I2, the P channel MOS transistor Qp2 and the resistor R15 constitute a 100% negative feedback circuit with the source follower including the offset voltage Voffset, this 100% negative feedback. Depending on the function of the circuit, the levels of the gate input voltages Vgn1 and Vgn2 of the differential N-channel MOS transistors Qn1 and Qn2 match. Since the source-gate voltage Vsg p1 of the P-channel MOS transistor Qp1 and the source-gate voltage Vsg p2 of the P-channel MOS transistor Qp2 are equal to each other, from the above (1) and (2), The following equation is given:

Pout_DiffAmp + Vsg p1 = R16 · Iout + Voffset + Vsg p2
Iout = (Pout_DiffAmp−Voffset) / R16 (3 formulas)
As understood from this (Equation 3), when the level of the output voltage Pout_DiffAmp of the differential amplifier 8 exceeds the level of the offset voltage Voffset of the voltage / current converter 9, the P-channel MOS functioning as a voltage / current conversion transistor. Conversion current Iout begins to flow through transistors Qp5 and Qp6. The conversion current Iout of the P-channel MOS transistor Qp6 is converted into an output conversion current Iconv by N-channel MOS transistors Qn3 and Qn4 that function as output current mirrors of the voltage / current converter 9. Assuming that the effective element area of the N-channel MOS transistors Qn3 and Qn4 functioning as output current mirrors is N: M, the output conversion current Iconv is given by the following equation.

Iconv = M · Iout / N (4 formulas)
<< Saturation prevention characteristics >>
FIG. 3 is a diagram showing a characteristic of the transmission power level signal Vramp versus the transmission power Pout, which is one of the effects of preventing saturation by the differential amplifier 8 and the voltage / current converter 9 arranged in the RF power amplifier shown in FIG. It is.

  In FIG. 3, a broken line L1 is a characteristic of a general RF power amplifier in which the differential amplifier 8 and the voltage / current converter 9 are not arranged. When the transmission power level signal Vramp becomes approximately 2.3 volts, the transmission power Pout Can be understood to be saturated at about 33.5 dBm.

  In FIG. 3, a solid line L2 is a characteristic of the RF power amplifier according to the embodiment of the present invention of FIG. 1 in which the differential amplifier 8 and the voltage / current converter 9 are arranged, and the transmission power level signal Vramp is approximately 2. It can be understood that even when the voltage is 3 volts, the transmission power Pout increases slightly without being saturated at about 33.4 dBm.

  FIG. 4 is a diagram showing a characteristic of transmission power Pout versus power efficiency, which is one of the effects of preventing saturation by the differential amplifier 8 and the voltage / current converter 9 arranged in the RF power amplifier shown in FIG.

  In FIG. 4, a broken line L1 is a characteristic of a general RF power amplifier in which the differential amplifier 8 and the voltage / current converter 9 are not arranged. When the transmission power Pout is about 33.45 dBm, the power efficiency is about It can be seen that it drops to 35.3%.

  In FIG. 4, a solid line L2 is a characteristic of the RF power amplifier according to the embodiment of the present invention of FIG. 1 in which the differential amplifier 8 and the voltage / current converter 9 are arranged, and the transmission power Pout is about 33. It can be seen that even at 38 dBm, the power efficiency is only reduced to approximately 35.9%.

  FIG. 5 is a diagram showing a characteristic of the transmission power level signal Vramp versus the bias voltage Vgs3 which is one of the effects of preventing saturation by the differential amplifier 8 and the voltage / current converter 9 arranged in the RF power amplifier shown in FIG. It is.

  The bias voltage Vgs3 on the vertical axis in FIG. 5 is a bias circuit between the gate and source of the LD type MOS field effect transistor included in the final stage amplifier 23 of the RF power amplifier circuit 2 of the RF power amplifier shown in FIG. 24 is a value of the bias voltage supplied from 24.

  In FIG. 5, the broken line L1 is a characteristic of a general RF power amplifier in which the differential amplifier 8 and the voltage / current converter 9 are not arranged. When the transmission power level signal Vramp is approximately 2.4 volts, the bias voltage Vgs3 It can be seen that increases to around 1.4 volts.

  In FIG. 5, a solid line L2 is a characteristic of the RF power amplifier according to the embodiment of the present invention of FIG. 1 in which the differential amplifier 8 and the voltage / current converter 9 are arranged, and the transmission power level signal Vramp is approximately 2. It can be understood that even when the voltage is 4 volts, the bias voltage Vgs3 increases only to about 1.35 volts.

  FIG. 6 is a diagram showing a switching spectrum versus frequency characteristic which is one of the effects of preventing saturation by the differential amplifier 8 and the voltage / current converter 9 arranged in the RF power amplifier shown in FIG.

  Characteristics (A), characteristics (B), and characteristics (C) on the left side of FIG. 6 are general RF power amplifiers in which the differential amplifier 8 and the voltage / current converter 9 are not disposed, and the power supply voltage Vdd is 4.7. It is a characteristic when changing to bolt, 3.5 volts, and 3.1 volts, respectively. Further, the characteristics (D), characteristics (E), and characteristics (F) on the right side of FIG. 6 indicate the RF according to the embodiment of the present invention of FIG. 1 in which the differential amplifier 8 and the voltage / current converter 9 are arranged. This is a characteristic when the power supply voltage Vdd is changed to 4.7 volts, 3.5 volts, and 3.1 volts in the power amplifier.

  According to the GMSK standard for mobile phones, the value of the switching spectrum, which is nonlinear distortion at a frequency away from the center frequency by ± 0.4 MHz, is defined as −10 dBm or less.

  In a general RF power amplifier in which the differential amplifier 8 and the voltage / current converter 9 are not arranged, when the power supply voltage Vdd is reduced to 3.1 volts, it is a non-linear distortion at a frequency +0.4 MHz away from the center frequency. It can be understood from the characteristic (C) on the left side of FIG. 6 that the value of the switching spectrum is −10 dBm or more and the GMSK standard cannot be satisfied.

  On the other hand, in the RF power amplifier according to the embodiment of the present invention of FIG. 1 in which the differential amplifier 8 and the voltage / current converter 9 are arranged, even if the power supply voltage Vdd is reduced to 3.1 volts, the center It can be understood from the characteristic (F) on the right side of FIG. 6 that the value of the switching spectrum, which is nonlinear distortion at a frequency +0.4 MHz away from the frequency, is −10 dBm or less and satisfies the GMSK standard. It should be noted that the center frequency is 1. for the characteristics (A), characteristics (B), and characteristics (C) on the left side of FIG. 6 and the characteristics (D), characteristics (E), and characteristics (F) on the right side of FIG. The frequency is set to 9 GHz.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the present invention is an RF power amplifier shown in FIG. 1 in which the transistors of the first stage amplifier 21, the next stage amplifier 22 and the last stage amplifier 23 included in the RF power amplifier circuit 2 are limited to LD type MOS field effect transistors. Instead, for example, the transistor of the final stage amplifier 23 can be replaced with a heterojunction bipolar transistor (HBT).

  Further, the RF power amplifier of the present invention is applied to a multimode RF power amplifier mounted on a multimode mobile phone terminal that supports each of the GSM800, GSM850, DCS1800, PCS1900, and WCDMA2100 systems in the GSM / EDGE system. be able to.

FIG. 1 is a diagram showing a configuration of an RF power amplifier according to an embodiment of the present invention. FIG. 2 is a diagram showing a configuration of an attenuator and a differential amplifier arranged in the RF power amplifier shown in FIG. FIG. 3 is a diagram showing a transmission power level signal versus transmission power characteristic which is one of the effects of saturation prevention by the attenuator and the differential amplifier arranged in the RF power amplifier shown in FIG. FIG. 4 is a diagram showing a characteristic of transmission power versus power efficiency, which is one of the effects of saturation prevention by the attenuator and the differential amplifier arranged in the RF power amplifier shown in FIG. FIG. 5 is a diagram showing the characteristics of the transmission power level signal versus the bias voltage, which is one of the effects of preventing saturation by the differential amplifier 8 and the voltage / current converter 9 arranged in the RF power amplifier shown in FIG. . FIG. 6 is a diagram showing a switching spectrum versus frequency characteristic which is one of the effects of saturation prevention by the attenuator and the differential amplifier arranged in the RF power amplifier shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Input matching circuit 2 RF power amplifier circuit 3 Directional coupler 4 RF detection circuit 5 Buffer amplifier 6 Ramp filter 7 Error amplifier 8 Differential amplifier 9 Voltage / current converter 10 Output matching circuit 11 Low pass filter 12 Antenna switch antenna filter

Claims (20)

RF power amplifier circuit, directional coupler, RF detector circuit, error amplifier, control circuit,
The RF power amplifier circuit generates an RF transmission output signal by amplifying an RF transmission input signal and supplies the RF transmission output signal to the antenna through the main line of the directional coupler.
The sub line of the directional coupler is connected to the input of the RF detection circuit, and the power detection voltage from the output of the RF detection circuit is supplied to the inverting input terminal of the error amplifier,
The RF power amplifier circuit includes a multistage amplifier and a bias circuit, and a bias voltage generated from an output of the bias circuit is supplied to a control input electrode of a transistor of each stage of the multistage amplifier.
A non-inverting input terminal transmission power level signal of the error amplifier is supplied, and an automatic power control voltage generated from the output of the error amplifier is supplied to the input of the bias circuit,
The transmission power level signal is supplied to the first input terminal of the control circuit, the power detection voltage is supplied to the second input terminal of the control circuit, and the output of the control circuit is the non-inverting input terminal of the error amplifier. Supplied to
In response to the level of the power detection voltage being lower than the level of the transmission power level signal, the output of the control circuit controls the error amplifier so that the level of the automatic power control voltage decreases. RF power amplifier that is The sub line of the directional coupler is connected between a terminating resistor and the input of the RF detection circuit, and a detection voltage of the sub line of the directional coupler is supplied to an input terminal of the RF detection circuit. ,
The control circuit includes a differential amplifier that compares the level of the transmission power level signal and the level of the power detection voltage, and a non-inverting input terminal of the error amplifier in response to an output voltage of the differential amplifier. An output control circuit for controlling the voltage level,
When an offset voltage set to a predetermined value is generated inside the output control circuit and the level of the output voltage of the differential amplifier exceeds the offset voltage, the output of the control circuit is: The RF power amplifier according to claim 1, wherein the error amplifier is controlled so that a level of the automatic power control voltage is lowered.   The output control circuit is a voltage / current converter that converts the output voltage of the differential amplifier into an output current, and when the level of the output voltage of the differential amplifier exceeds the offset voltage, the output control circuit The RF power amplifier according to claim 2, wherein the voltage / current converter starts to flow current. The RF power amplifier further comprises a filter including a resistor that converts the output current of the voltage / current converter into a voltage;
The RF power amplifier according to claim 3, wherein the transmission power level signal and the output voltage of the control circuit are supplied to the non-inverting input terminal of the error amplifier via the filter. The RF power amplifier further comprises an output matching circuit,
The RF power amplifier according to claim 3, wherein the RF transmission output signal is supplied to the antenna via the main line of the directional coupler and the output matching circuit. The RF power amplifier further comprises an input matching circuit,
6. The RF power amplifier according to claim 5, wherein the RF transmission input signal is supplied to an input terminal of the RF power amplifier circuit via the input matching circuit. The RF power amplifier further comprises a buffer amplifier,
The RF power amplifier according to claim 6, wherein the transmission power level signal is supplied to the non-inverting input terminal of the error amplifier via the buffer amplifier.   The RF power amplifier is configured to be mountable on a mobile phone terminal, and the multistage amplifier and the bias circuit of the RF power amplifier circuit are configured to be operable with a battery mounted on the mobile phone terminal. Item 8. The RF power amplifier according to Item 7.   The RF power amplifier according to claim 8, wherein the transistors in the respective stages of the multistage amplifier of the RF power amplifier circuit are field effect transistors.   The RF power amplifier according to claim 9, wherein the field effect transistor is an LD type MOS field effect transistor. An RF power amplifier operating method comprising an RF power amplifier circuit, a directional coupler, an RF detector circuit, an error amplifier, and a control circuit,
The RF power amplifier circuit generates an RF transmission output signal by amplifying an RF transmission input signal and supplies the RF transmission output signal to the antenna through the main line of the directional coupler,
The sub line of the directional coupler is connected to the input of the RF detection circuit, and the power detection voltage from the output of the RF detection circuit is supplied to the inverting input terminal of the error amplifier,
The RF power amplifier circuit includes a multistage amplifier and a bias circuit, and a bias voltage generated from an output of the bias circuit is supplied to a control input electrode of a transistor of each stage of the multistage amplifier.
A non-inverting input terminal transmission power level signal of the error amplifier (7) is supplied, and an automatic power control voltage generated from the output of the error amplifier is supplied to the input of the bias circuit,
The transmission power level signal is supplied to the first input terminal of the control circuit, the power detection voltage is supplied to the second input terminal of the control circuit, and the output of the control circuit is the non-inverting input terminal of the error amplifier. Supplied to
In response to the level of the power detection voltage being lower than the level of the transmission power level signal, the output of the control circuit controls the error amplifier so that the level of the automatic power control voltage decreases. A method of operating an RF power amplifier. The sub line of the directional coupler is connected between a terminating resistor and the input of the RF detection circuit, and a detection voltage of the sub line of the directional coupler is supplied to an input terminal of the RF detection circuit. ,
The control circuit includes a differential amplifier that compares the level of the transmission power level signal and the level of the power detection voltage, and a non-inverting input terminal of the error amplifier in response to an output voltage of the differential amplifier. An output control circuit for controlling the voltage level,
When an offset voltage set to a predetermined value is generated inside the output control circuit and the level of the output voltage of the differential amplifier exceeds the offset voltage, the output of the control circuit is: 12. The method of operating an RF power amplifier according to claim 11, wherein the error amplifier is controlled so that the level of the automatic power control voltage is lowered.   The output control circuit is a voltage / current converter that converts the output voltage of the differential amplifier into an output current, and when the level of the output voltage of the differential amplifier exceeds the offset voltage, the output control circuit The method of operating an RF power amplifier according to claim 12, wherein the voltage / current converter starts to flow current. The RF power amplifier further comprises a filter including a resistor that converts the output current of the voltage / current converter into a voltage;
14. The method of operating an RF power amplifier according to claim 13, wherein the transmission power level signal and the output voltage of the control circuit are supplied to the non-inverting input terminal of the error amplifier via the filter. The RF power amplifier further comprises an output matching circuit,
14. The F power amplifier according to claim 13, wherein the RF transmission output signal is supplied to the antenna via the main line of the directional coupler and the output matching circuit. The RF power amplifier further comprises an input matching circuit,
The method of operating an RF power amplifier according to claim 15, wherein the RF transmission input signal is supplied to an input terminal of the RF power amplifier circuit via the input matching circuit. The RF power amplifier further comprises a buffer amplifier,
17. The method of operating an RF power amplifier according to claim 16, wherein the transmission power level signal is supplied to the non-inverting input terminal of the error amplifier via the buffer amplifier.   The RF power amplifier is configured to be mountable on a mobile phone terminal, and the multistage amplifier and the bias circuit of the RF power amplifier circuit are configured to be operable with a battery mounted on the mobile phone terminal. Item 18. A method of operating an RF power amplifier according to Item 17.   19. The method of operating an RF power amplifier according to claim 18, wherein the transistors at each stage of the multi-stage amplifier of the RF power amplifier circuit are field effect transistors.   20. The method of operating an RF power amplifier according to claim 19, wherein the field effect transistor is an LD type MOS field effect transistor.

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