JP2010068034A - Delta sigma modulating circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a delta sigma modulating circuit that is reducible in current consumption and chip area. <P>SOLUTION: The digital sigma modulating circuit includes an integrator which outputs an integrated signal generated by integrating an input signal, a plurality of resistances connected in series and generating voltages of a plurality of levels, a dither signal selecting circuit which outputs a voltage of at least one level among the voltages of the plurality of levels as a dither signal based upon a selection signal for selecting the level of the dither signal, and a quantizer which performs quantization based upon the integrated signal and dither signal. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a delta-sigma modulation circuit.

A delta-sigma modulation circuit is generally known as a circuit used for an AD converter. In a delta-sigma modulation circuit, a dither signal is often used to remove idle tones that occur in the signal band when there is no signal. The digital sigma modulation circuit used in the AD converter has an analog circuit configuration, and the dither signal inserted into the delta sigma modulation circuit needs to have an analog value. Such a dither signal can be generated, for example, by converting a pseudo random signal of several bits generated by a digital circuit into an analog signal. As a circuit for generating an analog signal having a level corresponding to a pseudo-random signal, for example, a sample hold DA converter using an operational amplifier in an output stage is known (Patent Document 1).
JP 2007-81567 A

  However, when a sample-and-hold DA converter using an operational amplifier is used in the output stage, current consumption may increase in order to improve the response characteristic of the operational amplifier, particularly when operating at a high frequency. The chip area is also increasing.

  The present invention has been made in view of the above problems, and an object thereof is to provide a delta-sigma modulation circuit capable of reducing current consumption and chip area.

  In order to achieve the above object, a delta-sigma modulation circuit according to the present invention includes an integrator that outputs an integrated signal obtained by integrating an input signal, a plurality of resistors that are connected in series and generate a voltage of a plurality of levels, and a dither signal. Based on a selection signal for selecting a level, a dither signal selection circuit that outputs at least one of the plurality of levels of voltage as the dither signal, and based on the integration signal and the dither signal And a quantizer for performing quantization.

  A delta-sigma modulation circuit capable of reducing current consumption can be provided.

  FIG. 1 is a diagram showing an overall configuration of a delta-sigma modulation circuit according to an embodiment of the present invention. The delta sigma modulation circuit 10 includes an integrator 11, a dither circuit 12, a quantizer 13, and a dither clock generation circuit 14. The integrator 11 outputs an integrated signal obtained by integrating the input signal. The dither circuit 12 generates and outputs a dither signal according to the dither clock DCLK. Based on the clock signal CLK, the quantizer 13 adds the dither signal output from the dither circuit 12 to the integrated signal output from the integrator 11, performs quantization, and outputs the output signal of the delta-sigma modulation circuit 10. Output as. The dither clock generation circuit 14 generates a dither clock DCLK based on the quantized signal indicating the quantization result in the quantizer 13.

  FIG. 2 is a diagram illustrating a configuration example of the quantizer 13. As shown in the figure, in this embodiment, the output of the integrator 11 is the differential outputs VP and VN, and the output of the dither circuit 12 is also the differential outputs VDP and VDN. The quantizer 13 is configured to receive these differential input signals and output differential outputs VOP and VON.

  The quantizer 13 includes a comparator 31 and a latch circuit 32. The comparator 31 receives the differential outputs VP and VN from the integrator 11 and the differential outputs VDP and VDN from the dither circuit 12. Then, the comparator 31 compares the signal obtained by adding the dither signal VDP to the integration signal VP and the signal obtained by adding the dither signal VDN to the integration signal VN while the clock signal CLK is at one logic value (for example, L level). Then, a signal indicating the comparison result is differentially output. The differential output from the comparator 31 is latched by the latch circuit 32 and output as the differential outputs VOP and VON of the quantizer 13. The latch circuit 32 outputs differential quantized signals VD1 and VD2 indicating the quantization result.

  FIG. 3 is a diagram illustrating a configuration example of the comparator 31. The comparator 31 includes P-channel MOSFETs 41 to 43 and N-channel MOSFETs 44 to 53. In the P-channel MOSFET 41, the power supply voltage VDD is applied to the source, and the clock signal CLK is input to the gate. The sources of the P channel MOSFETs 42 and 43 are connected to the drain of the P channel MOSFET 41.

  The N-channel MOSFET 45 has a drain connected to the drain of the P-channel MOSFET 42 and a source grounded. The N-channel MOSFET 46 has a drain connected to the drain of the P-channel MOSFET 43 and a source grounded. The voltage at the connection point between the P-channel MOSFET 42 and the N-channel MOSFET 45 is applied to the gates of the P-channel MOSFET 43 and the N-channel MOSFET 46. The voltage at the connection point between the P-channel MOSFET 43 and the N-channel MOSFET 46 is applied to the gates of the P-channel MOSFET 42 and the N-channel MOSFET 45.

  The N-channel MOSFET 44 has a drain connected to a connection point between the P-channel MOSFET 42 and the N-channel MOSFET 45, a source grounded, and a clock signal CLK input to the gate. The N-channel MOSFET 47 has a drain connected to a connection point between the P-channel MOSFET 43 and the N-channel MOSFET 46, a source grounded, and a clock signal CLK input to the gate.

  The N-channel MOSFET 48 has a drain connected to a connection point between the P-channel MOSFET 42 and the N-channel MOSFET 45, and an integration signal VP input to the gate. The N-channel MOSFET 49 is connected in parallel with the N-channel MOSFET 48, and the dither signal VDP is input to the gate. The drain of the N-channel MOSFET 50 is connected to the connection point between the P-channel MOSFET 43 and the N-channel MOSFET 46, and the integration signal VN is input to the gate. The N-channel MOSFET 51 is connected in parallel with the N-channel MOSFET 50, and the dither signal VDN is input to the gate.

  The N channel MOSFET 52 has a drain connected to the source of the N channel MOSFET 48, a source grounded, and a gate connected to the drain of the N channel MOSFET 50. The N-channel MOSFET 53 has a drain connected to the source of the N-channel MOSFET 50, a source grounded, and a gate connected to the drain of the N-channel MOSFET 48.

  The voltage at the connection point between the P-channel MOSFET 42 and the N-channel MOSFET 45 is an output signal VCN that is one of the differential outputs of the comparator 31, and the voltage at the connection point between the P-channel MOSFET 43 and the N-channel MOSFET 46 is The output signal VCP is the other differential output of the comparator 31.

  In such a comparator 31, when the clock signal CLK is at the H level, the N-channel MOSFETs 44 and 47 are turned on, and the output signals VCN and VCP are at the L level.

  On the other hand, when the clock signal CLK is at the L level, the N-channel MOSFETs 44 and 47 are turned off and the P-channel MOSFET 41 serving as a current source is turned on. Then, the output signals VCN and VCP are changed by the operation of the differential circuit constituted by the N-channel MOSFETs 48 to 51.

  That is, when the signal obtained by adding the dither signal VDP to the integration signal VP is larger than the signal obtained by adding the dither signal VDN to the integration signal VN, the N-channel MOSFETs 48 and 49 are turned on and the N-channel MOSFETs 50 and 51 are turned off. Then, the output signal VCN becomes L level and the output signal VCP becomes H level. Conversely, when the signal obtained by adding the dither signal VDP to the integration signal VP is smaller than the signal obtained by adding the dither signal VDN to the integration signal VN, the N-channel MOSFETs 48 and 49 are turned off and the N-channel MOSFETs 50 and 51 are turned on. Then, the output signal VCN becomes H level and the output signal VCP becomes L level.

  FIG. 4 is a diagram illustrating a configuration example of the latch circuit 32 and the dither clock generation circuit 14. The latch circuit 32 includes inverter circuits 61 and 62 and NAND circuits 63 and 64. One output signal VCP from the comparator 31 is input to the NAND circuit 63 via the inverter circuit 61. The other output signal VCN from the comparator 31 is input to the NAND circuit 64 via the inverter circuit 62. The output of the NAND circuit 63 is input to the NAND circuit 64, the output of the NAND circuit 64 is input to the NAND circuit 63, and the output of the NAND circuit 63 is the output signal VOP of the quantizer 13 and the NAND circuit 64. Is the other output signal VON of the quantizer 13. The outputs from the inverter circuits 61 and 62 are input to the EXOR circuit 66 constituting the dither clock generation circuit 14 as differential quantized signals VD1 and VD2.

  In such a latch circuit 32, when the integration signals VCN and VCP are at the L level, the output signals VOP and VON are not changed and the previous state is maintained. When the integration signal VCP is H level and the integration signal VCN is L level, the output signal VOP is H level and the output signal VON is L level. When the integration signal VCP is L level and the integration signal VCN is H level, the output signal VOP is L level and the output signal VON is H level. Further, the dither clock DCLK output from the dither clock generation circuit 14 is L level when the logic levels of the quantized signals VD1 and VD2 are the same, and is H level when they are different.

  FIG. 5 is a diagram illustrating a configuration example of the dither circuit 12. The dither circuit 12 includes a pseudo random signal generation circuit 70, a decoder 72, and a dither signal output circuit 74. The pseudo random signal generation circuit 70 generates and outputs pseudo random signals TPDF1 to TPDF3 having, for example, a 3-bit triangular distribution every time the dither clock DCLK changes from, for example, an L level to an H level. The decoder 72 decodes the pseudo random signals TPDF1 to TPDF3 and outputs decoded selection signals CODE1 to CODE5 and CODE1B to CODE5B. The decoder 72 sets only one of the selection signals CODE1 to CODE5 to the H level based on the pseudo random signals TPDF1 to TPDF3. The selection signals CODE1B to CODE5B are signals obtained by inverting the selection signals CODE1 to CODE5. The dither signal output circuit 74 receives selection signals CODE1 to CODE5, CODE1B to CODE5B, and adjustment signals SEL1 to SEL3. The dither signal output circuit 74 outputs dither signals VDP and VDN having levels corresponding to the selection signals CODE1 to CODE5 and CODE1B to CODE5B. The dither signal output circuit 74 adjusts the maximum level of the dither signals VDP and VDN based on the adjustment signals SEL1 to SEL3.

  FIG. 6 is a diagram illustrating a configuration example of the dither signal output circuit 74. The dither signal output circuit 74 includes resistors R1 to R4, RA1 to RA3, RB1 to RB3, transfer gates TP1 to TP5, TN1 to TN5 (dither signal selection circuit), P channel MOSFETs 80 to 82, inverter circuits 84 to 86, and N The channel MOSFETs 88 to 90 are included.

  The resistors R1 to R4 are connected in series, and generate a plurality of levels of voltages V1 to V5 obtained by dividing the voltage applied to both ends. The transfer gates TP1 to TP5 are turned on when the selection signals CODE1 to CODE5 are at the H level, respectively. Similarly, the transfer gates TN1 to TN5 are turned on when the selection signals CODE1 to CODE5 are at the H level, respectively. Therefore, for example, when only the selection signal CODE1 among the selection signals CODE1 to CODE5 is at the H level, the transfer gates TP1 and TN1 are turned on, the transfer gates TP2 to TP5 and TN2 to TN5 are turned off, and the voltage V1 is set as the dither signal VDP. The voltage V5 is output as the dither signal VDN. For example, when only the selection signal CODE2 is at the H level, the transfer gates TP2 and TN2 are turned on, the voltage V2 is output as the dither signal VDP, and the voltage V4 is output as the dither signal VDN. That is, the transfer gates TP1 to TP5, TN1 to TN5 select voltages having levels according to the selection signals CODE1 to CODE5 and CODE1B to CODE5B from the voltages V1 to V5, and output them as dither signals VDP and VDN.

  The resistors RA1 to RA3 are connected in series to the power supply side of the resistors R1 to R4. The resistors RB1 to RB3 are connected in series to the ground side of the resistors R1 to R4. These resistors RA1 to RA3 and RB1 to RB3 are used as adjusting resistors for adjusting the maximum levels of the dither signals VDP and VDN. Specifically, the voltages V1 and V5 are adjusted by controlling on / off of the P-channel MOSFETs 80 to 82 and the N-channel MOSFETs 88 to 90 on the basis of the adjustment signals SEL1 to SEL3 in which only one of them becomes the H level. Is done. For example, when the selection signal SEL1 is at the H level, the P-channel MOSFET 80 and the N-channel MOSFET 88 are turned on, the power supply voltage VDD is divided by the resistors RA1, R1 to R4, and RB1, and the voltages V1 to V5 are generated. For example, when the selection signal SEL3 is at the H level, the P-channel MOSFET 82 and the N-channel MOSFET 90 are turned on, and the power supply voltage VDD is divided by the resistors RA1 to RA3, R1 to R4, RB1 to RB3, and the voltages V1 to V5 Is generated. That is, the maximum levels of the dither signals VDP and VDN are maximum when the adjustment signal SEL1 is at the H level, and are minimum when the adjustment signal SEL3 is at the H level. A circuit constituted by resistors RA1 to RA3, RB1 to RB3, P channel MOSFETs 80 to 82, inverter circuits 84 to 86, and N channel MOSFETs 88 to 90 corresponds to the adjustment circuit of the present invention, and P channel MOSFETs 80 to 82, A circuit constituted by the inverter circuits 84 to 86 and the N-channel MOSFETs 88 to 90 corresponds to the application control circuit of the present invention.

  FIG. 7 is a timing chart showing an example of the operation of the delta-sigma modulation circuit 10. Assume that the clock signal CLK changes from the L level to the H level at time t1. Then, the N-channel MOSFETs 44 and 47 of the comparator 31 are turned on, and at time t2, the output signals VCN and VCP of the comparator 31 become L level and the quantized signals VD1 and VD2 become H level. Therefore, the output signals VOP and VON of the latch circuit 32 do not change. On the other hand, when the quantized signals VD1 and VD2 both become H level, the dither clock DCLK output from the EXOR circuit 66 constituting the dither clock generation circuit 14 becomes L level.

  Then, it is assumed that the clock signal CLK changes from H level to L level at time t3. At this time, for example, if the signal obtained by adding the dither signal VDP to the integration signal VP is greater than the signal obtained by adding the dither signal VDN to the integration signal VN, the output signal VCN of the comparator 31 is at the L level and the output signal VCP at time t4. Becomes H level, the quantized signal VD1 becomes H level, and the quantized signal VD2 becomes L level. Therefore, the output of the latch circuit 32 changes the output signal VOP to the H level and the output signal VON to the L level. Thus, when the clock signal CLK changes from the H level to the L level, the quantization is performed in the comparator 31, the result of the quantization is latched by the latch circuit 32, and the output signals VOP, VON of the quantizer 13 are latched. Is output as

  At time t4, the logic levels of the output signals VCN and VCP of the comparator 31 are different from each other, so that the dither clock DCLK output from the dither clock generation circuit 14 becomes H level. When the dither clock DCLK becomes H level, the pseudo random signals TPDF1 to TPDF3 output from the pseudo random signal generation circuit 70 change. The selection signals CODE1 to CODE5 and CODE1B to CODE5B output from the decoder 72 also change in accordance with the pseudo random signals TPDF1 to TPDF3. Further, when the selection signals CODE1 to CODE5 and CODE1B to CODE5B are changed, the transfer gates TP1 to TP5 and TN1 to TN5 that are turned on are changed, and the signal levels of the dither signals VDP and VDN are changed. That is, after the quantization result is latched by the latch circuit 32 and the quantization is completed, the signal levels of the dither signals VDP and VDN change. In the dither signal output circuit 74, the voltages V1 to V5 at a plurality of levels are generated by dividing the voltages applied across the resistors R1 to R4, so that the transfer gates TP1 to TP5 and TN1 to TN5 are generated. When the ON state of the signal changes, the signal levels of the dither signals VDP and VDN change immediately.

  The delta sigma modulation circuit 10 of the present embodiment has been described above. As described above, in the delta-sigma modulation circuit 10, the voltage selected according to the pseudo-random signals TPDF1 to TPDF3 among the plurality of levels of voltages V1 to V5 generated by the resistors R1 to R4 connected in series. Are output as dither signals VPD and VDN. Therefore, a dither signal with good response characteristics can be obtained without increasing current consumption and chip area as in the case of using an operational amplifier. In particular, when the resistance values of the resistors R1 to R4 are increased, the current flowing through the dither signal output circuit 74 is reduced, and the current consumption can be reduced.

  Further, in the delta sigma modulation circuit 10, the voltage applied to both ends of the resistors R1 to R4 can be adjusted based on the control signals SEL1 to SEL3. As a result, the maximum levels of the dither signals VDP and VDN can be adjusted according to the characteristics of the idle tone in the device to which the delta sigma modulation circuit 10 is applied.

  In particular, in the delta-sigma modulation circuit 10, the maximum levels of the dither signals VDP and VDN are adjusted using resistors RA1 to RA3 and RB1 to RB3. That is, the adjustment range of the maximum level of the dither signals VDP and VDN can be easily changed by changing the resistance value and the number of adjustment resistors provided at both ends of the resistors R1 to R4.

  In the delta-sigma modulation circuit 10, the dither clock DCLK is changed in accordance with the completion of the quantization, and the signal levels of the dither signals VDP and VDN are changed. That is, after the quantization using the dither signals VDP and VDN at a certain level is completed, the dither signals VDP and VDN change to the next level, so that the dither signals VDP and VDN are reliably transmitted to the quantizer 13. The generation of idle tones can be suppressed.

  In addition, the said embodiment is for making an understanding of this invention easy, and is not for limiting and interpreting this invention. The present invention can be changed and improved without departing from the gist thereof, and the present invention includes equivalents thereof. For example, even when the number of output bits of the pseudo-random signal is changed, the resistance of the resistors R1 to R4 is further divided and a decoding signal and a control switch are added, so that the chip area can be easily changed without significantly increasing the area. can do.

It is a figure which shows the whole structure of the delta-sigma modulation circuit which is one Embodiment of this invention. It is a figure which shows the structural example of a quantizer. It is a figure which shows the structural example of a comparator. It is a figure which shows the structural example of a latch circuit and a dither clock generation circuit. It is a figure which shows the structural example of a dither circuit. It is a figure which shows the structural example of a dither signal output circuit. It is a figure which shows an example of operation | movement of a delta-sigma modulation circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Delta-sigma modulation circuit 11 Integrator 12 Dither circuit 13 Quantizer 14 Dither clock generation circuit 31 Comparator 32 Latch circuit 70 Pseudo random signal generation circuit 72 Decoder 74 Dither signal output circuit

Claims (4)

An integrator that outputs an integrated signal obtained by integrating the input signal;
A plurality of resistors connected in series and generating multiple levels of voltage;
A dither signal selection circuit that outputs at least one of the plurality of levels of voltage as the dither signal based on a selection signal for selecting the level of the dither signal;
A quantizer for performing quantization based on the integrated signal and the dither signal;
A delta-sigma modulation circuit comprising: A delta-sigma modulation circuit according to claim 1,
An adjustment circuit for adjusting a voltage applied across the plurality of resistors based on a control signal for adjusting the maximum level of the dither signal;
A delta-sigma modulation circuit. A delta-sigma modulation circuit according to claim 2,
The adjustment circuit includes:
A plurality of adjusting resistors connected in series to one end of the plurality of resistors;
An application control circuit that applies a predetermined level of voltage to one end of any of the plurality of adjustment resistors based on the control signal;
A delta-sigma modulation circuit comprising: A delta-sigma modulation circuit according to any one of claims 1 to 3,
Further comprising a selection signal control circuit for changing the selection signal after the quantization is completed based on the quantized signal output from the quantizer;
A delta-sigma modulation circuit.

Images