JP2010067743A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the following problem that: there is restriction in mask design or the like in alignment; a different mark is aligned wrongly for the alignment mark to be originally aligned in the case that the alignment mark is adjacently arranged; in the case of auto-alignment, determination on the device side cannot be made, and alignment is finished in the state of the wrong alignment mark; if matching inspection is performed with respect to the whole number after exposure and development, the inspection is detected without proceeding to the next process; and in the sampling inspection of about a few pieces from a lot, the inspection cannot be detected to proceed to the next process, thus causing a product failure. <P>SOLUTION: In alignment in the exposure of a semiconductor device or the like, the range of searching a target is limited in such a manner that an adjacent target is not included. Thereby, an undesired target is not mistaken for the target for searching. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a technique effective when applied to an exposure technique in a method of manufacturing a semiconductor device (or a semiconductor integrated circuit device).

  Japanese Patent Application Laid-Open No. 6-120312 (Patent Document 1) discloses a technique for shortening a search time by reducing a search area of an alignment pattern in exposure.

Japanese Unexamined Patent Publication No. Hei 6-12312

  There are manual alignment and auto alignment as alignment (mask and wafer alignment) methods in the same magnification projection exposure that are frequently used for exposure of power MOSFETs and the like. In manual alignment, the operator aligns the alignment mark on the mask and the alignment mark on the wafer by moving the wafer stage with an observation optical system. On the other hand, in the automatic alignment, after the above-described manual alignment, the apparatus automatically performs alignment using the auto alignment mark on the mask and the auto alignment mark on the wafer. In the auto alignment method, a laser (He—Ne) is applied to an auto alignment mark at an angle of 45 °, and an alignment signal is generated from the scattered light. The wafer stage is moved so that the wafer auto-alignment signal comes to the center of the mask auto-alignment signals (four). If there is no wafer signal in the mask signal, the wafer stage is moved in a predetermined sequence to search for the wafer signal. When it is confirmed that there is a wafer signal at the center of the mask signal, exposure is started.

  When there is a restriction on the mask design or the like during alignment, if the alignment marks are arranged adjacent to each other, the mark may be mistaken for the alignment mark to be originally aligned and a different mark may be aligned. In the case of manual alignment, it is possible to determine whether the alignment is incorrect with the alignment mark by checking the product pattern etc. after the alignment is completed, but in the case of auto alignment, the device side cannot determine Alignment ends with the wrong alignment mark and exposure is performed. After development, if all the alignment inspections are performed, they are detected without proceeding to the next process, but they are not detected by sampling inspection of several sheets from the lot, but proceed to the next process, resulting in a defective product.

  The present invention has been made to solve these problems.

  An object of the present invention is to provide a manufacturing process of a highly reliable semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  In other words, the present invention limits the search range of a target so as not to include an adjacent target in alignment in exposure of a semiconductor device or the like so that an undesired target is not misidentified as a search target. .

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  In other words, in aligning the exposure of a semiconductor device or the like, the target search range is limited so as not to include adjacent targets, thereby avoiding misidentification of an undesired target as a search target. It is possible to reduce the occurrence of defects such as exposure in a state of being shifted.

[Outline of Embodiment]
First, an outline of a typical embodiment of the invention disclosed in the present application will be described.

1. A semiconductor device manufacturing method including the following steps:
(A) a step of setting the wafer on a wafer stage provided in the 1 × projection exposure apparatus so that the first main surface thereof faces outward;
(B) after the step (a), automatically searching for a target pattern for automatic alignment on the first main surface of the wafer on the wafer stage;
(C) after the step (b), performing automatic alignment using the automatic alignment target pattern on the first main surface of the wafer on the wafer stage;
(D) After the step (c), the device pattern on the mask set in the equal magnification projection exposure apparatus is applied to the resist film on the first main surface of the wafer on the wafer stage. Optically projecting,
Here, the automatic search of the target pattern for automatic alignment in the step (b) is performed in the first search range narrower than the maximum search range possible in the automatic alignment of the equal magnification projection exposure apparatus.

  2. In the method of manufacturing a semiconductor device according to the item 1, the first search range is narrower than the maximum search range in all the θ, X, and Y axis directions.

  3. In the method for manufacturing a semiconductor device according to the item 1 or 2, the unity projection exposure apparatus is a reflection type projection exposure apparatus.

  4). In the method of manufacturing a semiconductor device according to any one of items 1 to 3, the automatic search range in step (b) is limited by detecting a position in the θ, X, and Y axis directions with a sensor. .

  5. 4. In the method of manufacturing a semiconductor device according to any one of items 1 to 3, the limitation of the automatic search range in the step (b) is that the positions in the θ, X, and Y axis directions are data from their position control systems. Is done by monitoring.

[Description format, basic terms, usage in this application]
1. In the present application, the description of the embodiment may be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Each part of a single example, one part is the other part of the details, or part or all of the modifications. Moreover, as a general rule, the same part is not repeated. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  2. Similarly, in the description of the embodiment, etc., regarding the material, composition, etc., “X consisting of A” etc. is an element other than A unless specifically stated otherwise and clearly not in context. It is not excluded that one of the main components. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but also includes SiGe alloys, other multi-component alloys containing silicon as a main component, and members containing other additives. Needless to say. Similarly, the term “silicon oxide film” refers not only to relatively pure undoped silicon oxide, but also to FSG (Fluorosilicate Glass), TEOS-based silicon oxide, and SiOC ( Silicon Oxicarbide) or Carbon-doped Silicon oxide (OSG) (Organosilicate glass), PSG (Phosphorus Silicate Glass), BPSG (Borophosphosilicate Glass) and other thermal oxide films, CVD oxide films, SOG (Spin ON Glass) , Nano-clustering silica (NSC), etc., coated silicon oxide, silica-based low-k insulating film (porous insulating film) in which pores are introduced in similar members, and these are the main Needless to say, it includes a composite film with another silicon-based insulating film as an essential component.

  Needless to say, “gold-plated layer” includes not only high-purity layers but also gold-containing main components (gold-based metal). Various underlayers and intermediate layers are allowed. Similarly, “aluminum electrode” and the like include not only high-purity ones but also those containing various additives (aluminum metal) containing aluminum as a main component. Further, the “aluminum-based metal electrode” is not limited to an aluminum-based metal layer alone, and needless to say, includes an aluminum-based metal layer as a main component.

  3. Similarly, suitable examples of graphics, positions, attributes, and the like are given, but it is needless to say that the present invention is not strictly limited to those cases unless explicitly stated otherwise, and unless otherwise apparent from the context.

  4). In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  5. “Wafer” usually refers to a single crystal silicon wafer on which a semiconductor device (same as a semiconductor integrated circuit device and an electronic device) is formed, but an insulating substrate such as an epitaxial wafer, an SOI substrate, an LCD glass substrate, and the like. Needless to say, a composite wafer such as a semiconductor layer is also included.

  6). “MISFET (Metal Insulator Semiconductor Field Effect Transistor)” includes a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and a gate insulating film other than an oxide.

[Details of the embodiment]
The embodiment will be further described in detail. In the drawings, the same or similar parts are denoted by the same or similar symbols or reference numerals, and description thereof will not be repeated in principle.

1. Description of an outline of a projection optical system of a reflection-type equal-magnification projection exposure apparatus used in a method of manufacturing a semiconductor device according to an embodiment of the present application (mainly FIG. 1)
FIG. 1 is a perspective view showing an outline of a projection optical system of a reflection type equal magnification projection exposure apparatus used in a method for manufacturing a semiconductor device according to an embodiment of the present application. Based on this, the outline of the projection optical system of the reflection type equal magnification projection exposure apparatus used in the method of manufacturing a semiconductor device according to the embodiment of the present application will be described.

  As shown in FIG. 1, the projection optical system of the reflection type equal size projection exposure apparatus 3 (for example, MPA-600FA manufactured by Canon Inc.) scans the arc slit illumination light beam 4 in the direction 9 in the direction of its center point (actual In this case, the entire wafer 1 is exposed at a time by moving the mask 2 and the wafer 1), and therefore belongs to the full scan type. By making the illumination light beam 4 arc-shaped, chromatic aberration and various aberrations can be suppressed. The exposure light (illumination light) uses, for example, broadband light (for example, a band including g, h, i lines of a high-pressure mercury lamp) extending from the ultraviolet region to the ultraviolet region end of the visible region. Widely used for patterning of relatively large patterns such as pads and electrode pads. After passing through the mask 2, the arcuate slit-like illumination light beam 4 is reflected by the trapezoidal mirror 5 along the optical axis 8, is again reflected by the trapezoidal mirror 5 via the concave mirror 6 and the convex mirror 7, and 1 is reached, and the resist film thereon is exposed to light.

2. Description of alignment and the like in exposure processing, which is the main part of the method of manufacturing a semiconductor device according to an embodiment of the present application (mainly FIGS. 2 to 4)
FIG. 2 is a block flow diagram showing the flow of exposure processing for wafer lots in the method of manufacturing a semiconductor device according to one embodiment of the present application. FIG. 3 is a top view (FIG. 3A) of a wafer, a mask, etc. in an exposure process, which is the main part of the method of manufacturing a semiconductor device according to an embodiment of the present application, and a plan view of a target pattern for manual alignment (FIG. 3). 3 (b)) and a perspective view of the apparatus (FIG. 3 (c)) for explaining the operation of the wafer stage, the XY table, and the like. FIG. 4 is a top view (FIG. 3A) of a wafer, a mask, etc., in an exposure process, which is a main part of the method of manufacturing a semiconductor device according to an embodiment of the present application, and a plan view of a target pattern for automatic alignment (FIG. 3 (b)) and a detection waveform diagram when the automatic alignment target pattern is scanned with a laser beam (FIG. 3C). Based on these, alignment and the like in the exposure process, which is a main part of the method of manufacturing a semiconductor device according to the embodiment of the present application, will be described.

  In the following, the flow of exposure will be described using an example of lot processing with about 25 200φ wafers (usually loaded with the same product) as a unit lot (300 phi or 450 phi if necessary). As shown in FIG. 2, manual alignment 101 is performed on the first wafer 1. First, as shown in FIG. 3 (c), the first wafer 1 is placed on the upper surface 54a of the wafer stage 54 with its device surface 1a (first main surface) facing upward (actually, due to the device design, gravity and It may be different from the opposite direction). The wafer stage 54 can rotate by θ and is installed on an XY table 53 including an X table 51 and a Y table 52. Here, the device surface 1 a of the wafer 1 is optically opposed to the pattern surface 2 a of the mask 2 along the optical axis 8.

  As shown in FIG. 3A, there are device pattern regions 33 on the device pattern surface 2a of the mask 2, and alignment target pattern placement regions 31a and 31b on the mask are provided at a plurality of locations. (A plurality of places are also received for the purpose of θ, that is, rotation direction adjustment). Similarly, the device surface 1a of the wafer 1 also has device pattern areas 34, and alignment on the wafer is performed at a plurality of positions corresponding to the target pattern arrangement areas 31a and 31b for alignment on the mask. Target pattern arrangement areas 32a and 32b are provided.

  As shown in FIG. 3B, the alignment target pattern arrangement region 31b on the mask and the alignment target pattern arrangement region 32b on the wafer (the other are the same) are respectively on the mask. A manual alignment target pattern 35 and a manual alignment target pattern 36 on the wafer are provided. Manual alignment is performed by superimposing these target patterns 35, 36 optically or on the image, as shown in the middle figure. Manual alignment can also be viewed here as rough alignment before automatic alignment.

  After manual alignment 101, automatic alignment 102 is performed on the first wafer 1 as shown in FIG. As shown in FIGS. 4A and 4B, in the same manner as the manual alignment target patterns 35 and 36, the automatic alignment target patterns 37 and 38 are respectively aligned with the alignment target patterns on the mask. It is provided in the arrangement areas 31a and 31b and the alignment target pattern arrangement areas 32a and 32b on the wafer. As shown in FIG. 4B, automatic alignment is performed by, for example, applying an automatic alignment target pattern 37 on a mask and an automatic alignment target pattern 38 on a wafer in the process to a laser beam (for example, This is done by detecting optical signals scattered from the respective target patterns 37, 38 by scanning with a visible laser. More specifically, as shown in the middle diagram of FIG. 4B, these target patterns 37 and 38 are optically or superposed on the image. When viewed as an electrical signal, as shown in the middle diagram of FIG. 4C, the process is performed in the middle of the peaks MP1 and MP2 and MP3 and MP4 corresponding to the target pattern 37 for automatic alignment on the mask. The position of the XY table 53 and the θ orientation of the wafer stage 54 are changed so that the peaks MW1 and MW2 corresponding to the target pattern for automatic alignment on the wafer come. As described above, the positional relationship between the device pattern area 33 on the mask and the device pattern area 34 on the wafer shown in FIG.

  After the automatic alignment 102 with respect to the first wafer 1, exposure 103 is performed with respect to the first wafer 1 as shown in FIG. When the exposure 103 for the first wafer 1 is completed, the first wafer 1 is transferred to the outside of the wafer stage 54, and instead, the second wafer 1 is transferred to the wafer stage 54 as before. Set to When the second wafer 1 is set on the wafer stage 54, the automatic alignment 104 with respect to the second wafer 1 is executed as before. Since the previous manual alignment position (initial position) has been registered this time, the second wafer 1 has already been moved to the initial position at the start of automatic alignment 104. No alignment is necessary. When the automatic alignment 104 for the second wafer 1 is completed, the exposure 105 for the second wafer 1 is executed. When the exposure 105 for the second wafer 1 is completed, the second wafer 1 is transferred to the outside of the wafer stage 54. When such a cycle is repeated and the automatic alignment 106 and exposure 107 for the last wafer 1 are completed, the exposure processing for the lot is completed.

3. Description of automatic search range limiting method and the like in alignment in exposure processing, which is the main part of the method of manufacturing a semiconductor device according to an embodiment of the present application (mainly FIGS. 5 to 7)
FIG. 5 is a principle explanatory view for explaining a method for limiting the search range for automatic alignment in the exposure process, which is the main part of the method of manufacturing a semiconductor device according to the embodiment of the present application (FIG. 5 (b) is the rotational direction, ie, θ displacement. FIG. 6 is an apparatus configuration diagram illustrating a first specific example (position acquisition by a sensor) of a method for limiting a search range for automatic alignment in exposure processing, which is a main part of a method for manufacturing a semiconductor device according to an embodiment of the present application. It is. FIG. 7 is an apparatus for explaining a first specific example (use of stage position display data) of a method for limiting a search range for automatic alignment in exposure processing, which is a main part of a method for manufacturing a semiconductor device according to an embodiment of the present application. It is a block diagram. Based on these, an automatic search range limiting method and the like in alignment in exposure processing, which is a main part of the method for manufacturing a semiconductor device according to an embodiment of the present application, will be described.

  As shown in FIG. 5, the full-scan reflection-type equal-magnification projection exposure apparatus described in Section 1 has a relatively wide automatic search capability possible range (maximum search range; The X direction is 2 mm, the Y direction is 1 mm, and the θ azimuth is already aligned to a considerable extent by pre-alignment and manual alignment, so the remaining search remains in a very small range, and the θ azimuth is not an independent dimension) That is, it has a search range (maximum search range of the apparatus) 41 for automatic alignment. However, in such a wide automatic search capability possible range 41, the target pattern 39 for automatic alignment on the wafer in other processes such as the target pattern in the next process is often arranged. There is. Therefore, in this state, when the automatic alignment is started from the automatic alignment start point 43 during the automatic alignment of the second and subsequent lots, the automatic alignment target There is a possibility that an error occurs in searching for the automatic alignment target pattern 39 on the wafer in another process instead of the pattern 38 and executing automatic alignment for the erroneous target pattern. In order to prevent such a malfunction, as shown in FIG. 5, the target pattern 39 for automatic alignment on the wafer in such another process does not enter the search range, and the automatic position on the wafer in that process does not exist. The matching target pattern 38 is a limited search range 42 (first search range) so as to surely enter the search range. For example, the X direction is 1.3 mm and the Y direction is 0.36 mm, and the range of the θ direction is set slightly smaller than the range of the θ direction of the maximum search range, for example.

  The X, Y, and θ ranges of the limited search range 42 are included in the X, Y, and θ ranges of the maximum search range 41. That is, in the three-dimensional space (X, Y, θ), the limited search range 42 forms a narrow range included in the maximum search range 41.

  FIG. 6 shows an example of such a search range limiting method. As shown in FIG. 6, the wafer drive system including the drive system for the XY table 53 and the wafer stage 54 is controlled by a stage position control system 58. Here, the stage position monitoring unit 59 receives θ direction information, X direction position information, and Y direction position information from the θ direction sensor 55, the X position sensor 56, and the Y position sensor 57 attached to the XY table 53, respectively. get. Then, the acquired data is compared with the limited search range 42 registered in advance, and when it goes outside the same area, a stop signal is automatically sent to the stage position control system 58, and the wafer is The drive system is stopped, an alarm is displayed, and the device is stopped. Instead of displaying an alarm, control may be performed so that another direction or direction is automatically searched.

  FIG. 7 shows another example of such a search range limiting method. Here, the stage position is monitored using a stage position signal generated inside the stage position display unit 60 of the stage position control system 58 instead of acquiring data by the position sensor.

4). Description of a semiconductor device manufacturing method according to an embodiment of the present application and a power MISFET manufactured thereby (mainly FIGS. 8 to 15)
FIG. 8 is a top view of the chip region of the power MISFET manufactured by the method of manufacturing a semiconductor device according to the embodiment of the present application. FIG. 9 is a diagram for explaining a main process of the manufacturing method of the semiconductor device according to the embodiment of the present application (corresponding to the XX ′ cross section of FIG. FIG. 2 is a device cross-sectional flow diagram (when aluminum-based electrode patterning is completed). FIG. 10 is a device cross-sectional flow diagram (final passivation application) for explaining a main process of the manufacturing method of the semiconductor device according to the embodiment of the present application. FIG. 11 is a device cross-sectional flow diagram (pad opening resist application) for explaining a main process of the manufacturing method of the semiconductor device according to the embodiment of the present application. FIG. 12 is a device cross-sectional flow diagram (pad opening resist film patterning) for explaining a main process of the method of manufacturing a semiconductor device according to the embodiment of the present application. FIG. 13 is a device cross-sectional flow diagram (final passivation film etching) for explaining a main process of the method of manufacturing a semiconductor device according to the embodiment of the present application. FIG. 14 is a device cross-sectional flow diagram (removal of resist film for pad opening) for explaining the main process of the manufacturing method of the semiconductor device according to one embodiment of the present application. FIG. 15 is a device cross-sectional flow diagram (rear surface metal electrode plating) for explaining a main process of the method for manufacturing a semiconductor device according to the embodiment of the present application. Based on these, a method for manufacturing a semiconductor device according to an embodiment of the present application and a power MISFET (including a power MOSFET) manufactured thereby will be described.

  First, the upper surface structure of the device will be described. As shown in FIG. 8, when the wafer process is almost completed, most of the chip region 10 is covered with a final passivation film 19 such as a polyimide film. A source electrode opening 20 is provided at the center of the chip region 10. A gate electrode opening 23 is provided at the end of the chip region 10.

  Next, the cross-sectional structure of the device will be described. As shown in FIG. 9, an n − type epitaxial layer 11 that is a drift region is formed on an n + type single crystal silicon substrate 1 that is a drain region. A P-type body region 12 is formed in the device surface region of the n − -type epitaxial layer 11, and an N-type source region 15 and a P-type body contact region 14 are formed in the surface region. A polysilicon gate electrode 16 is formed on the surface of the n − type epitaxial layer 11 with a gate insulating film 22 interposed therebetween. Above and on the side of the polysilicon gate electrode 16 is a CVD silicon oxide film or the like. The interlayer insulating film 17 is covered. On the surface of the interlayer insulating film 17 and the n − type epitaxial layer 11, a source electrode 18 made of an aluminum-based metal electrode film or the like (a gate / metal external electrode is formed by the same layer) is formed. .

  Hereinafter, the main part of the manufacturing process (centering on the pad opening) will be sequentially described. As shown in FIG. 10, a polyimide film 19 that is a final passivation film is applied on the metal electrode film 18. Next, as shown in FIG. 11, a photoresist film 21 is applied on the polyimide film 19. By exposing and developing the photoresist film 21 as described in the preceding section, a resist film pattern 21 as shown in FIG. 12 is obtained. Next, as shown in FIG. 13, using the resist film pattern 21 as an etching mask, the polyimide film 19 is etched to form a source electrode opening 20. Thereafter, as shown in FIG. 14, the unnecessary resist film 21 is removed. Finally, an electrode metal 13 such as gold is plated on the back surface of the wafer 1.

5). Summary The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  For example, in the above-described embodiment, the case where the present invention is applied to the pad opening process of the power MISFET has been specifically described. However, the present invention is not limited thereto, and other processes of the power MISFET (for example, aluminum-based electrode patterning). Needless to say, the present invention can be applied to other similar processes and other processes of a single unit and a semiconductor integrated circuit device.

It is a perspective view which shows the outline | summary of the projection optical system of the reflection type equal magnification projection exposure apparatus used for the manufacturing method of the semiconductor device of one embodiment of this application. FIG. 6 is a block flow diagram showing a flow of exposure processing for a wafer lot in a method for manufacturing a semiconductor device according to an embodiment of the present application. FIG. 3A is a top view of a wafer, a mask, and the like in an exposure process, which is a main part of a method for manufacturing a semiconductor device according to an embodiment of the present application, and FIG. )) And a perspective view of the apparatus for explaining the operation of the wafer stage, the XY table, etc. (FIG. 3C). FIG. 3A is a top view of a wafer, a mask, and the like in an exposure process, which is a main part of a method for manufacturing a semiconductor device according to an embodiment of the present application, and FIG. And FIG. 3C is a detection waveform diagram when the automatic alignment target pattern is scanned with a laser beam. FIG. 5A is a principle explanatory view for explaining a method for limiting a search range for automatic alignment in exposure processing, which is a main part of a method for manufacturing a semiconductor device according to an embodiment of the present application. ) Is the rotational direction, ie, θ displacement). It is an apparatus block diagram explaining the 1st specific example (position acquisition by a sensor) of the limiting method of the search range of the automatic alignment in the exposure process which is the principal part of the manufacturing method of the semiconductor device of one embodiment of this application. BRIEF DESCRIPTION OF THE DRAWINGS In the apparatus block diagram explaining the 1st specific example (use of stage position display data) of the limitation method of the search range of the automatic alignment in the exposure process which is the principal part of the manufacturing method of the semiconductor device of one embodiment of this application is there. It is a top view of the chip | tip area | region of power MISFET manufactured by the manufacturing method of the semiconductor device of one embodiment of this application. FIG. 8 is a cross-sectional view taken along the line XX ′ in FIG. 8 for explaining the main process of the method of manufacturing a semiconductor device according to the embodiment of the present invention. Therefore, only the unit portion is shown. The same applies hereinafter) Device cross-sectional flow diagram (when aluminum-based electrode patterning is completed). It is a device section flow figure (final passivation application) for explaining the principal part process of the manufacturing method of the semiconductor device of one embodiment of this application. It is a device section flow figure (resist application for pad opening) for explaining the principal part process of the manufacturing method of the semiconductor device of one embodiment of this application. It is a device section flow figure (resist film patterning for pad opening) for explaining the principal part process of the manufacturing method of the semiconductor device of one embodiment of this application. It is a device section flow figure (final passivation film etching) for explaining the principal part process of the manufacturing method of the semiconductor device of one embodiment of this application. It is a device section flow figure (resist film removal for pad opening) for explaining the principal part process of the manufacturing method of the semiconductor device of one embodiment of this application. It is a device cross section flow figure (back surface metal electrode plating) for demonstrating the principal part process of the manufacturing method of the semiconductor device of one embodiment of this application.

Explanation of symbols

1 Wafer (or N-type semiconductor substrate)
1a First main surface of wafer (device surface of semiconductor substrate or uppermost surface of wafer including laminated structure)
2 Mask 2a Pattern surface of mask 3 Reflective equal-magnification projection exposure apparatus 4 Arc slit illumination light beam 5 Trapezoidal mirror 6 Concave mirror 7 Convex mirror 8 Optical axis (including idealized optical axis)
9 Scan direction of mask and wafer 10 Semiconductor chip or chip region 11 N type epitaxial layer (N type drift region)
12 channel region (or channel P-type impurity region or P-type body region, part of which constitutes the channel region)
13 Drain electrode (drain electrode metal film)
14 P-type body contact region 15 N-type source region 16 Gate electrode 17 Interlayer insulating film 18 Source electrode 19 Final passivation film 20 Source electrode opening (or source pad)
21 resist film 22 gate insulating film 23 gate electrode opening (or gate pad)
31a, 31b Target pattern arrangement area for alignment on mask 32a, 32b Target pattern arrangement area for alignment on wafer 33 Device pattern area on mask 34 Device pattern area on wafer 35 Manual position on mask Target pattern for alignment 36 Target pattern for manual alignment on a wafer 37 Target pattern for automatic alignment on a mask 38 Target pattern for automatic alignment on a wafer in the process 39 Automatic on a wafer in another process Target pattern for alignment 40 Laser beam scan path (or laser beam)
41 Search range for automatic alignment (maximum search range of the device)
42 Limited search range (first search range)
43 Automatic Positioning Start Point 51 X Table 52 Y Table 53 XY Table 54 Wafer Stage 54a Main Surface of Wafer Stage 55 θ Position Sensor 56 X Position Sensor 57 Y Position Sensor 58 Stage Position Control Unit 59 Stage Position Monitoring Unit 60 Stage position display unit 101 Manual alignment for the first wafer 102 Automatic alignment for the first wafer 103 Exposure for the first wafer 104 Automatic alignment for the second wafer 105 Exposure for the second wafer 106 Automatic alignment for the final wafer of the lot 107 Exposure to the final wafer of the lot MP1, MP2, MP3, MP4 Detection signal peak by the automatic alignment target pattern on the mask MW1, MW2 Automatic alignment on the wafer Peak of detection signal by target pattern θ Rotation in horizontal plane X Movement in X-axis direction Y Movement in Y-axis direction

Claims (5)

A semiconductor device manufacturing method including the following steps:
(A) a step of setting the wafer on a wafer stage provided in the 1 × projection exposure apparatus so that the first main surface thereof faces outward;
(B) after the step (a), automatically searching for a target pattern for automatic alignment on the first main surface of the wafer on the wafer stage;
(C) after the step (b), performing automatic alignment using the automatic alignment target pattern on the first main surface of the wafer on the wafer stage;
(D) After the step (c), the device pattern on the mask set in the equal magnification projection exposure apparatus is applied to the resist film on the first main surface of the wafer on the wafer stage. Optically projecting,
Here, the automatic search of the target pattern for automatic alignment in the step (b) is performed in the first search range narrower than the maximum search range possible in the automatic alignment of the equal magnification projection exposure apparatus.     In the method of manufacturing a semiconductor device according to the item 1, the first search range is narrower than the maximum search range in all the θ, X, and Y axis directions.     In the method of manufacturing a semiconductor device according to the item 1, the equal magnification projection exposure apparatus is a reflection type projection exposure apparatus.     In the method of manufacturing a semiconductor device according to the item 1, the restriction of the automatic search range in the step (b) is performed by detecting a position in the θ, X, and Y axis directions with a sensor.     In the method of manufacturing a semiconductor device according to the item 1, the automatic search range is limited in the step (b) by monitoring the positions in the θ, X, and Y axis directions by monitoring data from their position control systems. Is called.

Images