JP2010062597A - A/d converter and measuring device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an A/D converter for reducing the effect of a conversion error generated by a plurality of A/D conversion circuits, while suppressing a processing load. <P>SOLUTION: A light reception circuit 20 changes the order for starting A/D conversion of the A/D conversion circuits for each period of A/D conversion processing, and adds an in-phase digital signal for a digital signal converted from analog to digital at each period. For example, an A/D conversion change section 22 performs A/D conversion in order of the A/D conversion circuits 21A, 21B, 21C, in order of the A/D conversion circuits 21B, 21C, 21A, and in order of the A/D conversion circuits 21C, 21A, 21B, in the first, second, and third periods, respectively. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an A / D converter that performs A / D conversion by time division using a plurality of A / D conversion circuits, and a measurement device using the A / D converter.

  An A / D converter that converts an analog signal into a digital signal is required to have high speed. However, an A / D converter having a high conversion speed is very expensive. Therefore, conventionally, a method has been proposed in which a plurality of A / D conversion circuits having a relatively low conversion speed are connected in parallel and A / D conversion is performed in a time division manner (see, for example, Patent Document 1 and Patent Document 2).

  FIG. 1 is a diagram showing the configuration of an A / D converter that uses three A / D conversion circuits and triples the conversion speed. In this example, an A / D converter that is driven at 90 MHz as a whole will be described using an A / D converter circuit that is driven at 30 MHz. The A / D converter shown in the figure includes an A / D conversion circuit 11A, an A / D conversion circuit 11B, an A / D conversion circuit 11C, an A / D conversion switching unit 12, an integration processing unit 13, and a memory 14. Yes.

  When the trigger signal is input, the A / D conversion switching unit 12 sequentially controls the A / D conversion circuit 11A, the A / D conversion circuit 11B, and the A / D conversion circuit 11C to start A / D conversion. . Each time the main A / D conversion clock is input, the A / D conversion switching unit 12 sends a start command signal (sub-signal) to the A / D conversion circuit 11A, the A / D conversion circuit 11B, and the A / D conversion circuit 11C, respectively. (A / D conversion clock) is output to perform A / D conversion.

  FIG. 2 shows each signal in time series. The A / D conversion switching unit 12 outputs a start command signal A to the A / D conversion circuit 11A when a trigger signal and a main A / D conversion clock are first input. When the main A / D conversion clock is next input, the A / D conversion switching unit 12 outputs a start command signal B, and when the main A / D conversion clock is input next, the start command signal C is output. Output. Next, when the main A / D conversion clock is input, the process repeats from the output of the start command signal A. In this manner, A / D conversion is repeatedly performed in the order of the A / D conversion circuit 11A, the A / D conversion circuit 11B, and the A / D conversion circuit 11C. In this example, the A / D converter performs nine times of input of the main A / D conversion clock as one cycle and performs A / D conversion processing a plurality of times (a plurality of cycles). The digital signal subjected to A / D conversion in each cycle is added by the integration processing unit 13.

  FIG. 3 is a diagram illustrating the integration processing of the integration processing unit 13. In the display such as “A11” shown in the figure, the first “A” is the identifier of the A / D conversion circuit, the next tenth digit is the cycle, and the first digit is the conversion order in one cycle. . The integration processing unit 13 adds a digital signal having the same phase to the digital signal subjected to A / D conversion in each cycle. For example, the output value of the first A / D conversion circuit 11A in the first period (A11 in the figure), the output value of the first A / D conversion circuit 11A in the second period (A21 in the figure), and the first output in the third period The output value of the A / D conversion circuit 11A (A31 in the figure) is added.

  However, as described in Patent Document 1, each A / D conversion circuit has an inherent A / D conversion error. Therefore, as shown in FIG. 3, for example, the A / D conversion circuit 11B outputs a value larger than the output value of the A / D conversion circuit 11A, and the A / D conversion circuit 11C is smaller than the A / D conversion circuit 11A. When outputting values, adding the output values of the same phase increases the error.

  Therefore, in the A / D converter of Patent Document 1, an error of each A / D conversion circuit is obtained in advance, and a process corresponding to the error is corrected. FIG. 4 is a flowchart showing the operation of error measurement and correction processing. In the error measurement operation shown in FIG. 6A, first, an analog value input to the A / D converter is set to be constant (s11). Thereafter, a dummy analog A / D conversion is performed by inputting a certain analog value and causing each A / D converter circuit to perform A / D conversion (s12). The integration processing unit obtains the maximum value from the addition results of the A / D conversion circuits A, B, and C (s13). Then, a difference (error) between the A / D conversion circuit that outputs the maximum value and the other A / D conversion circuits is obtained (s14). Finally, from the obtained error, an error corresponding to the number of additions (3 times the obtained error if the number of additions is 3) is used as correction data (s15). The correction data is calculated individually for each A / D conversion circuit.

  In the correction process shown in FIG. 5B, first, an A / D conversion process is performed, and the process waits until an integration process result is obtained (s21). Thereafter, the integration processing unit adds correction data corresponding to each A / D conversion circuit to the acquired all A / D conversion values (s22). Therefore, the inherent error for each A / D conversion circuit is eliminated.

Actually, since the error of each A / D conversion circuit changes due to a temperature change or the like, the error measurement and correction processing shown in FIG. 4 is performed each time (for example, every few seconds) even during the A / D conversion operation. This is necessary and the processing load increases.
JP 2001-339303 A JP 7-183809 A

  An object of the present invention is to provide an A / D converter that reduces the influence of a conversion error generated by using a plurality of A / D conversion circuits while suppressing a processing load.

  The present invention includes a plurality of A / D conversion circuits, start signal generation means for outputting a start command signal for starting A / D conversion to the plurality of A / D conversion circuits at a predetermined time interval, and one An analog signal input terminal, wherein the analog signal input terminal is connected to the plurality of A / D conversion circuits in parallel, and the start signal generating means includes the plurality of A / D converters. The conversion circuit performs A / D conversion in a first order with a predetermined number of times as one cycle, and repeatedly performs a conversion process for causing the plurality of A / D conversion circuits to perform the predetermined number of A / D conversions in a second order, And adding means for adding the digital signals having the same phase as the digital signals subjected to A / D conversion in the first order and the digital signals subjected to A / D conversion in the second order.

  As described above, according to the present invention, the start order of the A / D conversion circuit is changed and the digital signals having the same phase are added every cycle of the A / D conversion process. For example, different A / D conversion circuits are used for the first A / D conversion in the first period and the first A / D conversion in the second period. Accordingly, it is possible to prevent error expansion caused by adding digital signals having the same phase. Further, if the number of additions matches the number of A / D conversion circuits, the conversion error can be canceled out. The error referred to here is not an absolute error (offset error) of the A / D conversion circuit, but a relative output value caused by different A / D conversion circuits used for the same input value. Say error.

  According to the present invention, it is possible to reduce the influence of a conversion error generated by using a plurality of A / D conversion circuits.

  Hereinafter, a distance measurement device (laser radar device) will be described as an embodiment according to the A / D conversion circuit and the measurement device of the present invention. The laser radar device is attached to, for example, an automobile, irradiates laser light in front of the host vehicle, and measures the distance from the object from the time until the irradiated laser light is reflected from the object and returned. The measuring device of the present invention is not limited to a laser radar device, and may be any device as long as it receives a signal and performs measurement.

  FIG. 5 is a block diagram showing the main part of the laser radar device. As shown in FIG. 1A, the laser radar apparatus includes a control circuit 30, an LD (Laser Diode) drive circuit 35, an LD 36, a PD (Photo Diode) 37, a light receiving circuit 20, and a memory 38.

  The LD drive circuit 35 controls the light emission of the LD 36 based on the measurement start instruction from the control circuit 30. Laser light emitted from the LD 36 is reflected on an object (for example, a vehicle or road surface) as a detection target, as shown in FIG. The reflected light that has been reflected back to the object is received by the PD 37. The PD 37 outputs an analog signal corresponding to the intensity of the received reflected light to the light receiving circuit 20.

  The light receiving circuit 20 converts the input analog signal into a digital signal and outputs the digital signal to the control circuit 30. The control circuit 30 functionally includes an integration processing unit 31 and a distance measurement control unit 32. The integration processing unit 31 corresponds to the addition means of the present invention, and performs the addition process of the digital signal input from the light receiving circuit 20. The distance measurement control unit 32 measures the distance to the object based on the required time from when the laser light is irradiated until the reflected light is received. Usually, since the intensity of the reflected light is weak with only one light emission and it is difficult to differentiate it from noise, the laser radar device performs light emission and measurement a plurality of times and adds the output value of the light receiving circuit 20. Perform the process.

  As shown in FIG. 5B, the light receiving circuit 20 includes an A / D conversion circuit 21A, an A / D conversion circuit 21B, and an A / D conversion circuit 21C connected in parallel to the PD 37. The light receiving circuit 20 includes an A / D conversion switching unit 22 connected to each A / D conversion circuit. The A / D converter of the present invention is realized by the light receiving circuit 20 and the integration processing unit 31 in the control circuit 30. An analog signal input from the PD 37 corresponds to an analog signal input terminal of the present invention.

  The distance measurement control unit 32 issues a measurement start instruction to the LD drive circuit 35 and simultaneously outputs a trigger signal to the A / D conversion switching unit 22. Further, the distance measurement control unit 32 outputs a main A / D conversion clock to the A / D conversion switching unit 22 in accordance with the drive frequency (90 MHz in the present embodiment).

  The A / D conversion switching unit 22 corresponds to the start signal generating means of the present invention. When a trigger signal is input, the A / D conversion switching unit 22 switches the A / D conversion circuit 21A, the A / D conversion circuit 21B, and the A / D conversion circuit 21C. A / D conversion is started under sequential control. Each time the main A / D conversion clock is input, the A / D conversion switching unit 22 sends a start command signal (sub-signal) to the A / D conversion circuit 21A, the A / D conversion circuit 21B, and the A / D conversion circuit 21C, respectively. (A / D conversion clock) is output to perform A / D conversion. The start command signal to each A / D conversion circuit is output at a frequency of 30 MHz.

  FIG. 6 shows each signal in time series. As shown in FIG. 6A, the A / D conversion switching unit 22 outputs a start command signal A to the A / D conversion circuit 21A when a trigger signal and a main A / D conversion clock are first input. . When the main A / D conversion clock is next input, the A / D conversion switching unit 22 outputs a start command signal B to the A / D conversion circuit 21B. Next, when a main A / D conversion clock is input, a start command signal C is output to the A / D conversion circuit 21C. Next, when the main A / D conversion clock is input, the process repeats from the output of the start command signal A. As described above, the A / D conversion switching unit 22 repeatedly performs A / D conversion in the order of the A / D conversion circuit 21A, the A / D conversion circuit 21B, and the A / D conversion circuit 21C. The light receiving circuit 20 performs the A / D conversion process of a plurality of periods, with nine inputs of the main A / D conversion clock as one measurement period. In this embodiment, for ease of explanation, an example in which A / D conversion is performed nine times in one cycle is shown, but actually, the number of A / D conversions in one cycle is further increased.

  The digital signal after A / D conversion in each cycle is added by the integration processing unit 31 of the control circuit 30. The integration processing unit 31 integrates the digital signal corresponding to the elapsed time from the trigger signal output in each measurement cycle, and records it in the memory 38. That is, the integration processing unit 31 performs processing for adding digital signals having the same phase in each cycle.

  Here, the light receiving circuit 20 of the present embodiment changes the A / D conversion start order of the A / D conversion circuit for each period of the A / D conversion process. For example, as shown in FIG. 5B, when the main A / D conversion clock is input in the second period, the A / D conversion switching unit 22 first supplies a start command signal to the A / D conversion circuit 21B. B is output. The A / D conversion switching unit 22 does not output a start command signal when the first trigger signal and the main A / D conversion clock are input, and pauses for one clock. That is, the A / D conversion switching unit 22 outputs the start command signal C to the A / D conversion circuit 21C last in the first cycle, and outputs the start command signal B to the A / D conversion circuit 21B in the previous clock. is doing. Therefore, since the A / D conversion circuit 21B cannot be driven for the first clock in the second period, A / D conversion is performed after one clock has elapsed. This deviation is corrected by the integration processing unit 31. That is, in the second period, the integration processing unit 31 treats the digital signal output after one clock has elapsed after the trigger signal is output as the same phase as the first digital signal in the first period.

  When the main A / D conversion clock is input next, the A / D conversion switching unit 22 outputs a start command signal C to the A / D conversion circuit 21C. Next, when a main A / D conversion clock is input, a start command signal A is output to the A / D conversion circuit 21A. Then, when the main A / D conversion clock is input next, the process repeats from the output of the start command signal B. As described above, in the second period, the A / D conversion switching unit 22 repeatedly performs A / D conversion in the order of the A / D conversion circuit 21B, the A / D conversion circuit 21C, and the A / D conversion circuit 21A.

  Further, as shown in FIG. 5C, the A / D conversion switching unit 22 first supplies a start command signal to the A / D conversion circuit 21C when the main A / D conversion clock is input in the third period. C is output. Then, the start command signal A is output to the A / D conversion circuit 21A. Further, a start command signal B is output to the A / D conversion circuit 21B. Thus, in the third period, the A / D conversion switching unit 22 repeatedly performs A / D conversion in the order of the A / D conversion circuit 21C, the A / D conversion circuit 21A, and the A / D conversion circuit 21B. Even in the third period, when the first trigger signal and the main A / D conversion clock are input, the A / D conversion switching unit 22 does not output the start command signal and pauses for one clock. Further, even in the third period, the integration processing unit 31 treats the digital signal output after one clock has elapsed after the trigger signal is output as the same phase as the first digital signal in the first period.

  FIG. 7 is a diagram illustrating the integration process of the integration processing unit 31. The integration processing unit 31 adds a digital signal having the same phase to the digital signal subjected to A / D conversion in each cycle. For example, the output value of the first A / D conversion circuit 21A in the first cycle (A11 in the figure), the output value of the first A / D conversion circuit 21B in the second cycle (B21 in the figure), and the first output in the third cycle The output value of the A / D conversion circuit 21C (C31 in the figure) is added.

  In the example shown in FIG. 7, even if the input values are the same, the A / D conversion circuit 21B outputs a larger value than the A / D conversion circuit 21A, and the A / D conversion circuit 21C It has a relative error that outputs a value smaller than 21A. However, since the A / D conversion start order is changed for each A / D conversion processing cycle, the integration processing unit 31 adds A / D conversion circuits 21A, 21B, Since the output value of 21C is added, the conversion error can be canceled.

  Note that the conversion order is not limited to the above example, and any order may be used as long as the number of A / D conversions of the A / D conversion circuit in each phase is the same. For example, A / D conversion is performed in the order of the A / D conversion circuits 21A, 21B, and 21C in the first period, and A / D conversion is performed in the order of the A / D conversion circuits 21C, 21A, and 21B in the second period. Alternatively, A / D conversion may be performed in the order of the A / D conversion circuits 21B, 21C, and 21A.

  In the above example, the number of measurements (the number of additions) is made to match an integer multiple of the number of A / D conversion circuits, but it is not always necessary to make them match. For example, if the number of A / D conversion circuits is three and measurement is performed for four cycles, an error occurs for one cycle, but the error for three cycles is canceled out, so the conversion error as a whole is reduced. can do. In particular, as the number of times of measurement increases and the number of additions increases, the influence of the conversion error decreases. Further, the number of A / D conversion circuits may be three or more.

  The influence of the relative error between the A / D conversion circuits will be described with reference to FIG. FIG. 8 is a diagram showing the reflection intensity of the laser reflected light on the time axis. The vertical axis (intensity) of the graph shown in the figure is a value recorded in the memory 38 after the integration processing unit 31 has integrated.

  As shown in FIG. 5A, the distance measurement control unit 32, when there is a reflection intensity that exceeds the threshold value, the time (the light emission timing) at which the highest reflection intensity is obtained from the time when the LD 36 starts to emit light (light emission timing). The time difference up to (light reception timing) is obtained, and the distance to the object is obtained based on this time difference.

  Here, when the conventional addition processing as shown in FIG. 3 is performed, the relative error of the A / D conversion circuit increases, and the waveform of the reflection intensity changes as shown in FIG. 8B. Therefore, even if the reflection intensity actually indicates noise, the threshold value may be exceeded, and the distance from the object cannot be measured accurately.

  Also, in the conventional method of correcting the error by adding correction data as shown in FIG. 4, the reflection intensity is increased as a whole as shown in FIG. Even if it is the reflection intensity shown, a situation exceeding the threshold value occurs. Further, if the threshold value is increased in order to avoid the influence of noise, there is a possibility that the actual reflection intensity of the object cannot be detected.

  On the other hand, as shown in FIG. 7, the light receiving circuit 20 of the present embodiment changes the A / D conversion start order of the A / D conversion circuit for each period of the A / D conversion process, and at each period. Since the digital signal having the same phase is added to the A / D converted digital signal, it is possible to reduce the relative error without adding correction data. Therefore, the situation as shown in FIG. 8B or FIG. 8C does not occur while suppressing the processing load.

  Next, FIG. 9 is a flowchart showing the measurement operation of the laser radar apparatus. This operation is started when the distance measurement control unit 32 outputs a trigger signal. First, the A / D conversion switching unit 22 first selects the A / D conversion circuit 21A as an A / D conversion circuit that performs A / D conversion (s31). Then, the integration processing unit 31 initializes the memory 38 (s32).

  The distance measurement control unit 32 drives the LD drive circuit 35 to cause the LD 36 to emit light (s33). The light receiving circuit 20 receives the main A / D conversion clock from the distance measurement control unit 32, and performs A / D conversion processing by the A / D conversion circuit selected in the selection processing in s31 (s34). The integration processing unit 31 integrates the digital signal output value output from the light receiving circuit 20 (s35). Thereafter, the A / D conversion switching unit 22 selects the next A / D conversion circuit (s36). For example, when the A / D conversion circuit 21A is driven, the A / D conversion circuit 21B is selected. When the A / D conversion circuit 21B is driven, the A / D conversion circuit 21C is selected, and the A / D conversion circuit 21A is selected. When the D conversion circuit 21C is driven, the A / D conversion circuit 21A is selected.

  The A / D conversion processing, integration processing, and A / D conversion circuit selection processing as described above are repeated a predetermined number of times (one cycle) (s37). The A / D conversion switching unit 22 determines which A / D conversion circuit has finally performed the A / D conversion after the processing for one cycle is completed (s38). If the A / D conversion circuit 21A performs A / D conversion, the A / D conversion circuit 21B is selected (s39). When A / D conversion is performed by the A / D conversion circuit 21B, the A / D conversion circuit 21C is selected (s40). When A / D conversion is performed by the A / D conversion circuit 21C, the A / D conversion circuit 21A is selected (s41). Then, the processing is repeated from the light emission of the LD 36 for a predetermined number of integration times (three times in the examples of FIGS. 6 and 7) (s42).

  As described above, the light receiving circuit of the present embodiment changes the A / D conversion start order of the A / D conversion circuit for each period of the A / D conversion process. In the integration processing unit, when the digital signals having the same phase are added, the output values of the different A / D conversion circuits are added in each cycle, and the relative conversion error between the A / D conversion circuits is reduced. Can do.

It is a figure which shows the structure of the A / D converter which used 3 A / D conversion circuits, and tripled the conversion speed. It is the figure which represented each signal in time series. It is a conceptual diagram which shows the integration process of the integration process part. It is a flowchart which shows the operation | movement of the conventional error measurement and correction process. It is a block diagram which shows the principal part of the laser radar apparatus which concerns on this embodiment. It is the figure which represented each signal which concerns on this embodiment in time series. It is a conceptual diagram which shows the integration process of the integration process part 31 which concerns on this embodiment. It is the figure which represented the intensity | strength of the laser reflected light on the time axis. It is a flowchart which shows the measurement operation | movement of a laser radar apparatus.

Claims (2)

A plurality of A / D conversion circuits;
Start signal generating means for outputting a start command signal for starting A / D conversion to the plurality of A / D conversion circuits at predetermined time intervals;
One analog signal input terminal, and
An A / D converter in which the plurality of A / D conversion circuits are connected in parallel to the analog signal input terminal,
The start signal generating unit performs A / D conversion on the plurality of A / D conversion circuits in a first order with a predetermined number of times as one cycle, and the plurality of A / D conversion circuits in the second order on the predetermined number of times. Let the A / D conversion process be repeated,
An A / D converter comprising: addition means for adding the digital signals having the same phase as the digital signals that have been A / D converted in the first order and the digital signals that have been A / D converted in the second order.   The measurement apparatus using the A / D converter according to claim 1, wherein the predetermined number of times corresponds to a time required for one measurement.

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