JP2010062565A6 - Manufacturing method of semiconductor device - Google Patents

Abstract

A gate length of a semiconductor device is stably manufactured by using an end point detection method by monitoring plasma emission in dry etching for determining a gate length.
A method of manufacturing a semiconductor device in which a source diffusion layer, a drain diffusion layer, and a columnar semiconductor layer are arranged hierarchically in a vertical direction on a substrate, and a gate is arranged on a side wall of the columnar semiconductor layer. A first insulating film or a conductive film is formed so as to embed the layer, and the first insulating film or the conductive film is planarized by detecting an end point with a stopper formed on the columnar semiconductor layer. Forming a conductive film, etching the second insulating film or conductive film, calculating an etching rate during etching, and etching back the second insulating film or conductive film, the second insulating film or conductive film The etching amount of the first insulating film or the conductive film is controlled by detecting the etching end point of the first insulating film or the conductive film using the etching rate.
[Selection] Figure 1

Description

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to an SGT (Surrounding Gate Transistor) which is a vertical MOS transistor having a columnar semiconductor layer, a side wall of which is a channel region, and a gate electrode surrounding the channel region. The present invention relates to a structure and a manufacturing method thereof.

In order to realize high integration and high performance of a semiconductor device, an SGT is a vertical gate transistor having a columnar semiconductor layer formed on the surface of a semiconductor substrate and having a gate formed on the side wall so as to surround the columnar semiconductor layer. (Surrounding Gate Transistor) has been proposed (for example, Patent Document 1: JP-A-2-188966). In the SGT, the drain, gate and source are arranged in the vertical direction, so that the occupied area can be greatly reduced as compared with the conventional planar type transistor.

FIG. 22A shows a plan view of a CMOS inverter configured using the SGT of Patent Document 1, and FIG. 22B shows a cross-sectional structure of the cut line AA ′ in the plan view of FIG. Show.
22A and 22B, an N well 302 and a P well 303 are formed on the Si substrate 301, and a columnar silicon layer 305 for forming a PMOS in the N well region is formed on the Si substrate surface. A columnar silicon layer 306 for forming an NMOS is formed in the region, and a gate 308 is formed so as to surround each columnar silicon layer. The P + drain diffusion layer 310 formed below the columnar semiconductor forming the PMOS and the N + drain diffusion layer 312 formed below the columnar semiconductor forming the NMOS are connected to the output terminal Vout, and the columnar silicon layer forming the PMOS. The source diffusion layer 309 formed at the top is connected to the power supply potential Vcc, the source diffusion layer 311 formed at the top of the columnar silicon layer forming the NMOS is connected to the ground potential Vss, and the common gate 308 of PMOS and NMOS is A CMOS inverter is formed by being connected to the input terminal Vin.

A process flow is shown in Non-Patent Document 1 as an example of a manufacturing method of SGT. The outline of the SGT columnar silicon layer and gate electrode formation process flow of Non-Patent Document 1 is shown in FIG. This process flow will be described below. Using the silicon substrate shown in FIG. 23A, the columnar silicon layer 403 is formed by etching the silicon substrate 402 as shown in FIG. 23B. As shown in FIG. 23C, a gate insulating film 404 is formed. As shown in FIG. 23D, a gate conductive film 405 is formed. As shown in FIG. 23E, the gate conductive film 405 and the gate insulating film 404 above the columnar silicon layer are polished by CMP. As shown in FIG. 23F, the gate conductive film 405 is etched back to process the gate conductive film 405 surrounding the columnar silicon layer so as to have a desired gate length. As shown in FIG. 23G, a gate wiring pattern resist 406 is formed by lithography. As shown in FIG. 23H, the gate conductive film 405 is etched to form a gate electrode and a gate wiring.

Japanese Patent Laid-Open No. 2-188966

Ruigan Li et al. "50nm Vertical Surrounding Gate MOSFET with S-factor of 75mv / dec", Device Research Conference, 2001, p. 63

However, the SGT manufacturing method shown in FIG. 21 has the following problems.
In the above process flow, since the end point detection method by monitoring the fluctuation of the plasma emission intensity cannot be used in the dry etching of the gate electrode, the time-designated etching must be used. In this case, since the gate length is directly affected by the variation in the etching rate of the apparatus during work for each lot and for each wafer, the variation in the gate length becomes very large. If the variation in gate length increases, the variation in transistor characteristics naturally increases.
Therefore, in order to reduce the variation in SGT characteristics, it is essential to use end point detection that can absorb fluctuations in the etching rate for each lot and for each wafer in the etching of the gate length.

The present invention has been made in view of the above circumstances, and an object thereof is to stably manufacture a gate length by using an endpoint detection method by monitoring plasma emission in dry etching for determining a gate length. To do.

According to one aspect of the present invention, a semiconductor device is manufactured in which a source diffusion layer, a drain diffusion layer, and a columnar semiconductor layer are arranged hierarchically in a vertical direction on a substrate, and a gate is arranged on a sidewall of the columnar semiconductor layer. A way to
A columnar semiconductor layer is disposed on the surface of the semiconductor substrate, and an insulating film is disposed on the surfaces of the semiconductor substrate and the columnar semiconductor layer,
The method
Forming a first gate conductive film so as to cover a hard mask formed on the columnar semiconductor layer and a surface of the columnar semiconductor layer;
Planarizing an upper portion of the first gate conductive film using the hard mask as a stopper;
Forming a second gate conductive film on the planarized surface of the first gate conductive film;
Anisotropically etching the second gate conductive film;
Monitoring the plasma emission intensity generated from the second gate conductive film during the etching and detecting the etching end point of the second gate conductive film from the change in the plasma emission intensity;
And anisotropically etching the first gate conductive film,
The etching rate of the second gate conductive film calculated from the time required from the start to the end of the etching of the second gate conductive film and the film thickness of the second gate conductive film, and the first gate conductive The end point of the etching of the first gate conductive film is detected by specifying the etching rate of the first gate conductive film using the relative ratio of the etching rates of the film and the second gate conductive film. A method of manufacturing a semiconductor device is provided.
In a preferred aspect of the present invention, in the semiconductor device manufacturing method, both the first gate conductive film and the second gate conductive film are polysilicon. In another preferred aspect of the present invention, in the method for manufacturing a semiconductor device, the first gate conductive film and the second gate conductive film are the same metal film. According to still another preferred aspect of the present invention, in the method for manufacturing a semiconductor device, the first gate conductive film and the second gate conductive film are different metal films.
According to another aspect of the present invention, a semiconductor device is manufactured in which a source diffusion layer, a drain diffusion layer, and a columnar semiconductor layer are arranged hierarchically in a vertical direction on a substrate, and a gate is arranged on a sidewall of the columnar semiconductor layer. A way to
A columnar semiconductor layer is disposed on the surface of the semiconductor substrate,
The method
Forming a first insulating film so as to cover a hard mask formed on the columnar semiconductor layer and a surface of the columnar semiconductor layer;
Planarizing an upper portion of the first insulating film using the hard mask as a stopper;
Forming a second insulating film on the planarized surface of the first insulating film;
Etching the second insulating film anisotropically;
Monitoring the plasma emission intensity generated from the second insulating film during the etching, and detecting the etching end point of the second insulating film from the change in the plasma emission intensity;
And anisotropically etching the first insulating film,
The etching rate of the second insulating film calculated from the time required from the start to the end of etching of the second insulating film and the film thickness of the second insulating film, the first insulating film, and the first insulating film An end point of etching of the first insulating film is detected by specifying the etching rate of the first insulating film using the relative ratio of the etching rate to the second insulating film. A manufacturing method is provided.
In a preferred aspect of the present invention, in the method for manufacturing a semiconductor device, both the first insulating film and the second insulating film are silicon oxide films.

It is the top view and sectional drawing of SGT of this invention. It is process drawing which shows the manufacturing method of this invention in process order. It is process drawing which shows the manufacturing method of this invention in process order. It is process drawing which shows the manufacturing method of this invention in process order. It is process drawing which shows the manufacturing method of this invention in process order. It is process drawing which shows the manufacturing method of this invention in process order. It is process drawing which shows the manufacturing method of this invention in process order. It is process drawing which shows the manufacturing method of this invention in process order. It is process drawing which shows the manufacturing method of this invention in process order. It is a figure which shows the plasma emission characteristic at the time of using this invention. It is process drawing which shows the manufacturing method of this invention in process order. It is process drawing which shows the manufacturing method of this invention in process order. It is process drawing which shows the manufacturing method of this invention in process order. It is process drawing which shows the manufacturing method of this invention in process order. It is the top view and sectional drawing of SGT of this invention. It is process drawing which shows the manufacturing method of this invention in process order. It is process drawing which shows the manufacturing method of this invention in process order. It is process drawing which shows the manufacturing method of this invention in process order. It is process drawing which shows the manufacturing method of this invention in process order. It is process drawing which shows the manufacturing method of this invention in process order. It is process drawing which shows the manufacturing method of this invention in process order. It is the top view and sectional drawing of the conventional SGT. It is a figure which shows the manufacturing method of the conventional SGT.

Hereinafter, a method for manufacturing an SGT capable of detecting the end point by monitoring the plasma emission intensity in the dry etching of the gate electrode will be described.

Embodiment 1 of the present invention provides a method for accurately controlling the etching amount of a gate electrode by using an end point detection method using a plasma emission intensity monitor when the gate electrode is formed by dry etching.
FIG. 1 shows a plan view (a) of an SGT targeted by the present invention and a cross-sectional view (b) along AA ′. The NMOS SGT used in this example will be described below with reference to FIG.
A columnar silicon layer 102 is formed on the silicon substrate 101, and a gate insulating film 105 and a gate electrode 106 a are formed around the columnar silicon layer 102. An N + drain diffusion layer 103 is formed below the columnar silicon layer 102, and an N + source diffusion layer 104 is formed above the columnar silicon layer 102. A contact 107 is formed on the N + drain diffusion layer 103, a contact 108 is formed on the N + source diffusion layer 104, and a contact 109 is formed on the gate wiring 106b extending from the gate electrode 106a.
The SGT performs transistor operation by connecting the N + source diffusion layer 104 to the GND potential, connecting the N + drain diffusion layer 103 to the Vcc potential, and applying a potential of 0 to Vcc to the gate electrode 106a. Actually, the source diffusion layer and the drain diffusion layer may operate in a switched state.

FIG. 2 to FIG. 14 show an example of a manufacturing method that enables the accurate columnar silicon layer to be etched. In each figure, (a) is a plan view and (b) is a cross-sectional view taken along line A-A ′.

As shown in FIG. 2, a pad oxide film 112 is formed on the silicon substrate 101 to relieve stress between the silicon substrate and the hard mask, and then a silicon nitride film 110 as a hard mask is formed.

As shown in FIG. 3, the resist is patterned by lithography using a columnar silicon layer mask, and the pad oxide film 112 and the hard mask 110 are patterned by dry etching.

As shown in FIG. 4, the silicon layer is etched using the hard mask 110 to form the columnar silicon layer 102.

As shown in FIG. 5, an N + diffusion layer 103 is formed in the diffusion layer below the columnar silicon layer by impurity implantation or the like.

As shown in FIG. 6, a gate insulating film 105 is formed. Subsequently, for example, polysilicon is deposited as the first gate conductive film 106 so as to embed the columnar silicon layer 102.

As shown in FIG. 7, the first gate conductive film 106 and the gate insulating film 105 on the columnar silicon layer are polished by CMP, and the upper surface of the first gate conductive film 106 is planarized. By planarizing the upper portion of the first gate conductive film 106 by CMP, the gate length can be easily controlled as will be described later. In the CMP, the first hard mask 110 on the columnar silicon layer is used as a CMP stopper. By using, for example, a silicon nitride film as the hard mask, the selectivity with respect to the gate conductive film can be increased, so that the CMP polishing amount can be controlled with high reproducibility.

As shown in FIG. 8, polysilicon is deposited as the second gate conductive film 111.

As shown in FIG. 9, the second gate conductive film 111 is etched back. In the figure, the structure at the time when the hard mask is exposed and the end point is detected is shown.
As shown in the plasma emission characteristics at the time of etch back in FIG. 10A, when the etching is started (point A1), the emission intensity rapidly increases. When the hard mask begins to be exposed, the amount of polysilicon to be etched decreases, and the emission intensity begins to decrease (point B1). By monitoring the decrease in the emission intensity, the end point of etching can be detected.
Since the film thickness of the second gate conductive film until the hard mask is exposed is determined by the amount of film formation, the etching rate of the second gate conductive film 111 can be calculated using the time from the start to the end of etching. Can do. In this regard, as described above, since the upper portion of the first gate conductive film 106 has been polished and planarized in advance, the amount of the etched second gate conductive film and the etching time can be accurately specified. Therefore, the etching rate of the second gate conductive film can be calculated with high accuracy. When this rate is used, the overetch amount for a desired film thickness can be calculated in consideration of the etching rate at the time of etching, so that the gate length can be stably formed. That is, from the etching rate of the second gate conductive film calculated when the second gate conductive film is actually etched and the relative ratio of the etching rates of the first gate conductive film and the second gate conductive film. Then, the etching rate when actually etching the first gate conductive film can be calculated. Then, from the etching rate of the first gate conductive film, the etching time until the first gate conductive film has a desired film thickness can be obtained with high accuracy.
At this time, the columnar silicon layer is protected from etching by the first hard mask 110 on the columnar silicon layer.

In the above description, the first gate conductive film and the second gate conductive film are both polysilicon, but the first gate conductive film and the second gate conductive film may be the same metal film.
Further, the first gate conductive film and the second gate conductive film may be different metal films. In this case, the plasma emission characteristics from the second gate conductive film are as shown in FIG. When etching is started (point A2), the light emission intensity increases rapidly. When the hard mask is exposed, the second gate conductive film disappears, and the light emission intensity begins to decrease (point B2). By monitoring the decrease in the emission intensity, the end point of etching can be detected.
If the relative ratio of the etching rates of the first gate conductive film and the second gate conductive film is known, the first gate conductive film and the second gate conductive film may be made of the same material or different materials. The etching amount of the gate conductive film can be controlled.

By specifying the etching time from the etching rate of the first conductive film with high accuracy as described above, a gate electrode having a desired gate length is formed after dry etching, as shown in FIG. Is done.

As shown in FIG. 12, the pad oxide film 112 and the hard mask 110 are removed by dry etching or wet etching. Subsequently, by patterning the gate electrode, the gate electrode 106a surrounding the columnar silicon layer and the gate wiring 106b for forming a contact or the like are formed.

As shown in FIG. 13, the diffusion layer 104 on the upper part of the columnar silicon layer is formed by impurity implantation or the like.

As shown in FIG. 14, the transistor is formed by forming an interlayer film and forming contacts (107, 108, 109).

In the second embodiment of the present invention, when the silicon oxide film inserted between the lower part of the columnar silicon layer and the gate electrode is formed by dry etching in order to reduce the gate capacitance, the end point detection method by the plasma emission intensity monitor A method for accurately controlling the etching amount of a silicon oxide film is provided.
FIG. 15 shows a plan view (a) and a cross-sectional view (b) along AA ′ of the SGT targeted by the present invention. The NMOS SGT used in this example will be described below with reference to FIG.
A columnar silicon layer 202 is formed on the silicon substrate 201, and a gate insulating film 205 and a gate electrode 206 a are formed around the columnar silicon layer 202. An N + drain diffusion layer 203 is formed below the columnar silicon layer 202, and an N + source diffusion layer 204 is formed above the columnar silicon layer 202. A silicon oxide film 213 is formed between the N + drain diffusion layer 203 and the gate electrodes (206a, 206b) in order to reduce the gate capacitance. A contact 207 is formed on the N + drain diffusion layer 203, a contact 208 is formed on the N + source diffusion layer 204, and a contact 209 is formed on the gate wiring 206b extending from the gate electrode 206a. Since the silicon oxide film 213 is as thin as several tens of nm, it is necessary to control the film thickness accurately.
The SGT performs transistor operation by connecting the N + source diffusion layer 204 to the GND potential, connecting the N + drain diffusion layer 203 to the Vcc potential, and applying a potential of 0 to Vcc to the gate electrode 206a. Actually, the source diffusion layer and the drain diffusion layer may operate in a switched state.

FIG. 16 to FIG. 21 show an example of a method for manufacturing the above SGT. In each figure, (a) is a plan view and (b) is a cross-sectional view taken along line A-A ′. Since the process up to the formation of the N + diffusion layer in FIG. 5 is the same as that in the first embodiment, the subsequent steps will be described.

As shown in FIG. 16, a silicon oxide film 213 is formed so as to embed the columnar silicon layer 202.

As shown in FIG. 17, the silicon oxide film 213 above the columnar silicon layer is polished by CMP to planarize the upper surface of the silicon oxide film. In the CMP, the hard mask 210 on the columnar silicon layer is used as a CMP stopper. By using, for example, a silicon nitride film as the hard mask, the selectivity with respect to the silicon oxide film can be increased, so that the CMP polishing amount can be controlled with high reproducibility.

As shown in FIG. 18, a silicon oxide film 213 is formed so as to embed the columnar silicon layer 202.

As shown in FIG. 19, the silicon oxide film is etched back. In the figure, the structure at the time when the silicon nitride film as a hard mask is exposed and the end point is detected is shown. The algorithm used for end point detection is the same as in the case of the first embodiment (FIG. 6).

When the silicon oxide film is etched back, the etching rate of the silicon oxide film 213 is calculated as in the first embodiment, and the etching time from the etching rate to the desired film thickness is specified. Thus, as shown in FIG. 20, after dry etching, a silicon oxide film 213 having a desired thickness is formed on the N + diffusion layer 203 in order to reduce the gate capacitance.

As shown in FIG. 21, a gate insulating film 205 and a gate conductive film 206 are formed. Since the subsequent steps are the same as those in the first embodiment, they are omitted here.

The present invention is not limited to the above-described embodiment, and includes a step of forming a first insulating film or conductive film so as to embed a columnar semiconductor layer, and the first insulating film or conductive film is formed on the columnar semiconductor layer. A step of detecting the end point using a stopper and flattening, a step of forming a second insulating film or conductive film, and a step of etching the second insulating film or conductive film and calculating an etching rate at the time of etching And detecting the end point of etching of the first insulating film or conductive film using the etching rate of the second insulating film or conductive film when etching back the second insulating film or conductive film, If it is a manufacturing method including the process of controlling the etching amount of a 1st insulating film or a electrically conductive film, it will not restrict | limit to the above-mentioned Example.

As described above, according to the manufacturing method of the present invention, it is possible to control the etching amount using end point detection in dry etching for forming the gate electrode of the SGT. The length can be manufactured stably. As a result, an SGT having stable characteristics can be manufactured.

101, 201: silicon substrate 102, 202: columnar silicon layer 103, 203: lower diffusion layer 104, 204: upper diffusion layer 105, 205: gate insulating film 106: first gate conductive film 106a: gate electrode 106b: Gate wiring 107, 108, 109: Contact 110, 210: Hard mask 111: Second gate conductive film 112, 212: Pad oxide film 213: Silicon oxide film 301: Silicon substrate 302: N well 303: P well 305: PMOS Columnar silicon layer 306: NMOS columnar silicon layer 308: Gate 309: P + source diffusion layer 310: P + drain diffusion layer 311: N + source diffusion layer 312: N + drain diffusion layer 402: Silicon substrate 403: Columnar silicon layer 404: Gate insulating film 405: Gate conductive film 406: Register Door

Claims (6)

A method of manufacturing a semiconductor device in which a source diffusion layer, a drain diffusion layer, and a columnar semiconductor layer are arranged hierarchically in a vertical direction on a substrate, and a gate is arranged on a sidewall of the columnar semiconductor layer,
A columnar semiconductor layer is disposed on the surface of the semiconductor substrate, and an insulating film is disposed on the surfaces of the semiconductor substrate and the columnar semiconductor layer,
The method
Forming a first gate conductive film so as to cover a hard mask formed on the columnar semiconductor layer and a surface of the columnar semiconductor layer;
Planarizing an upper portion of the first gate conductive film using the hard mask as a stopper;
Forming a second gate conductive film on the planarized surface of the first gate conductive film;
Anisotropically etching the second gate conductive film;
Monitoring the plasma emission intensity generated from the second gate conductive film during the etching and detecting the etching end point of the second gate conductive film from the change in the plasma emission intensity;
And anisotropically etching the first gate conductive film,
The etching rate of the second gate conductive film calculated from the time required from the start to the end of the etching of the second gate conductive film and the film thickness of the second gate conductive film, and the first gate conductive The end point of the etching of the first gate conductive film is detected by specifying the etching rate of the first gate conductive film using the relative ratio of the etching rates of the film and the second gate conductive film. A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein both the first gate conductive film and the second gate conductive film are polysilicon.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first gate conductive film and the second gate conductive film are the same metal film.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first gate conductive film and the second gate conductive film are different metal films. A method of manufacturing a semiconductor device in which a source diffusion layer, a drain diffusion layer, and a columnar semiconductor layer are arranged hierarchically in a vertical direction on a substrate, and a gate is arranged on a sidewall of the columnar semiconductor layer,
A columnar semiconductor layer is disposed on the surface of the semiconductor substrate,
The method
Forming a first insulating film so as to cover a hard mask formed on the columnar semiconductor layer and a surface of the columnar semiconductor layer;
Planarizing an upper portion of the first insulating film using the hard mask as a stopper;
Forming a second insulating film on the planarized surface of the first insulating film;
Etching the second insulating film anisotropically;
Monitoring the plasma emission intensity generated from the second insulating film during the etching, and detecting the etching end point of the second insulating film from the change in the plasma emission intensity;
And anisotropically etching the first insulating film,
The etching rate of the second insulating film calculated from the time required from the start to the end of etching of the second insulating film and the film thickness of the second insulating film, the first insulating film, and the first insulating film An end point of etching of the first insulating film is detected by specifying the etching rate of the first insulating film using the relative ratio of the etching rate to the second insulating film. Production method.   6. The method of manufacturing a semiconductor device according to claim 5, wherein both the first insulating film and the second insulating film are silicon oxide films.

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