JP2010062237A - Method of manufacturing semiconductor integrated circuit apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a means that prevents a needle position from drastically varying with elapsed time even when a wafer chuck as a heat source separates from a probe card in a wafer test in which the probe card is heated to a card temperature corresponding to a test temperature, by locating a wafer stage as a heat source immediately under the probe card together with a tested wafer. <P>SOLUTION: In a probe test in which a probe card is preheated, when a wafer stage as a heating source moves to a position different from a predetermined heating position and does not return in a relatively long time, whether or not the stay is indispensable for the inspection is determined. If the stay is not indispensable, the wafer stage is returned to a waiting position immediately under the probe card. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a technique effective when applied to a wafer test technique in a method of manufacturing a semiconductor integrated circuit device (or a semiconductor device).

  Japanese Patent Application Laid-Open No. 2004-266206 (Patent Document 1) discloses a technique for heating a probe card in advance by a preheating hot plate having approximately the same size as a wafer to be inspected in a probe test. ing.

  In Japanese Patent Laid-Open No. 6-349909 (Patent Document 2), in the probe test, a dedicated heating / cooling means for heating or cooling the wafer to be inspected and the probe card, respectively, is provided. A technique for controlling the probe cards to the same temperature is disclosed.

JP 2004-266206 A JP-A-6-349909

  In a wafer test in the manufacturing process of a semiconductor device, a wafer stage, which is a heat source (cooling source), is positioned together with a wafer to be tested directly under the probe card, so that the probe card is subjected to test temperature (by convection or radiation) The wafer is heated or cooled to a card temperature corresponding to the wafer temperature at the time of testing. For example, when probing at a high temperature exceeding 100 degrees Celsius and a temperature below 20 degrees Celsius below 20 degrees Celsius, the probe card variation due to heat is saturated and the test is started after the position does not vary. This waiting time is about 2 hours when it is long. When observing the wafer with a camera in the prober for checking the needle trace on the bonding pad on the wafer during the probe test, the wafer chuck (wafer stage) as the heat source is removed from the probe card. Because of the separation, the probe card cools during high temperature testing and warms during low temperature testing. As a result, the needle position changes, and the amount of change increases with the elapsed time. Further, when the needle mark confirmation is performed outside the prober, the prober may leave the prober and may be left for a long time. For this reason, when the test is resumed, a waiting time comparable to that before the start of the test is required, and work efficiency is remarkably deteriorated.

  The present invention has been made to solve these problems.

  An object of the present invention is to provide an efficient manufacturing process of a semiconductor integrated circuit device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, according to the present invention, in the probe test performed by preheating the probe card, the wafer stage as a heating source moves to a position different from a predetermined heating position, and is relatively long (first time or more). If it does not return, it is determined whether or not the stay is indispensable for inspection. If it is not indispensable, the wafer stage is returned to the standby position directly below the probe card.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, when a probe test is performed by preheating the probe card, the wafer stage as a heating source moves to a position different from the predetermined heating position and does not return for a relatively long time (first time or more). In this case, it is determined whether or not the stay is indispensable for inspection, and if it is not indispensable, the wafer stage is returned to the standby position immediately below the probe card. It is possible to avoid a prolonged wafer test time due to a cause such as a decrease in temperature of the probe card due to a long stay due to standby or the like.

[Outline of Embodiment]
First, an outline of a typical embodiment of the invention disclosed in the present application will be described.

1. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) setting a wafer on a wafer stage held at a first temperature different from room temperature in a wafer prober;
(B) After the step (a), in the wafer prober, moving the wafer stage in which the wafer is set and held at the first temperature below the probe card;
(C) After the step (b), in the wafer prober, the wafer stage set and held at the first temperature is below the probe card, Performing an electrical test on the wafer to be inspected at the first temperature using the probe card;
(D) after the step (c), the step of moving the wafer stage, in which the wafer is set and held at the first temperature, to the outside of the probe card in the wafer prober;
(E) after the step (d), moving the wafer on the wafer stage held at the first temperature outside the wafer stage in the wafer prober;
Here, during the operation of the wafer prober, the idle time during which the wafer stage is not under the probe card and the wafer prober is not operating effectively is monitored. If the idle time exceeds the first time interval, the wafer is set, and the wafer stage held at the first temperature is automatically moved below the probe card. And let's wait there.

  2. In the method for manufacturing a semiconductor integrated circuit device according to the item 1, the first temperature is not less than 100 degrees Celsius and not more than 200 degrees Celsius.

  3. In the method of manufacturing a semiconductor integrated circuit device according to the item 1, the first temperature is minus 70 degrees Celsius or more and 0 degrees Celsius or less.

  4). 4. The method of manufacturing a semiconductor integrated circuit device according to any one of items 1 to 3, wherein the semiconductor integrated circuit device has a flash memory unit.

  5. 5. The method for manufacturing a semiconductor integrated circuit device according to any one of 1 to 4, wherein the semiconductor integrated circuit device has a logic unit.

  6). 6. The method of manufacturing a semiconductor integrated circuit device according to any one of 1 to 5, wherein the probe card is a cantilever type.

  7). 6. The method of manufacturing a semiconductor integrated circuit device according to any one of items 1 to 5, wherein the probe card is an advanced type.

  8). 8. The method of manufacturing a semiconductor integrated circuit device according to any one of 1 to 7, wherein the first time interval is not less than 2 minutes and less than 20 minutes.

  9. In the method of manufacturing a semiconductor integrated circuit device according to the item 4, the electrical test includes a data retention test of the flash memory unit.

  10. 6. The manufacturing method of a semiconductor integrated circuit device according to the item 5, wherein the electrical test includes a function test of the logic unit.

11. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) loading a wafer transfer container containing a plurality of wafers into a wafer prober;
(B) after the step (a), transferring a first wafer of the plurality of wafers in the wafer transfer container into the wafer prober;
(C) setting the first wafer on a wafer stage held at a first temperature different from normal temperature in the wafer prober;
(D) After the step (c), the step in which the first wafer is set in the wafer prober and the wafer stage held at the first temperature is moved below the probe card. ;
(E) After the step (d), the wafer stage in which the first wafer is set and maintained at the first temperature is below the probe card in the wafer prober. Waiting for the temperature of the probe card to stabilize;
(F) After the subsequent steps of steps (d) and (e), the wafer stage in which the first wafer is set and held at the first temperature in the wafer prober. Performing an electrical test on the first wafer at the first temperature using the probe card with the probe card underneath the probe card;
(G) After the step (f), in the wafer prober, the first wafer is set, and the wafer stage held at the first temperature is moved out of the probe card. The step of causing;
(H) After the step (g), in the state where the first wafer is set and the wafer stage held at the first temperature is moved to the lower outside of the probe card, Performing a needle mark inspection on a wafer of
(I) after the later steps of the steps (g) and (h), the first wafer on the wafer stage held at the first temperature in the wafer prober; Moving the wafer stage to the outside;
(J) After the step (i), a step of transferring the first wafer into the wafer transfer container;
(K) After the step (i), the steps (b) to (d), step (b) are sequentially performed on each wafer other than the first wafer among the plurality of wafers in the wafer transfer container. repeating steps f) to (g) and steps (i) to (j);
Here, during the operation of the wafer prober, the idle time during which the wafer stage is not under the probe card and the wafer prober is not operating effectively is monitored. If the idle time exceeds the first time interval, the first wafer is set, and the wafer stage held at the first temperature is automatically moved below the probe card. Move to and wait there.

  12 12. In the method for manufacturing a semiconductor integrated circuit device according to the item 11, the first temperature is not less than 100 degrees Celsius and not more than 200 degrees Celsius.

  13. 12. In the method for manufacturing a semiconductor integrated circuit device according to the item 11, the first temperature is minus 70 degrees Celsius or more and 0 degrees Celsius or less.

  14 14. The method for manufacturing a semiconductor integrated circuit device according to any one of 11 to 13, wherein the semiconductor integrated circuit device has a flash memory unit.

  15. 15. The method for manufacturing a semiconductor integrated circuit device according to any one of 11 to 14, wherein the semiconductor integrated circuit device has a logic unit.

  16. 16. The method of manufacturing a semiconductor integrated circuit device according to any one of 11 to 15, wherein the probe card is a cantilever type.

  17. 16. The manufacturing method of a semiconductor integrated circuit device according to any one of 11 to 15, wherein the probe card is an advanced type.

  18. 18. In the method for manufacturing a semiconductor integrated circuit device according to any one of 11 to 17, the first time interval is not less than 2 minutes and less than 20 minutes.

  19. 15. The manufacturing method of a semiconductor integrated circuit device according to the item 14, wherein the electrical test includes a data retention test of the flash memory unit.

  20. 16. The method for manufacturing a semiconductor integrated circuit device according to the item 15, wherein the electrical test includes a function test of the logic unit.

  21. 21. In the method of manufacturing a semiconductor integrated circuit device according to any one of 11 to 20, the step (e) is performed between steps (d) and (f) on the second wafer next to the first wafer. The process of performing.

22. 24. In the method of manufacturing a semiconductor integrated circuit device according to any one of Items 1 to 21, when the wafer stage is waiting below the probe card, the wafer stage is compared with a non-measurement movement time. Wait in close proximity to the probe card.
23. 23. In the method of manufacturing a semiconductor integrated circuit device according to the item 22, the clearance between the probe card and the wafer on the wafer stage when the wafer stage is waiting is below the probe card. This is almost the same as the clearance when moving the measurement point.

[Description format, basic terms, usage in this application]
1. In the present application, the description of the embodiment may be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Each part of a single example, one part is the other part of the details, or part or all of the modifications. Moreover, as a general rule, the same part is not repeated. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  2. Similarly, in the description of the embodiment, etc., regarding the material, composition, etc., “X consisting of A” etc. is an element other than A unless specifically stated otherwise and clearly not in context. It is not excluded that one of the main components. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but also includes SiGe alloys, other multi-component alloys containing silicon as a main component, and members containing other additives. Needless to say.

  Needless to say, “gold wire” includes not only high-purity ones but also gold-containing main components (gold-based metal). Similarly, “aluminum pads” and the like are not limited to those of high purity, but of course include those containing aluminum as a main component and containing various additives (aluminum-based metal). Needless to say, the pads are not limited to those made of only the aluminum-based metal layer, and include those whose main component is the aluminum-based metal layer.

  3. Similarly, suitable examples of graphics, positions, attributes, and the like are given, but it is needless to say that the present invention is not strictly limited to those cases unless explicitly stated otherwise, and unless otherwise apparent from the context.

  For example, “square”, “rectangular”, or “rectangular” does not mean a geometrically exact figure, but indicates that the shape is almost similar to that figure. . Therefore, it goes without saying that chamfering, chamfering, slight unevenness and the like are allowed.

  4). In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  5. “Wafer” usually refers to a single crystal silicon wafer on which a semiconductor integrated circuit device (same as a semiconductor device and an electronic device) is formed, but an insulating substrate such as an epitaxial wafer, an SOI substrate, an LCD glass substrate and the like. Needless to say, a composite wafer such as a semiconductor layer is also included. The wafer divided into individual integrated circuit devices is called a “semiconductor chip” or simply “chip”. In the present application, the semiconductor as the substrate mainly refers to a silicon-based semiconductor, but may be a GaAs-based or other compound-based semiconductor.

  6). “Actual bonding pad” means an aluminum pad or the like that actually bonds a gold wire or the like thereto. On the other hand, the “dummy pad” actually means an inspection aluminum pad or the like in which a gold wire or the like is not bonded thereto. These are collectively referred to as “bonding pads”.

  7). The “actual probe needle” is a probe inspection needle that is tested against an actual bonding pad. On the other hand, the “dummy probe needle” is a needle for placing a probe mark on the dummy pad. These are collectively referred to as “probe needles”. Further, the “probe mark” is an indentation made when the actual probe needle or the dummy probe needle contacts.

  8). “Idle time” refers to the length of time during which the wafer prober is not operating effectively during the operation of the wafer prober. Say. Therefore, even if the needle trace inspection takes a longer time than the normal required time, the idle time is zero when the processing is proceeding normally. On the other hand, even if the standard processing time has not yet elapsed since the start of the needle trace inspection, if the stop state (for example, a manual waiting state) continues unnecessarily, it corresponds to an idle time.

[Details of the embodiment]
The embodiment will be further described in detail. In the drawings, the same or similar parts are denoted by the same or similar symbols or reference numerals, and description thereof will not be repeated in principle.

1. Description of chip layout and the like of semiconductor integrated circuit device manufactured by manufacturing method of semiconductor integrated circuit device according to one embodiment of the present application (mainly FIG. 6)
FIG. 6 is an overall chip layout diagram of a semiconductor integrated circuit device manufactured by the method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present application. Based on this, a chip layout and the like of the semiconductor integrated circuit device manufactured by the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application will be described.

  First, the entire chip layout will be described. As shown in FIG. 6, there is an integrated circuit portion 7 in the device main surface 1a of a substantially square or rectangular semiconductor chip 1 (chip region), and an interface portion extends along each side in the peripheral region around it. Is provided. In this interface part, rectangular aluminum bonding pads 3 (actual bonding pads) having a rectangular shape (substantially the same shape, the same dimensions, the same orientation, and the same material) are substantially linear (intervals are not always equal). ) Is arranged. The actual bonding pad may be square, but in view of various process requirements, a rectangular area is advantageous.

  In the chip corner portion, there is a dummy pad 5 (substantially the same material as the bonding pad 3) having a substantially square shape and an area smaller than that of the actual bonding pad 3. Needless to say, the dummy pad 5 is not necessarily square. Any structure can be used as long as the direction and distance of contact position deviation can be easily recognized.

2. Description of the main part of the manufacturing process such as probe inspection in the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present application (mainly FIGS. 7 and 9 to 12)
FIG. 7 is a process block flow diagram for explaining a main part of the manufacturing process such as probe inspection by the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. FIG. 9 is a schematic cross-sectional view of an example of the final form of the semiconductor integrated circuit device according to the manufacturing method of the semiconductor integrated circuit device of one embodiment of the present application. FIG. 10 is a schematic top view of a probe test state for explaining a state of probe inspection in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. FIG. 11 is an enlarged view of a portion indicated by a broken line P in FIG. FIG. 12 is a schematic front view of a probe test state and the like for explaining a state of probe inspection and probe mark inspection in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. Based on these drawings, a description will be given of the main part of the manufacturing process such as probe inspection by the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application.

  First, as shown in FIG. 7, a wafer test 131 is executed by the prober 51 (FIG. 12) on the wafer 11 for which the wafer process 71 has been completed. As shown in FIGS. 10 and 12, the prober 51 is divided into a wafer probe unit 59 and a wafer alignment unit 57 (also serving as an internal needle trace inspection unit or an internal probe trace inspection unit). In the probe test execution step 107 (FIG. 1) in the wafer test 131 (FIG. 7), an actual probe provided in the periphery of the probe card 50 with the opening 49 facing the chip area 1 to be inspected. The electrical test is executed with the tips of the needle 47 and the dummy probe needle 48 in contact with the corresponding actual bonding pad 3 and dummy pad 5, respectively. In the probe inspection execution step 107 (FIG. 1), the wafer 11 is vacuum-sucked on the wafer stage 60. FIG. 11 shows an enlarged view of the point circle P in FIG.

  As shown in FIGS. 7 and 12, after executing the probe inspection 107, the wafer stage 60 moves to the probe mark inspection unit 57 with the wafer 11 placed thereon, where the optical observation system 63 causes the internal probe to move. Trace inspection 111 is performed. The probe mark inspection 111 is performed, for example, by observing how much the probe mark on the substantially square dummy pad 5 is displaced in which direction from the center of the dummy pad 5.

  Here, if the displacement of the contact position is within an allowable range, the wafer is sent to the next process, and the measured displacement is fed back to the alignment of the next wafer to be inspected. If there is data that doubts the normality of the probe test 107, for example, if the displacement of the contact position is above a certain level, the probe test 107 is executed again or the wafer is determined to be defective. Note that the probe mark inspection 111 may be skipped as necessary. That is, it may be executed for almost all product chip areas (or some product chip areas) and (if any) the inspection chip areas of all wafers, or a part of a lot For almost all product chip areas (or some product chip areas) and inspection chip areas of a wafer, or for almost all product chip areas (or some product chip areas) and inspection of some wafers The probe mark inspection 111 may be performed on at least one of the chip regions. The probe mark inspection 111 may be executed as the external needle mark inspection 112 (FIG. 1) using the external needle mark inspection device 61. In this case, however, it generally takes more time than using the internal needle trace inspection device 57.

  As shown in FIG. 7, the wafer 11 for which the last test by the prober 51 has been completed is subjected to a back-grinding process 73 and then a dicing process 74 for dividing into individual chips 1 is performed. Thereafter, as shown in FIGS. 9 and 7, the divided chip 1 is formed on a multilayer wiring board 33 (may be on a lead frame) through an adhesive member such as DAF (Die Attach Film). -Bonding 75 is performed. Subsequently, as shown in FIGS. 9 and 7, wire bonding 76 using a capillary is performed between the lead 32 and the actual bonding pad 3 by the gold wire 31 or the like. As a result, the bonding ball 12 is formed on the actual bonding pad 3.

  Thereafter, as shown in FIGS. 9 and 7, a resin sealing 77 is performed by a sealing resin 34 such as an epoxy resin, for example, by transfer molding (a compression molding method may be used). Furthermore, as shown in FIGS. 9 and 7, bumps 35 are attached.

  The wafer shipment product is directly transferred to the shipment process 80 after the back grinding process 73 is performed.

3. Detailed description of the wafer test process in the method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present application (mainly FIGS. 1 to 5, FIG. 8, and FIGS. 13 to 16)
In the following, a cantilever type probe card will be described as an example, but the present invention can be applied almost as it is to a probe test using an advanced probe card or the like described in section 4. In the following example, the high-temperature logic test 131c (FIG. 1 or 4) performed at a test temperature (first temperature) of about 100 degrees Celsius or more and 200 degrees Celsius or less will be specifically described. Low-temperature logic test 131d (FIG. 1 or 4) performed at a test temperature (first temperature) of 70 degrees or more and zero degrees or less, test temperature (first temperature) of 100 degrees Celsius or more and 200 degrees or less High-temperature memory test 131b (FIG. 1 or FIG. 4) performed at a low temperature and a low-temperature memory test performed at a test temperature (first temperature) of minus 70 degrees Celsius or more and zero degrees or less (generally, an extremely warm wafer probe)・ It can be applied almost as it is to the test. In the following, a semiconductor integrated circuit device (flash memory mixed chip) equipped with a flash memory portion (generally a memory portion) and a logic portion (logic test mainly tests this portion, for example, a function test). ) Test (for example, data retention test) will be described as an example, but it goes without saying that the present invention can also be applied to a semiconductor integrated circuit device having no flash memory section.

  FIG. 1 is a process block flow diagram showing the flow of wafer testing by individual probers in the method of manufacturing a semiconductor integrated circuit device according to one embodiment of the present application. FIG. 2 is a flowchart for explaining a wafer stage position control method in each prober in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. FIG. 3 is a process block flow diagram showing a flow of processing for wafer batches within individual probers in the method of manufacturing a semiconductor integrated circuit device according to one embodiment of the present application. FIG. 4 is a process block flow diagram illustrating the flow of the entire wafer test process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. FIG. 5 is a prober top view showing an example of a prober used in the wafer test process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. FIG. 8 is a block diagram showing an example of a configuration of a prober control system for explaining a wafer stage position control method in each prober in the method of manufacturing a semiconductor integrated circuit device according to one embodiment of the present application. FIG. 13 is an apparatus partial schematic front view for explaining the relationship between a probe card and a wafer in each prober in the method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention, taking a cantilever type probe card as an example. It is a figure (probe card part). FIG. 14 is a schematic diagram of an essential part of an apparatus for explaining the relationship between a probe card and a wafer in each prober in the method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention, taking a cantilever probe card as an example. It is a front process flow figure (at the time of probe standby). FIG. 15 is a schematic diagram of an essential part of an apparatus for explaining the relationship between a probe card and a wafer in each prober in the method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention, taking a cantilever probe card as an example. It is a front process flowchart (at the time of wafer alignment or a probe trace inspection). FIG. 16 is a schematic diagram of the main part of the apparatus for explaining the relationship between the probe card and the wafer in each prober in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present invention, taking a cantilever probe card as an example. It is a front process flow figure (at the time of needle position alignment). Based on these, the details of the wafer test process in the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present application will be described.

  First, the overall flow of the wafer test process will be described. As shown in FIG. 4, the wafer test process 131 for a flash memory mixed chip usually includes a measurement temperature (for example, a normal temperature of 25 degrees Celsius, a high temperature of 160 degrees Celsius, a low temperature of 40 degrees Celsius) and a test purpose (data). A plurality of probe test processes (first memory test 131a, second memory test 131b, first logic test 131c, first logic test, etc.) with different retention tests and other memory tests, logic tests, etc. 2 logic test 131d) and a high-temperature baking process (first baking process 141, second baking process 142) such as data retention bake performed at a temperature of about 250 degrees Celsius, for example. Yes. In a mass production process, if the temperature change frequency is high, the actual operation time of the prober decreases, and therefore, a plurality of probers 51a, 51b, 51c are usually provided for the combination of temperature and test purpose (memory test or logic test). , 51d, and the individual probers 51a, 51b, 51c, 51d execute the wafer test 131 while keeping the temperature as constant as possible. Of course, if the actual operating time of the prober may be reduced, the same prober may be used for wafer testing at different temperatures.

  Next, based on FIG. 1 and FIG. 5, the flow of a wafer test (a high temperature logic test 131c as an example of an emergency temperature wafer probe test) for each wafer will be described. As shown in FIG. 1, for example, a hoop that accommodates, for example, 25 (unit lots) of 300φ wafers (450φ, 200φ or other diameter wafers) in a load port 53 of a prober 51 (here, logic test). 52 (wafer transfer container) is installed (transfer container loading step 101 in FIG. 1). Next, the wafer 11 to be inspected is transferred from the hoop 52 to the pre-alignment unit 55 inside the prober 51 by the wafer robot 54 (wafer carry-in step 102 in FIG. 1). Next, in the pre-alignment unit 55, the pre-alignment optical system 62 recognizes a position recognition index (notch, orientation flat, etc.) on the circumference of the wafer 11, and confirms the orientation of the wafer 11 (FIG. 1). Pre-alignment step 103). The time required for this pre-alignment is usually about 30 seconds.

  Next, based on the result of the pre-alignment 103, the wafer 11 is set in a predetermined orientation on the wafer stage 60 set to the test temperature with the device surface 11a of the wafer 11 facing up (FIG. 1). Step 104). Next, the wafer stage 60 moves to the wafer alignment unit 57 according to the movement of the XY table 42 with the wafer 11 placed thereon, where the wafer alignment optical system 63 causes the wafer alignment 105 (FIG. 1). Is executed (required time is generally about 45 seconds). During the wafer alignment 105, as shown in FIG. 15, the XY table 42 is moved in the horizontal direction so that the wafer alignment optical system 63 is directly above the wafer stage 60. In this state, if necessary, the XY table 42 moves horizontally and the wafer stage 60 moves in the vertical direction to optically observe the device surface 11a of the wafer 11 and extract a registered reference graphic. Then, the reference point on the wafer is recognized. As can be seen from FIG. 15, the wafer alignment optical system 63 is fixed to the main body of the prober 51. Similarly, the probe card 50 is also fixed to the main body of the prober 51 through the card holder 44. On the other hand, the needle alignment optical system 64 and the wafer stage 60 are fixed on the XY table 42.

  Next, the XY table 42 shifts and the needle alignment optical system 64 moves to the lower part of the probe card 50, where the needle alignment 106 (FIG. 1) is executed (required time is generally 1 minute). Degree). Thus, the prober 51 has recognized the position of the circuit pattern on the wafer 11 and the position of the probe needle tip on the probe card 50. At the time of the needle alignment 106, the XY table 42 moves in the horizontal direction so that the needle alignment optical system 64 is located directly below the probe needle 46 of the probe card 50 as shown in FIG. In this state, if necessary, the XY table 42 moves horizontally, the wafer stage 60 moves in the vertical direction, the tip of the probe needle 46 serving as a reference is optically observed, and the probe needle 46 A reference point (a reference point on the probe card 50 side) is recognized.

  Next, the wafer stage 60 moves to the probe unit 59 according to the movement of the XY table 42 with the wafer 11 placed thereon. In this state, when the temperature of the probe card 50 and the test temperature are large, the process waits. When the temperature of the probe card 50 and the test temperature are small, an electrical test is performed with the probe needle in contact with the bonding pad on the wafer 11 (electrical test execution step 107 in FIG. 1). When the electrical test is executed, the XY table 42 is moved in the horizontal direction so that the wafer stage 60 comes directly under the probe card 50 as shown in FIG. Then, the XY table 42 comes closer to the probe card 50 than during normal movement. In this state, when the desired horizontal mutual position is reached, contact between the probe needle 46 and the bonding pad on the wafer 11 is performed, and an electrical test is performed. When the measurement at one place is completed, release, proximity movement, and contact operation (the entire wafer may be tested with a single contact, which is a so-called full wafer test) are repeated for the entire wafer 11. Perform electrical tests.

  When the electrical test 107 using the probe needle is completed, the wafer stage 60 moves to the wafer load & unload unit 56 according to the movement of the XY table 42 while the wafer 11 is placed. Therefore, the wafer robot 54 picks up the wafer 11 from the wafer stage 60 (wafer release step 108 in FIG. 1) and carries it out of the apparatus (wafer unloading step 109 in FIG. 1). When all the wafers have been electrically tested, the hoop 52 is unloaded from the load port 53 (wafer transfer container unload step 110 in FIG. 1).

  Here, after the electrical test execution step 107, a wafer needle mark inspection is executed as necessary. The wafer needle mark inspection may be the internal wafer needle mark inspection 111 in the wafer alignment unit 57 or the external wafer needle mark inspection 112 by the external needle mark inspection device 61. In general, the internal wafer needle trace inspection 111 is considered to be more efficient. The internal wafer needle mark inspection 111 is executed in the state shown in FIG.

  Next, based on FIG. 3, the flow of the emergency temperature wafer test 131c (131b, 131d) by individual probers for one whole lot (for example, the hoop 52 containing 25 wafers 11) will be described. As shown in FIG. 3, first, before performing the probe inspection 121 (electrical test) on the first wafer 11 of the lot, the wafer 11 is usually placed on the wafer stage 60 set at the test temperature. While waiting, the upper surface 11a of the wafer 11 is brought close to and directly under the probe card 50, thereby waiting for the proximity waiting process 125 (first stability) for stabilizing the temperature of the probe card 50 at a temperature close to the test temperature. Standby), that is, pre-heating is performed (required time is usually about 5 minutes). Needless to say, when the temperature of the probe card 50 is already stable at the predetermined inspection temperature, the first stabilization waiting step can be skipped.

  When the temperature of the probe card 50 is stabilized, the probe inspection 121 (electrical test) is performed on the first wafer 11 of the lot (execution of the probe inspection on the first wafer). Subsequently, for example, a needle trace inspection 122 is performed on the first wafer 11. The needle trace inspection 122 is executed as an internal needle trace inspection, for example. When a long time is required as compared with the standard processing time (15 to 30 minutes) of the needle trace inspection 122, the temperature of the probe card 50 may be considerably different from the test temperature. Then, the proximity waiting process 126 (second stabilization waiting) for stabilizing the temperature of the probe card 50 at a temperature close to the test temperature is executed. On the other hand, the second stabilization waiting 126 can be skipped when a long time is not required as compared with the standard processing time of the needle mark inspection 122. Next, probe inspection 123 (electrical test) is performed on the second wafer 11 of the lot (execution of probe inspection for the second wafer). The time required for the probe inspections 121 and 123 is typically about 2 to 7 hours per wafer.

  Thereafter, probe inspection (electrical test) is performed on all inspection target wafers that make up a lot in sequence without performing needle trace inspection 122 and stabilization standbys 125 and 126, etc. Thus, the electrical test 124 is performed on the last wafer 11 in the lot. If necessary, the needle trace inspection 122 (subsequent needle trace inspection) and the stabilization standbys 125 and 126 (subsequent stabilization standby) may be selectively executed each time or appropriately.

  Next, referring to FIG. 13, the wafer stage 60 when the electrical test (ie, probe inspection) or stabilization waiting 125, 126 (including the later stabilization waiting) is performed on the wafer 11 by the probe needle 46. The relationship of the probe card 50 will be described. As shown in FIG. 13, the distance between the tip of the probe needle and the upper surface of the wafer (precisely, the upper surface of the bonding pad), that is, the clearance D between the probe needle and the wafer (the height of the probe needle itself varies depending on the type. It is preferable to set as follows according to the contents of processing. When the probe needle is in contact with the bonding pad during the probe inspection, the probe needle / wafer clearance D is of course zero. When moving to the next test site on the same wafer (during movement within the wafer), it moves in a non-contact proximity state. Also, during the stabilization standbys 125 and 126, it is preferable to maintain a non-contact proximity state equivalent to that during the movement in the wafer from the viewpoint of ensuring accuracy or temperature uniformity. During other normal movements (when the wafer stage 60 moves), for example, when the wafer stage 60 moves from the probe unit 59 to the outside (portion other than the probe unit 59 in the prober 51), and the wafer When the stage 60 moves from the outside to the probe unit 59, it is preferable from the viewpoint of operational stability or safety that the stage 60 is moved in a state where a normal interval larger than the non-contact proximity state is maintained. The probe needle / wafer clearance D in the non-contact proximity state is preferably about 200 to 700 micrometers, for example. Further, the probe needle / wafer clearance D at the normal interval is preferably about 10 to 40 mm.

  Next, a temperature stabilization system for the probe card 50 will be described with reference to FIG. Since the wafer stage 60 is normally held at the inspection temperature by its internal cooling system or heating system, the wafer stage 60 is in a state immediately below the probe card 50, that is, the probe inspection 107 (FIG. 1) or During the stabilization standbys 125 and 126 (FIG. 3), the probe card 50 is considered to be at a temperature close to the inspection temperature (first temperature). However, when the entire period of the wafer test 131 (FIG. 3) by the individual prober 51 (FIG. 1) is viewed, the wafer stage 60 is not directly under the probe card 50 in many periods (the wafer stage is absent). Period). In the absence of the wafer stage, the temperature of the probe card 50 naturally goes away from the inspection temperature in the direction approaching the normal temperature. This occurs for various reasons within the wafer stage absence period, but the most serious problem is when, for example, the needle trace inspection 122 (FIG. 3) takes an unexpectedly long time. This is because the needle trace inspection 122 often requires manual operation. Manual work involving human factors is often left unattended for a long time due to the absence of humans, multiple occurrences of manual operation requests, mistakes, and the like. As a result, a situation occurs in which the wafer stage absence period is unnecessarily prolonged. If the temperature of the probe card 50 deviates significantly from the inspection temperature by leaving it for a long time, it may take 2 hours or more until the temperature of the probe card 50 becomes stable and close to the inspection temperature. is there.

  In order to avoid this problem, the following processing is useful. In other words, during the absence of the wafer stage, the operation of the prober 51 is automatically monitored so that the wafer prober 51 is substantially in a continuous time when the wafer stage 60 is not below the probe card 50. The idle time during which no effective operation is performed is monitored, and when this idle time exceeds the first time interval, the wafer stage is set and held at the first temperature (inspection temperature). 60 is automatically moved below the probe card 50 and waits there (preferably waiting in proximity). This procedure will be described with reference to FIGS. As shown in FIGS. 2 and 8, the prober operation monitoring system 65 provided in the prober 51 (which may be external) monitors the prober control system 66 to thereby provide an XY table control system 67, a wafer alignment control system. 68. The operation of the needle alignment control system 69 and the like is monitored. In the prober operation monitoring system 65, first, the wafer stage 60 is in a state immediately below the probe card 50 (wafer stage staying period) or the wafer stage 60 is not in the state immediately below the probe card 50 (wafer). It is determined whether or not the stage is absent (wafer stage position determination 151). Here, if the wafer stage 60 is in a state immediately below the probe card 50, the prober operation monitoring system 65 maintains the state as it is. However, if the wafer stage 60 is not directly under the probe card 50, the prober operation monitoring system 65 monitors the operation of the prober 51 related to the wafer stage 60 (wafer stage related operation monitoring 152). , Count the length of the unnecessary continuous wafer stage absence period. The idle time is a predetermined time interval (the first time interval is, for example, about 5 minutes. Generally, it is preferably 2 minutes or more and less than 20 minutes, and more preferably 3 minutes or more and less than 18 minutes). It is determined whether or not the above has been reached (idle time length determination 153). Here, if the idle time is less than the predetermined time interval, the prober operation monitoring system 65 maintains the state as it is. However, if the idle time is equal to or greater than the predetermined time interval, the prober operation monitoring system 65 instructs the prober control system 66 to return the wafer stage 60 to the position immediately below the probe card 50, and the wafer stage 60. Is returned to the position immediately below the probe card 50 (return immediately below the probe card 154), and is set in a stabilization standby state (preferably waiting in proximity). In this stabilization standby state, it is preferable that the probe needle / wafer clearance D is equivalent to that in the non-contact proximity state from the viewpoint of temperature stability in a short time. However, if the stabilization time may be slightly increased, the probe needle / wafer clearance D may be set to an appropriate value between the probe needle / wafer clearance D equal to the normal interval or the non-contact proximity state. Good.

4). Description of other probe cards used in the wafer test process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (mainly FIGS. 17 and 18)
In recent years, it has been possible to reduce the pad pitch or increase the number of simultaneous test chips (full wafer test that tests all chips with one contact or semi-test that tests all chips with several contacts) For the full wafer test), various types of so-called advanced probe cards have begun to be used in place of conventional cantilever probe cards. These various advanced probe cards can be applied in place of the cantilever type probe card in the example of section 3. The structure will be briefly described below.

  FIG. 17 is an example of another probe card used in the wafer test process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application, that is, an example of a vertical needle probe card (a kind of advanced probe card). FIG. 14 is a cross-sectional view (substantially corresponding to FIG. 13 of section 3, the same applies hereinafter). FIG. 18 shows another probe card used in the wafer test process in the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present invention, that is, a micro cantilever type probe card (a kind of advanced probe card). It is sectional drawing which shows an example. Based on these, an outline of the structure of another probe card used in the wafer test process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application will be described.

  First, the vertical needle probe card will be described. As shown in FIG. 17, the main body 50 of the probe card is composed of a printed wiring board (generally, it is replaced for each test type) in the same manner as a normal probe card. On the upper surface of the probe card main body 50, a connector portion 43 (or pogo pin contact portion) arranged in a ring shape is provided in the same manner as a normal probe card. Are connected to a tester (a logic tester in the case of the logic test of section 3). On the other hand, a ceramic needle holder 37 holding a large number of probe needles 46 (for example, made of palladium alloy) is fixed to the lower surface of the main body 50 of the probe card via a ring-shaped metal frame 41 and fixing screws 38. Has been. In the ceramic needle holder 37, there is a needle support cavity 39, and the probe needle 46 is fixed at the ceiling thereof, and each lower end of the probe needle 46 has a pore in the floor portion of the needle support cavity 39. It penetrates and is held relatively freely. These many probe needles 46 are connected to the main body 50 of the probe card via the interposer 40.

  Next, a micro cantilever type probe card will be described. As shown in FIG. 18, the main body 50 of the probe card is composed of a printed wiring board (generally, it is replaced for each test type) in the same manner as a normal probe card. As in the example of FIG. 17, a connector portion 43 (or pogo pin contact portion) arranged in a ring shape is provided on the upper surface of the probe card main body 50. , And a tester (a logic tester in the case of the logic test of section 3). On the other hand, a ceramic needle holder 37 holding a large number of probe needles 46 (for example, a thin film metal plate patterned by lithography) is provided on the lower surface of the probe card main body 50 via a ring-shaped metal frame 41. It is fixed. These many probe needles 46 are connected to the main body 50 of the probe card via the interposer 40. In this case, since the vertical degree of freedom of the probe needle 46 is smaller than that of the previous vertical needle probe card, a stiffener (for example, made of stainless steel) for preventing deflection is formed on the upper surface of the probe card main body 50. Reinforcing structure) 36 is fixed.

5. Summary The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  For example, in the above-described embodiment, the conventional cantilever type probe card has been specifically described as a prober type. However, the present application is not limited thereto, and a vertical type probe card, Needless to say, the present invention can also be applied to probe inspection using an advanced probe card or a MEMS type probe card utilizing a photolithography or MEMS technology such as a spring pin type probe card or a thin film probe.

  In the above-described embodiment, the chip layout in which the bonding pads are arranged in two rows has been specifically described as an example. However, the present application is not limited thereto, and the chip in which the bonding pads are arranged in one row. Needless to say, the present invention can also be applied to a chip layout in which bonding pads are arranged in three or more columns and in a matrix.

FIG. 3 is a process block flow diagram showing a wafer test flow by individual probers in the method of manufacturing a semiconductor integrated circuit device of one embodiment of the present application. It is a flowchart explaining the position control method of the wafer stage in each prober in the manufacturing method of the semiconductor integrated circuit device of one embodiment of this application. It is a process block flow diagram showing a flow of processing for wafer batches within individual probers in the method of manufacturing a semiconductor integrated circuit device according to one embodiment of the present application. It is a process block flow diagram illustrating the flow of the entire wafer test process in the method for manufacturing a semiconductor integrated circuit device of one embodiment of the present application. It is a prober top view which shows an example of the prober used for the wafer test process in the manufacturing method of the semiconductor integrated circuit device of one embodiment of this application. 1 is an overall view of a chip layout of a semiconductor integrated circuit device manufactured by a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present application; FIG. 5 is a process block flow diagram illustrating a main part of a manufacturing process such as probe inspection by a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present application. 1 is a block diagram showing an example of a configuration of a prober control system for explaining a method for controlling the position of a wafer stage in each prober in a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present application. 1 is a schematic cross-sectional view of an example of a final form of a semiconductor integrated circuit device according to a manufacturing method of a semiconductor integrated circuit device of an embodiment of the present application; It is a probe test state schematic top view for demonstrating the mode of the probe test | inspection in the manufacturing method of the semiconductor integrated circuit device of one embodiment of this application. It is an enlarged view of the part of the broken line P of FIG. FIG. 5 is a schematic front view of a probe test state and the like for explaining a state of probe inspection and probe mark inspection in the method for manufacturing a semiconductor integrated circuit device of one embodiment of the present application. An apparatus partial schematic front view for explaining the relationship between a probe card and a wafer in each prober in a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention, taking a cantilever type probe card as an example (probe) -Card part). An apparatus main part schematic front process for explaining the relationship between a probe card and a wafer in each prober in the method of manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention, taking a cantilever type probe card as an example. It is a flowchart (at the time of probe standby). An apparatus main part schematic front process for explaining the relationship between a probe card and a wafer in each prober in the method of manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention, taking a cantilever type probe card as an example. It is a flow diagram (during wafer alignment or probe mark inspection). An apparatus main part schematic front process for explaining the relationship between a probe card and a wafer in each prober in the method of manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention, taking a cantilever type probe card as an example. It is a flow figure (at the time of needle position alignment). Section showing an example of another probe card used in the wafer test process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application, that is, an example of a vertical probe card (a type of advanced probe card) FIG. An example of another probe card used in the wafer test process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application, that is, a micro cantilever type probe card (a kind of advanced probe card) FIG.

Explanation of symbols

1 Chip area on chip or wafer (inspected chip area)
1a Top surface of chip (or device surface)
3 Actual bonding pad 5 Dummy pad (Pad trace inspection pad)
7 Internal circuit area 11 Wafer 11a Upper surface (or device surface) of wafer
12 Ball 31 Bonding wire 32 Lead 33 Wiring board 34 Resin sealing part 35 Bump electrode 36 Stiffener (reinforcing structure)
37 Needle holder (made of ceramic) 38 Fixing screw 39 Needle support cavity 40 Interposer 41 Ring-shaped metal frame 42 XY table 43 Pogo pin (or connector part)
44 Card holder 45 Test head 46 Probe needle 47 Actual probe needle 48 Dummy probe needle 49 Probe card opening 50 Probe card (or wiring board of the probe card body)
51, 51a, 51b, 51c, 51d Prober 52 Wafer transfer container (hoop)
53 Wafer Transfer Container Port 54 Wafer Transfer Robot 55 Pre-Alignment Unit 56 Wafer Load & Unload Unit 57 Wafer Alignment Unit (Internal Needle Trace Inspection Unit)
59 Probe unit 60 Wafer stage 61 External needle trace inspection device 62 Pre-alignment optical system 63 Wafer alignment optical system 64 Needle alignment optical system 65 Prober control monitoring system 66 Prober control system 67 XY table control system 68 Wafer alignment control System 69 Needle alignment control system 71 Wafer process (preceding wafer test) 73 Back grinding process 74 Wafer dicing 75 Die bonding 76 Wire bonding 77 Resin sealing 78 Bump attachment 79 Final test 80 Shipment 101 Wafer Transport container load 102 Wafer loading 103 Pre-alignment 104 Wafer moves onto stage 105 Wafer alignment 106 Needle alignment 107 Probe execution (electrical test execution)
108 Wafer moves from stage 109 Wafer unloading 110 Wafer transfer container unload 111 Internal needle trace inspection 112 External needle trace inspection 121 Probe execution for first wafer 122 Needle trace inspection for first wafer 123 Second Execute a probe on the last wafer 124 Execute a probe on the last wafer in the lot 125 First stabilization wait 126 Second stabilization wait 130 Wafer process before wafer test 131 Wafer test 131a First memory Test 131b second memory test 131c first logic test 131d second logic test 132 BG (back grinding)
133 Dicing (Division of wafer into chips)
134 Assembly (die bonding, wire bonding, sealing, etc.)
135 Final Electrical Test 136 Shipment 141 First Bake Process 142 Second Bake Process 151 Monitor if Wafer Stage is Directly Underneath Probe Card 152 Monitor Prober Operation Associated with Wafer Stage 153 Unnecessary Determine whether the time outside the area directly below the probe card has exceeded the first time 154 Return the wafer stage to the area directly below the probe card
D Distance between probe needle tip and wafer upper surface (more precisely, bonding pad upper surface) P Portion indicated by dotted circle

Claims (20)

A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) setting a wafer on a wafer stage held at a first temperature different from room temperature in a wafer prober;
(B) After the step (a), in the wafer prober, moving the wafer stage in which the wafer is set and held at the first temperature below the probe card;
(C) After the step (b), in the wafer prober, the wafer stage set and held at the first temperature is below the probe card, Performing an electrical test on the wafer to be inspected at the first temperature using the probe card;
(D) after the step (c), the step of moving the wafer stage, in which the wafer is set and held at the first temperature, to the outside of the probe card in the wafer prober;
(E) after the step (d), moving the wafer on the wafer stage held at the first temperature outside the wafer stage in the wafer prober;
Here, during the operation of the wafer prober, the idle time during which the wafer stage is not under the probe card and the wafer prober is not operating effectively is monitored. If the idle time exceeds the first time interval, the wafer is set, and the wafer stage held at the first temperature is automatically moved below the probe card. .     In the method for manufacturing a semiconductor integrated circuit device according to the item 1, the first temperature is not less than 100 degrees Celsius and not more than 200 degrees Celsius.     In the method of manufacturing a semiconductor integrated circuit device according to the item 1, the first temperature is minus 70 degrees Celsius or more and 0 degrees Celsius or less.     In the method of manufacturing a semiconductor integrated circuit device according to the item 1, the semiconductor integrated circuit device has a flash memory section.     In the method of manufacturing a semiconductor integrated circuit device according to the item 1, the semiconductor integrated circuit device has a logic unit.     In the method for manufacturing a semiconductor integrated circuit device according to the item 1, the probe card is a cantilever type.     In the method for manufacturing a semiconductor integrated circuit device according to the item 1, the probe card is an advanced type.     In the method for manufacturing a semiconductor integrated circuit device according to the item 1, the first time interval is not less than 2 minutes and less than 20 minutes.     In the method of manufacturing a semiconductor integrated circuit device according to the item 4, the electrical test includes a data retention test of the flash memory unit.     6. The manufacturing method of a semiconductor integrated circuit device according to the item 5, wherein the electrical test includes a function test of the logic unit. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) loading a wafer transfer container containing a plurality of wafers into a wafer prober;
(B) after the step (a), transferring a first wafer of the plurality of wafers in the wafer transfer container into the wafer prober;
(C) setting the first wafer on a wafer stage held at a first temperature different from normal temperature in the wafer prober;
(D) After the step (c), the step in which the first wafer is set in the wafer prober and the wafer stage held at the first temperature is moved below the probe card. ;
(E) After the step (d), the wafer stage in which the first wafer is set and maintained at the first temperature is below the probe card in the wafer prober. Waiting for the temperature of the probe card to stabilize;
(F) After the subsequent steps of steps (d) and (e), the wafer stage in which the first wafer is set and held at the first temperature in the wafer prober. Performing an electrical test on the first wafer at the first temperature using the probe card with the probe card underneath the probe card;
(G) After the step (f), in the wafer prober, the first wafer is set, and the wafer stage held at the first temperature is moved out of the probe card. The step of causing;
(H) After the step (g), in the state where the first wafer is set and the wafer stage held at the first temperature is moved to the lower outside of the probe card, Performing a needle mark inspection on a wafer of
(I) after the later steps of the steps (g) and (h), the first wafer on the wafer stage held at the first temperature in the wafer prober; Moving the wafer stage to the outside;
(J) After the step (i), a step of transferring the first wafer into the wafer transfer container;
(K) After the step (i), the steps (b) to (d), step (b) are sequentially performed on each wafer other than the first wafer among the plurality of wafers in the wafer transfer container. repeating steps f) to (g) and steps (i) to (j);
Here, during the operation of the wafer prober, the idle time during which the wafer stage is not under the probe card and the wafer prober is not operating effectively is monitored. If the idle time exceeds the first time interval, the first wafer is set, and the wafer stage held at the first temperature is automatically moved below the probe card. Move to.     12. In the method for manufacturing a semiconductor integrated circuit device according to the item 11, the first temperature is not less than 100 degrees Celsius and not more than 200 degrees Celsius.     12. In the method for manufacturing a semiconductor integrated circuit device according to the item 11, the first temperature is minus 70 degrees Celsius or more and 0 degrees Celsius or less.     12. The method for manufacturing a semiconductor integrated circuit device according to the item 11, wherein the semiconductor integrated circuit device has a flash memory unit.     12. The method for manufacturing a semiconductor integrated circuit device according to the item 11, wherein the semiconductor integrated circuit device has a logic unit.     12. The manufacturing method of a semiconductor integrated circuit device according to the item 11, wherein the probe card is a cantilever type.     12. In the method for manufacturing a semiconductor integrated circuit device according to the item 11, the probe card is an advanced type.     12. In the method for manufacturing a semiconductor integrated circuit device according to the item 11, the first time interval is not less than 2 minutes and less than 20 minutes.     15. The manufacturing method of a semiconductor integrated circuit device according to the item 14, wherein the electrical test includes a data retention test of the flash memory unit.     16. The method for manufacturing a semiconductor integrated circuit device according to the item 15, wherein the electrical test includes a function test of the logic unit.

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