JP2010056297A - Solid-state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To actualize a solid-state imaging device with more improved sensitivity and reduced noise. <P>SOLUTION: The solid-state imaging device includes a pixel array 1 having a plurality of two-dimensionally arranged pixels and a plurality of column signal lines 52 and 53 provided per column. Each pixel includes a photodiodes PD1A, PD1B, PD2A, and PD2B, reading transistors TrG1A, TrG1B, TrG2A, and TrG2B, reference transistors TrR1 and TrT2 connected between the reading transistors and a reference signal line 15, and amplifying transistors TrA1 and TrA2 having gates connected to connection nodes between the reading transistors and the reference transistors. Two adjacent pixels in each column form a group, and each group includes a selecting transistor TsR connected between two amplifying transistors in the group, and one of the two amplifying transistors is connected to the column signal line, and the other is connected to a power supply line. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a solid-state image sensor, and more particularly to a MOS solid-state image sensor.

  In recent years, imaging devices using solid-state imaging devices are widely used in digital cameras, digital TV cameras, mobile phones, and the like.

  The solid-state imaging device includes a pixel array in which a plurality of pixels are arranged two-dimensionally, a column signal line provided for each column, and a detection signal output from the pixel, and an AD conversion of the detection signal output to the column signal line A reading circuit that performs processing and the like, and a signal processing unit that performs control processing and signal processing.

  The basic configuration of the solid-state imaging device is described in Patent Documents 1 to 4 and the like, and is widely known.

  If the threshold value of each transistor in the pixel varies, the read detection signal changes by the variation. Further, it is necessary to reset the pixels to the initial state before reading the detection signal from each pixel. Therefore, a reset signal is applied to set the pixel to an initial state, and a detection signal corresponding to the initial state is read and stored as a noise signal. Then, the detection signal is read, and after performing CDS (Correlated Double Sampling) processing for subtracting the noise signal from the detection signal, the detection signal is AD converted. By the CDS process, the influence due to the variation in the threshold value of the transistor is removed. Various circuits for performing CDS processing have been proposed.

  FIG. 1 is a diagram showing a configuration of a conventional example of a pixel 11 and an ADC 21 when performing a CDS process. Although only one pixel is shown in FIG. 1, a plurality of pixels 11 are arranged in the column direction, each pixel is connected to a common column signal line 13, and one ADC is connected to one column signal line 13. A circuit 21 is connected. A plurality of sets of such pixels 11, column signal lines 13, and ADC circuits 21 are arranged in the row direction.

  As shown in FIG. 1, the pixel 11 includes a photodiode PD whose anode is connected to the ground, a read transistor TrG connected to the cathode of the photodiode PD, and a reset voltage line 15 and a read transistor TrG. A connected reference (reset) transistor TrR; an amplifying transistor TrA having a gate connected to a connection node between the readout transistor TrG and the reference transistor TrR and one controlled electrode connected to the power line 14; A selection transistor TrS connected between the other controlled electrode of the amplification transistor TrA and the column signal line 13; A pixel control circuit (not shown) generates a readout signal TG, a reset signal RST, and a selection signal SLCT, and via the driver 6, the gates of the readout transistors TrG, the gates of the reference transistors TrR, and all the pixels in the same row Each is applied to the gate of the selection transistor TrS. The reset voltage line 15 is always supplied with the reset voltage VR, and the power supply line 14 is always supplied with the power supply voltage. Note that the reset voltage VR may be supplied to the power supply line 14. The power supply line 14 may be arranged so as to extend in the row direction, or may have a lattice shape extending in both the row direction and the column direction.

  An ADC circuit 21 is connected to the column signal line 13 via the constant current source 12 and the switch 10.

  The ADC circuit 21 includes a comparison circuit 22, a first capacitance element C1 connected to the inverting (−) input node of the comparison circuit 22, a switch SW1 connected between the output node and the inverting input node of the comparison circuit 22, It has a canceling capacitive element C10 connected to the non-inverting (+) input node of the comparison circuit 22, and a counter 24 that counts the clock during the designated period. The comparison circuit 22 is realized by an operational amplifier or the like.

  Here, the constant current source 12, the switch 10, and the ADC circuit 21 are collectively referred to as a readout circuit 25.

  FIG. 2 is a time chart showing the operation of the conventional example of FIG. The operation is performed in the order of noise reading processing, signal reading processing, and AD conversion (ADC) processing.

  In the noise reading process, the switch SW10 is turned off (non-conducting), the switch SW1 is turned on (on) (conducting), the selection signal SLCT is turned on (“On” (“high (H)”)), and the reset signal Turn on RST. The read signal TG is off. Thereby, the transistors TrR and TrS of the pixel from which the detection signal is read are turned on. Since the reset voltage VR is applied to the gate of TrA, TrA is turned on, and the column signal line 13 is set to the voltage (N level) of the noise signal (reset noise signal). When the reset signal RST is turned off and SW1 and SW10 are turned on, the voltages at the two input nodes of the comparison circuit 22 are both set to the N level. Thereafter, SW1 and SW10 are turned off. As a result, the N level is held in C1. When the reset signal RST is turned on, the gate voltage of TrA becomes the reset voltage VR, and is reset to a constant state regardless of the previous state.

  In the signal read process, the read signal TG is turned on (transfer state). Thereby, TrG is turned on, and the charge (detection signal) corresponding to the exposure amount of the photodiode PD is transferred to the gate of TrA and converted into a voltage. This voltage is amplified by TrA and output to the column signal line 13 via the selection transistor TrS, and the column signal line 13 is set to the voltage of the temporary detection signal. The temporary detection signal is a signal obtained by combining the detection signal and the noise signal, and the voltage is the sum (N + S level) of the noise signal voltage and the detection signal voltage. Then, after the read signal TG is turned off and then SW10 is turned on, the voltage at the non-inverting (+) input node of the comparison circuit 22 is set to the S + N level. At this time, the voltage of the inverting (−) input node of the comparison circuit 22 is N level, and the output signal of the comparison circuit 22 is set to a low level indicating that the voltage of the non-inverting input node is lower than the voltage of the inverting input node. The Here, the voltage of the non-inverting input node is S + N level, the voltage of the inverting input node is N level, and the voltage difference is S level, that is, the voltage of the detection signal obtained by subtracting the noise signal voltage from the temporary detection signal voltage. To do. In this state, the selection signal SLCT is turned off and the SW10 is turned off.

  In the ADC processing, a comparison signal whose voltage rises with a predetermined slope is applied to the capacitor C10, and the voltage of the non-inverting input node of the comparison circuit 22 starts to rise from the S + N level due to the capacitance coupling of C10. At the same time, the counter 24 starts counting the clock CLK. When the voltage at the non-inverting input node of the comparison circuit 22 exceeds the voltage at the inverting input node, the output signal of the comparison circuit 22 changes from a low level to a high level. The counter 24 stops the count operation in response to this change, and outputs the count value as digital detection data that is the result of AD conversion.

  Even if the signal voltage of the PD is the same, the detection signal read out from the pixel varies due to the variation in the threshold value (Vth) of the amplifying transistor TrA, but in the conventional example of FIG. 1, the noise level (N level) is set in advance. It is read and stored, and the noise level is removed from the read provisional detection signal to reduce the influence of variation in the threshold value (Vth) of the amplifying transistor TrA.

  The above ADC circuit is an example, and various other ADC circuits are known.

  In the configuration example of FIG. 1, one pixel includes one photodiode and four transistors. In other words, four transistors are provided for one photodiode. For this reason, there has been a problem that the ratio of the area of the photodiode is reduced and the sensitivity is lowered. Therefore, the reference (reset) transistor TrR, the amplification transistor TrA, and the selection transistor TrS are commonly used to reduce the number of transistors per photodiode.

  FIG. 3 is a diagram illustrating a configuration example in which two photodiodes are provided per pixel. Here, a pixel having a plurality of photodiodes is referred to as a shared pixel. As illustrated, each shared pixel 40 includes two photodiodes PDA and PDB, two readout transistors TrGA and TrGB, a reference (reset) transistor TrR, an amplification transistor TrA, and a selection transistor. TrS.

  FIG. 4 is a time chart showing an operation of reading the charge of the photodiode of the shared pixel 40 of FIG. The readout of the photodiode PDA and the photodiode PDB of one shared pixel 40 is performed in a time-sharing manner, and each readout operation is configured by noise readout, signal readout, and ADC operation, similar to the operation described in FIG. However, the ADC operation is omitted in the time chart of FIG.

  When reading the charge of the photodiode PDA, the SLCT and RST of the shared pixel in the row to be read are turned on, and the TGA and TGB are turned off. At this time, the SLCT, RST, TGA, and TGB of the shared pixels in other rows are all turned off. Thereafter, the noise reading operation is performed with RST turned off. Next, after turning on the TGA, the TGA is turned off again to perform a signal read operation. Thereafter, SLCT, RST, TGA, and TGB are turned off to perform an ADC operation, and the operation of reading the charge of the photodiode PDA is completed.

  Next, when reading the charge of the photodiode PDB, the SLCT and RST of the shared pixel in the read target row are turned on, and the TGA and TGB are turned off. At this time, the SLCT, RST, TGA, and TGB of the shared pixels in other rows are all turned off. Thereafter, the noise reading operation is performed with RST turned off. Next, after the TGB is turned on, the TGB is turned off again to perform a signal read operation. Thereafter, SLCT, RST, TGA, and TGB are turned off to perform an ADC operation, and the charge reading operation of the photodiode PDB is completed. Thereafter, the above operation is repeated by changing the position of the column to be read.

  In the pixel configuration of FIG. 3, since one shared pixel includes two photodiodes and five transistors, 2.5 transistors are provided for each photodiode. Sensitivity can be improved by relatively increasing the ratio. A configuration in which four photodiodes are provided in one shared pixel has also been proposed. The pixel configuration of FIG. 3 has the advantage of high sensitivity since the parasitic capacitance of the photodiode is small and the conversion gain is high.

  FIG. 5 is a diagram showing an arrangement and wiring example of connection contacts between the column signal line 13 and the power supply line 14 of the two shared pixels 40 in the configuration of FIG. In FIG. 5, reference numeral 31 denotes a TrA gate signal line of one shared pixel, 32 denotes a TrS gate signal line of one shared pixel, 33 denotes a TrA gate signal line of the other shared pixel, and 34 denotes a gate signal line of the other shared pixel TrA. The gate signal line of the TrS of the other shared pixel is shown. Reference numerals 37 and 38 denote contacts with the TrA power supply line 14, and 39 denotes a contact with the TrS column signal line 13. As shown in FIG. 5, it is necessary to arrange two gate signal lines and two contacts (1.5 if considering adjacent shared pixels) for one shared pixel 40, The layout area of the shared circuit is increased. When the layout area of the shared circuit is increased, the ratio of the area of the photodiode is decreased, which causes a problem that sensitivity is lowered.

  FIG. 6 is a diagram illustrating a pixel configuration example of a solid-state imaging device with further improved sensitivity. The pixel configuration example of FIG. 6 has a configuration in which the selection transistor TrS is excluded from the configuration example of FIG. The reset voltage line 15 is configured such that a switch is provided at the end of the row so that a voltage can be supplied independently for each row. Therefore, in FIG. 6, one shared pixel in an adjacent row is represented by 40-1, the other shared pixel is represented by 40-2, and elements and signals of each shared pixel are represented by 1 or 2.

  FIG. 7 is a time chart showing an operation of reading the charge of the photodiode of the shared pixel 40 of FIG. The readout of the photodiode PDA and the photodiode PDB of each shared pixel 40 is performed in a time-sharing manner, and each readout operation is configured by noise readout, signal readout, and ADC operation, similar to the operation described in FIG. The ADC operation is omitted in the time chart of FIG.

  When reading the charge of the photodiode PD1A of the shared pixel 40-1, VR1 of the shared pixel 40-1 of the row to be read is set high (High), RST1 is turned on, and TG1A and TG1B are turned off. At this time, VR2 of the shared pixels in the other rows including the shared pixel 40-2 is set to low (Low), RST2 is turned on, and TG2A and TG2B are turned off. Thereafter, RST1 is turned off and a noise reading operation is performed. Next, after turning on TG1A, TG1A is turned off again to perform a signal read operation. Thereafter, RST1 is turned on to perform an ADC operation, and the charge reading operation of the photodiode PD1A is completed.

  Next, when reading the charge of the photodiode PD1B of the shared pixel 40-1, VR1 of the shared pixel 40-1 in the row to be read is set high, RST1 is turned on, and TG1A and TG1B are turned off. At this time, VR2 of the shared pixels in the other rows including the shared pixel 40-2 is set to low (Low), RST2 is turned on, and TG2A and TG2B are turned off. Thereafter, RST1 is turned off and a noise reading operation is performed. Next, after turning on TG1B, TG1B is turned off again to perform a signal read operation. Thereafter, RST1 is turned on to perform an ADC operation, and the operation of reading the charge of the photodiode PD1B is completed.

  Thereafter, the above operation is repeated by changing the position of the column to be read. Therefore, when reading the charges of the photodiodes PD2A and PD2B of the next shared pixel 40-2, VR1 in FIG. 6 is set to Low and RST1 is turned on.

  As described above, in the conventional example shown in FIGS. 6 and 7, in the shared pixel of the row that is not to be read, the reset voltage VR is set to Low and the reset transistor TrR is turned on, whereby the amplification transistor TrA is turned on. Only the signal of the shared pixel to be read is output to the column signal line 13 by setting the gate voltage to Low and turning off TrA, that is, high resistance.

  In the conventional example shown in FIG. 6, since the selection transistor TrS is removed as compared with the conventional example of FIG. 3, the number of transistors per one photodiode is two. Thereby, the ratio of the area of the photodiode can be increased to improve the sensitivity.

  However, if the VR of the shared pixel that is not the readout target is too low, the charge of the photodiode being exposed may leak to the column signal line through the readout transistor TrGA or TrGB. On the other hand, if VR is too high, the resistance of the reading transistor TrGA or TrGB is not sufficiently high, and there is a problem that noise from a shared pixel that is not a target increases during reading.

  FIG. 8 is a diagram showing an arrangement and wiring example of connection contacts between the column signal line 13 and the power supply line 14 of the two shared pixels 40-1 and 40-2 in the configuration of FIG. As shown in FIG. 8, since one wiring is reduced as compared with the case of FIG. 5, the layout area of the shared circuit can be reduced, the ratio of the photodiode area can be increased, and the sensitivity can be improved.

JP 2006-217245 A JP 2007-115994 A JP 2000-077845 Japanese Patent Laid-Open No. 2001-024948

  As described above, although the pixel configuration of FIG. 6 can slightly improve the sensitivity by reducing the layout area of the shared circuit, the noise increases.

  Solid-state imaging devices are required to further improve sensitivity and reduce noise.

  A solid-state imaging device according to a first aspect is a solid-state imaging device including a pixel array having a plurality of pixels arranged two-dimensionally and a plurality of column signal lines provided for each column of the pixel array. Each pixel includes a photodiode, a reading transistor connected to the photodiode, a reference transistor connected between the reading transistor and a reference signal line, and a gate having the reading transistor and the reference transistor An amplifying transistor connected to a connection node of the transistors, two adjacent pixels in each column form a group, and each group is connected between the two amplifying transistors of the group A selection transistor, and one of the two amplification transistors is the column signal line. Is connected, the other is connected to the power supply line.

  A solid-state imaging device according to a second aspect is a solid-state imaging device including a pixel array having a plurality of pixels arranged two-dimensionally and a plurality of column signal lines provided for each column of the pixel array. Each pixel includes a photodiode, a reading transistor connected to the photodiode, a reference transistor connected between the reading transistor and a reference signal line, and a gate having the reading transistor and the reference transistor An amplifying transistor connected to a connection node of the transistors, two adjacent pixels in each column form a group, and the two amplifying transistors in each group are connected, and the two amplifying transistors One of the transistors for use is connected to the column signal line, and the other is connected to the power supply line.

  In the solid-state imaging device of the first embodiment, two pixels adjacent in the column direction form a group, the selection transistors of each group are shared, the layout area of the shared circuit portion is reduced, and the photodiode area ratio By increasing the value, sensitivity is further improved.

  In the solid-state imaging device of the second embodiment, two pixels adjacent in the column direction form a group, and the output node of the amplification transistor of each group is shared, so that the readout path of the group that is not the readout target is further increased. Noise can be reduced by using high resistance.

  FIG. 9 is a block diagram illustrating a general configuration of the solid-state imaging device of the embodiment. As shown in FIG. 9, the solid-state imaging device includes a pixel array 1 in which a plurality of pixels are two-dimensionally arranged, a signal processor 2 that performs control processing and signal processing, and internal voltage generation that generates various voltages used internally. Pixel control that generates a circuit 3, a shift register 4 that outputs a selection signal for selecting a row from which detection data is read in accordance with a signal from the signal processor 2, and various control signals for reading a pixel detection signal from the selection signal A circuit row 5, a driver row 6 for applying a control signal to the transistors in the pixel, a pixel readout circuit row 7 for simultaneously reading out detection signals for one row of pixels from the pixel array 1, and a detection signal for the read pixels in one row Is converted to digital data (detection data) by ADC circuit array 8 and ADC circuit array 8 performs AD conversion. Having a bus circuit 9 for transferring the detection data of the row of pixels to the signal processor, a shift register 10 for operating the bus circuit 9, a.

  In the pixel array 1, the horizontal direction is referred to as a row direction, and the vertical direction is referred to as a column direction. In the pixel control circuit column 5 and the driver column, the same circuits are arranged in the column direction by the number of rows, and the activated circuits are shifted one by one. In the pixel readout circuit array 7 and the ADC circuit array 8, the same circuits are arranged in the row direction by the number of columns, and all the circuits operate in parallel.

  Since the basic configuration of the solid-state imaging device is widely known, further explanation is omitted.

  FIG. 10 is a diagram illustrating a configuration of a pixel group 51 that forms the pixel array 1 of the solid-state imaging device according to the first embodiment. Although only one pixel group is shown in FIG. 10, a plurality of pixel groups 51 are arranged in the column direction, and each pixel group is connected to a common first column line 52 and second column line 53. Two column lines 52 and 53 are connected to power supply VDD or readout circuit 55 via switch units 54 and 55. The switch unit 54 includes two switches SW11 and SW12, and the switch unit 55 includes two switches SW21 and SW22. The switches SW11 and SW21 perform corresponding operations, and the switches SW12 and SW22 perform corresponding operations. Do. That is, when the switches SW11 and SW21 are in the conductive (on) state, the switches SW12 and SW22 are in the nonconductive (off) state, the first column line 52 is connected to the readout circuit 25, and the second column line 53 is connected. Is connected to the power supply VDD. When the switches SW11 and SW21 are in the off state, the switches SW12 and SW22 are in the on state, the first column line 52 is connected to the power supply VDD, and the second column line 53 is connected to the readout circuit 25. Become.

  A plurality of sets of columns of pixel groups 51, first and second column lines 52 and 53, and readout circuits 25 as described above are arranged in the row direction.

  As illustrated in FIG. 10, the pixel group 51 includes a first shared pixel, a second shared pixel, and a selection transistor TrS. The first shared pixel includes two photodiodes PD1A and PD1B whose anodes are connected to the ground, a reading transistor TrG1A connected to the cathode of the photodiode PD1A, and a reading transistor connected to the cathode of the photodiode PD1B. TrG1B, a reference (reset) transistor TrR1 connected between the reset voltage line 15 and the two readout transistors TrG1A and TrG1B, a gate having two readout transistors TrG1A and TrG1B and the reference transistor TrR1 An amplifying transistor TrA1 connected to the connection node and having one controlled electrode connected to the second column line 53; The second shared pixel includes two photodiodes PD2A and PD2B whose anodes are connected to the ground, a reading transistor TrG2A connected to the cathode of the photodiode PD2A, and a reading transistor connected to the cathode of the photodiode PD2B. TrG2B, a reference (reset) transistor TrR2 connected between the reset voltage line 15 and the two read transistors TrG2A and TrG2B, a gate having two read transistors TrG2A and TrG2B, and a reference transistor TrR2 An amplifying transistor TrA2 connected to the connection node and having one controlled electrode connected to the first column line 52; The other controlled electrode of the amplification transistor TrA1 is connected to one of the non-control electrodes of the selection transistor TrS, and the other controlled electrode of the amplification transistor TrA2 is connected to the other non-control electrode of the selection transistor TrS. . Accordingly, one pixel group 51 includes four photodiodes PD1A, PD1B, PD2A, and PD2B, and charges accumulated in the four photodiodes PD1A, PD1B, PD2A, and PD2B are read out in a time division manner.

  A pixel control circuit (not shown) generates read signals TG1A, TG1B, TG2A, TG2B, reset signals RST1, RST2, and a selection signal SLCT. These generated signals are sent to the gates of the read transistor, the reference transistor gate, and the select transistor gate of all pixel groups in the same row through a corresponding driver in the driver row 6 of FIG. Respectively. A reset voltage VR is always supplied to the reset voltage line 15.

  FIG. 11 is a diagram showing an arrangement and wiring example of connection contacts with the first and second column lines 52 and 53 of one pixel group 51 in the configuration of the first embodiment of FIG. In FIG. 11, reference numeral 31 denotes the gate signal line of the TrA1 of one shared pixel, 34 denotes the gate signal line of the TrA2 of the other shared pixel, and 56 denotes the gate signal line of the TrS. Reference numeral 57 denotes a contact with the second column line 53 of TrA1, and 58 denotes a contact with the first column line 52 of TrA2. As shown in FIG. 11, two gate signal lines and two contacts are arranged for one pixel group 51 having four photodiodes (pixels). Compared to the conventional example of FIG. 5, the layout area of the shared circuit is small. Thereby, the ratio of the area of the photodiode can be increased, and the sensitivity is improved.

  FIG. 12 is a time chart showing an operation of reading out charges accumulated in the four PD1A, PD1B, PD2A, and PD2B of the pixel group 51 of the first embodiment shown in FIG. The readout of the four photodiodes PD is performed in a time-sharing manner, and each readout operation is configured by noise readout, signal (signal) readout, and ADC operation, similar to the operation described in FIG. In the time chart of FIG. 12, the ADC operation is omitted.

  When reading the charge of the photodiode PD1A, SW11 and SW21 are turned on, and SW12 and SW22 are turned off. As a result, the first column line 52 is connected to the readout circuit 25 and the second column line 53 is connected to the power supply VDD. In other words, one control electrode of TrA1 is connected to VDD, the other control electrode of TrA2 is connected to readout circuit 25, and power supply VDD, second column line 53, TrA1, TrS, TrA2, first column line 52, A path to the reading circuit 25 is formed.

  Read processing is performed in this state. In the noise readout process, SLCT, RST1, and RST2 of the pixel group 51 in the readout target row are turned on, and TG1A, TG1B, TG2A, and TG2B are turned off. Thereby, since the reference voltage VR is applied to the gates of TrA1 and TrA2, TrA1 and TrA2 are turned on, and the path from the power supply VDD to the first column line 52 via the second column line 53, TrA1, TrS, and TrA2 Are formed, and the first column line 52 is set to the voltage (N level) of the noise signal (reset noise signal). The readout circuit 25 stores the voltage of the noise signal. Then, RST1 is turned off. By turning on RST1, the gate voltage of TrA1 becomes the reset voltage VR, and is reset to a constant state regardless of the previous state.

  Next, a signal (signal) reading process is performed. In this process, TG1A is turned on from the previous state. Thereby, TrG1A is turned on, and a charge (detection signal) corresponding to the exposure amount of the photodiode PD1A is transferred to the gate of TrA1. Accordingly, TrA1 is turned on, and a path from the power supply VDD to the first column line 52 through the second column line 53, TrA1, TrS, and TrA2 is formed. TrA1 amplifies the voltage corresponding to the transferred charge and outputs it to the first column line 52 via TrS and TrA2. Thereby, the first column line 52 is set to the voltage of the temporary detection signal. The temporary detection signal is a signal obtained by combining the detection signal and the noise signal, and the voltage is the sum of the noise signal voltage and the detection signal voltage. Thereafter, TG1A is turned off again, and the signal reading operation is completed.

  Thereafter, SW11, SW12, SW21, SW22, SLCT, RST1, RST2, TG1A, TG1B, TG2A and TG2B are turned off to perform the ADC operation. The readout circuit 25 calculates a detection voltage by subtracting the stored noise signal voltage from the temporary detection signal voltage. In this way, the charge reading operation of the photodiode PD1A is completed.

  Next, when reading the charge of the photodiode PD1B, similarly to reading the charge of the photodiode PD1A, SW11 and SW21 are turned on, SW12 and SW22 are turned off, and the first column line 52 is connected to the readout circuit 25. The second column line 53 is connected to the power supply VDD. In this state, SLCT, RST1, and RST2 of the pixel group 51 in the row to be read are turned on, and TG1A, TG1B, TG2A, and TG2B are turned off. Thereafter, RST1 is turned off and noise reading processing is performed. Subsequently, TG1B is turned on from the previous state. Thereby, TrG1B is turned on, and a charge (detection signal) corresponding to the exposure amount of the photodiode PD1B is transferred to the gate of TrA1 and converted into a voltage. This voltage is amplified by TrA1 and output as a temporary detection signal to the first column line 52 via TrS and TrA2. Thereafter, TG1A is turned off again to perform a signal read operation.

  Thereafter, SW11, SW12, SW21, SW22, SLCT, RST1, RST2, TG1A, TG1B, TG2A and TG2B are turned off to perform the ADC operation. The readout circuit 25 calculates a detection voltage by subtracting the stored noise signal voltage from the temporary detection signal voltage. In this way, the charge reading operation of the photodiode PD1B is completed.

  When reading the charge of the photodiode PD2A, SW11 and SW21 are turned off, and SW12 and SW22 are turned on. As a result, the first column line 52 is connected to the power supply VDD, and the second column line 53 is connected to the readout circuit 25. In other words, one control electrode of TrA1 is connected to the readout circuit 25, the other control electrode of TrA2 is connected to the power supply VDD, and the power supply VDD, the first column line 52, TrA2, TrS, TrA1, and the second column line 53 are connected. A path to the readout circuit 25 is formed.

  In the noise readout process, SLCT, RST1, and RST2 of the pixel group 51 in the readout target row are turned on, and TG1A, TG1B, TG2A, and TG2B are turned off. Thus, since the reference voltage VR is applied to the gates of TrA1 and TrA2, TrA1 and TrA2 are turned on, and the path from the power supply VDD to the second column line 53 via the first column line 52, TrA2, TrS, and TrA1 And the second column line 53 is set to the voltage of the noise signal. The readout circuit 25 stores the voltage of the noise signal. Then, RST2 is turned off. By turning on RST2, the gate voltage of TrA1 becomes the reset voltage VR, and is reset to a constant state regardless of the previous state.

  Next, a signal (signal) reading process is performed. In this process, TG2A is turned on from the previous state. Thereby, TrG2A is turned on, and a charge (detection signal) corresponding to the exposure amount of the photodiode PD2A is transferred to the gate of TrA2. Accordingly, TrA2 is turned on, and a path from the power supply VDD to the second column line 53 via the first column line 52, TrA2, TrS, and TrA1 is formed. TrA2 amplifies the voltage corresponding to the transferred charge and outputs it to the second column line 53 via TrS and TrA1. Thereby, the first column line 52 is set to the voltage of the temporary detection signal. The temporary detection signal is a signal obtained by combining the detection signal and the noise signal, and the voltage is the sum of the noise signal voltage and the detection signal voltage. Thereafter, TG2A is turned off again, and the signal reading operation is completed.

  Thereafter, SW11, SW12, SW21, SW22, SLCT, RST1, RST2, TG1A, TG1B, TG2A and TG2B are turned off to perform the ADC operation. The readout circuit 25 calculates a detection voltage by subtracting the stored noise signal voltage from the temporary detection signal voltage. In this way, the charge reading operation of the photodiode PD2A is completed.

  Next, when reading the charge of the photodiode PD2B, as in reading the charge of the photodiode PD2A, SW11 and SW21 are turned off, SW12 and SW22 are turned on, and the first column line 52 is connected to the power supply VDD. The two column lines 53 are connected to the read circuit 25. In this state, the SLCT, RST1, and RST2 of the shared pixel 51 in the read target row are turned on, and TG1A, TG1B, TG2A, and TG2B are turned off. Thereafter, RST2 is turned off and noise reading processing is performed. Subsequently, TG2B is turned on from the previous state. Thereby, TrG2B is turned on, and a charge (detection signal) corresponding to the exposure amount of the photodiode PD2B is transferred to the gate of TrA2 and converted into a voltage. This voltage is amplified by TrA2 and output as a temporary detection signal to the second column line 53 via TrS and TrA1. Thereafter, TG2A is turned off again to complete the signal reading operation.

  Thereafter, SW11, SW12, SW21, SW22, SLCT, RST1, RST2, TG1A, TG1B, TG2A and TG2B are turned off to perform the ADC operation. The readout circuit 25 calculates a detection voltage by subtracting the stored noise signal voltage from the temporary detection signal voltage. In this way, the charge reading operation of the photodiode PD2B is completed.

  As described above, the charges accumulated in the four photodiodes of the shared pixel 51 are read out. In the conventional example of the figure, two transistors TrA and TrS are connected between the power supply line 14 and the column signal line 13 during the read operation, whereas in the first embodiment, the first and second columns are connected. Three transistors TrA1, TrS and TrA2 are connected between the lines 52 and 53. However, since the reset voltage VR is applied to one of TrA1 and TrA2 and enters a low resistance state, it is possible to obtain the same signal strength as in the conventional example.

  In the first embodiment, the switch units 54 and 55 are used when reading the charges of the two photodiodes PD1A and PD1B in the first group and when reading the charges of the two photodiodes PD2A and PD2B of the second group. Thus, the connection of the first and second column lines 52 and 53 is switched so that the relationship between the TrA1 and TrA2 with respect to the power supply VDD and the readout circuit 25 is symmetric.

  When it is not necessary to maintain symmetry, the switch units 54 and 55 are not provided, and the relationship between the first and second column lines 52 and 53, the power supply VDD, and the readout circuit 25 is fixed. It is also possible to do. In other words, the first column line 52 is connected to the readout circuit 25 as a column signal line, and the second column line 53 is connected to the power supply VDD as a power supply line.

  FIG. 13 is a diagram illustrating a configuration of a pixel group 61 that forms the pixel array 1 of the solid-state imaging device according to the second embodiment. Although only one pixel group is shown in FIG. 13, a plurality of pixel groups 61 are arranged in the column direction, and each pixel group is connected to a common first column line 52 and second column line 53. Two column lines 52 and 53 are connected to power supply VDD or readout circuit 55 via switch units 54 and 55. The switch unit 54 includes two switches SW11 and SW12, and the switch unit 55 includes two switches SW21 and SW22. The switches SW11 and SW21 perform corresponding operations, and the switches SW12 and SW22 perform corresponding operations. Do. That is, when the switches SW11 and SW21 are in the conductive (on) state, the switches SW12 and SW22 are in the nonconductive (off) state, the first column line 52 is connected to the readout circuit 25, and the second column line 53 is connected. Is connected to the power supply VDD. When the switches SW11 and SW21 are in the off state, the switches SW12 and SW22 are in the on state, the first column line 52 is connected to the power supply VDD, and the second column line 53 is connected to the readout circuit 25. Become.

  A plurality of sets of columns of the pixel group 61 as described above, the first and second column lines 52 and 53, and the readout circuit 25 are arranged in the row direction.

  As illustrated in FIG. 13, the pixel group 61 includes a first shared pixel and a second shared pixel. The first shared pixel includes two photodiodes PD1A and PD1B whose anodes are connected to the ground, a reading transistor TrG1A connected to the cathode of the photodiode PD1A, and a reading transistor connected to the cathode of the photodiode PD1B. TrG1B, a reference (reset) transistor TrR1 connected between the reset voltage line 15 and the two readout transistors TrG1A and TrG1B, a gate having two readout transistors TrG1A and TrG1B and the reference transistor TrR1 An amplifying transistor TrA1 connected to the connection node and having one controlled electrode connected to the second column line 53; The second shared pixel includes two photodiodes PD2A and PD2B whose anodes are connected to the ground, a reading transistor TrG2A connected to the cathode of the photodiode PD2A, and a reading transistor connected to the cathode of the photodiode PD2B. TrG2B, a reference (reset) transistor TrR2 connected between the reset voltage line 15 and the two read transistors TrG2A and TrG2B, a gate having two read transistors TrG2A and TrG2B, and a reference transistor TrR2 An amplifying transistor TrA2 connected to the connection node and having one controlled electrode connected to the first column line 52; The other controlled electrode of the amplifying transistor TrA1 is connected to the other controlled electrode of the amplifying transistor TrA2. Accordingly, one pixel group 61 includes four photodiodes PD1A, PD1B, PD2A, and PD2B, and charges accumulated in the four photodiodes PD1A, PD1B, PD2A, and PD2B are read out in a time division manner. The reset voltage lines including the reset voltage lines 15 of the first and second shared pixels shown in the figure are configured so that a voltage can be supplied independently for each row by providing a switch at the end of the row. Here, the voltage applied to the reset voltage line 15 of the first shared pixel is represented by VR1, and the voltage applied to the reset voltage line 15 of the second shared pixel is represented by VR2.

  Similar to the first embodiment, a pixel control circuit (not shown) generates read signals TG1A, TG1B, TG2A, TG2B, and reset signals RST1, RST2, and applies them to the corresponding transistors.

  FIG. 14 is a diagram showing an arrangement and wiring example of connection contacts with the first and second column lines 52 and 53 of one pixel group 61 in the configuration of the second embodiment of FIG. In FIG. 14, reference numeral 31 indicates the gate signal line of the TrA1 of one shared pixel, and 34 indicates the gate signal line of the TrA2 of the other shared pixel. Reference numeral 57 denotes a contact with the second column line 53 of TrA1, and 58 denotes a contact with the first column line 52 of TrA2. As shown in FIG. 14, two gate signal lines and two contacts are arranged for one pixel group 61 having four photodiodes (pixels). Compared to the conventional example of FIG. 8, the layout area of the shared circuit is smaller by one contact number. Thereby, the ratio of the area of the photodiode can be increased, and the sensitivity is improved.

  FIG. 15 is a time chart showing an operation of reading out charges accumulated in the four PD1A, PD1B, PD2A, and PD2B of the pixel group 61 of the second embodiment shown in FIG. The readout of the four photodiodes PD is performed in a time-sharing manner, and each readout operation is configured by noise readout, signal readout, and ADC operation similarly to the operation described in FIG. In the time chart of FIG. 15, the ADC operation is omitted.

  When reading the charge of the photodiode PD1A, SW11 and SW21 are turned on, and SW12 and SW22 are turned off. As a result, the first column line 52 is connected to the readout circuit 25 and the second column line 53 is connected to the power supply VDD. In other words, one control electrode of TrA1 is connected to VDD, the other control electrode of TrA2 is connected to readout circuit 25, and power supply VDD, second column line 53, TrA1, TrA2, first column line 52, readout circuit A route to 25 is formed.

  Read processing is performed in this state. In the noise readout process, RST1 and RST2 of the pixel group 51 in the readout target row are turned on, TG1A, TG1B, TG2A, and TG2B are turned off, and VR1 and VR2 are turned on (high reference voltage). As a result, since a high reference voltage is applied to the gates of TrA1 and TrA2, TrA1 and TrA2 are turned on, and a path from the power supply VDD to the first column line 52 via the second column line 53, TrA1 and TrA2 is formed. Then, the first column line 52 is set to the voltage (N level) of the noise signal (reset noise signal). The readout circuit 25 stores the voltage of the noise signal. Then, RST1 is turned off. When RST1 is turned on, the gate voltage of TrA1 becomes a high reference voltage, and is reset to a constant state regardless of the previous state. Note that RST1 and RST2 of pixel groups in rows other than the read target are turned on, VR1 and VR2 are turned off (low voltage), and TrA1 and TrA2 are turned off, that is, in a high resistance state. Hereinafter, this condition is maintained for rows other than the read target.

  Next, a signal (signal) reading process is performed. In this process, TG1A is turned on from the previous state. Thereby, TrG1A is turned on, and a charge (detection signal) corresponding to the exposure amount of the photodiode PD1A is transferred to the gate of TrA1. Accordingly, TrA1 is turned on, and a path from the power supply VDD to the first column line 52 via the second column line 53, TrA1, and TrA2 is formed. TrA1 amplifies the voltage corresponding to the transferred charge and outputs it to the first column line 52 via TrA2. Thereby, the first column line 52 is set to the voltage of the temporary detection signal. The temporary detection signal is a signal obtained by combining the detection signal and the noise signal, and the voltage is the sum of the noise signal voltage and the detection signal voltage. Thereafter, TG1A is turned off again, and the signal reading operation is completed.

  Thereafter, SW11, SW12, SW21, SW22, TG1A, TG1B, TG2A and TG2B are turned off, RST1 and RST2 are turned on, VR1 and VR2 are turned off, and the ADC operation is performed. The readout circuit 25 calculates a detection voltage by subtracting the stored noise signal voltage from the temporary detection signal voltage. In this way, the charge reading operation of the photodiode PD1A is completed.

  Next, when reading the charge of the photodiode PD1B, similarly to reading the charge of the photodiode PD1A, SW11 and SW21 are turned on, SW12 and SW22 are turned off, and the first column line 52 is connected to the readout circuit 25. The second column line 53 is connected to the power supply VDD. In this state, RST1 and RST2 of the shared pixel 51 in the row to be read are turned on, TG1A, TG1B, TG2A and TG2B are turned off, and VR1 and VR2 are turned on (high reference voltage). Thereafter, RST1 is turned off and noise reading processing is performed. Subsequently, TG1B is turned on from the previous state. Thereby, TrG1B is turned on, and a charge (detection signal) corresponding to the exposure amount of the photodiode PD1B is transferred to the gate of TrA1 and converted into a voltage. This voltage is amplified by TrA1 and output as a temporary detection signal to the first column line 52 via TrA2. Thereafter, TG1A is turned off again to complete the signal reading operation.

  Thereafter, SW11, SW12, SW21, SW22, TG1A, TG1B, TG2A and TG2B are turned off, RST1 and RST2 are turned on, and VR1 and VR2 are turned off to perform the ADC operation. The readout circuit 25 calculates a detection voltage by subtracting the stored noise signal voltage from the temporary detection signal voltage. In this way, the charge reading operation of the photodiode PD1B is completed.

  When reading the charge of the photodiode PD2A, SW11 and SW21 are turned off, and SW12 and SW22 are turned on. As a result, the first column line 52 is connected to the power supply VDD, and the second column line 53 is connected to the readout circuit 25. In other words, one control electrode of TrA1 is connected to the readout circuit 25, the other control electrode of TrA2 is connected to the power supply VDD, the power supply VDD, the first column line 52, TrA2, TrA1, the second column line 53, and the readout. A path to the circuit 25 is formed.

  In the noise readout process, RST1 and RST2 of the pixel group 61 in the readout target row are turned on, TG1A, TG1B, TG2A, and TG2B are turned off, and VR1 and VR2 are turned on. Thereby, since the reference voltage is applied to the gates of TrA1 and TrA2, TrA1 and TrA2 are turned on, and a path from the power supply VDD to the second column line 53 via the first column line 52, TrA2 and TrA1 is formed. The second column line 53 is set to the voltage of the noise signal. The readout circuit 25 stores the voltage of the noise signal. Then, RST2 is turned off. By turning on RST2, the gate voltage of TrA2 becomes the reference voltage, and is reset to a constant state regardless of the previous state.

  Next, a signal (signal) reading process is performed. In this process, VR2 is turned off and TG2A is turned on from the previous state. Thereby, TrG2A is turned on, and a charge (detection signal) corresponding to the exposure amount of the photodiode PD2A is transferred to the gate of TrA2. Accordingly, TrA2 is turned on, and a path from the power supply VDD to the second column line 53 via the first column line 52, TrA2, TrS, and TrA1 is formed. TrA2 amplifies the voltage corresponding to the transferred charge and outputs it to the first column line 52 via TrS and TrA1. Thereby, the first column line 52 is set to the voltage of the temporary detection signal. The temporary detection signal is a signal obtained by combining the detection signal and the noise signal, and the voltage is the sum of the noise signal voltage and the detection signal voltage. Thereafter, TG2A is turned off again, and the signal reading operation is completed.

  Thereafter, SW11, SW12, SW21, SW22, TG1A, TG1B, TG2A and TG2B are turned off, RST1 and RST2 are turned on, and VR1 and VR2 are turned off to perform the ADC operation. The readout circuit 25 calculates a detection voltage by subtracting the stored noise signal voltage from the temporary detection signal voltage. In this way, the charge reading operation of the photodiode PD2A is completed.

  Next, when reading the charge of the photodiode PD2B, as in reading the charge of the photodiode PD2A, SW11 and SW21 are turned off, SW12 and SW22 are turned on, and the first column line 52 is connected to the power supply VDD. The two column lines 53 are connected to the read circuit 25. In this state, RST1 and RST2 of the shared pixel 51 in the row to be read are turned on, TG1A, TG1B, TG2A and TG2B are turned off, and VR1 and VR2 are turned on. Thereafter, RST2 is turned off and noise reading processing is performed. Subsequently, VR2 is turned off and TG2B is turned on from the previous state. Thereby, TrG2B is turned on, and a charge (detection signal) corresponding to the exposure amount of the photodiode PD2B is transferred to the gate of TrA2 and converted into a voltage. This voltage is amplified by TrA2 and output as a temporary detection signal to the second column line 53 via TrA1. Thereafter, TG2A is turned off again to complete the signal reading operation.

  Thereafter, SW11, SW12, SW21, SW22, TG1A, TG1B, TG2A and TG2B are turned off, RST1 and RST2 are turned on, and VR1 and VR2 are turned off to perform the ADC operation. The readout circuit 25 calculates a detection voltage by subtracting the stored noise signal voltage from the temporary detection signal voltage. In this way, the charge reading operation of the photodiode PD2B is completed.

  As described above, the charges accumulated in the four photodiodes of the shared pixel 51 are read out. In the conventional example of FIG. 6, one transistor TrA is connected between the power supply line 14 and the column signal line 13 during the read operation, whereas in the second embodiment, the first and second column lines are connected. Between the transistors 52 and 53, two transistors TrA1 and TrA2 are connected. However, since the reset voltage VR is applied to one of TrA1 and TrA2 and enters a low resistance state, it is possible to obtain the same signal strength as in the conventional example.

  In the second embodiment, the switch units 54 and 55 are used when reading the charges of the two photodiodes PD1A and PD1B of the first group and when reading the charges of the two photodiodes PD2A and PD2B of the second group. Thus, the connection of the first and second column lines 52 and 53 is switched so that the relationship between the TrA1 and TrA2 with respect to the power supply VDD and the readout circuit 25 is symmetric.

  When it is not necessary to maintain symmetry, the switch units 54 and 55 are not provided, and the relationship between the first and second column lines 52 and 53, the power supply VDD, and the readout circuit 25 is fixed. It is also possible to do.

  Furthermore, in the second embodiment, in the shared pixel other than the read target row, two high resistance state TrA1 and TrA2 are connected in series between the first and second column lines 42 and 53, so As compared with the conventional example in which the TrA is connected, the resistance can be increased. Therefore, it is possible to easily perform control for reducing the leakage of electric charges from the shared pixels other than the read target row and the influence of noise.

  As mentioned above, although embodiment of this invention was described, it cannot be overemphasized that various modifications are possible.

  For example, any readout circuit including an ADC circuit may be used, and a system that does not perform noise readout processing may be used.

  Various variations of the number of photodiodes included in one shared pixel are possible.

FIG. 1 is a diagram illustrating a configuration of a pixel and an ADC circuit portion of a conventional solid-state imaging device. FIG. 2 is a time chart showing the operation of the conventional example of FIG. FIG. 3 is a diagram showing a configuration of a pixel and a readout circuit portion of another conventional solid-state imaging device. FIG. 4 is a time chart showing the operation of the conventional example of FIG. FIG. 5 is a diagram showing a layout example of the shared circuit portion of the conventional example of FIG. FIG. 6 is a diagram showing a configuration of a pixel and a readout circuit portion of another conventional solid-state imaging device. FIG. 7 is a time chart showing the operation of the conventional example of FIG. FIG. 8 is a diagram showing a layout example of the shared circuit portion of the conventional example of FIG. FIG. 9 is a block diagram illustrating a general configuration of the solid-state imaging device of the embodiment. FIG. 10 is a diagram illustrating a configuration of a pixel and a readout circuit portion of the solid-state imaging device according to the first embodiment. FIG. 11 is a diagram illustrating a layout example of the shared circuit portion of the solid-state imaging device according to the first embodiment of FIG. FIG. 12 is a time chart showing the operation of the solid-state imaging device of the first embodiment shown in FIG. FIG. 13 is a diagram illustrating a configuration of a pixel and a readout circuit portion of the solid-state imaging device according to the second embodiment. FIG. 14 is a diagram illustrating a layout example of the shared circuit portion of the solid-state imaging device according to the second embodiment of FIG. FIG. 15 is a time chart showing the operation of the solid-state imaging device of the first embodiment shown in FIG.

Explanation of symbols

15 Reference (Reset) Power Line 25 Read Circuit 51, 61 Pixel Group 52 First Column Line 53 Second Column Line 54 First Switch Circuit 55 Second Switch Circuit PD1A, PD1B, PD2A, PD2B Photodiode TrG1A, TrG1B, TrG2A, TrG2B Read transistor TrR1, TrR2 Reset transistor TrA1, TrA2 Amplify transistor TrS Select transistor

Claims (8)

A pixel array having a plurality of pixels arranged in two dimensions;
A plurality of column signal lines provided for each column of the pixel array, and a solid-state imaging device comprising:
Each pixel is
A photodiode;
A read transistor connected to the photodiode;
A reference transistor connected between the read transistor and a reference signal line;
An amplifying transistor having a gate connected to a connection node of the reading transistor and the reference transistor;
Two adjacent pixels in each column form a group,
Each group includes a selection transistor connected between the two amplification transistors of the group,
One of the two amplifying transistors is connected to the column signal line, and the other is connected to a power supply line.   When reading the output of the photodiode of one pixel of each group, the readout transistor of the one pixel is turned on, the reference transistor is turned off, the selection transistor is turned on, and the output of the other pixel is turned on. The solid-state imaging device according to claim 1, wherein a reading transistor is turned off, the reference transistor is turned on, and the amplification transistor is turned on.   Each pixel is a shared pixel comprising a plurality of photodiodes and a plurality of readout transistors respectively corresponding to the plurality of photodiodes, and the plurality of readout transistors are used for the reference The solid-state imaging device according to claim 1, which is commonly connected to the transistors. The power line is provided for each column,
The column signal line and the power supply line provided for each column, one state where one is connected to the power supply and the other is connected to the readout circuit, and the second state where one is connected to the readout circuit and the other is connected to the power supply The solid-state image sensor of any one of Claim 1 to 3 provided with the switch circuit switched between a state. A pixel array having a plurality of pixels arranged in two dimensions;
A plurality of column signal lines provided for each column of the pixel array, and a solid-state imaging device comprising:
Each pixel is
A photodiode;
A read transistor connected to the photodiode;
A reference transistor connected between the read transistor and a reference signal line;
An amplifying transistor having a gate connected to a connection node of the readout transistor and the reference transistor,
Two adjacent pixels in each column form a group,
The two amplifying transistors in each group are connected,
One of the two amplifying transistors is connected to the column signal line, and the other is connected to a power supply line.   When reading the output of the photodiode of one pixel of each group, turn on the readout transistor of the one pixel, turn off the reference transistor, turn off the readout transistor of the other pixel, The solid-state imaging device according to claim 5, wherein a reference transistor is turned on to turn on the amplification transistor.   Each pixel is a shared pixel comprising a plurality of photodiodes and a plurality of readout transistors respectively corresponding to the plurality of photodiodes, and the plurality of readout transistors are used for the reference The solid-state imaging device according to claim 5, which is commonly connected to the transistors. The power line is provided for each column,
The column signal line and the power supply line provided for each column, one state where one is connected to the power supply and the other is connected to the readout circuit, and the second state where one is connected to the readout circuit and the other is connected to the power supply The solid-state image sensor of any one of Claim 5 to 7 provided with the switch circuit switched between a state.

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