JP2010055667A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device with a small layout area. <P>SOLUTION: In the MRAM (Magnetic Random Access Memory), a magnetization current is made to flow in selected one digit line DL, magnetic resistance elements 5 of 8 pieces (or 248 pieces) of a memory cell MC are put into a half selection state, and a data signal DI is written in parallel in all of the magnetic resistance elements 5 of 8 pieces (or 248 pieces) of the memory cell MC, and hence storage data of the magnetic resistance element 5 never be reversed erroneously, so that large magnetization current can be made to flow in the digit line DL, currents made to flow in the magnetic resistance element 5 and a transistor 6 can be made small. Consequently, the layout area of the memory cell MC is reduced by reducing the channel width of the transistor 6. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device using a magnetoresistive element that stores a data signal by changing a level of a resistance value.

  The nonvolatile semiconductor memory device can hold stored data even when the power supply voltage is cut off, and does not need to supply the power supply voltage in a standby state. For this reason, it is widely used in portable devices that are required to have low power consumption.

  One such nonvolatile semiconductor memory device is an MRAM (Magnetic Random Access Memory) that stores data using the magnetoresistive effect. One of the MRAMs uses STTS (Spin Torque Transfer Magnetization Switching) (for example, see Non-Patent Document 1).

  The MRAM includes a memory array including a plurality of memory cells arranged in a plurality of rows and a plurality of columns, a word line provided corresponding to each row, and a bit line and a source line provided corresponding to each column. Prepare. Each memory cell includes a magnetoresistive element and a transistor. One electrode of the magnetoresistive element is connected to the bit line, the other electrode is connected to the source line via the transistor, and the gate of the transistor is connected to the word line.

At the time of the write operation, the word line of the selected row is set to the selection level to turn on the transistor of each memory cell of the row, and the bit line and source of the column in which the write current having the polarity corresponding to the write data is selected The magnetoresistive element of the selected memory cell is put into a high resistance state or a low resistance state by flowing between the lines. During the read operation, the word line of the selected row is set to the selection level, the transistor of each memory cell in that row is turned on, and the source line is connected via the magnetoresistive element and transistor of the memory cell selected from the bit line of the selected column. The data stored in the memory cell is read based on the current flowing through the memory cell.
IEEE 2005 A Novel Nonvolatile Memory with Spin Torque Transfer Magnetization Switching: Spin-RAM

  In order to reduce the layout area of such an MRAM memory cell, it is necessary to reduce the write current and the channel width of the memory cell transistor. As a method of reducing the write current, a digit line is provided corresponding to each row, a current is passed through the digit line of the selected row, a magnetic field in the hard axis direction of each magnetoresistive element of that row is generated, A method for easily reversing the resistance state of the magnetoresistive element is conceivable.

  However, in this method, since all the magnetoresistive elements in the selected row are in a half-selected state, if there is a magnetoresistive element whose resistance state is easily reversed in the selected row, the resistance state of the magnetoresistive element That is, the stored data may be reversed by mistake. For this reason, the magnetic field due to the current of the digit line cannot be sufficiently increased, and the reduction in the layout area of the memory cell may be suppressed.

  Therefore, a main object of the present invention is to provide a semiconductor memory device having a small layout area.

  The semiconductor memory device according to the present invention is provided with M × N memory cells arranged in M rows and N columns (where each of M and N is an integer of 2 or more), corresponding to each M row. M word lines provided, M digit lines provided corresponding to M rows, N bit lines provided corresponding to N columns, and N columns corresponding to N columns, respectively. A memory array including N source lines provided is provided. Each memory cell has a magnetoresistive element that stores a data signal according to a change in resistance level, a gate connected to a corresponding word line, a source connected to a corresponding source line, and a drain connected via a magnetoresistive element. And a transistor connected to the bit line. The semiconductor memory device further includes a row decoder, a first driver, and N second drivers. The row decoder sets one of the M word lines to a selection level according to the row address signal, and turns on N transistors corresponding to the word line. The first driver applies a magnetizing current to the digit line in the same row as the word line selected by the row decoder, and puts the magnetoresistive elements of the N memory cells in the row into a half-selected state. The N second drivers are provided corresponding to the N columns, respectively, and receive N data signals. Each second driver causes a write current in a direction according to the logic of the received data signal to flow between the bit line and the source line of the corresponding column, so that the memory cell of the corresponding column that has been half-selected is supplied. Write a data signal to the magnetoresistive element.

  In the semiconductor memory device according to the present invention, data is written in parallel to all the N memory cells that are half-selected by the magnetic field of the digit line of the selected row. Therefore, even if some of the N memory cells in the selected row are likely to invert the stored data, the stored data in the memory cell is rewritten to the write data and will not be inverted by mistake. Therefore, the magnetic field due to the digit line current can be sufficiently increased, and the channel width of the memory cell transistor can be reduced to reduce the memory cell layout area.

  FIG. 1 is a block diagram showing the overall configuration of an MRAM according to an embodiment of the present invention. In FIG. 1, this MRAM includes memory arrays MA1 and MA2, a row decoder 1, a column decoder 2, a write circuit 3, and a read circuit 4. The memory array MA1 is used as a RAM (Random Access Memory), and the memory array MA1 is used as a ROM (Read Only Memory).

  As shown in FIG. 2, the memory array MA1 corresponds to a plurality of memory cells MC arranged in a plurality of rows and a plurality of columns, a plurality of word lines WL provided corresponding to the plurality of rows, and a plurality of rows, respectively. A plurality of digit lines DL, a plurality of bit lines BL provided corresponding to a plurality of columns, and a plurality of source lines SL provided corresponding to the plurality of columns, respectively.

  Each memory cell MC includes a magnetoresistive element 5 and an N channel MOS transistor 6. N channel MOS transistor 6 has its gate connected to corresponding word line WL, its source connected to corresponding source line SL, and its drain connected to corresponding bit line BL via magnetoresistive element 5.

  The magnetoresistive element 5 uses STTS, and stores data according to the level change of the resistance value. The magnetoresistive element 5 is in a half-selected state in which the resistance state is easily reversed by a magnetic field generated when a magnetizing current is passed through the corresponding digit line DL. The magnetoresistive element 5 in the half-selected state changes to a high resistance state or a low resistance state depending on the polarity of the write current flowing through the corresponding transistor 6 between the corresponding bit line BL and the source line SL. .

  The memory array MA2 has the same configuration as the memory array MA1 except that the number of columns is different. For example, the number of columns of the memory array MA2 is 248, and the number of columns of the memory array MA1 is 8. The number of rows in the memory arrays MA1 and MA2 is the same. The word line WL of the memory array MA1 and the word line WL of the memory array MA2 are formed as one. Digit line DL is provided separately in memory arrays MA1 and MA2.

  Returning to FIG. 1, the row decoder 1 selects one of the plurality of word lines WL in accordance with the row address signal, and selects the selected word line WL at the “H” level (power supply voltage) of the selected level. VCC), and the N channel MOS transistor 6 of each memory cell MC corresponding to the word line WL is made conductive. The column decoder 2 selects one of the plurality of columns according to the column address signal.

  Write circuit 3 selects memory array MA1 or MA2 in accordance with an external control signal, and writes data in parallel to all memory cells MC corresponding to word line WL selected by row decoder 1 in selected memory array MA. Include. That is, write circuit 3 applies a magnetizing current to digit line DL corresponding to word line WL selected by row decoder 1 in selected memory array MA1, and all memory cells MC corresponding to that digit line DL. To the semi-selected state. The write circuit 3 causes a current having a polarity according to the write data signal of the column to flow between the bit line BL and the source line SL of each column of the selected memory array MA, and the selected word line WL. Data is written in parallel to all memory cells MC corresponding to.

  When the write data signal of a certain column is at “L” level (“0”), write circuit 3 applies bit line BL and source line SL of that column to “H” level (power supply voltage VCC) and “ L ”level (ground voltage VSS). Thereby, a write current flows from the bit line BL to the source line SL via the magnetoresistive element 5 and the N-channel MOS transistor 6 of the memory cell MC, and the magnetoresistive element 5 is brought into a low resistance state, for example.

  When the write data signal of a certain column is at “H” level (“1”), the bit line BL and source line SL of that column are set to “L” level (ground voltage VSS) and “H” level ( The power supply voltage VCC). As a result, a write current flows from the source line SL to the bit line BL via the N-channel MOS transistor 6 and the magnetoresistive element 5 of the memory cell MC, and the magnetoresistive element 5 is brought into a high resistance state, for example.

  The read circuit 4 applies a read voltage sufficiently lower than the write voltage between the bit line BL and the source line SL of the column selected by the column decoder 2, and the memory selected by the bit line BL and the decoders 1 and 2. Based on the read current flowing through the path of the cell MC and the source line SL, the data stored in the memory cell MC is read. For example, when the read current is smaller than a predetermined threshold current, since the magnetoresistive element 5 of the memory cell MC is in a high resistance state, the stored data is “1”. On the contrary, when the read current is larger than the predetermined threshold current, since the magnetoresistive element 5 of the memory cell MC is in the low resistance state, the stored data is “0”.

  FIG. 3 is a circuit block diagram showing the configuration of the write circuit 3. In FIG. 3, only the memory cells MC for two rows are shown for simplification of the drawing. In FIG. 3, the write circuit 3 includes DL drivers 10 and 13, data latch circuits LA0 to LA255, and BL / SL drivers 14 and 15.

  DL driver 10 includes an AND gate 11 and an N-channel MOS transistor 12 provided corresponding to each row of memory array MA1. One input node of AND gate 11 receives signal DLE1 for instructing activation of digit line DL of memory array MA1, and the other input node is connected to corresponding word line WL. N channel MOS transistor 12 is connected between one end of corresponding digit line DL and the line of ground voltage VSS, and the gate thereof receives the output signal of AND gate 11. The other end of each digit line DL receives power supply voltage VCC.

  When the signal DLE1 becomes the “H” level of the activation level and the corresponding word line WL is set to the “H” level of the selection level, the output signal of the AND gate 11 is raised to the “H” level, and the transistor 12 conducts. As a result, a magnetizing current flows from the power supply voltage VCC line to the ground voltage VSS line via the digit line DL and the transistor 12, and a magnetic field is generated around the digit line DL, and each memory corresponding to the digit line DL is generated. The magnetoresistive element 5 of the cell MC is set to a half-selected state.

  When the signal DLE1 becomes the “L” level of the inactivation level or the corresponding word line WL is set to the “L” level of the non-selection level, the output signal of the AND gate 11 becomes the “L” level. . In this case, the transistor 12 becomes non-conductive and no magnetizing current flows through the digit line DL.

  DL driver 13 includes AND gates 11 and N-channel MOS transistors 12 provided corresponding to the respective rows of memory array MA2. One input node of AND gate 11 receives signal DLE2 for instructing activation of digit line DL of memory array MA2, and the other input node is connected to corresponding word line WL. Since other configurations and operations of DL driver 13 are the same as those of DL driver 10, description thereof will not be repeated.

  Data latch circuits LA0-LA7 are provided corresponding to eight columns of memory array MA1, respectively, and data latch circuits LA8-LA255 are provided corresponding to 248 columns of memory array MA2. The data latch circuits LA0 to LA255 are divided into 32 groups of 8 in advance. Corresponding to the 32 groups, 32 column selection lines CSL0 to CSL31 are respectively provided. Write data signals DI0 to DI7 are supplied to the eight data latch circuits LA of each group, respectively. The 32 groups are sequentially selected for a predetermined time, and the data signals DI0 to DI7 are respectively written in parallel to the eight data latch circuits LA of the selected group.

  Each data latch circuit LA takes in the corresponding write data signal DI when the corresponding column selection line CSL is at the “H” level of the selection level, and the corresponding column selection line CSL is “L” at the non-selection level. The corresponding write data signal DI is held and output in response to the change to "" level.

  The BL / SL driver 14 is activated when the memory array selection line MSL1 is set to the “H” level of the selection level and the control signal R / W is set to the “L” level, and the data latch circuits LA0 to LA7 The output data signal is written in parallel to the eight memory cells MC in the half-selected state of the memory array MA1.

  The BL / SL driver 15 is activated when the memory array selection line MSL2 is set to the selection level “H” level and the control signal R / W is set to the “L” level, and the data latch circuits LA8 to LA255 are activated. Output data signals are written in parallel to 288 memory cells MC in the half-selected state of memory array MA2.

  FIG. 4 is a circuit diagram showing the configuration of the data latch circuit LA0 and the BL / SL driver 14. In FIG. 4, data latch circuit LA0 includes inverters 20-22. The inverter 20 is activated when the column selection line CSL0 is at the “L” level, which is a non-selection level, and inverts the output signal of the inverter 21 and gives it to the inverter 21. Inverter 22 is activated when column selection line CSL0 is at the “H” level of the selection level, and inverts write data signal DI0 and applies it to inverter 21.

  When write data signal DI0 is applied and column select line CSL0 is raised to the selected level “H” level, inverter 20 is deactivated and inverter 22 is activated, and write data signal DI0 is inverted. 22 and 21 to be output to the next stage. Next, when the column selection line CSL0 falls to the “L” level of the non-selection level, the inverter 20 is activated and the inverter 22 is deactivated, and the write data signal is generated by the latch circuit comprising the inverters 20 and 21. DI0 is held and output to the next stage. The other data latch circuits LA1 to LA255 have the same configuration as the data latch circuit LA0.

  BL / SL driver 14 includes a BL driver 16 and an SL driver 17 provided corresponding to each column of memory array MA1. The BL driver 16 includes a gate circuit 23, NAND gates 24 and 26, an OR gate 25, a P channel MOS transistor 27, and an N channel MOS transistor 28. SL driver 17 includes a NAND gate 29, a P channel MOS transistor 30, and an N channel MOS transistor 31.

  Write data signal DI0 is input to one input node of NAND gate 24 and OR gate 25 via inverter 22 and input to one input node of NAND gate 29 via inverters 22 and 21. Memory array select line MSL 1 is connected to one input node of gate circuit 23 and NAND gate 26. Control signal R / W is input to the other input node of gate circuit 23 and OR gate 25. The output signal of the gate circuit 23 is input to the other input node of the NAND gates 24 and 29. The output signal of the OR gate 25 is input to the other input node of the NAND gate 26.

  P-channel MOS transistor 27 is connected between a line of power supply voltage VCC and one end of corresponding bit line BL, and the gate thereof receives an output signal of NAND gate 24. N channel MOS transistor 28 is connected between one end of corresponding bit line BL and the line of ground voltage VSS, and the gate thereof receives the output signal of NAND gate 26.

  P-channel MOS transistor 30 is connected between a line of power supply voltage VCC and one end of corresponding source line SL, and its gate receives an output signal of NAND gate 29. N channel MOS transistor 31 is connected between one end of corresponding source line SL and the line of ground voltage VSS, and the gate thereof receives the output signal of NAND gate 29. The BL / SL driver 15 has the same configuration as the BL / SL driver 14.

  Next, operations of the data latch circuit LA0, the BL driver 16, and the SL driver 17 shown in FIG. 4 will be described. During the write operation, control signal R / W is set to the “L” level. When both corresponding memory array selection line MSL1 and column selection line CSL0 are set to the selection level “H” level and corresponding write data signal DI0 is set to “L” level, the output signals of NAND gates 24 and 26 Both become "L" level, P channel MOS transistor 27 becomes conductive and N channel MOS transistor 28 becomes nonconductive, and one end of corresponding bit line BL is set to "H" level. Further, the output signal of NAND gate 29 attains "H" level, P channel MOS transistor 30 is rendered non-conductive, N channel MOS transistor 31 is rendered conductive, and one end of corresponding source line SL is at "L" level. Is done.

  Next, when the signal DLE1 is set to the activation level “H” level and the selected word line WL is set to the selection level “H” level, the magnetizing current is applied to the digit line DL corresponding to the word line WL. Then, the magnetoresistive element 5 of each memory cell MC corresponding to the digit line DL is set in a half-selected state. Further, N channel MOS transistor 6 of each memory cell MC corresponding to the selected word line WL is turned on. Thus, the power voltage VCC line, the P channel MOS transistor 27, the bit line BL, the magnetoresistive element 5, the N channel MOS transistor 6, the source line SL, the N channel MOS transistor 31, and the ground voltage VSS line are written. Current flows, and the magnetoresistive element 5 is brought into a low resistance state, for example.

  When the corresponding memory array selection line MSL1 and column selection line CSL0 are set to the selection level “H” level and the corresponding write data signal DI0 is set to “H” level, the outputs of NAND gates 24 and 26 are output. Both signals attain "H" level, P channel MOS transistor 27 is rendered non-conductive, N channel MOS transistor 28 is rendered conductive, and one end of corresponding bit line BL is set to "L" level. Further, the output signal of NAND gate 29 attains "L" level, P channel MOS transistor 30 becomes conductive and N channel MOS transistor 31 becomes nonconductive, and one end of corresponding source line SL becomes "H" level. Is done.

  Next, when the signal DLE1 is set to the activation level “H” level and the selected word line WL is set to the selection level “H” level, the magnetizing current is applied to the digit line DL corresponding to the word line WL. Then, the magnetoresistive element 5 of each memory cell MC corresponding to the digit line DL is set in a half-selected state. Further, N channel MOS transistor 6 of each memory cell MC corresponding to the selected word line WL is turned on. Thus, the power voltage VCC line, the P channel MOS transistor 30, the source line SL, the N channel MOS transistor 6, the magnetoresistive element 5, the bit line BL, the N channel MOS transistor 28, and the ground voltage VSS line are written. Current flows, and the magnetoresistive element 5 is brought into a high resistance state, for example.

  In read operation, control signal R / W is set to “H” level. When the corresponding memory array selection line MSL1 and column selection line CSL0 are set to the selection level “H” level, the output signals of the NAND gates 24 and 26 are set to the “H” level and the “L” level, respectively. 28 become non-conductive, and one end of the corresponding bit line BL is set to a high impedance state. Further, the output signal of NAND gate 29 attains "H" level, P channel MOS transistor 30 is rendered non-conductive, N channel MOS transistor 31 is rendered conductive, and one end of corresponding source line SL is at "L" level. Is done.

  Further, the selected word line WL is set to the selection level “H” level, and the N-channel MOS transistor 6 of each memory cell MC corresponding to the word line WL is turned on. Read circuit 4 applies a read voltage sufficiently lower than the voltage during the write operation between bit line BL and source line SL of the selected column, and source line SL from bit line BL via selected memory cell MC. The data stored in the selected memory cell MC is read based on the current flowing through the memory cell.

  When the memory array selection line MSL1 is at the non-selection level “L” level, the output signal of the gate circuit 23 becomes “L” level regardless of the data signal DI and the control signal R / W, and the NAND gate 24 , 26 and 29 both attain "H" level, P channel MOS transistors 27 and 30 are rendered non-conductive, N channel MOS transistors 28 and 31 are rendered conductive, and one ends of bit line BL and source line SL Is supplied with the ground voltage VSS.

  FIG. 5 is a time chart showing the write operation of this MRAM. In FIG. 5, a write data signal DIx indicates any one of the write data signals DI0 to DI7. The bit line BLx and the source line SLx indicate the bit line BL and the source line SL of the column to which the data signal DIx is written.

  At time t0 to t3, eight data signals DI0 to DI7 are written in parallel to the eight memory cells MC in the selected row of the memory array MA1. FIG. 5 shows the time change of the signal when the “H” level data signal DIx is written in a certain memory cell MC among the eight memory cells MC.

  First, at time t0, the control signal R / W is set to the “L” level to start the write operation, and the write data signals DI0 to DI7 are input. A write data signal DIx among write data signals DI0-DI7 is raised to "H" level.

  Next, at time t1, the signal DLE1 is raised to the activation level “H” level, the selected word line WL is raised to the selection level “H” level, and the selected word line WL of the memory array MA1 is selected. The magnetizing current IDL1 is caused to flow through the digit line DL corresponding to. Thereby, the magnetoresistive element 5 of each memory cell MC corresponding to the digit line DL is brought into a half-selected state.

  Further, the transistor 6 of each memory cell MC corresponding to the selected word line WL is turned on. Further, both the column selection line CSL0 and the memory array selection line MSL1 are raised to the “H” level of the selection level, and the BL / SL driver 14 writes the write data signals DI0 to DI7 between the seven bit lines BL and the source line SL. A voltage having a polarity corresponding to DI7 is applied, and data signals DI0 to DI7 are written in parallel to the selected seven memory cells MC. FIG. 5 shows a state in which the bit line BLx and the source line SLx are set to the “L” level and the “H” level, respectively.

  Next, at time t2, the signal DLE1 falls to the “L” level of the inactivation level, and the current IDL1 of the digit line DL is cut off. Next, at time t3, the word line WL, the column selection line CSL0, and the memory array selection line MSL1 are all lowered to the “L” level of the non-selection level. As a result, transistor 6 of each memory cell MC is rendered non-conductive, both bit line BL and source line SL are set to “L” level, and one writing to memory array MA1 is completed. The reason why the current IDL1 of the digit line DL is cut off before the transistor 6 of the memory cell MC is turned off is to prevent erroneous writing due to an excessively applied magnetic field.

  At time t3 to t6, eight data signals DI0 to DI7 are written in parallel to the eight memory cells MC in the selected row of the memory array MA1. FIG. 5 shows a time change of a signal when an “L” level data signal DIx is written in a certain memory cell MC among the eight memory cells MC. In this case, bit line BLx and source line SLx are set to “H” level and “L” level, respectively. Other operations are the same as the write operations at times t0 to t3.

  At times t6 to t8, data signal DI is written to each of data latch circuits LA8 to LA255 corresponding to memory array MA2. That is, at time t6, control signal R / W is set to “H” level and memory array selection lines MSL1 and MSL2 are both set to “L” level to inactivate BL / SL drivers 14 and 15, Line BL and source line SL are fixed at the “L” level. Further, the data signals DI0 to DI7 are input 31 times in a predetermined cycle, and the column selection lines CSL1 to CSL31 are sequentially set to the “H” level one by one in a predetermined cycle. As a result, the data signal DI is written to each of the data latch circuits LA8 to LA255.

  Further, from time t8 to t11, 248 data signals DI output from the data latch circuits LA8 to LA255 are written in parallel to 248 memory cells MC in the selected row of the memory array MA2. FIG. 5 shows a time change of a signal when the data signal DIx of “H” level is written in a certain memory cell MC among 248 memory cells MC.

  First, at time t8, the control signal R / W is set to the “L” level and the writing operation is started. Next, at time t9, the signal DLE2 is raised to the activation level “H” level, the selected word line WL is raised to the selection level “H” level, and the selected word line WL of the memory array MA2 is selected. A magnetizing current IDL2 is passed through the digit line DL corresponding to. Thereby, the magnetoresistive element 5 of each memory cell MC corresponding to the digit line DL is brought into a half-selected state.

  Further, the transistor 6 of each memory cell MC corresponding to the selected word line WL is turned on. Further, the memory array selection line MSL2 is raised to the “H” level of the selection level, and the BL / SL driver 15 converts the output data signals DI of the data latch circuits LA8 to LA255 between the 248 bit lines BL and the source lines SL. A voltage having a corresponding polarity is applied, and 248 data signals DI are written in parallel to the selected 248 memory cells MC. FIG. 5 shows a state in which the bit line BLx and the source line SLx are set to the “H” level and the “L” level, respectively.

  Next, at time t10, signal DLE2 falls to “L” level, which is an inactivation level, and current IDL2 of digit line DL is cut off. Next, at time t11, both the word line WL and the memory array selection line MSL2 are lowered to the “L” level which is the non-selection level, and the writing to the memory array MA2 is completed.

  FIG. 6 is a circuit block diagram showing a comparative example of this embodiment, which is compared with FIG. In FIG. 6, in this comparative example, the DL driver 13 is removed, and the digit lines DL and the DL driver 10 are provided in common in the memory arrays MA1 and MA2. Accordingly, signals DLE1 and DLE2 are replaced with signal DLE. Further, the data latch circuits LA0 to LA255 are removed, and the BL / SL drivers 14 and 15 are replaced with the BL / DL driver 35. The BL / SL driver 35 is activated when the control signal R / W is at the “L” level, and is set to the “H” level among the column selection lines CSL0 to CSL31 according to the data signals DI0 to DI7. Eight sets of bit lines BL and source lines SL corresponding to CSL are driven, and data signals DI0 to DI7 are written into eight memory cells MC.

  During the write operation, control signal R / W is set to “L” level and BL / SL driver 35 is activated. The selected word line WL is set to the “H” level and the signal DLE is set to the “H” level, and a magnetizing current flows through the digit line DL corresponding to the selected word line WL, so that the corresponding digit line DL is supported. The magnetoresistive elements 5 of the 256 memory cells MC to be half-selected are set. Further, the transistors 6 of the 256 memory cells MC corresponding to the selected word line WL are turned on. Further, the data signals DI0 to DI7 are input, and any one of the column selection lines CSL0 to CSL31 is set to “H” level, and the BL / SL driver 35 applies the column selection line CSL to the column selection line CSL. Data signals DI0 to DI7 are written into the corresponding eight memory cells MC.

  In this comparative example, the magnetoresistive elements 5 of the 256 memory cells MC corresponding to one digit line DL are set in a half-selected state, and the data signal DI is written only in the magnetoresistive elements 5 of the eight memory cells MC. It is. Therefore, in the magnetoresistive element 5 in which the stored data is easily inverted among the magnetoresistive elements 5 of the remaining 248 memory cells MC, the stored data may be erroneously inverted.

  On the other hand, in the present invention, the eight (or 248) magnetoresistive elements 5 of the memory cells MC corresponding to one digit line DL are set to the half-selected state, and the eight (or the half-selected state) (or The data signal DI is written in parallel to all the magnetoresistive elements 5 of the (248) memory cells MC. Therefore, the stored data of the magnetoresistive element 5 will not be erroneously inverted. For this reason, a large magnetization current can be passed through the digit line DL, and the current passed through the magnetoresistive element 5 and the transistor 6 can be reduced. Therefore, the channel width of the transistor 6 can be reduced to reduce the layout area of the memory cell MC, and the layout area of the MRAM can be reduced.

  In the present invention, since the length of the digit line DL of the memory array MA1 is shorter than the length of the digit line DL of the memory array MA2, the writing operation of the memory array MA1 which is a RAM can be performed at high speed.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a block diagram showing an overall configuration of an MRAM according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing a configuration of a memory array shown in FIG. 1. FIG. 2 is a circuit block diagram showing a configuration of a writing circuit shown in FIG. 1. FIG. 4 is a circuit diagram showing a configuration of a data latch circuit and a BL / SL driver shown in FIG. 3. 5 is a time chart showing a write operation of the MRAM shown in FIGS. It is a circuit block diagram which shows the comparative example of embodiment.

Explanation of symbols

  MA1, MA2 memory array, 1 row decoder, 2 column decoder, 3 write circuit, 4 read circuit, MC memory cell, WL word line, DL digit line, BL bit line, SL source line, CSL column select line, MSL memory Array selection line, 5 Magnetoresistive element, 6, 12, 28, 31 N channel MOS transistor, 10, 13 DL driver, 11 AND gate, 14, 15, 35 BL / SL driver, LA data latch circuit, 16 BL driver, 17 SL driver, 20-22 inverter, 23 gate circuit, 24, 26, 29 NAND gate, 25 OR gate, 27, 30 P channel MOS transistor.

Claims (1)

M × N memory cells arranged in M rows and N columns (where each of M and N is an integer equal to or greater than 2), and M word lines provided corresponding to the M rows, , M digit lines provided corresponding to the M rows, N bit lines provided corresponding to the N columns, respectively, and N bit lines provided corresponding to the N columns, respectively. A memory array including a plurality of source lines,
Each memory cell has a magnetoresistive element that stores a data signal according to a change in resistance value, a gate connected to a corresponding word line, a source connected to a corresponding source line, and a drain via the magnetoresistive element. A transistor connected to a corresponding bit line,
A row decoder for setting any one of the M word lines to a selection level according to a row address signal and conducting N transistors corresponding to the word lines;
A first driver that applies a magnetizing current to a digit line in the same row as the word line selected by the row decoder and sets the magnetoresistive elements of N memory cells in the row to a half-selected state; Correspondingly provided, each receives N data signals, each passing a write current in a direction according to the logic of the received data signal between the bit line and source line of the corresponding column, and half-select A semiconductor memory device comprising N second drivers for writing the data signal to the magnetoresistive elements of the memory cells in the corresponding column brought into a state.

Images