JP2010049762A - Pipeline processing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pipeline processing device which establishes synchronization in a short time. <P>SOLUTION: A dummy signal generation circuit 13 inputs a video signal simultaneously with input to a pipeline processing circuit 11, and generates a dummy signal in which a synchronizing signal which has the same phase as that of the video signal output from the pipeline processing circuit 11 is inserted by using a cycle T of the synchronization signal included in the video signal and a delay time Td from input of the video signal in the pipeline processing circuit 11 to its output. A synchronization detection circuit 15 connects to the dummy signal generation circuit 13 during storing the video signal in the pipeline processing circuit, and detects the synchronization signal from the dummy signal generated in the dummy signal generation circuit 13. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a technology of a pipeline processing apparatus that pipelines a video signal.

  In general, a pipeline processing device that performs pipeline processing on an input video signal is formed in a video encoding device such as an encoder, a decoder, a post filter, or a pre-analysis unit, and video signal processing. In this pipeline processing apparatus, the pipeline processing circuit 11 and the synchronization detection circuit 15 are generally connected in cascade as shown in FIG.

  The pipeline processing circuit 11 performs certain processing such as filter processing for changing the spatial frequency characteristics of the video signal, for example, on the input video signal. In addition, there is also a feature that the output to the synchronization detection circuit 15 cannot be started unless the process of storing all the frames included in the input video signal in the storage unit (not shown) is completed.

  On the other hand, the synchronization detection circuit 15 receives the video signal output from the pipeline processing circuit 11, detects the synchronization signal inserted in the video signal, and each of the video signals included in the video signal based on the synchronization signal. Frames are output sequentially.

  Therefore, when the delay time Td is a delay time Td based on the processing of the pipeline processing circuit 11 and the synchronization establishment time Ts is a time required for the synchronization detection circuit 15 to establish synchronization, the video signal is processed by the pipeline processing apparatus 100. The time required from the input to the time until the synchronization is established and output is the sum of the delay time Td and the synchronization establishment time Ts.

  In addition, as shown in FIG. 5, a configuration in which a plurality of pipeline processing circuits and synchronization detection circuits are connected in cascade in a plurality of stages is generally employed. In such a configuration, the time required from when the video signal is input to the pipeline processing apparatus 100 until the synchronization is established and output is set to Td1 as the delay time in the first pipeline processing circuit 11a. When the synchronization establishment time in the first synchronization detection circuit 15a is Ts1, the delay time in the second pipeline processing circuit 11b is Td2, and the synchronization establishment time in the second synchronization detection circuit 15b is Ts2. The total time of the time Td1 and the synchronization establishment time Ts1 is a time obtained by further adding the total time of the delay time Td2 and the synchronization establishment time Ts2.

  FIG. 6 is a diagram showing a time chart of each circuit constituting the pipeline processing apparatus shown in FIG. The signal low level of the video signal output from each circuit indicates an invalid state, the signal high level indicates a valid state, Fn (n is an integer of 1 or more) indicates a frame number, and is described between the frames. The vertical line indicates the synchronization position.

  First, the video signal (input) becomes valid, and the output of the first pipeline processing circuit 11a becomes valid after the delay time Td1 has elapsed. Thereafter, after the synchronization establishment time Ts1 elapses, the output of the first synchronization detection circuit 15a becomes valid. Then, the output of the second pipeline processing circuit 11b becomes valid after the delay time Td2 elapses, and the output of the second synchronization detection circuit 15b becomes valid after the synchronization establishment time Ts2 elapses.

  As a result, in the conventional pipeline processing apparatus 100, the output of the video signal becomes valid after the delay time Td1 + synchronization establishment time Ts1 + delay time Td2 + synchronization establishment time Ts2 from the video signal input.

  In addition, when the first synchronization detection circuit 15a and the second synchronization detection circuit 15b require two frames to establish synchronization, the first synchronization detection circuit 15a loses the frames F1 and F2 and starts from the frame F3. Will be output. Similarly, in the second synchronization detection circuit 15b, the frame F3 and the frame F4 are lost and output from the frame F5.

  As a result, in the conventional pipeline processing apparatus 100, the four frames F1 to F4 are lost at the synchronization establishment time Ts1 and the synchronization establishment time Ts2, and the frames after the frame F5 are output as video signals.

  Therefore, since the pipeline processing circuit and the synchronization detection circuit are connected in cascade, the delay from the input of the video signal to the output is very large, and several frames input before the synchronization is established are lost. There was a problem that it was not output. In particular, as the number of stages of the pipeline processing circuit and the synchronization detection circuit increases, such a delay problem and a frame loss problem appear prominently.

To deal with this frame loss problem, Patent Document 1 discloses a technique for preventing data loss by delaying a signal before synchronization is established using a delay device.
JP-A-10-004439

  However, when the number of stages of each circuit is increased in order to delay the received signal itself, there is a problem that the delay time increases in proportion to the number of stages. Further, since the pipeline processing circuit starts output to the next stage after the video signal storage is completed as described above, there is a problem that it takes time to start the synchronization establishment processing.

  The present invention has been made in view of the above, and an object of the present invention is to provide a pipeline processing apparatus capable of establishing synchronization in a short time.

  The present invention described in claim 1 is a processing means for inputting a data signal in which a synchronization signal is inserted between each data and reading and outputting the data signal after storing the data signal in the storage means; and The data signal is input simultaneously with the input to the processing means, and a period of the synchronization signal included in the data signal and a delay time from when the data signal is input to the processing means until it is output are used. Generating means for generating a dummy signal in which a synchronization signal having the same phase as that of the data signal output from the processing means is inserted; connected to the generating means during the storage process; and generated by the generating means And a synchronization detecting means for detecting the synchronization signal from the dummy signal.

  The present invention as claimed in claim 2, wherein the synchronization detection means is connected to the processing means when the storage processing is completed, and synchronizes the data signal output from the processing means with the detected synchronization signal. The gist is to output.

  According to the third aspect of the present invention, when the storage process is being performed, the connection destination of the synchronization detection unit is the generation unit, and when the storage process is completed, switching is performed to switch the connection destination to the processing unit. The gist is to further include means.

  The gist of the present invention described in claim 4 is that the dummy signal is generated by delaying a remainder of the delay time divided by the period of the synchronization signal.

  According to the present invention, it is possible to provide a pipeline processing apparatus capable of establishing synchronization in a short time.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a configuration diagram showing a block configuration of the pipeline processing apparatus according to the present embodiment. The pipeline processing apparatus 100 includes a pipeline processing circuit 11, a dummy signal generation circuit 13 connected in parallel to the pipeline processing circuit 11, and synchronization detection located at the subsequent stage of the pipeline processing circuit 11 and the dummy signal generation circuit 13. The circuit 15 includes a switch circuit 17 that connects the synchronization detection circuit 15 to the pipeline processing circuit 11 or the dummy signal generation circuit.

  The pipeline processing circuit 11 has a function of performing certain processing such as filter processing for changing the spatial frequency characteristics of the video signal, for example, on the video signal in which the synchronization signal is inserted between the frames. In addition, the storage unit (not shown) stores all the frames included in the input video signal after the storage process is completed, and the output to the synchronization detection circuit 15 is started. . The pipeline processing circuit 11 corresponds to processing means described in the claims.

  The dummy signal generation circuit 13 inputs a video signal simultaneously with the input to the pipeline processing circuit 11, and after the synchronization signal cycle T included in the input video signal and the video signal are input to the pipeline processing circuit 11. Using the delay time Td until output, a function is provided for generating a dummy signal in which a synchronization signal having the same phase as the video signal output from the pipeline processing circuit 11 is inserted. The dummy signal generation circuit 13 corresponds to a generation unit described in the claims.

  The synchronization detection circuit 15 is connected to the dummy signal generation circuit 13 when the pipeline processing circuit 11 is storing video signals, and detects the synchronization signal from the dummy signal generated by the dummy signal generation circuit 13. It has. When the storage processing in the pipeline processing circuit 11 is completed, the synchronization signal is connected to the pipeline processing circuit 11 and each frame of the video signal output from the pipeline processing circuit 11 is detected from the dummy signal. It has a function to output in synchronization with. The synchronization detection circuit 15 corresponds to synchronization detection means described in the claims.

  When the pipeline processing circuit 11 is storing video signals, the switch circuit 17 sets the connection destination of the synchronization detection circuit 15 as the dummy signal generation circuit 13 and when the storage processing in the pipeline processing circuit 11 is completed. Has a function of switching the connection destination to the pipeline processing circuit 11. The switch circuit 17 corresponds to switching means described in the claims.

  Next, the processing flow of the pipeline processing apparatus 100 shown in FIG. 1 will be described. First, the pipeline processing circuit 11 stores the input video signal in a storage unit (not shown), reads out after the storage of all the frames is completed, and starts output after performing predetermined processing. (Step S101). Here, the time from when the video signal is input to the pipeline processing circuit 11 until it is output is defined as the delay time Td as described above.

  On the other hand, the dummy signal generation circuit 13 receives the video signal from the pipeline processing circuit 11 at the same time, inputs the video signal, and adjusts a certain phase from the input video signal, so that the same phase as the pipeline processing circuit 11 is obtained. Is generated and output (step S102).

  Here, a method for generating a dummy signal will be specifically described. The video signal has a structure in which synchronization signals are repeatedly inserted at intervals of a period T in units of frames. Further, as described above, the pipeline processing circuit 11 requires the delay time Td from the input to the output of the video signal. Therefore, a dummy signal is generated that is output by delaying the remaining time Td 'obtained by dividing the delay time Td spent in the pipeline processing circuit 11 by the period T of the synchronizing signal in the video signal. This makes it possible to generate a dummy signal having a synchronization signal at the same position as the synchronization signal position of the video signal output from the pipeline processing circuit 11. Since the generated dummy signal is used only for synchronization detection in the synchronization detection circuit 15, no specific condition other than the synchronization signal position is required.

  The switch circuit 17 selects the dummy signal generation circuit 13 during the period in which the pipeline processing circuit 11 stores the video signal in the storage unit (not shown), and after the storage processing is completed, the pipeline circuit The processing circuit 11 is selected, and the dummy signal generated by the dummy signal generation circuit 13 or the video signal output from the pipeline processing circuit 11 is output to the synchronization detection circuit 15 (step S103).

  Here, the switching operation of the switch circuit 17 will be specifically described. The switch circuit 17 determines the valid / invalid state of the signal output from the pipeline processing circuit 11 based on the presence / absence of a synchronization signal. When the synchronization signal is output within the same T time as the period T, the valid state is set. When the synchronous signal is not output, the disabled state is set. Then, the switch circuit 17 selects the dummy signal generated by the dummy signal generation circuit 13 in the period within the delay time Td after the signal input to the pipeline processing circuit 11 changes from the invalid state to the valid state. This period corresponds to a video signal storing process in the pipeline processing circuit 11 and corresponds to a period in which a signal output from the pipeline processing circuit 11 is in an invalid state. Then, after the delay time Td has elapsed, the switch circuit 17 selects the video signal output from the pipeline processing circuit 11. This period corresponds to a period in which the storage processing in the pipeline processing circuit 11 is completed and the signal output from the pipeline processing circuit 11 is in a valid state.

  Finally, the synchronization detection circuit 15 detects the synchronization signal using the dummy signal generated by the dummy signal generation circuit 13 during a period when the video signal is not output from the pipeline processing circuit 11, and the video signal is detected by the pipeline processing circuit. In the period transmitted from 11, each frame of the transmitted video signal is synchronized and output using the synchronization signal (step S104).

  Accordingly, when the time required for synchronization detection in the synchronization detection circuit 15 is set as the synchronization establishment time Ts, the time required from when the video signal is input to the pipeline processing apparatus 100 until the synchronization is established and output is delayed. It becomes a larger value (Max (Td, Ts)) of time Td and synchronization establishment time Ts. Therefore, synchronization can be established in a shorter time than the delay time Td + synchronization establishment time Ts of the conventional method shown in FIG.

  In addition, as shown in FIG. 2, the connection configuration of each circuit shown in FIG. The pipeline processing apparatus 100 shown in FIG. 2 includes a first pipeline processing circuit 11a, a first dummy signal generation circuit 13a connected in parallel to the first pipeline processing circuit 11a, and a first pipeline processing. The first synchronization detection circuit 15a and the first synchronization detection circuit 15a located at the subsequent stage of the circuit 11a and the first dummy signal generation circuit 13a are used as the first pipeline processing circuit 11a or the first dummy signal generation circuit 13a. Connected in parallel to the first switch circuit 17a, the second pipeline processing circuit 11b for inputting the video signal output from the first synchronization detection circuit 15a, and the second pipeline processing circuit 11b. The second dummy signal generation circuit 13b and the second synchronization located in the subsequent stage of the second pipeline processing circuit 11b and the second dummy signal generation circuit 13b A circuit 15b output, a configuration in which a second switch circuit 17b which connects the second synchronous detection circuit 15b to the second pipeline processing circuit 11b or the second dummy signal generating circuit 13b.

  Here, the delay time in the first pipeline processing circuit 11a is Td1, the synchronization establishment time in the first dummy signal generation circuit 13a is Ts1, and the delay time in the second pipeline processing circuit 11b is Td2. When the synchronization establishment time in the second dummy signal generation circuit 13b is Ts2, the time required from when the video signal is input to the pipeline processing apparatus 100 until the synchronization is established and output is the same as described above. Furthermore, the larger value (Max (Td1, Ts1)) of the delay time Td1 and the synchronization establishment time Ts1, and the larger value (Max (Td2, Ts2)) of the delay time Td2 and the synchronization establishment time Ts2 Total time. Therefore, synchronization can be established in a shorter time than the conventional delay time Td1 + synchronization establishment time Ts1 + delay time Td2 + synchronization establishment time Ts2 shown in FIG.

  FIG. 3 is a diagram showing a time chart of each circuit constituting the pipeline processing apparatus shown in FIG. The signal low level of the video signal output from each circuit indicates an invalid state, the signal high level indicates a valid state, Fn (n is an integer of 1 or more) indicates a frame number, and is described between the frames. The vertical line indicates the synchronization position.

  First, the video signal (input) becomes valid, and the output of the first pipeline processing circuit 11a becomes valid after the delay time Td1 has elapsed. At this time, the first dummy signal generation circuit 13a is also operating at the same time. Since the first dummy signal generation circuit 13a only adjusts the synchronization position, the dummy signal is generated at an early timing Td 'from the input of the video signal. Output is enabled. Further, since the first synchronization detection circuit 15a is connected to the first dummy signal generation circuit 13a by the first switch circuit 17a, synchronization is established after Ts1 after the dummy signal is valid. Therefore, in the first synchronization detection circuit 15a, synchronization is established in the time of Max (Td1, Td1 '+ Ts1). The second pipeline processing circuit 11b, the second dummy signal generation circuit 13b, the second switch circuit 17b, and the second synchronization detection circuit 15b have the same time chart.

  As a result, the time required from when the video signal is input to the pipeline processing apparatus 100 until the synchronization is established and output is Max (Td1, Td1 ′ + Ts1) and Max (Td2, Td2 ′ + Ts2). It becomes the total time, and synchronization can be established in a shorter time than the conventional pipeline processing apparatus. Since Td1 ′ is a time sufficiently smaller than Td1 and Td2 ′ is a time sufficiently smaller than Td2, Max (Td1, Td1 ′ + Ts1) is a value substantially equal to the aforementioned Max (Td1, Ts1). Thus, Max (Td2, Td2 ′ + Ts2) is substantially equal to Max (Td2, Ts2) described above.

  Even if the first synchronization detection circuit 15a requires two frames before the synchronization is established, the first synchronization detection circuit 15a detects the synchronization in advance using a dummy signal. The output can be started from the first frame F1 without losing F1 and the frame F2. Similarly, even if the second synchronization detection circuit 15b requires two frames before synchronization is established, the second synchronization detection circuit 15b detects the synchronization in advance using a dummy signal. The output can be started from the first frame F1 without losing the frames F1 and F2.

  As a result, the pipeline processing apparatus 100 according to the present embodiment outputs the video signal from the first frame without losing the four frames F1 to F4 at the synchronization establishment time Ts1 and the synchronization establishment time Ts2. be able to.

  In the present embodiment, the case where the pipeline processing circuit, the dummy signal generation circuit, the synchronization detection circuit, and the switch circuit are cascaded in one or two stages has been described. Similar effects can be obtained.

  Further, in the present embodiment, the signal input to the pipeline processing apparatus 100 has been described as a video signal in which a synchronization signal is inserted between each frame, but a signal having a similar data structure, that is, The present invention can also be applied to a data signal in which a synchronization signal is inserted between each data.

  According to the present embodiment, with respect to a conventional pipeline processing apparatus, a dummy signal generation circuit connected in parallel to the pipeline processing circuit and a connection destination to the synchronization detection circuit are connected to the pipeline processing circuit or the dummy signal generation circuit. And a switch for selecting either of the above, a dummy signal generation circuit is selected during a period in which a video signal is stored in the pipeline processing circuit, and a pipeline processing circuit is selected in a period after the storage processing is completed To do. The dummy signal generation circuit generates a dummy signal having the same phase as the output of the pipeline processing circuit using the period of the synchronization signal included in the video signal and the delay time for the video signal to pass through the pipeline processing circuit. Therefore, the video signal storage process and the synchronization detection process in the pipeline processing circuit can be started almost at the same time, so that the entire time from the input of the video signal to the establishment and output of the synchronization can be shortened. it can. Further, since synchronization is detected in advance using a dummy signal, frame loss can be prevented.

  Finally, the pipeline processing apparatus 100 described in the present embodiment is configured by a computer, and each process of each functional block is executed by a program. In addition, each operation of the pipeline processing apparatus 100 described in the present embodiment is recorded as a program on a recording medium such as a CD (Compact Disk) or an FD (Floppy (registered trademark) Disk), and the recording medium is stored in a computer. The program described above is installed in a computer or downloaded to a computer via an arbitrary communication line, or installed from a recording medium, and the computer is operated by the program, whereby the above-described processes are piped. Of course, it can function as the line processing apparatus 100. In addition, it should be added that the use of such a recording medium can improve the distribution.

It is a block diagram which shows the block configuration of the pipeline processing apparatus which concerns on this Embodiment. It is a block diagram which shows the structure which connected the connection structure of each circuit shown in FIG. It is a figure which shows the time chart of each circuit which comprises the pipeline processing apparatus shown in FIG. It is a block diagram which shows the block configuration of the conventional pipeline processing apparatus. FIG. 5 is a configuration diagram illustrating a configuration in which a plurality of stages of connection configurations of the circuits illustrated in FIG. 4 are connected in cascade. It is a figure which shows the time chart of each circuit which comprises the pipeline processing apparatus shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Pipeline processing circuit 11a ... 1st pipeline processing circuit 11b ... 2nd pipeline processing circuit 13 ... Dummy signal generation circuit 13a ... 1st dummy signal generation circuit 13b ... 2nd dummy signal generation circuit 15 ... Period detection circuit 15a ... 1st period detection circuit 15b ... 2nd period detection circuit 17 ... Switch circuit 17a ... 1st switch circuit 17b ... 2nd switch circuit 100 ... Pipeline processor S101-S104 ... Step

Claims (4)

Processing means for inputting a data signal in which a synchronization signal is inserted between each data and reading and outputting the data signal after the storage processing for storing the data signal in the storage means is completed;
The data signal is input simultaneously with the input to the processing means, and a period of the synchronization signal included in the data signal and a delay time from when the data signal is input to the processing means until it is output are used. Generating means for generating a dummy signal in which a synchronization signal having the same phase as the data signal output from the processing means is inserted;
Synchronization detecting means connected to the generating means during the storage process and detecting the synchronization signal from the dummy signal generated by the generating means;
A pipeline processing apparatus comprising: The synchronization detection means includes
2. The pipeline processing according to claim 1, wherein when the storage processing is completed, the pipeline processing is connected to the processing unit, and the data signal output from the processing unit is output in synchronization with the detected synchronization signal. apparatus.   And a switching unit that switches the connection destination to the processing unit when the storage process is completed. Item 3. The pipeline processing apparatus according to Item 2. The dummy signal is
4. The pipeline processing apparatus according to claim 1, wherein the pipeline processing apparatus is generated by delaying a remainder time obtained by dividing the delay time by the period of the synchronization signal. 5.

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