JP2010048649A - Semiconductor integrated circuit device and method for testing the semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device which can make a noise immunity evaluation of a circuit to be subjected to noise immunity evaluation with high precision. <P>SOLUTION: When the noise immunity of the circuit to be subjected to noise immunity evaluation 16 is measured, a control circuit 21 controls variable current sources 19 20 under the control of an external noise control signal, allows the sum of the current value of a current passed by the variable current source 19 and the current value of a current passed by the variable current source 20 to be maintained at a constant value, and causes increase/decrease changes, in the opposite directions for the current passed by the variable current source 19 and the current passed by the variable current source 20. When an increase/decrease change occurs in the current passed by the variable current source 19, increase/decrease changes in voltage drop is produced in resistors 18A, 18B. The increase/decrease change in voltage drop occurring in the resistor 18A is supplied to the circuit to be subjected to noise immunity evaluation 16 as high-potential side power supply noise, while the increase/decrease change in voltage drop occurring in the resistor 18B is supplied to the circuit which is to be subjected to noise immunity evaluation 16 as low-potential side power supply noise. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device equipped with a power supply noise generating circuit for testing and a method for testing the semiconductor integrated circuit device.

  The performance of a semiconductor integrated circuit device is degraded by power supply noise. However, a general method for knowing in advance the degree of performance degradation is not known. Conventionally, in order to investigate the degree of performance degradation, it is common practice to measure the characteristics by applying power supply noise to an actually created noise tolerance evaluation target circuit.

  FIG. 10 is a circuit diagram showing an example of a conventional semiconductor integrated circuit device together with an external power supply. In FIG. 10, 1 is an example of a conventional semiconductor integrated circuit device, and 2 is an external power supply for supplying a power supply voltage to the semiconductor integrated circuit device 1. In the semiconductor integrated circuit device 1, 3 is a noise tolerance evaluation target circuit, 4A is a power supply wiring on the high potential side, 4B is a power supply wiring on the low potential side, 5 is a variable current source forming a power noise generation circuit, and 6-8. Are NMOS transistors, and 9 to 11 are input terminals for inputting noise control signals SA1 to SA3 comprising digital signals.

In the semiconductor integrated circuit device 1, when measuring the noise tolerance of the noise tolerance evaluation target circuit 3, the NMOS transistors 6 to 8 are turned on and off by the noise control signals SA1 to SA3 to increase or decrease the current flowing through the variable current source 5. And the power supply voltage including the power supply noise generated thereby is given to the noise tolerance evaluation target circuit 3.
JP 2001-264394 A JP 2003-50264 A JP 2003-216682 A

  In the semiconductor integrated circuit device 1, the amount of power supply noise is determined by the variable current source 5, the noise control signals SA1 to SA3, and the parasitic impedances of the power supply wirings 4A and 4B. The parasitic impedances of the power supply wirings 4A and 4B include parasitic impedances such as bonding wires and power wirings in the semiconductor package and measurement probes. However, it is difficult to know the exact value of the parasitic impedance in advance. . For this reason, the voltage value of the power supply voltage including the power supply noise given to the noise tolerance evaluation target circuit 3 cannot be accurately known, and the noise tolerance evaluation of the noise tolerance evaluation target circuit 3 cannot be performed with high accuracy. was there.

  In view of the above, an object of the present invention is to provide a semiconductor integrated circuit device and a test method for the semiconductor integrated circuit device that can perform noise tolerance evaluation of a noise tolerance evaluation target circuit with high accuracy.

  The first semiconductor integrated circuit device includes a noise tolerance evaluation target circuit, a first resistor, a second resistor, a first variable current source, a second variable current source, and a control circuit. It is. The first resistor is connected between a first power supply line and a first power supply line of the noise tolerance evaluation target circuit. The second resistor is connected between a second power supply line and a second power supply line of the noise tolerance evaluation target circuit.

  According to the first semiconductor integrated circuit device, a voltage drop generated in the first resistor due to an increase / decrease change in the current flowing through the first variable current source during noise tolerance measurement of the noise tolerance evaluation target circuit. The increase / decrease change can be given to the noise tolerance evaluation target circuit as noise of the power supply voltage on the high potential side. Further, an increase / decrease change in the voltage drop generated in the second resistor due to an increase / decrease change in the current flowing through the first variable current source is given to the noise tolerance evaluation target circuit as noise of the power supply voltage on the low potential side. be able to.

  A first semiconductor integrated circuit device disclosed herein includes a noise tolerance evaluation target circuit, a first resistor, a second resistor, a first variable current source, a second variable current source, and a control circuit. It has. The first resistor is connected between a first power supply line and a first power supply line of the noise tolerance evaluation target circuit. The second resistor is connected between a second power supply line and a second power supply line of the noise tolerance evaluation target circuit.

  The first variable current source is connected between a connection portion between the first resistor and the first power supply wiring and a connection portion between the second resistance and the second power supply wiring. Is. The second variable current source is connected between a connection portion between the first resistor and the first power supply wiring and a connection portion between the second resistor and the second power supply wiring. It has been done.

  The control circuit controls the first variable current source and the second variable current source at the time of noise tolerance measurement of the noise tolerance evaluation target circuit, and a current value of a current flowing through the first variable current source And the current value of the current flowing through the second variable current source are maintained at a constant value, and the change is increased or decreased between the current flowing through the first variable current source and the current flowing through the second variable current source. Is something that causes

  The second semiconductor integrated circuit device disclosed herein includes a noise tolerance evaluation target circuit, a first resistor, a first variable current source, a second variable current source, and a control circuit. . The first resistor is connected between a first power supply line and a first power supply line of the noise tolerance evaluation target circuit.

  The first variable current source is connected between a connection portion between the first resistor and the first power supply wiring and a second power supply wiring of the noise tolerance evaluation target circuit. The second variable current source is connected between a connection portion between the first resistor and the first power supply wiring and the second power supply wiring.

  The control circuit controls the first variable current source and the second variable current source at the time of noise tolerance measurement of the noise tolerance evaluation target circuit, and a current value of a current flowing through the first variable current source And the current value of the current flowing through the second variable current source are maintained at a constant value, and the change is increased or decreased between the current flowing through the first variable current source and the current flowing through the second variable current source. Is something that causes

  The third semiconductor integrated circuit device disclosed herein includes a noise tolerance evaluation target circuit, a second resistor, a first variable current source, a second variable current source, and a control circuit. . The second resistor is connected between a second power supply line and a second power supply line of the noise tolerance evaluation target circuit.

  The first variable current source is connected between a first power supply wiring of the noise tolerance evaluation target circuit and a connection portion between the second resistor and the second power supply wiring. The second variable current source is connected between the first power supply wiring and a connection portion between the second resistor and the second power supply wiring.

  The control circuit controls the first variable current source and the second variable current source at the time of noise tolerance measurement of the noise tolerance evaluation target circuit, and a current value of a current flowing through the first variable current source And the current value of the current flowing through the second variable current source are maintained at a constant value, and the change is increased or decreased between the current flowing through the first variable current source and the current flowing through the second variable current source. Is something that causes

  A fourth semiconductor integrated circuit device disclosed herein includes a noise tolerance evaluation target circuit, a first resistor, a second resistor, a third variable current source, a fourth variable current source, and a fifth A variable current source and a control circuit. The first resistor is connected between a first power supply line and a first power supply line of the noise tolerance evaluation target circuit. The second resistor is connected between a second power supply line and a second power supply line of the noise tolerance evaluation target circuit.

  The third variable current source is connected between a connection portion between the first resistor and the first power supply wiring and a connection portion between the second resistance and the second power supply wiring. It is a thing. The fourth variable current source is connected between a connection portion between the first resistor and the first power supply wiring and a connection portion between the second resistance and the second power supply wiring. It is a thing. The fifth variable current source is connected between a connection portion between the first resistor and the first power supply wiring and a connection portion between the second resistor and the second power supply wiring. It has been done.

  The control circuit controls the third variable current source, the fourth variable current source, and the fifth variable current source to measure the third variable current source when the noise tolerance measurement of the noise tolerance evaluation target circuit is performed. The total value of the current value of the current flowing through the current source, the current value of the current flowing through the fourth variable current source, and the current value of the current flowing through the fifth variable current source is maintained at a constant value. The variable current source causes a change in the current flowing from the fifth variable current source and / or the current from the fourth variable current source.

  The first semiconductor integrated circuit device testing method disclosed herein includes a noise tolerance evaluation target circuit and a first power supply wiring connected between the first power supply wiring and the first power supply wiring of the noise tolerance evaluation target circuit. 1 resistor, a second resistor connected between the second power supply wiring and the second power supply wiring of the noise tolerance evaluation target circuit, the first resistance, and the first power supply wiring A first variable current source connected between a connection portion between the second resistor and the second power supply wiring, the first resistance, and the first power supply wiring. And a second variable current source connected between the connection portion of the second resistor and the second power supply wiring. The method of testing a semiconductor integrated circuit device.

  A test method for a first semiconductor integrated circuit device includes a step of supplying a power supply voltage from the outside between the first power supply wiring and the second power supply wiring, the first variable current source, Controlling a second variable current source, and maintaining a total value of a current value of a current flowing through the first variable current source and a current value of a current flowing through the second variable current source at a constant value, And a step of causing an increase / decrease change in the current flowing through the first variable current source and the current flowing through the second variable current source.

  The second semiconductor integrated circuit device testing method disclosed herein includes a noise tolerance evaluation target circuit, a first power supply wiring connected between the first power supply wiring and the first power supply wiring of the noise tolerance evaluation target circuit. A first variable current source connected between a first resistor, a connection portion between the first resistor and the first power supply wiring, and a second power supply wiring of the noise tolerance evaluation target circuit; A test method for a semiconductor integrated circuit device, comprising: a connection portion between the first resistor and the first power supply wiring; and a second variable current source connected between the second power supply wiring. .

  The second semiconductor integrated circuit device testing method includes a step of supplying a power supply voltage between the first power supply wiring and the second power supply wiring from the outside, the first variable current source, Controlling a second variable current source, and maintaining a total value of a current value of a current flowing through the first variable current source and a current value of a current flowing through the second variable current source at a constant value, And a step of causing an increase / decrease change in the current flowing through the first variable current source and the current flowing through the second variable current source.

  The third method for testing a semiconductor integrated circuit device disclosed herein is a noise immunity evaluation target circuit and a second power supply wiring connected between the second power supply wiring and the second power supply wiring of the noise immunity evaluation target circuit. 2, a first variable current source connected between the first power supply wiring of the noise tolerance evaluation target circuit, and a connection portion between the second resistance and the second power supply wiring; A test method for a semiconductor integrated circuit device comprising: the first power supply wiring; and a second variable current source connected between a connection portion between the second resistor and the second power supply wiring. .

  According to a third method for testing a semiconductor integrated circuit device, a step of supplying a power supply voltage from the outside between the first power supply wiring and the second power supply wiring, the first variable current source, Controlling a second variable current source, and maintaining a total value of a current value of a current flowing through the first variable current source and a current value of a current flowing through the second variable current source at a constant value, And a step of causing an increase / decrease change in the current flowing through the first variable current source and the current flowing through the second variable current source.

  A fourth semiconductor integrated circuit device testing method disclosed herein is a noise immunity evaluation target circuit and a first power supply wiring connected between the first power supply wiring and the first power supply wiring of the noise immunity evaluation target circuit. 1 resistor, a second resistor connected between the second power supply wiring and the second power supply wiring of the noise tolerance evaluation target circuit, the first resistance, and the first power supply wiring , A third variable current source connected between the connection portion of the second resistor and the second power supply wiring, the first resistor and the first power supply wiring A fourth variable current source connected between a connection portion between the second resistor and the second power supply wiring, the first resistance, and the first power supply wiring Connected between the connecting portion between the second resistor and the second power supply wiring. The semiconductor integrated circuit device having a variable current source is a method of testing.

  According to a fourth method for testing a semiconductor integrated circuit device, a step of supplying a power supply voltage from the outside between the first power supply wiring and the second power supply wiring, the third variable current source, The fourth variable current source and the fifth variable current source are controlled, the current value of the current flowing through the third variable current source, the current value of the current flowing through the fourth variable current source, and the fifth A total value of the current values of the currents supplied by the variable current source is maintained at a constant value, and one or both of the current supplied by the third variable current source and the current supplied by the fourth variable current source are And a step of causing an increase / decrease change in the current flowing through the fifth variable current source.

  According to the disclosed first semiconductor integrated circuit device, when the noise tolerance measurement of the noise tolerance evaluation target circuit is performed, the current flowing through the first variable current source is changed or increased, which is generated in the first resistor. The increase / decrease change of the voltage drop can be given to the noise tolerance evaluation target circuit as noise of the power supply voltage on the high potential side. Further, an increase / decrease change in the voltage drop generated in the second resistor due to an increase / decrease change in the current flowing through the first variable current source is given to the noise tolerance evaluation target circuit as noise of the power supply voltage on the low potential side. be able to.

  In this case, the control circuit keeps the total value of the current value of the current flowing through the first variable current source and the current value of the current flowing through the second variable current source at a constant value. The current value of the current flowing through the power supply wiring and the second power supply wiring is kept constant, and the voltage drop due to the parasitic impedance of the first power supply wiring and the second power supply wiring is reduced only by the resistance component. It can be a voltage drop. As a result, it is possible to accurately know the voltage value of the power supply voltage including noise applied to the noise tolerance evaluation target circuit, so that the noise tolerance evaluation of the noise tolerance evaluation target circuit can be performed with high accuracy.

  According to the disclosed second semiconductor integrated circuit device, when the noise tolerance measurement of the noise tolerance evaluation target circuit is performed, the current flowing through the first variable current source is changed or increased, which is generated in the first resistor. The increase / decrease change of the voltage drop can be given to the noise tolerance evaluation target circuit as noise of the power supply voltage on the high potential side.

  In this case, the control circuit keeps the total value of the current value of the current flowing through the first variable current source and the current value of the current flowing through the second variable current source at a constant value. The current value of the current flowing through the power supply wiring and the second power supply wiring is kept constant, and the voltage drop due to the parasitic impedance of the first power supply wiring and the second power supply wiring is reduced only by the resistance component. It can be a voltage drop. As a result, it is possible to accurately know the voltage value of the power supply voltage including noise applied to the noise tolerance evaluation target circuit, so that the noise tolerance evaluation of the noise tolerance evaluation target circuit can be performed with high accuracy.

  According to the disclosed third semiconductor integrated circuit device, when the noise tolerance measurement of the noise tolerance evaluation target circuit is performed, the current flowing through the first variable current source is changed or increased, which is generated in the second resistor. An increase / decrease change of the voltage drop can be given to the noise tolerance evaluation target circuit as noise of the power supply voltage on the low potential side.

  In this case, the control circuit keeps the total value of the current value of the current flowing through the first variable current source and the current value of the current flowing through the second variable current source at a constant value. The current value of the current flowing through the power supply wiring and the second power supply wiring is kept constant, and the voltage drop due to the parasitic impedance of the first power supply wiring and the second power supply wiring is reduced only by the resistance component. It can be a voltage drop. As a result, it is possible to accurately know the voltage value of the power supply voltage including noise applied to the noise tolerance evaluation target circuit, so that the noise tolerance evaluation of the noise tolerance evaluation target circuit can be performed with high accuracy.

  According to the disclosed fourth semiconductor integrated circuit device, when the noise tolerance measurement of the noise tolerance evaluation target circuit is performed, the current flowing through the third variable current source is changed or increased, which is generated in the first resistor. The increase / decrease change of the voltage drop can be given to the noise tolerance evaluation target circuit as noise of the power supply voltage on the high potential side. Further, an increase / decrease change in the voltage drop generated in the second resistor due to an increase / decrease change in the current flowing through the fourth variable current source is given to the noise tolerance evaluation target circuit as noise of the power supply voltage on the low potential side. be able to.

  In this case, the control circuit includes a current value of a current flowing through the third variable current source, a current value of a current flowing through the fourth variable current source, and a current value of a current flowing through the fifth variable current source. Therefore, the voltage drop due to the parasitic impedance of the first power supply wiring and the second power supply wiring can be made the voltage drop of only the resistance component. As a result, it is possible to accurately know the voltage value of the power supply voltage including noise applied to the noise tolerance evaluation target circuit, so that the noise tolerance evaluation of the noise tolerance evaluation target circuit can be performed with high accuracy.

  According to the disclosed test method of the first semiconductor integrated circuit device, the increase / decrease change of the voltage drop generated in the first resistor due to the increase / decrease change in the current flowing through the first variable current source is changed to the high potential side. The noise tolerance evaluation target circuit can be given as noise of the power supply voltage. Further, an increase / decrease change in the voltage drop generated in the second resistor due to an increase / decrease change in the current flowing through the first variable current source is given to the noise tolerance evaluation target circuit as noise of the power supply voltage on the low potential side. be able to.

  In this case, since the total value of the current value of the current flowing through the first variable current source and the current value of the current flowing through the second variable current source is kept constant, the first power supply wiring and The current value of the current flowing through the second power supply wiring is kept constant, and the voltage drop due to the parasitic impedance of the first power supply wiring and the second power supply wiring is a voltage drop of only the resistance component. Can do. As a result, it is possible to accurately know the voltage value of the power supply voltage including noise applied to the noise tolerance evaluation target circuit, so that the noise tolerance evaluation of the noise tolerance evaluation target circuit can be performed with high accuracy.

  According to the disclosed test method of the second semiconductor integrated circuit device, the increase / decrease change of the voltage drop generated in the first resistor due to the increase / decrease change in the current flowing through the first variable current source is changed to the high potential side. The noise tolerance evaluation target circuit can be given as noise of the power supply voltage.

  In this case, since the total value of the current value of the current flowing through the first variable current source and the current value of the current flowing through the second variable current source is kept constant, the first power supply wiring and The current value of the current flowing through the second power supply wiring is kept constant, and the voltage drop due to the parasitic impedance of the first power supply wiring and the second power supply wiring is a voltage drop of only the resistance component. Can do. As a result, it is possible to accurately know the voltage value of the power supply voltage including noise applied to the noise tolerance evaluation target circuit, so that the noise tolerance evaluation of the noise tolerance evaluation target circuit can be performed with high accuracy.

  According to the disclosed test method of the third semiconductor integrated circuit device, the increase / decrease change of the voltage drop generated in the second resistor due to the increase / decrease change in the current flowing through the first variable current source is reduced to the low potential side. The noise tolerance evaluation target circuit can be given as noise of the power supply voltage.

  In this case, since the total value of the current value of the current flowing through the first variable current source and the current value of the current flowing through the second variable current source is kept constant, the first power supply wiring and The current value of the current flowing through the second power supply wiring is kept constant, and the voltage drop due to the parasitic impedance of the first power supply wiring and the second power supply wiring is a voltage drop of only the resistance component. Can do. As a result, it is possible to accurately know the voltage value of the power supply voltage including noise applied to the noise tolerance evaluation target circuit, so that the noise tolerance evaluation of the noise tolerance evaluation target circuit can be performed with high accuracy.

  According to the disclosed test method of the fourth semiconductor integrated circuit device, the increase / decrease change of the voltage drop generated in the first resistor due to the increase / decrease change in the current flowing through the third variable current source is changed to the high potential side. The noise tolerance evaluation target circuit can be given as noise of the power supply voltage. Further, an increase / decrease change in the voltage drop generated in the second resistor due to an increase / decrease change in the current flowing through the fourth variable current source is given to the noise tolerance evaluation target circuit as noise of the power supply voltage on the low potential side. be able to.

  In this case, the total value of the current value of the current flowing through the third variable current source, the current value of the current flowing through the fourth variable current source, and the current value of the current flowing through the fifth variable current source is constant. Since the value is maintained, the voltage drop due to the parasitic impedance of the first power supply wiring and the second power supply wiring can be a voltage drop of only the resistance component. As a result, it is possible to accurately know the voltage value of the power supply voltage including noise applied to the noise tolerance evaluation target circuit, so that the noise tolerance evaluation of the noise tolerance evaluation target circuit can be performed with high accuracy.

  A semiconductor integrated circuit device and a semiconductor integrated circuit device testing method according to first to fourth embodiments of the present invention will be described below with reference to FIGS. The present invention is not limited to the first to fourth embodiments of the semiconductor integrated circuit device and the semiconductor integrated circuit device testing method of the present invention.

(First embodiment)
FIG. 1 is a circuit diagram showing a first embodiment of a semiconductor integrated circuit device of the present invention together with an external power supply. In FIG. 1, 14 is a first embodiment of the semiconductor integrated circuit device of the present invention, and 15 is an external power supply for supplying a power supply voltage to the first embodiment 14 of the semiconductor integrated circuit device of the present invention. In the semiconductor integrated circuit device according to the first embodiment 14 of the present invention, reference numeral 16 denotes a noise tolerance evaluation target circuit, 17A denotes a high potential side power supply wiring, and 17B denotes a low potential side power supply wiring. The power supply wirings 17A and 17B include a power supply wiring in the semiconductor package such as a bonding wire, and a power supply wiring at a connection portion between the external power supply 15 and the first embodiment 14 of the semiconductor integrated circuit device of the present invention.

  Reference numeral 18A denotes a resistor connected between the power supply wiring 17A and the power supply wiring (VDD power supply wiring) on the high potential side of the noise tolerance evaluation target circuit 16, and 18B denotes a low potential of the power supply wiring 17B and the noise tolerance evaluation target circuit 16. It is a resistor connected to the power supply wiring (VSS power supply wiring) on the side.

  Reference numeral 19 denotes a variable current source for generating power supply noise. The variable current source 19 includes a connection portion between the resistor 18A and the power supply wiring on the high potential side of the noise tolerance evaluation target circuit 16, and a connection portion between the resistor 18B and the power supply wiring on the low potential side of the noise tolerance evaluation target circuit 16. Connected between.

  Reference numeral 20 denotes a variable current source for stabilizing current consumption. This variable current source 20 is connected between a connection portion between the resistor 18A and the power supply wiring 17A and a connection portion between the resistor 18B and the power supply wiring 17B. ing.

  21 is a control circuit. The control circuit 21 is controlled by a noise control signal given from the outside to control the variable current sources 19 and 20, and the sum of the current value of the current flowing through the variable current source 19 and the current value of the current flowing through the variable current source 20. By keeping the value constant, the current flowing from the variable current source 19 and the current flowing from the variable current source 20 are caused to increase or decrease in opposite directions. Reference numeral 22 denotes a decoupling capacitor for reducing power supply noise due to an inductance component generated in the power supply wirings 17A and 17B in some cases.

  The first embodiment of the method for testing a semiconductor integrated circuit device of the present invention is directed to the first embodiment 14 of the semiconductor integrated circuit device of the present invention. From the external power supply 15 between the power supply wirings 17A and 17B. A step of supplying a power supply voltage, and the variable current sources 19 and 20 are controlled, and the total value of the current value of the current flowing through the variable current source 19 and the current value of the current flowing through the variable current source 20 is kept constant. And a step of causing an increase / decrease change in the current flowing through the variable current source 19 and the current flowing through the variable current source 20.

  When an increase / decrease change is generated in the current flowing through the variable current source 19, an increase / decrease change in voltage drop (IR drop) occurs in the resistors 18A, 18B. The increase / decrease change of the voltage drop generated in the resistor 18A is given to the noise tolerance evaluation target circuit 16 as noise of the power supply voltage on the high potential side. The increase / decrease change of the voltage drop generated in the resistor 18B is given to the noise tolerance evaluation target circuit 16 as noise of the power supply voltage on the low potential side.

Here, assuming that the current value of the current flowing from the variable current source 19 is I ₁ and the current value of the current flowing from the variable current source 20 is I ₂ , the control circuit 21 indicates that the current value I ₂ is a value represented by the equation (1). The variable current source 20 is controlled so that However, the current value Iconst is a value sufficiently larger than the current consumed by the noise tolerance evaluation target circuit 16.

  Further, the voltage drop Vdelta generated in the resistor 18A is as shown in Expression (2), where R is the resistance value of the resistor 18A.

  If the resistance component of the parasitic impedance of the power supply wiring 17A is Rp and the inductance component is Lp, the voltage drop Vdrop generated in the power supply wiring 17A when the current of the current value I flows in the power supply wiring 17A is As shown in equation (3).

  The current flowing through the power supply wiring 17A is Iconst as shown in Expression (1), and Iconst does not vary with time, so the second term of Expression (3) is always zero. Therefore, the power supply voltage Vmacro supplied to the noise tolerance evaluation target circuit 16 is set so that the resistance value of the resistor 18B is the same as that of the resistor 18A, the voltage drop generated in the power supply wiring 17B is the same as the voltage drop generated in the power supply wiring 17A, Assuming that the voltage output from the external power supply 15 is Vsupply, the following expression (4) is obtained.

  As described above, since the voltage drop due to the parasitic impedance of the power supply wirings 17A and 17B can be a voltage drop of only the resistance component, the voltage value of the power supply voltage including noise given to the noise tolerance evaluation target circuit 16 is accurately known. be able to.

Therefore, when measuring the noise immunity of the noise immunity evaluation target circuit 16, first, the current value I ₁ of the current flowing through the variable current source 19 is set to a certain value within the allowable range, and the noise immunity evaluation target circuit 16. Is measured, and the output voltage Vsupply of the external power supply 15 is set so that the voltage becomes 2Rp · Iconst higher than the power supply voltage Vmacro applied to the noise tolerance evaluation target circuit 16. Next, the amount of power supply noise given to the noise tolerance evaluation target circuit 16 is determined, and the current values I ₁ and I ₂ are set so that the power supply voltage Vmacro given to the noise tolerance evaluation target circuit 16 has a power supply voltage waveform with the noise. Try to change.

  If the current flowing through the variable current source 20 deviates from the equation (1), the current flowing through the power supply wirings 17A and 17B will vary with time, and the power supply due to the inductance component Lp of the parasitic impedance of the power supply wirings 17A and 17B. Noise is generated. In the first embodiment 14 of the semiconductor integrated circuit device of the present invention, a decoupling capacitor 22 is connected in parallel to the variable current source 20 in order to reduce power supply noise generated by the inductance component Lp.

(First Specific Example of First Embodiment of Semiconductor Integrated Circuit Device of the Present Invention)
FIG. 2 is a circuit diagram showing a first specific example of the first embodiment of the semiconductor integrated circuit device of the present invention together with an external power supply. The variable current source 19 is composed of a PMOS transistor 23. The PMOS transistor 23 has a source connected to the connection portion between the resistor 18A and the power supply wiring on the high potential side of the noise tolerance evaluation target circuit 16, and a drain connected to the resistor 18B and the power supply wiring on the low potential side of the noise tolerance evaluation target circuit 16. It is connected to the connecting part.

  The variable current source 20 includes an NMOS transistor 24 and resistors 25 and 26. The NMOS transistor 24 has a drain connected to a connection portion between the resistor 18A and the power supply wiring 17A via a resistor 25, and a source connected to a connection portion between the resistor 18B and the power supply wiring 17B via a resistor 26. .

  The control circuit 21 includes an NMOS transistor 27, a power supply 28, a current source 29, an input terminal 30 for inputting a noise control signal SB composed of an analog signal, and a substrate potential supply circuit 31. The NMOS transistor 27 has a gate connected to the input terminal 30, a power source 28 as a power source, a current source 29 as a load element, and a source follower circuit. The source is the gate of the PMOS transistor 23, the gate of the NMOS transistor 24, and the substrate. It is connected to the input node of the potential supply circuit 31.

  Even when the gate voltages of the PMOS transistor 23 and the NMOS transistor 24 are changed, the substrate potential supply circuit 31 accurately calculates the total value of the source-drain current of the PMOS transistor 23 and the drain-source current of the NMOS transistor 24. The substrate potential adjusted to a constant value is supplied to the NMOS transistor 24.

  FIG. 3 is a circuit diagram showing a configuration of the substrate potential supply circuit 31. In FIG. 3, 32 is a high potential side power supply wiring, 33 is a low potential side power supply wiring, 34 is an input node, 35 is a PMOS transistor, 36 to 38 are NMOS transistors, 39 and 40 are resistors, and 41 is a differential amplifier. , 42 are output nodes. The source voltage of the NMOS transistor 27 is supplied to the input node 34, and the voltage VO output to the output node 42 is supplied to the NMOS transistor 24 as the substrate potential.

  In this example, the size ratio between the PMOS transistor 35 and the NMOS transistor 38 is designed to be the same as the size ratio between the PMOS transistor 23 and the NMOS transistor 24. Further, when the substrate potential supply circuit 31 does not perform the substrate potential adjustment operation (when the potential of the input node 34 is 0 V), the magnitude relationship between the current Ip flowing through the PMOS transistor 35 and the current In flowing through the NMOS transistor 38 is expressed as Ip The sizes of the PMOS transistor 35, the NMOS transistor 38, the PMOS transistor 23, and the NMOS transistor 24 are determined so that> In.

  Here, if a voltage is applied to the input node 34, Ip> In, so that the voltage at the inverting input terminal of the differential amplifier 41 is Vp, and the voltage at the non-inverting input terminal of the differential amplifier 41 is Vn. <Vn, and the potential VO of the output node 42 increases. When the voltage VO at the output node 42 increases, the on-resistance value of the NMOS transistor 38 decreases due to the substrate effect, and the current In flowing through the NMOS transistor 38 increases. Eventually, the increase in the potential VO of the output node 42 stops when Vp = Vn, that is, when Ip = In, and the voltage VO of the output node 42 is the current of the PMOS transistor 35 and the NMOS transistor 38. The potentials are equal to each other.

  In the first specific example of the first embodiment of the semiconductor integrated circuit device of the present invention, by increasing or decreasing the potential of the noise control signal SB, the current flowing through the PMOS transistor 23 can be increased or decreased. Thus, the increase / decrease change of the voltage drop generated in the resistors 18A, 18B can be given to the noise tolerance evaluation target circuit 16 as power supply noise.

  In this case, when the potential of the noise control signal SB increases, the current flowing through the PMOS transistor 23 decreases and the current flowing through the NMOS transistor 24 increases. When the potential of the noise control signal SB decreases, the current flowing through the PMOS transistor 23 increases and the current flowing through the NMOS transistor 24 decreases. In this case, the substrate potential supply circuit 31 supplies the substrate potential VO of the NMOS transistor 24 according to the potential of the noise control signal SB so that the absolute values of the current changes of the PMOS transistor 23 and the NMOS transistor 24 are equal. .

  Here, for example, it is assumed that the standard power supply voltage applied to the noise tolerance evaluation target circuit 16 is 1.2 V, and power supply noise occurs at a maximum of ± 100 mV on each of the high potential side and the low potential side. Further, it is assumed that the inductance component Lp of the parasitic impedance of the power supply wirings 17A and 17B is several hundred to several thousand pico-henry, and the power supply noise fluctuates in steps at a speed of 100 mV at 100 ps.

Therefore, when a signal that changes at 100 mV / 100 ps is given to the noise tolerance evaluation target circuit 16, the time change of the current I flowing through the power supply wirings 17A and 17B is dI / dt = 1 × 10 ⁹ . Accordingly, voltage fluctuations generated in the power supply wirings 17A and 17B are about Lp (dI / dt) = 0.1 to 1.0 [V], respectively. This is a voltage fluctuation that is not negligible compared to the power supply voltage and power supply noise. If no countermeasures are taken, the noise tolerance evaluation target is caused by the voltage fluctuation caused by the parasitic impedance of the power supply wirings 17A and 17B. It is difficult to give the target power supply noise to the circuit 16.

  In the first specific example of the first embodiment 14 of the semiconductor integrated circuit device of the present invention, the resistance values of the resistors 18A, 18B, 25 and 26 are 1Ω, the current flowing through the PMOS transistor 23 and the current flowing through the NMOS transistor 24 are When 200 mA and the output voltage of the external power supply 15 are set to 1.4 V and the noise tolerance evaluation target circuit 16 is caused to cause arbitrary power supply fluctuations between 1.0 to 1.4 V, the current flows to the power supply wirings 17A and 17B. Since the current value is constant at 200 mA, voltage fluctuations caused by the parasitic impedance of the power supply wirings 17A and 17B can be ignored.

  In the first specific example of the first embodiment 14 of the semiconductor integrated circuit device of the present invention, the amount of power supply noise can be changed by changing the degree of increase / decrease change of the noise control signal SB made of an analog signal. More types of power supply noise can be given to the noise tolerance evaluation target circuit 16 than in the case of the conventional semiconductor integrated circuit device shown in FIG.

(Second Specific Example of the First Embodiment of the Semiconductor Integrated Circuit Device of the Present Invention)
FIG. 4 is a circuit diagram showing a second specific example of the first embodiment of the semiconductor integrated circuit device of the present invention together with an external power supply. The variable current source 19 includes NMOS transistors 45 to 47. The NMOS transistors 45 to 47 have their drains connected to the connection portion between the resistor 18A and the power supply wiring on the high potential side of the noise tolerance evaluation target circuit 16, and their sources connected to the power supply on the low potential side of the resistor 18B and the noise tolerance evaluation target circuit 16. Connected to the connection with the wiring.

  The variable current source 20 includes NMOS transistors 48-50. The NMOS transistors 48 to 50 have drains connected to a connection portion between the resistor 18A and the power supply wiring 17A, and sources connected to a connection portion between the resistor 18B and the power supply wiring 17B. All of the NMOS transistors 45 to 50 may flow the same current value, or may weight the flowing current.

  The control circuit 21 has input terminals 51 to 53 for inputting noise control signals SC1 to SC3 made of digital signals, and inverters 54 to 56 for inverting the noise control signals SC1 to SC3. The input terminal 51 is connected to the gate of the NMOS transistor 45 and the input terminal of the inverter 54. The input terminal 52 is connected to the gate of the NMOS transistor 46 and the input terminal of the inverter 55. The input terminal 53 is connected to the gate of the NMOS transistor 47 and the input terminal of the inverter 56.

  The output terminal of the inverter 54 is connected to the gate of the NMOS transistor 48. The output terminal of the inverter 55 is connected to the gate of the NMOS transistor 49. The output terminal of the inverter 56 is connected to the gate of the NMOS transistor 50.

  Power supply noise can be generated by switching one or more of the NMOS transistors 45 to 47 and one or more of the NMOS transistors 48 to 50 by the noise control signals SC1 to SC3. Since the number of NMOS transistors to be switched in the NMOS transistors 45 to 47 is the same as the number of NMOS transistors to be switched in the NMOS transistors 48 to 50, the number of NMOS transistors that are turned on when viewed from the external power supply 15. Is always constant, and the current value of the current flowing through the power supply wirings 17A and 17B is a constant value.

  Further, when the sizes of the NMOS transistors 45 to 50 are the same, it is possible to generate power supply noise having different fluctuation levels by changing the number of NMOS transistors to be switched. Further, when weighting the current flowing through the NMOS transistors 45 to 50, the NMOS transistor to be switched is changed not only when the number of NMOS transistors to be switched is changed but also when the number of NMOS transistors to be switched is one. As a result, it is possible to generate power supply noise having different fluctuation levels. Therefore, more types of power supply noise can be given to the noise tolerance evaluation target circuit 16 than in the case of the conventional semiconductor integrated circuit device shown in FIG.

  Further, if the potentials of the noise control signals SC1 to SC3 are changed in the period of the basic clock used by the first embodiment 14 of the semiconductor integrated circuit device of the present invention, the power supply noise synchronized with the basic clock is changed to the noise tolerance evaluation target circuit. 16 can be given. Further, if the potentials of the noise control signals SC1 to SC3 are changed at a cycle slower than the cycle of the basic clock, power supply noise having a cycle slower than that of the basic clock can be given to the noise tolerance evaluation target circuit 16. Further, if the potentials of the noise control signals SC1 to SC3 are changed at a period earlier than that of the basic clock, power supply noise that varies within the basic clock can be given.

  As described above, according to the first embodiment 14 of the semiconductor integrated circuit device of the present invention, an increase / decrease change of the voltage change generated in the resistor 18A by causing the current flowing through the variable current source 19 to increase / decrease is increased to a high potential. The noise tolerance evaluation target circuit 16 can be given as noise of the power supply voltage on the side. In addition, by causing the current flowing from the variable current source 20 to increase or decrease, the increase or decrease of the voltage drop generated in the resistor 18B can be given to the noise tolerance evaluation target circuit 16 as noise of the power supply voltage on the low potential side.

  In this case, the control circuit 21 controls the variable current sources 19 and 20, and maintains the total value of the current value of the current flowing through the variable current source 19 and the current value of the current flowing through the variable current source 20 at a constant value. The current value of the current flowing through the power supply wirings 17A and 17B can be set to a constant value, and the voltage drop due to the parasitic impedance of the power supply wirings 17A and 17B can be a voltage drop of only the resistance component. As a result, since the voltage value of the power supply voltage including the power supply noise given to the noise tolerance evaluation target circuit 16 can be accurately known, the noise tolerance evaluation of the noise tolerance evaluation target circuit 16 can be performed with high accuracy.

(Second Embodiment)
FIG. 5 is a circuit diagram showing a second embodiment of the semiconductor integrated circuit device of the present invention together with an external power supply. In the second embodiment 57 of the semiconductor integrated circuit device according to the present invention, the low-potential-side resistor 18B provided in the first embodiment 14 of the semiconductor integrated circuit device according to the present invention is deleted. The apparatus is configured in the same manner as in the first embodiment. The variable current sources 19 and 20 and the control circuit 21 can be configured similarly to the case shown in FIG. 2 or FIG.

  The second embodiment of the method for testing a semiconductor integrated circuit device according to the present invention is directed to the second embodiment 57 of the semiconductor integrated circuit device according to the present invention, and an external power source is provided between the power supply wirings 17A and 17B. 15, the power supply voltage is supplied from the control circuit 15 and the variable current sources 19 and 20 are controlled, and the total value of the current value of the current flowing through the variable current source 19 and the current value of the current flowing through the variable current source 20 is kept constant. In addition, the method includes a step of causing an increase / decrease change in the current flowing through the variable current source 19 and the current flowing through the variable current source 20.

  According to the second embodiment 57 of the semiconductor integrated circuit device of the present invention, an increase / decrease change in the voltage drop generated in the resistor 18A by causing an increase / decrease change in the current flowing through the variable current source 19 is reduced to the power supply voltage on the high potential side. It can be given to the noise tolerance evaluation target circuit 16 as noise.

  In this case, the control circuit 21 controls the variable current sources 19 and 20, and maintains the total value of the current value of the current flowing through the variable current source 19 and the current value of the current flowing through the variable current source 20 at a constant value. The current value of the current flowing through the power supply wirings 17A and 17B can be set to a constant value, and the voltage drop due to the parasitic impedance of the power supply wirings 17A and 17B can be a voltage drop of only the resistance component. As a result, since the voltage value of the power supply voltage including the power supply noise given to the noise tolerance evaluation target circuit 16 can be accurately known, the noise tolerance evaluation of the noise tolerance evaluation target circuit 16 can be performed with high accuracy.

(Third embodiment)
FIG. 6 is a circuit diagram showing a third embodiment of the semiconductor integrated circuit device of the present invention together with an external power supply. In the third embodiment 58 of the semiconductor integrated circuit device according to the present invention, the high-potential-side resistor 18A provided in the first embodiment 14 of the semiconductor integrated circuit device according to the present invention is deleted. The apparatus is configured in the same manner as in the first embodiment. The variable current sources 19 and 20 and the control circuit 21 can be configured similarly to the case shown in FIG. 2 or FIG.

  The third embodiment of the method for testing a semiconductor integrated circuit device according to the present invention is directed to the third embodiment 58 of the semiconductor integrated circuit device according to the present invention, and an external power source is provided between the power supply wirings 17A and 17B. 15, the power supply voltage is supplied from the control circuit 15 and the variable current sources 19 and 20 are controlled, and the total value of the current value of the current flowing through the variable current source 19 and the current value of the current flowing through the variable current source 20 is kept constant. In addition, the method includes a step of causing an increase / decrease change in the current flowing through the variable current source 19 and the current flowing through the variable current source 20.

  According to the third embodiment 58 of the semiconductor integrated circuit device of the present invention, an increase / decrease change in the voltage drop generated in the resistor 18B by causing an increase / decrease change in the current flowing through the variable current source 19 is reduced. It can be given to the noise tolerance evaluation target circuit 16 as noise.

  In this case, the control circuit 21 controls the variable current sources 19 and 20, and maintains the total value of the current value of the current flowing through the variable current source 19 and the current value of the current flowing through the variable current source 20 at a constant value. The current value of the current flowing through the power supply wirings 17A and 17B can be set to a constant value, and the voltage drop due to the parasitic impedance of the power supply wirings 17A and 17B can be a voltage drop of only the resistance component. As a result, since the voltage value of the power supply voltage including the power supply noise given to the noise tolerance evaluation target circuit 16 can be accurately known, the noise tolerance evaluation of the noise tolerance evaluation target circuit 16 can be performed with high accuracy.

(Fourth embodiment)
FIG. 7 is a circuit diagram showing a fourth embodiment of the semiconductor integrated circuit device of the present invention together with an external power supply. In FIG. 7, 60 is a first embodiment of the semiconductor integrated circuit device of the present invention, and 61 is an external power supply for supplying a power supply voltage to the first embodiment 60 of the semiconductor integrated circuit device of the present invention. In the fourth embodiment 60 of the semiconductor integrated circuit device of the present invention, 62 is a noise tolerance evaluation target circuit, 63A is a high-potential-side power supply wiring, and 63B is a low-potential-side power supply wiring. The power supply wirings 63A and 63B include a power supply wiring in the semiconductor package such as a bonding wire, a power supply wiring at a connection portion between the external power supply 61 and the fourth embodiment 60 of the semiconductor integrated circuit device of the present invention.

  Reference numeral 64A denotes a resistor connected between the power supply wiring 63A and the power supply wiring on the high potential side of the noise tolerance evaluation target circuit 62. Reference numeral 64B denotes a power supply wiring on the low potential side of the power supply wiring 63B and the noise tolerance evaluation target circuit 62. It is the resistance connected between.

  Reference numeral 65 denotes a variable current source for generating power source noise on the high potential side. The variable current source 65 is connected between a connection portion between the resistor 64A and the power supply wiring on the high potential side of the noise tolerance evaluation target circuit 62 and a connection portion between the resistor 64B and the power supply wiring 63B.

  Reference numeral 66 denotes a variable current source for generating power source noise on the low potential side. The variable current source 66 is connected between a connection portion between the resistor 64A and the power supply wiring 63A and a connection portion between the resistor 64B and the power supply wiring on the low potential side of the noise tolerance evaluation target circuit 62.

  Reference numeral 67 denotes a variable current source for stabilizing current consumption. The variable current source 67 is connected between a connection portion between the resistor 64A and the power supply wiring 63A and a connection portion between the resistor 64B and the power supply wiring 63B.

  Reference numeral 68 denotes a control circuit. The control circuit 68 is controlled by a noise control signal given from the outside to control the variable current sources 65 to 67, the current value of the current flowing through the variable current source 65, the current value of the current flowing through the variable current source 66, and the variable current. The total value of the currents flowing from the source 67 is kept constant, and either or both of the current flowing from the variable current source 65 and the current flowing from the variable current source 66 and the current flowing from the variable current source 67 are used. This causes an increase / decrease change.

  The fourth embodiment of the semiconductor integrated circuit device testing method of the present invention is directed to the fourth embodiment 60 of the semiconductor integrated circuit device of the present invention. From the external power supply 61 between the power supply wirings 63A and 63B. A step of supplying a power supply voltage, and control of the variable current sources 65 to 67, a current value of a current flowing through the variable current source 65, a current value of a current flowing through the variable current source 66, and a current value of a current flowing through the variable current source 67 And maintaining a constant value to cause an increase / decrease change in one or both of the current flowing from the variable current source 65 and the current flowing from the variable current source 66 and the current flowing from the variable current source 67. Is included.

  When only the high-potential-side power supply noise is given to the noise tolerance evaluation target circuit 62, the current value of the current flowing through the variable current source 66 is made constant, and the current flowing through the variable current source 65 is increased or decreased. In this way, a voltage drop increase / decrease change occurs in the resistor 64A, and the voltage drop increase / decrease change generated in the resistor 64A is given to the noise tolerance evaluation target circuit 62 as noise of the power supply voltage on the high potential side.

  When only the low-potential-side power supply noise is given to the noise tolerance evaluation target circuit 62, the current value of the current flowing through the variable current source 65 is made constant, and the current flowing through the variable current source 66 is increased or decreased. In this way, a change in voltage drop is generated in the resistor 64B, and the change in voltage drop generated in the resistor 64B is given to the noise tolerance evaluation target circuit 62 as noise of the power supply voltage on the low potential side.

  Further, when the high-potential-side and low-potential-side power supply noise is given to the noise tolerance evaluation target circuit 62, the current flowing from the variable current sources 65 and 66 is caused to increase or decrease. In this way, an increase / decrease change in the voltage drop occurs in each of the resistors 64A and 64B, and an increase / decrease change in the voltage drop generated in the resistor 64A is given to the noise tolerance evaluation target circuit 62 as noise of the power supply voltage on the high potential side. At the same time, an increase / decrease change in the voltage drop generated in the resistor 64B is given to the noise tolerance evaluation target circuit 62 as noise of the low-potential power supply voltage.

  When the current flowing from the variable current source 65 and the current flowing from the variable current source 66 are caused to increase or decrease in the same direction, the power supply wiring on the high potential side and the power supply on the low potential side of the noise tolerance evaluation target circuit 62 are used. Power supply noise having the same phase can be given to the wiring. Further, when the current flowing from the variable current source 65 and the current flowing from the variable current source 66 are caused to increase or decrease in the opposite directions, the high-potential-side power supply wiring and the low-potential-side power supply of the noise tolerance evaluation target circuit 62 are used. Power supply noise having an opposite phase can be given to the wiring.

(First Specific Example of Fourth Embodiment of Semiconductor Integrated Circuit Device of the Present Invention)
FIG. 8 is a circuit diagram showing a first specific example of the fourth embodiment of the semiconductor integrated circuit device of the present invention together with an external power supply. The variable current source 65 is composed of a PMOS transistor 70. The PMOS transistor 70 has a source connected to a connection portion between the resistor 64A and the power supply wiring on the high potential side of the noise tolerance evaluation target circuit 62, and a drain connected to a connection portion between the resistor 64B and the power supply wiring 63B.

  The variable current source 66 is composed of a PMOS transistor 71. The PMOS transistor 71 has a source connected to the connection portion between the resistor 64A and the power supply wiring 63A, and a drain connected to a connection portion between the resistor 64B and the power supply wiring on the low potential side of the noise tolerance evaluation target circuit 62.

  The variable current source 67 includes NMOS transistors 72 and 73 and resistors 74 and 75. The NMOS transistor 72 has a drain connected to a connection portion between the resistor 64A and the power supply wiring 63A via a resistor 74, and a source connected to a connection portion between the resistor 64B and the power supply wiring 63B. The NMOS transistor 73 has a drain connected to a connection portion between the resistor 64A and the power supply wiring 63B, and a source connected via a resistor 75 to a connection portion between the resistor 64B and the power supply wiring 63B.

  The control circuit 68 includes input terminals 76 and 77 for inputting noise control signals SD1 and SD2 made of analog signals, a control circuit 78 for controlling the PMOS transistor 70 and the NMOS transistor 72, and a PMOS transistor 71 and an NMOS transistor 73. And a control circuit 79 for controlling.

  The control circuit 78 supplies a gate voltage to the PMOS transistor 70 and the NMOS transistor 72 and supplies a substrate potential to the NMOS transistor 72. The control circuit 79 supplies a gate voltage to the PMOS transistor 71 and the NMOS transistor 73 and supplies a substrate potential to the NMOS transistor 73.

  The control circuit 78 includes an NMOS transistor 80, a power supply 81, a current source 82, and a substrate potential supply circuit 83. The NMOS transistor 80 has a gate connected to the input terminal 76, a power source 81 as a power source, a current source 82 as a load element, and forms a source follower circuit. The substrate potential supply circuit 83 is configured similarly to the substrate potential supply circuit 31 shown in FIG.

  The control circuit 79 includes an NMOS transistor 84, a power supply 85, a current source 86, and a substrate potential supply circuit 87. The NMOS transistor 84 has a gate connected to the input terminal 77, a power source 85 as a power source, a current source 86 as a load element, and forms a source follower circuit. The substrate potential supply circuit 87 is configured similarly to the substrate potential supply circuit 31 shown in FIG.

  In the first specific example of the fourth embodiment 60 of the semiconductor integrated circuit device of the present invention, when only the high-potential-side power supply noise is given to the noise tolerance evaluation target circuit 62, for example, the noise control signal SD2 is set to the intermediate potential. And the potential of the noise control signal SD1 is increased or decreased. In this way, the current value of the current flowing through the PMOS transistor 71 and the NMOS transistor 73 can be made constant, and the current flowing through the PMOS transistor 70 and the NMOS transistor 72 can be caused to increase or decrease in the reverse direction. In this case, an increase / decrease change in the voltage drop occurs in the resistor 64A due to an increase / decrease change in the current flowing through the PMOS transistor 70. Given to.

  Further, when only the low-potential-side power supply noise is given to the noise tolerance evaluation target circuit 62, for example, the noise control signal SD1 is fixed to an intermediate potential, and the potential of the noise control signal SD2 is changed. In this way, the current values of the currents flowing through the PMOS transistor 70 and the NMOS transistor 72 can be made constant, and the currents flowing through the PMOS transistor 71 and the NMOS transistor 73 can be increased or decreased in the reverse direction. In this case, an increase / decrease change in the voltage drop occurs in the resistor 64B due to an increase / decrease change in the current flowing through the PMOS transistor 71, and the increase / decrease change in the voltage drop of the resistor 64B is regarded as noise of the power supply voltage on the low potential side. Given to.

  In addition, when the high-potential-side and low-potential-side power supply noise is given to the noise tolerance evaluation target circuit 62, the potentials of the noise control signals SD1 and SD2 are changed. In this way, the current flowing through the PMOS transistor 70 and the NMOS transistor 72 can be caused to increase and decrease in the reverse direction, and the current flowing through the PMOS transistor 71 and the NMOS transistor 73 can be caused to increase and decrease in the reverse direction. it can. In this case, an increase / decrease change in the voltage drop occurs in the resistor 64A due to an increase / decrease change in the current flowing through the PMOS transistor 70, and the increase / decrease change in the voltage drop of the resistor 64A is regarded as noise of the power supply voltage on the high potential side. Given to. In addition, the increase / decrease change in the voltage drop occurs in the resistor 64B due to the increase / decrease change in the current flowing through the PMOS transistor 71, and the increase / decrease change in the voltage drop of the resistor 64B occurs in the noise tolerance evaluation target circuit 62 as noise of the low-potential power supply voltage. Given.

  Note that when the potential of the noise control signal SD1 increases, the current flowing through the PMOS transistor 70 decreases and the current flowing through the NMOS transistor 72 increases. When the potential of the noise control signal SD1 decreases, the current flowing through the PMOS transistor 70 increases and the current flowing through the NMOS transistor 72 decreases. In these cases, the substrate potential supply circuit 83 supplies the substrate potential VO1 of the NMOS transistor 72 according to the potential of the noise control signal SD1 so that the absolute values of the current changes of the PMOS transistor 70 and the NMOS transistor 72 are equal.

  When the potential of the noise control signal SD2 increases, the current flowing through the PMOS transistor 71 decreases and the current flowing through the NMOS transistor 73 increases. When the potential of the noise control signal SD2 becomes low, the current flowing through the PMOS transistor 71 increases and the current flowing through the NMOS transistor 73 decreases. In these cases, the substrate potential supply circuit 87 supplies the substrate potential VO2 of the NMOS transistor 73 according to the potential of the noise control signal SD2 so that the absolute values of the current changes of the PMOS transistor 71 and the NMOS transistor 73 are equal.

(Second Specific Example of Fourth Embodiment of Semiconductor Integrated Circuit Device of the Present Invention)
FIG. 9 is a circuit diagram showing a second specific example of the fourth embodiment of the semiconductor integrated circuit device of the present invention together with an external power supply. The variable current source 65 includes NMOS transistors 88 and 89. The NMOS transistors 88 and 89 have drains connected to the connection portion between the resistor 64A and the power supply wiring on the high potential side of the noise tolerance evaluation target circuit 62, and sources connected to a connection portion between the resistor 64B and the power supply wiring 63B. Yes.

  The variable current source 66 is composed of NMOS transistors 90 and 91. The NMOS transistors 90 and 91 have drains connected to a connection portion between the resistor 64A and the power supply wiring 63A, and sources connected to a connection portion between the resistor 64B and the power supply wiring on the low potential side of the noise tolerance evaluation target circuit 62. Yes.

  The variable current source 67 includes NMOS transistors 92 to 95. The NMOS transistors 92 to 95 have drains connected to a connection portion between the resistor 64A and the power supply wiring 63A, and sources connected to a connection portion between the resistor 64B and the power supply wiring 63B.

  The control circuit 68 has input terminals 96 to 99 for inputting noise control signals SE1 to SE4 composed of digital signals, and inverters 100 to 103 for inverting the noise control signals SE1 to SE4. The input terminal 96 is connected to the gate of the NMOS transistor 88 and the input terminal of the inverter 100. The input terminal 97 is connected to the gate of the NMOS transistor 89 and the input terminal of the inverter 101. The input terminal 98 is connected to the gate of the NMOS transistor 90 and the input terminal of the inverter 102. The input terminal 99 is connected to the gate of the NMOS transistor 91 and the input terminal of the inverter 103.

  The output terminal of the inverter 100 is connected to the gate of the NMOS transistor 92. The output terminal of the inverter 101 is connected to the gate of the NMOS transistor 93. The output terminal of the inverter 102 is connected to the gate of the NMOS transistor 94. The output terminal of the inverter 103 is connected to the gate of the NMOS transistor 95.

  When only the high-potential-side power supply noise is given to the noise tolerance evaluation target circuit 62, for example, the noise control signals SE3 and SE4 are fixed to the H level, and the potential of one or both of the noise control signals SE1 and SE2 is set. Change. In this way, the PMOS transistors 90 and 91 are fixed to ON and the NMOS transistors 94 and 95 are fixed to OFF, and either one or both of the PMOS transistors 88 and 89 and one or both of the NMOS transistors 92 and 93 are switched. Will do. In this case, an increase / decrease change in the voltage drop occurs in the resistor 64A due to an increase / decrease change in the current flowing through one or both of the PMOS transistors 88 and 89, and the increase / decrease change in the voltage drop of the resistor 64A is caused by the power supply voltage on the high potential side. The noise is given to the noise tolerance evaluation target circuit 62 as noise.

  Further, in this case, the number of NMOS transistors to be switched in the NMOS transistors 88 and 89 is the same as the number of NMOS transistors to be switched in the NMOS transistors 92 and 93. The number of NMOS transistors included is constant, and the current value of the current flowing through the power supply wirings 63A and 63B is a constant value.

  In addition, when only the low-potential-side power supply noise is given to the noise tolerance evaluation target circuit 62, for example, the noise control signals SE1 and SE2 are fixed to the H level, and one or both of the noise control signals SE3 and SE4 are fixed. Change the potential. In this way, the PMOS transistors 88 and 89 are fixed to ON, the NMOS transistors 92 and 93 are fixed to OFF, and either one or both of the PMOS transistors 90 and 91 and one or both of the NMOS transistors 94 and 95 are switched. Will do. In this case, an increase / decrease change in the voltage drop occurs in the resistor 64B due to an increase / decrease change in the current flowing through one or both of the PMOS transistors 90, 91, and the increase / decrease change in the voltage drop of the resistor 64B is caused by the power supply voltage on the low potential side. The noise is given to the noise tolerance evaluation target circuit 62 as noise.

  In this case, the number of NMOS transistors to be switched in the NMOS transistors 90 and 91 and the number of NMOS transistors to be switched in the NMOS transistors 94 and 95 are the same. The number of NMOS transistors included is constant, and the current value of the current flowing through the power supply wirings 63A and 63B is a constant value.

  When applying high-potential-side and low-potential-side power supply noise to the noise tolerance evaluation target circuit 62, the potential of either or both of the noise control signals SE1 and SE2 and the noise control signals SE3 and SE4. To change. In this way, one or both of the PMOS transistors 88 and 89, one or both of the PMOS transistors 90 and 91, one or both of the NMOS transistors 92 and 93, and any of the NMOS transistors 94 and 95 Either or both will perform the switching operation.

  In this case, an increase / decrease change in the voltage drop occurs in the resistor 64A due to an increase / decrease change in the current flowing through one or both of the PMOS transistors 88 and 89, and the increase / decrease change in the voltage drop of the resistor 64A is caused by the power supply voltage on the high potential side. The noise is supplied to the noise tolerance evaluation target circuit 62 as noise, and the increase / decrease change in the voltage drop occurs in the resistor 64B due to the increase / decrease change in the current flowing through one or both of the PMOS transistors 90, 91. The increase / decrease change is given to the noise tolerance evaluation target circuit 62 as noise of the power supply voltage on the low potential side.

  In this case, the number of switching NMOS transistors in the NMOS transistors 88 and 89 is equal to the number of switching NMOS transistors in the NMOS transistors 92 and 93. Further, the number of NMOS transistors to be switched in the NMOS transistors 90 and 91 and the number of NMOS transistors to be switched in the NMOS transistors 94 and 95 are the same. Therefore, when viewed from the external power supply 61, the number of NMOS transistors that are ON is constant, and the current value of the current flowing through the power supply wirings 63A and 63B is a constant value.

  Further, if the potentials of the noise control signals SE1 to SE4 are changed at the period of the basic clock used by the fourth embodiment 60 of the semiconductor integrated circuit device of the present invention, the power supply noise synchronized with the basic clock is converted into the noise tolerance evaluation target circuit. 62. Further, if the potentials of the noise control signals SE1 to SE2 are changed at a period slower than the period of the basic clock, power supply noise having a period later than the basic clock can be given to the noise tolerance evaluation target circuit 62. Further, if the potentials of the noise control signals SE1 to SE4 are changed at a period earlier than that of the basic clock, power supply noise that varies within the basic clock can be given.

  As described above, according to the fourth embodiment 60 of the semiconductor integrated circuit device of the present invention, an increase / decrease change of the voltage drop generated in the resistor 64A by causing the current flowing through the variable current source 65 to increase / decrease is increased. Can be given to the noise tolerance evaluation target circuit 62 as noise of the power supply voltage on the side. Further, by causing the current flowing from the variable current source 66 to increase or decrease, the increase or decrease of the voltage drop generated in the resistor 64B can be given to the noise tolerance evaluation target circuit 62 as noise of the power supply voltage on the low potential side.

  In this case, the control circuit 68 controls the variable current sources 65 to 67, the current value of the current flowing through the variable current source 65, the current value of the current flowing through the variable current source 66, and the current value of the current flowing through the variable current source 67. Is maintained at a constant value, the current value of the current flowing through the power supply wirings 63A and 63B is set to a constant value, and the voltage drop due to the parasitic impedance of the power supply wirings 63A and 63B is the voltage drop of only the resistance component. Can do. As a result, the voltage value of the power supply voltage including the noise given to the noise tolerance evaluation target circuit 62 can be accurately known, so that the noise tolerance evaluation of the noise tolerance evaluation target circuit 62 can be performed with high accuracy.

  Here, the semiconductor integrated circuit device and the test method of the semiconductor integrated circuit device of the present invention are organized. The semiconductor integrated circuit device and the test method of the semiconductor integrated circuit device of the present invention include at least the following semiconductor integrated circuit device and semiconductor: A method for testing an integrated circuit device is included.

(Appendix 1)
Noise tolerance evaluation target circuit,
A first resistor connected between the first power supply wiring and the first power supply wiring of the noise tolerance evaluation target circuit;
A second resistor connected between a second power supply wiring and a second power supply wiring of the noise tolerance evaluation target circuit;
A first variable current source connected between a connection portion between the first resistor and the first power supply wiring and a connection portion between the second resistance and the second power supply wiring;
A second variable current source connected between a connection portion between the first resistor and the first power supply wiring and a connection portion between the second resistor and the second power supply wiring; ,
When the noise tolerance measurement of the noise tolerance evaluation target circuit is performed, the first variable current source and the second variable current source are controlled, and the current value of the current flowing through the first variable current source and the second variable current source are controlled. A control circuit that keeps the total value of the currents flowing through the variable current source at a constant value and causes an increase / decrease change in the current flowing through the first variable current source and the current flowing through the second variable current source When,
A semiconductor integrated circuit device comprising:

(Appendix 2)
Noise tolerance evaluation target circuit,
A first resistor connected between the first power supply wiring and the first power supply wiring of the noise tolerance evaluation target circuit;
A first variable current source connected between a connection portion between the first resistor and the first power supply wiring and a second power supply wiring of the noise tolerance evaluation target circuit;
A second variable current source connected between a connection portion between the first resistor and the first power supply wiring, and the second power supply wiring;
When the noise tolerance measurement of the noise tolerance evaluation target circuit is performed, the first variable current source and the second variable current source are controlled, and the current value of the current flowing through the first variable current source and the second variable current source are controlled. A control circuit that keeps the total value of the currents flowing through the variable current source at a constant value and causes an increase / decrease change in the current flowing through the first variable current source and the current flowing through the second variable current source When,
A semiconductor integrated circuit device comprising:

(Appendix 3)
Noise tolerance evaluation target circuit,
A second resistor connected between a second power supply wiring and a second power supply wiring of the noise tolerance evaluation target circuit;
A first variable current source connected between a first power supply wiring of the noise tolerance evaluation target circuit and a connection portion between the second resistor and the second power supply wiring;
A second variable current source connected between the first power supply wiring and a connection portion between the second resistor and the second power supply wiring;
When the noise tolerance measurement of the noise tolerance evaluation target circuit is performed, the first variable current source and the second variable current source are controlled, and the current value of the current flowing through the first variable current source and the second variable current source are controlled. A control circuit that keeps the total value of the currents flowing through the variable current source at a constant value and causes an increase / decrease change in the current flowing through the first variable current source and the current flowing through the second variable current source When,
A semiconductor integrated circuit device comprising:

(Appendix 4)
The first variable current source includes a first conductivity type first field effect transistor as a variable current source transistor,
The second variable current source has a second conductivity type second field effect transistor as a variable current source transistor,
4. The semiconductor integrated circuit device according to any one of appendices 1 to 3, wherein the control circuit provides an analog control signal to a gate of the first field effect transistor and a gate of the second field effect transistor.

(Appendix 5)
The control circuit sets the substrate potential so that the absolute value of the increase / decrease change in the current flowing through the first field effect transistor is the same as the absolute value of the increase / decrease change in the current passed through the second field effect transistor. 5. The semiconductor integrated circuit device according to appendix 4, further comprising a substrate potential supply circuit that supplies the second field effect transistor.

(Appendix 6)
Noise tolerance evaluation target circuit,
A first resistor connected between the first power supply wiring and the first power supply wiring of the noise tolerance evaluation target circuit;
A second resistor connected between a second power supply wiring and a second power supply wiring of the noise tolerance evaluation target circuit;
A third variable current source connected between a connection portion between the first resistor and the first power supply wiring and a connection portion between the second resistance and the second power supply wiring;
A fourth variable current source connected between a connection portion between the first resistor and the first power supply wiring and a connection portion between the second resistor and the second power supply wiring;
A fifth variable current source connected between a connection portion between the first resistor and the first power supply wiring, and a connection portion between the second resistor and the second power supply wiring; ,
A current flowing through the third variable current source by controlling the third variable current source, the fourth variable current source, and the fifth variable current source during noise tolerance measurement of the noise tolerance evaluation target circuit; Current value of the current flowing through the fourth variable current source and the current value of the current flowing through the fifth variable current source are kept constant, and the third variable current source A control circuit for causing an increase / decrease change in one or both of a current flowing and a current flowing by the fourth variable current source, and a current flowing by the fifth variable current source;
A semiconductor integrated circuit device comprising:

(Appendix 7)
Noise tolerance evaluation target circuit,
A first resistor connected between the first power supply wiring and the first power supply wiring of the noise tolerance evaluation target circuit;
A second resistor connected between a second power supply wiring and a second power supply wiring of the noise tolerance evaluation target circuit;
A first variable current source connected between a connection portion between the first resistor and the first power supply wiring and a connection portion between the second resistance and the second power supply wiring;
A second variable current source connected between a connection portion between the first resistor and the first power supply wiring and a connection portion between the second resistor and the second power supply wiring; ,
A method for testing a semiconductor integrated circuit device having:
Supplying a power supply voltage from the outside between the first power supply wiring and the second power supply wiring;
The first variable current source and the second variable current source are controlled, and the sum of the current value of the current flowing through the first variable current source and the current value of the current flowing through the second variable current source Maintaining the value at a constant value, causing the current flowing from the first variable current source and the current flowing from the second variable current source to increase or decrease;
A method for testing a semiconductor integrated circuit device, comprising:

(Appendix 8)
Noise tolerance evaluation target circuit,
A first resistor connected between the first power supply wiring and the first power supply wiring of the noise tolerance evaluation target circuit;
A first variable current source connected between a connection portion between the first resistor and the first power supply wiring and a second power supply wiring of the noise tolerance evaluation target circuit;
A second variable current source connected between a connection portion between the first resistor and the first power supply wiring, and the second power supply wiring;
A method for testing a semiconductor integrated circuit device having:
Supplying a power supply voltage from the outside between the first power supply wiring and the second power supply wiring;
The first variable current source and the second variable current source are controlled, and the sum of the current value of the current flowing through the first variable current source and the current value of the current flowing through the second variable current source Maintaining the value at a constant value, causing the current flowing from the first variable current source and the current flowing from the second variable current source to increase or decrease;
A method for testing a semiconductor integrated circuit device, comprising:

(Appendix 9)
Noise tolerance evaluation target circuit,
A second resistor connected between a second power supply wiring and a second power supply wiring of the noise tolerance evaluation target circuit;
A first variable current source connected between a first power supply wiring of the noise tolerance evaluation target circuit and a connection portion between the second resistor and the second power supply wiring;
A second variable current source connected between the first power supply wiring and a connection portion between the second resistor and the second power supply wiring;
A method for testing a semiconductor integrated circuit device having:
Supplying a power supply voltage from the outside between the first power supply wiring and the second power supply wiring;
The first variable current source and the second variable current source are controlled, and the sum of the current value of the current flowing through the first variable current source and the current value of the current flowing through the second variable current source Maintaining the value at a constant value, causing the current flowing from the first variable current source and the current flowing from the second variable current source to increase or decrease;
A method for testing a semiconductor integrated circuit device, comprising:

(Appendix 10)
Noise tolerance evaluation target circuit,
A first resistor connected between the first power supply wiring and the first power supply wiring of the noise tolerance evaluation target circuit;
A second resistor connected between a second power supply wiring and a second power supply wiring of the noise tolerance evaluation target circuit;
A third variable current source connected between a connection portion between the first resistor and the first power supply wiring and a connection portion between the second resistance and the second power supply wiring;
A fourth variable current source connected between a connection portion between the first resistor and the first power supply wiring and a connection portion between the second resistor and the second power supply wiring;
A fifth variable current source connected between a connection portion between the first resistor and the first power supply wiring, and a connection portion between the second resistor and the second power supply wiring; ,
A method for testing a semiconductor integrated circuit device having:
Supplying a power supply voltage from the outside between the first power supply wiring and the second power supply wiring;
The third variable current source, the fourth variable current source, and the fifth variable current source are controlled, and the current value of the current that the third variable current source passes and the fourth variable current source are The total value of the current value of the flowing current and the current value of the current flowing by the fifth variable current source is kept constant, and the current flowing by the third variable current source and the fourth variable current source flow. A step of causing an increase / decrease change in any one or both of the current and the current flowing by the fifth variable current source;
A method for testing a semiconductor integrated circuit device, comprising:

1 is a circuit diagram showing a first embodiment of a semiconductor integrated circuit device of the present invention together with an external power supply. 1 is a circuit diagram showing a first specific example of a first embodiment of a semiconductor integrated circuit device of the present invention together with an external power supply. FIG. 1 is a circuit diagram showing a configuration of a substrate potential supply circuit in a control circuit included in a first specific example of a first embodiment of a semiconductor integrated circuit device of the present invention; FIG. It is a circuit diagram which shows the 2nd specific example of 1st Embodiment of the semiconductor integrated circuit device of this invention with an external power supply. It is a circuit diagram which shows 2nd Embodiment of the semiconductor integrated circuit device of this invention with an external power supply. It is a circuit diagram which shows 3rd Embodiment of the semiconductor integrated circuit device of this invention with an external power supply. It is a circuit diagram which shows 4th Embodiment of the semiconductor integrated circuit device of this invention with an external power supply. It is a circuit diagram which shows the 1st specific example of 4th Embodiment of the semiconductor integrated circuit device of this invention with an external power supply. It is a circuit diagram which shows the 2nd specific example of 4th Embodiment of the semiconductor integrated circuit device of this invention with an external power supply. It is a circuit diagram which shows an example of the conventional semiconductor integrated circuit device with an external power supply.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Example of conventional semiconductor integrated circuit device 2 ... External power supply 3 ... Noise tolerance evaluation object circuit 4A, 4B ... Power supply wiring 5 ... Variable current source 6-8 ... NMOS transistor 9-11 ... Input terminal 14 ... First embodiment of semiconductor integrated circuit device 15 ... external power supply 16 ... noise tolerance evaluation target circuit 17A, 17B ... power supply wiring 18A, 18B ... resistor 19,20 ... variable current source 21 ... control circuit 22 ... decoupling capacitor 23 ... PMOS transistor 24 ... NMOS transistor 25, 26 ... resistor 27 ... NMOS transistor 28 ... power supply 29 ... current source 30 ... input terminal 31 ... substrate potential supply circuit 32 ... power supply wiring on high potential side,
33 ... Low-potential-side power supply wiring 34 ... Input node 35 ... PMOS transistor 36-38 ... NMOS transistor 39, 40 ... Resistance 41 ... Differential amplifier 42 ... Output node 45-50 ... NMOS transistor 51-53 ... Input terminal 54- 56 ... Inverter 57 ... Second Embodiment of Semiconductor Integrated Circuit Device of the Present Invention 58 ... Third Embodiment of Semiconductor Integrated Circuit Device of the Present Invention 60 ... Fourth Embodiment of Semiconductor Integrated Circuit Device of the Present Invention 61 ... External Power Supply 62 ... Noise tolerance evaluation target circuit 63A, 63B ... Power supply wiring 64A, 64B ... Resistors 65-67 ... Variable current source 68 ... Control circuit 69 ... Decoupling capacitance 70, 71 ... PMOS transistor 72, 73 ... NMOS transistor 74, 75 ... Resistors 76, 77 ... Input terminals 78, 79 ... Control circuit 80 ... NMOS transistors Star 81 ... Power source 82 ... Current source 83 ... Substrate potential supply circuit 84 ... NMOS transistor 85 ... Power source 86 ... Current source 87 ... Substrate potential supply circuit 88-95 ... NMOS transistor 96-99 ... Input terminal 100-103 ... Inverter

Claims (5)

Noise tolerance evaluation target circuit,
A first resistor connected between the first power supply wiring and the first power supply wiring of the noise tolerance evaluation target circuit;
A second resistor connected between a second power supply wiring and a second power supply wiring of the noise tolerance evaluation target circuit;
A first variable current source connected between a connection portion between the first resistor and the first power supply wiring and a connection portion between the second resistance and the second power supply wiring;
A second variable current source connected between a connection portion between the first resistor and the first power supply wiring and a connection portion between the second resistor and the second power supply wiring; ,
When the noise tolerance measurement of the noise tolerance evaluation target circuit is performed, the first variable current source and the second variable current source are controlled, and the current value of the current flowing through the first variable current source and the second variable current source are controlled. A control circuit that keeps the total value of the currents flowing through the variable current source at a constant value and causes an increase / decrease change in the current flowing through the first variable current source and the current flowing through the second variable current source When,
A semiconductor integrated circuit device comprising: Noise tolerance evaluation target circuit,
A first resistor connected between the first power supply wiring and the first power supply wiring of the noise tolerance evaluation target circuit;
A first variable current source connected between a connection portion between the first resistor and the first power supply wiring and a second power supply wiring of the noise tolerance evaluation target circuit;
A second variable current source connected between a connection portion between the first resistor and the first power supply wiring, and the second power supply wiring;
When the noise tolerance measurement of the noise tolerance evaluation target circuit is performed, the first variable current source and the second variable current source are controlled, and the current value of the current flowing through the first variable current source and the second variable current source are controlled. A control circuit that keeps the total value of the currents flowing through the variable current source at a constant value and causes an increase / decrease change in the current flowing through the first variable current source and the current flowing through the second variable current source When,
A semiconductor integrated circuit device comprising: Noise tolerance evaluation target circuit,
A second resistor connected between a second power supply wiring and a second power supply wiring of the noise tolerance evaluation target circuit;
A first variable current source connected between a first power supply wiring of the noise tolerance evaluation target circuit and a connection portion between the second resistor and the second power supply wiring;
A second variable current source connected between the first power supply wiring and a connection portion between the second resistor and the second power supply wiring;
When the noise tolerance measurement of the noise tolerance evaluation target circuit is performed, the first variable current source and the second variable current source are controlled, and the current value of the current flowing through the first variable current source and the second variable current source are controlled. A control circuit that keeps the total value of the currents flowing through the variable current source at a constant value and causes an increase / decrease change in the current flowing through the first variable current source and the current flowing through the second variable current source When,
A semiconductor integrated circuit device comprising: Noise tolerance evaluation target circuit,
A first resistor connected between the first power supply wiring and the first power supply wiring of the noise tolerance evaluation target circuit;
A second resistor connected between a second power supply wiring and a second power supply wiring of the noise tolerance evaluation target circuit;
A third variable current source connected between a connection portion between the first resistor and the first power supply wiring and a connection portion between the second resistance and the second power supply wiring;
A fourth variable current source connected between a connection portion between the first resistor and the first power supply wiring and a connection portion between the second resistor and the second power supply wiring;
A fifth variable current source connected between a connection portion between the first resistor and the first power supply wiring, and a connection portion between the second resistor and the second power supply wiring; ,
A current flowing through the third variable current source by controlling the third variable current source, the fourth variable current source, and the fifth variable current source during noise tolerance measurement of the noise tolerance evaluation target circuit; Current value of the current flowing through the fourth variable current source and the current value of the current flowing through the fifth variable current source are kept constant, and the third variable current source A control circuit for causing an increase / decrease change in one or both of a current flowing and a current flowing by the fourth variable current source, and a current flowing by the fifth variable current source;
A semiconductor integrated circuit device comprising: Noise tolerance evaluation target circuit,
A first resistor connected between the first power supply wiring and the first power supply wiring of the noise tolerance evaluation target circuit;
A second resistor connected between a second power supply wiring and a second power supply wiring of the noise tolerance evaluation target circuit;
A first variable current source connected between a connection portion between the first resistor and the first power supply wiring and a connection portion between the second resistance and the second power supply wiring;
A second variable current source connected between a connection portion between the first resistor and the first power supply wiring and a connection portion between the second resistor and the second power supply wiring; ,
A method for testing a semiconductor integrated circuit device having:
Supplying a power supply voltage from the outside between the first power supply wiring and the second power supply wiring;
The first variable current source and the second variable current source are controlled, and the sum of the current value of the current flowing through the first variable current source and the current value of the current flowing through the second variable current source Maintaining the value at a constant value, causing the current flowing from the first variable current source and the current flowing from the second variable current source to increase or decrease;
A method for testing a semiconductor integrated circuit device, comprising:

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