JP2010044638A - Information processing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processing apparatus performing boot-up processing without depending on an address bit length of a slave device. <P>SOLUTION: The information processing apparatus includes: a serial interface for serially transmitting each bit of an address and serially receiving each bit of data; a boot memory for storing a boot program; and a control circuit for executing the boot program in start and performing start time processing. In the start time processing, the control circuit determines whether data serially received by the serial interface with first timing as start timing match prescribed data and, when the data do not match, determines whether the data serially received by the serial interface with second timing as start timing match the prescribed data. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention generally relates to an information processing system, and more particularly to an information processing system including an information processing apparatus that operates by receiving and executing firmware.

  In information processing apparatuses, firmware for performing information processing is often stored in an external ROM. When booting, the information processing apparatus downloads firmware from the external ROM, and executes the downloaded firmware to execute predetermined information processing. With such a configuration, it becomes possible to change the contents of information processing only by rewriting the firmware of the external ROM, and a highly flexible information processing system can be constructed.

  More specifically, a boot loader program is stored in a boot ROM inside the information processing apparatus, and at the time of booting, the information processing apparatus is activated by the boot loader program stored in the boot ROM. The information processing apparatus reads the firmware recorded in the external serial ROM according to the boot loader program, and starts information processing such as encoding / decoding.

  A predetermined keyword is arranged at the head of the firmware stored in the memory location starting from address 0 of the serial ROM. The control CPU of the information processing apparatus checks keywords in the downloaded data while downloading the firmware. When the information processing apparatus successfully reads a predetermined keyword, the information processing apparatus determines that the external ROM exists, and downloads the program stored in the position following the keyword from the external ROM. If reading of a predetermined keyword fails, it is determined that an error has occurred, and the information processing apparatus interrupts the boot-up process.

  FIG. 1 is a diagram showing a schematic configuration of an interface of the SPI protocol. SPI (Serial Peripheral Interface) is a serial protocol for connecting a microprocessor to various peripheral devices such as a memory, a sensor, a conversion device, and a control device. In the configuration shown in FIG. 1, communication between the SPI master 10 and the SPI slave 15 is performed. For communication, two data lines, one control line, and one synchronous clock are used. MOSI (Master Out Slave In) is a data line from the output of the SPI master 10 to the input of the SPI slave 15. MISO (Master In Slave Out) is a data line from the output of the SPI slave 15 to the input of the SPI master 10. SCK (Serial Clock) is a clock signal supplied from the SPI master 10 to the SPI slave 15 and is used to synchronize data bits. / SS (Slave Select) is a select signal for selecting individual slaves by the SPI slave 15 and is selected when the select signal is LOW. In the configuration example of FIG. 1, only one SPI slave is provided, so the SPI slave 15 is fixed in the selected state.

  The SPI master 10 includes a shift register 11 and a baud rate generator 12. The SPI slave 15 includes a shift register 16. The shift register 11 includes a reception shift register and a transmission shift register. For example, write data is written to the transmission shift register of the shift register 11 by the control CPU. The data stored in the transmission shift register of the shift register 11 is sequentially output to the MOSI bit by bit from the least significant bit or the most significant bit. Data input from the MISO is sequentially stored bit by bit in the reception shift register of the shift register 11. The stored reception data is read as read data by, for example, the control CPU. The baud rate generator 12 divides the clock signal according to a setting value set by the control CPU, for example, and generates a serial clock SCK. The serial clock SCK is supplied from the SPI master 10 to the SPI slave 15.

  In synchronization with the serial clock SCK, data is transferred from the SPI master 10 to the SPI slave 15 and data is transferred from the SPI slave 15 to the SPI master 10. The SPI slave 15 recognizes, as an instruction, 8-bit data transmitted first from the SPI master 10 after / SS becomes LOW (enable). For example, in the case of a read operation, the SPI master 10 first transmits instruction data indicating the read operation, and then transmits address data. The bit length of the address to be transmitted at this time varies depending on the memory capacity of the SPI slave 15 and is, for example, any one of 8 bits, 16 bits, 24 bits, and the like. After the address data is transmitted, the read data of the corresponding address is output from the SPI slave 15. Thereafter, by continuing to output the clock SCK from the SPI master 10, the SPI slave 15 automatically increments the address and outputs read data one after another.

  FIG. 2 is a diagram illustrating an example of a data read operation when the address bit length is 8 bits. The SPI slave 15 takes in 8-bit data output from the SPI master 10 to the MOSI as an instruction after / SS becomes LOW (enable), and recognizes that it is a read operation. The SPI master 10 outputs 8-bit address data A0 to A7 to the MOSI following the instruction data indicating the read operation. The SPI slave 15 sequentially outputs read data to the MISO in synchronization with the clock SCK, starting from the memory position indicated by the received address data.

  FIG. 3 is a diagram illustrating an example of a data read operation when the address bit length is 24 bits. The SPI master 10 outputs 24-bit address data A0 to A23 to the MOSI following the 8-bit instruction data indicating the read operation. The SPI slave 15 sequentially outputs read data to the MISO in synchronization with the clock SCK, starting from the memory position indicated by the received address data.

  FIG. 4 is a flowchart showing an example of the flow of boot-up processing when the address bit length is fixed. In step S1, various settings of the SPI master (for example, SPI master 10) are performed. In step S2, a read command is transmitted from the SPI master. This transmission operation takes 8 cycles. In step S3, the address “0” is transmitted from the SPI master. If the bit length of the address is n bits, this transmission operation requires n cycles. In step S4, the SPI master receives read data from the SPI slave. This reception operation takes 8 cycles. In step S5, for example, the CPU on the SPI master side determines whether or not the read data is hexadecimal “4D”. Here, “4D” is assumed to be the first keyword. If the read data is equal to the keyword, in step S6, for example, the CPU on the SPI master side determines whether or not the read data is hexadecimal “42”. Here, “42” is assumed to be the second keyword. If the read data is equal to the keyword, the process proceeds to the next step. Similarly, the third and subsequent keywords are also checked, and if all the keywords are read correctly, the firmware program following the keywords is downloaded. If even one keyword is not read correctly, the boot-up process is interrupted and the error process is executed.

  As described above, the bit width of the address when accessing the slave device from the master device via the SPI protocol varies depending on the type (memory capacity) of the slave device. In the case of the flowchart of the boot-up process shown in FIG. 4, the number of cycles required for step S3 differs depending on the type of slave device. Therefore, in an information processing apparatus that downloads firmware from a serial ROM and boots up, it is necessary to provide a boot loader ROM containing different programs according to the address bit width of the serial ROM. Since it is difficult to change the contents of the boot loader ROM, once the information processing apparatus is configured to download from a certain type of slave device, it cannot be changed even if the memory capacity of the external ROM is changed. turn into.

  For example, a boot program for an 8-bit address, a boot program for a 16-bit address, and a boot program for a 24-bit address are stored in the boot loader ROM, and one program is selected and executed at the time of booting. It is done. More efficiently, the processing part of the address output operation in the boot program (the processing part of step S3 in FIG. 4) can be switched between 8-bit address output, 16-bit address output, and 24-bit address output. That's fine. The switching selection signal at this time may be generated according to a signal applied to the external terminal of the information processing apparatus. However, with such a configuration, a cost increase due to an increase in the number of pins becomes a problem.

  For example, Patent Literature 1 and Patent Literature 2 disclose address determination methods for reading data from a serial ROM. The technique disclosed in Patent Document 1 is an invention that automatically determines the access mode of a serial EEPROM, and uses an acknowledge signal output from the serial EEPROM to determine whether it is a 1-byte address or a 2-byte address. However, since there is no signal corresponding to the acknowledge signal in the SPI protocol, this technique cannot be used for a system connected by the SPI protocol.

  The technique disclosed in Patent Document 2 is an invention that automatically determines the storage capacity of an EEPROM, and counts the number of address bits using a low-level output from the EEPROM after the effective address is input. However, since there is no protocol corresponding to low level output in SPI, this technology cannot be used for a system connected by the SPI protocol.

Even if the address bit width can be specified by some address determination method, it is necessary to incorporate processing such as address mode detection, address mode determination, and address transmission for each address mode into the boot program. That is, it is necessary to add a new process to the boot-up process of FIG. 4, which complicates the process and increases the cost.
JP 2004-21421 A JP 2002-73411 A

  In view of the above, there is a demand for an information processing apparatus capable of performing boot-up processing without depending on the address bit length of the slave device when downloading firmware from the slave device using the SPI protocol.

  The information processing apparatus serially transmits each bit of the address and serially receives each bit of data, a boot memory storing a start program, and executes the start program at the start to perform a start-up process The control circuit determines whether or not the data serially received by the serial interface coincides with predetermined data with the first timing as a start timing in the start-up process, In the case of mismatch, the second interface is used as a start timing to determine whether or not the data serially received by the serial interface matches the predetermined data.

  According to at least one embodiment, in a system connected by the SPI protocol, control corresponding to slave devices having different address bit widths is realized, and additional ROM and external terminals are not required, thereby reducing costs. be able to. Further, the number of extra cycles does not increase as compared with the configuration of the prior art.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 5 is a diagram illustrating an example of a configuration of an information processing apparatus that downloads firmware from a serial ROM. The information processing apparatus 20 includes an SPI interface (I / F) 21, a boot ROM 22, a control CPU 23, and a RAM interface (I / F) 24. The SPI interface 21, the boot ROM 22, the control CPU 23, and the RAM interface 24 are connected to each other via an internal bus 25. The RAM interface 24 of the information processing apparatus 20 is connected to the RAM 26, and the program executed by the control CPU 23, data related to processing, and the like are stored in the RAM 26. The SPI interface 21 of the information processing apparatus 20 is connected to the serial ROM 30 and transfers data between the SPI master (SPI interface 21) and the SPI slave (serial ROM 30) via MISO, MOSI, SCK, and / SS. Do. The configuration of the SPI protocol interface is as shown in FIG. The SPI interface 21 serially transmits each bit of the address to the MOSI and receives each bit of data serially from the MISO.

  The boot ROM 22 is a boot memory that stores a start program (boot loader program). When the information processing apparatus 20 is activated, the control CPU 23 executes the activation program of the boot ROM 22 to execute the activation process. The information processing apparatus 20 reads the firmware recorded in the serial ROM 30 in accordance with the boot loader program, and starts information processing such as encoding / decoding.

  FIG. 6 is a diagram illustrating an example of data stored in the serial ROM 30. As shown in FIG. 6, a predetermined keyword is arranged at the head portion of the firmware stored in the memory location starting from address 0 of the serial ROM 30. In the example shown in FIG. 6, hexadecimal data “4D” (ASCII code “M”) as the first keyword is stored in the first address position (address 0), and the second address position (address 1). ) Stores hexadecimal data “42” (“B” in ASCII code) as the second keyword. The third address position (address 2) stores hexadecimal data “38” (ASCII code “8”) as the third keyword, and the fourth address position (address 3) contains the fourth data. Hexadecimal data “36” (ASCII code “6”), which is a keyword, is stored.

  The control CPU 23 of the information processing device 20 checks the keywords (“M”, “B”, “8”, “6” in the example of FIG. 6) in the downloaded data while downloading the firmware from the serial ROM 30. I do. When the control CPU 23 successfully reads a predetermined keyword, the control CPU 23 determines that an external ROM exists, and downloads a program stored at a position subsequent to the keyword from the serial ROM 30. If reading of a predetermined keyword fails, it is determined that an error has occurred, and the information processing apparatus interrupts the boot-up process.

  In the information processing apparatus 20 of FIG. 5, the control CPU 23 determines whether or not the data serially received by the SPI interface 21 with the first timing as the start timing matches predetermined data (first keyword) in the startup process. Determine whether. When the determination result indicates that the data does not match, the control CPU 23 determines whether the data received serially by the SPI interface 21 matches the predetermined data (first keyword) with the second timing as the start timing. In this way, the determination as to whether the data received serially by the SPI interface 21 matches the predetermined data (first keyword) is repeated for the received data received sequentially at different start timings. Then, the control CPU 23 sequentially reads the subsequent data as necessary data from the timing when the data serially received by the SPI interface 21 matches the predetermined data (first keyword). These processes will be described in detail below.

  FIG. 7 is a flowchart showing a flow of boot-up processing of the information processing apparatus 20. The processing of each step in this flowchart is executed by the control CPU 23 or the SPI interface 21 that operates under the control of the control CPU 23.

  In step S1, various settings of the SPI interface 21 are performed. In step S2, a read command is transmitted from the SPI interface 21. This transmission operation requires, for example, 8 cycles. In step S 3, the address “0” is transmitted from the SPI interface 21. At this time, the control CPU 23 controls the SPI interface 21 so that the fixed bit value “0” is continuously transmitted to the MOSI as an address. The period during which the fixed bit value “0” continues to be transmitted is at least the number of cycles equal to the maximum value of the address bit length. That is, for example, when there are possible address modes of 8 bits, 16 bits, and 24 bits as the address bit length, the number of cycles equal to the maximum value of 24 bits, that is, a fixed bit value “0” for at least 24 cycles. Keep sending.

  In step S <b> 4, the SPI interface 21 receives read data from the serial ROM 30. This reception operation requires, for example, 8 cycles. In step S5, the control CPU 23 determines whether or not the read data is hexadecimal “4D”. Here, “4D” is the first keyword.

  FIG. 8 is a diagram illustrating an example of a data read operation. The serial ROM 30 takes in the 8-bit data “00000011” output to the MOSI by the SPI interface 21 after / SS becomes LOW (enable), and recognizes that it is a read operation. The SPI interface 21 continues to output the fixed value of the bit value “0” to the MOSI following the instruction data indicating the read operation. The serial ROM 30 sequentially outputs read data to the MISO in synchronization with the clock SCK, starting from the memory position indicated by the received address data. In the example of FIG. 8, the operation when the serial ROM 30 is a memory having an address bit length of 8 bits is shown. When eight address bits “0” are supplied to MOSI in synchronization with the 8th to 15th pulses of SCK, the serial ROM 30 starts outputting data at address 0. The output data is “01001101” appearing in MISO, that is, the hexadecimal number “4D” as the first keyword. The SPI interface 21 receives MISO data serially with the first timing (16th pulse of SCK) as the start timing. This first timing is a timing when the SPI interface 21 receives an address having a predetermined bit length (8 bits) and receives data corresponding to the address. If the read data received in this way matches the first keyword “4D”, the boot-up process proceeds to step S8 in FIG.

  If the read data does not match the first keyword (NO in step S5), the bootup process proceeds to step S6. In step S6, the check count value CHK_CNT for counting the number of checks is incremented by one. The check count value CHK_CNT is initially set to the initial value 0. In step S7, it is determined whether or not the check count value CHK_CNT is 3 or less. Here, the reason why it is determined whether or not the number is 3 or less is because the case of a configuration in which there are three possible bit lengths as the address bit length is illustrated. If there are n possible bit lengths as the address bit length, it is determined whether or not the check count value CHK_CNT is n or less.

  When the check count value CHK_CNT is 3 or less, the process returns to step S4, and the SPI interface 21 receives the read data from the serial ROM 30 again. The first read data reception (when CHK_CNT = 0) was data reception with the first timing (16th pulse of SCK) as the start timing. On the other hand, the reception of the read data this time (when CHK_CNT = 1) is data reception with the second timing (the 24th pulse of SCK) as the start timing.

  If the read data received from the second timing does not match the first keyword (NO in step S5), the bootup process proceeds again to step S6. In step S6, the check count value CHK_CNT for counting the number of checks is incremented by one. In step S7, it is determined whether or not the check count value CHK_CNT is 3 or less. When the check count value CHK_CNT is 3 or less, the process returns to step S4, and the SPI interface 21 receives the read data from the serial ROM 30 again. The reception of the read data this time (when CHK_CNT = 2) is data reception with the third timing (the 32nd pulse of SCK) as the start timing.

  FIG. 9 is a diagram illustrating an example of a data read operation. FIG. 9 shows a case where the serial ROM 30 is a memory having an address bit length of 24 bits. Even if eight address bits “0” are supplied to MOSI in synchronization with the 8th to 15th pulses of SCK, the serial ROM 30 does not start data output at address 0. Even if 16 address bits “0” are supplied to MOSI in synchronization with the 8th to 23rd pulses of SCK, the serial ROM 30 does not start data output at address 0. On the other hand, when 24 address bits “0” are supplied to MOSI in synchronization with the 8th to 31st pulses of SCK, the serial ROM 30 starts outputting data at address 0. The output data is “01001101” appearing in MISO, that is, the hexadecimal number “4D” as the first keyword. The SPI interface 21 receives MISO data serially with the third timing (the 32nd pulse of SCK) as the start timing. If the read data received in this way matches the first keyword “4D”, the boot-up process proceeds to step S8 in FIG.

  In step S <b> 8, the SPI interface 21 receives read data from the serial ROM 30. The data received here is the timing next to the timing (the SCK 32 pulse in the example of FIG. 9) when the data serially received by the SPI interface 21 matches the first keyword “4D”. (No. 40 pulse). Next, in step S9, it is determined whether or not the read data matches the hexadecimal number “42” (second keyword). If the read data is equal to the second keyword, the process proceeds to the next step S10. In step S <b> 10, the SPI interface 21 receives subsequent read data from the serial ROM 30. In step S11, it is determined whether or not the read data matches the hexadecimal number “38” (third keyword). If the read data is equal to the third keyword, the process proceeds to the next step S12. In step S <b> 12, the SPI interface 21 receives subsequent read data from the serial ROM 30. In step S13, it is determined whether or not the read data matches the hexadecimal number “36” (fourth keyword). If the read data is equal to the fourth keyword, the process proceeds to the next step S14.

  In step S14, the SPI interface 21 fetches subsequent data from the serial ROM 30 and executes necessary boot-up processing. That is, the firmware program stored after the first keyword in the serial ROM 30 is sequentially read by the SPI interface 21 and stored in the RAM 26 via the RAM interface 24. When downloading of the firmware to the RAM 26 is completed, control transfer from the boot program to the firmware is performed. Specifically, the control CPU 23 sets a program counter at the firmware execution start address in the RAM 26 and starts executing the firmware. By executing the firmware, desired information processing such as encoding / decoding is performed.

  If even one keyword has not been correctly read (that is, if NO in steps S7, S9, S11, or S13), the process proceeds to step S15. In step S15, the occurrence of an error is notified to the outside through the error terminal of the information processing apparatus 20 shown in FIG. Specifically, the error occurrence is notified by setting the signal level of the error terminal to a predetermined asserted state. Thereafter, the boot-up process is interrupted and the process is terminated.

  As can be seen by comparing the flowchart shown in FIG. 7 with the flowchart of the conventional process shown in FIG. 4, the operation shown in FIG. 7 is merely provided with a loop that returns to step S4 in the case of NO determination in step S5. is there. That is, in the operation shown in FIG. 7, the number of processing cycles required for bootup processing in a certain address mode (for example, the address bit length is 16) is the same as the bootup processing in a fixed configuration dedicated to the 16-bit address length. It is the same as the number of processing cycles required. The control flow shown in FIG. 7 can be controlled by a boot-up program stored in the boot ROM 22, and can also be realized by a hardware control circuit.

  As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.

The present disclosure includes the following contents.
(Appendix 1)
Serial interface that transmits each bit of address serially and receives each bit of data serially;
A boot memory for storing a startup program;
A control circuit that executes the startup program at startup to perform startup processing;
The control circuit determines whether or not the data received serially by the serial interface matches a predetermined data in the start-up process with a first timing as a start timing. Is configured to determine whether data serially received by the serial interface matches the predetermined data with a second timing as a start timing.
(Appendix 2)
The control circuit repeats the determination on whether the data serially received by the serial interface matches the predetermined data in the startup process for received data received at different start timings sequentially. The information processing apparatus according to supplementary note 1, which is characterized.
(Appendix 3)
The information processing apparatus according to claim 1 or 2, wherein the control circuit sequentially reads subsequent data as necessary data from a timing at which data serially received by the serial interface matches the predetermined data.
(Appendix 4)
4. The information processing apparatus according to claim 1, wherein the control circuit continues to transmit a fixed bit value as an address from the serial interface in the startup process.
(Appendix 5)
There are at least two bit lengths that the address can take, a first bit length and a second bit length, and the first timing is determined when the serial interface transmits an address of the first bit length. It is a timing for receiving data corresponding to an address, and the second timing is a timing for receiving data corresponding to the address when the serial interface transmits an address having the second bit length. The information processing apparatus according to any one of appendices 1 to 4.
(Appendix 6)
A serial interface that serially transmits each bit of an address and receives each bit of data serially, a boot memory that stores a startup program, and a control circuit that executes the startup program at startup and performs startup processing In an information processing apparatus including:
Determining whether the data received serially by the serial interface with a first timing as a start timing matches a predetermined data;
If the result of the determination is a data mismatch, it is determined whether the data received serially by the serial interface with the second timing as a start timing matches the predetermined data;
A download control method comprising the steps of sequentially reading subsequent data as necessary data from a timing when data serially received by the serial interface coincides with the predetermined data.
(Appendix 7)
The download control method according to claim 6, wherein a fixed bit value is continuously transmitted as an address from the serial interface.

It is a figure which shows schematic structure of the interface of SPI protocol. It is a figure which shows an example of the data read-out operation | movement in case an address bit length is 8 bits. It is a figure which shows an example of the data read-out operation | movement in case an address bit length is 24 bits. It is a flowchart which shows an example of the flow of the bootup process in case the bit length of an address is fixed. It is a figure which shows an example of a structure of the information processing apparatus which downloads firmware from a serial ROM. It is a figure which shows an example of the storage data of a serial ROM. It is a flowchart which shows the flow of the bootup process of information processing apparatus. It is a figure which shows an example of data read-out operation | movement. It is a figure which shows an example of data read-out operation | movement.

Explanation of symbols

20 Information processing device 21 SPI interface 22 Boot ROM
23 Control CPU
24 RAM interface 25 Internal bus 26 RAM
30 Serial ROM

Claims (5)

Serial interface that transmits each bit of address serially and receives each bit of data serially;
A boot memory for storing a startup program;
A control circuit that executes the startup program at startup to perform startup processing;
The control circuit determines whether or not the data received serially by the serial interface matches a predetermined data in the start-up process with a first timing as a start timing. Is configured to determine whether data serially received by the serial interface matches the predetermined data with a second timing as a start timing.   The control circuit repeats the determination on whether the data serially received by the serial interface matches the predetermined data in the startup process for received data received at different start timings sequentially. The information processing apparatus according to claim 1.   3. The information processing apparatus according to claim 1, wherein the control circuit sequentially reads subsequent data as necessary data from a timing at which data serially received by the serial interface matches the predetermined data.   4. The information processing apparatus according to claim 1, wherein the control circuit continues to transmit a fixed bit value as an address from the serial interface in the startup process.   There are at least two possible bit lengths of the address, a first bit length and a second bit length, and the first timing is determined when the serial interface transmits an address of the first bit length. It is a timing for receiving data corresponding to an address, and the second timing is a timing for receiving data corresponding to the address when the serial interface transmits an address having the second bit length. The information processing apparatus according to any one of claims 1 to 4.

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