JP2010040876A - Method of manufacturing semiconductor wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor wafer, in which production of particles caused by a contact track generated on a semiconductor wafer due to contact with a support boat etc., of a thermal processing device is further suppressed. <P>SOLUTION: The method of manufacturing the semiconductor wafer includes a beveling step S8 of forming a beveled surface at a circumferential edge of the semiconductor wafer, a thermal processing step S12 of performing thermal processing on the semiconductor wafer after the beveling step S8 in an atmosphere of ≥900°C, and a border part polishing step S14 of polishing an area, on a main surface of the semiconductor wafer after the thermal processing step S12, nearby a border part between the main surface and circumferential edge including the border part. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor wafer.

  In a semiconductor wafer such as a silicon wafer (hereinafter, also simply referred to as “wafer”), the main surface is mirror-polished and then heat-treated in an atmosphere of high-temperature argon gas or hydrogen gas to thereby remove the surface of the wafer. Performing modification (hereinafter also referred to as “surface modification treatment”) is generally performed. The surface modification treatment generally means that void (cavity) defects (V defects) generated by agglomeration of vacancies such as COP (Crystal Originated Particle) on the surface of the wafer 1 are eliminated. The heat treatment is performed using a heat treatment apparatus. In the heat treatment apparatus, a core tube is disposed inside the heat treatment furnace, a support boat that supports the wafer is disposed inside the furnace core tube, and heat treatment is performed in a state where the wafer is supported by the support boat.

  On the surface of the wafer that has been subjected to the heat treatment, a mark (hereinafter, also referred to as “contact mark”) caused by contact with the support boat is generated at a portion that is supported by the support boat. The contact mark becomes a source of dust generation in a subsequent process, and causes transfer of particles to the peripheral wafer supported by the support boat. Further, if there is a contact mark on the wafer, the mechanical strength of the wafer is lowered, and the wafer is likely to be cracked.

  In order to prevent various problems caused by such contact marks, a method of polishing the support surface side of the wafer has been devised (for example, see Patent Document 1 below). Here, the “support surface” refers to a surface supported by a support boat or the like on a main surface (a main surface and a back surface that are flat surfaces) of a wafer.

JP-A-11-260677

  However, even when the support surface side of the wafer is polished, the generation of particles that are thought to be caused by contact marks still occurs. Further, with higher integration of semiconductor devices, higher quality wafers are required, and it is desired to further suppress the generation of particles due to contact marks.

  Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor wafer that can further suppress the generation of particles due to contact marks generated on the semiconductor wafer due to contact with a support boat or the like of a heat treatment apparatus.

  (1) A semiconductor wafer manufacturing method of the present invention includes a chamfering process for forming a chamfered surface on a peripheral edge of a semiconductor wafer, and a heat treatment process for performing a heat treatment in an atmosphere of 900 ° C. or higher on the semiconductor wafer that has undergone the chamfering process. And a boundary portion polishing step for polishing a region in the vicinity of the boundary portion between the main surface and the peripheral portion of the main surface of the semiconductor wafer that has undergone the heat treatment step, including the boundary portion. And

  (2) It is preferable to further include a double-side polishing step for polishing both main surfaces of the semiconductor wafer between the heat treatment step and the boundary portion polishing step or after the boundary portion polishing step.

  (3) It is preferable that the diameter of the semiconductor wafer that has undergone the boundary polishing step is 300 mm or more.

  (4) The atmospheric gas in the heat treatment step is preferably composed of argon gas, hydrogen gas, nitrogen gas, or a mixed gas of argon gas and hydrogen gas.

  According to the present invention, it is possible to further suppress the generation of particles due to contact marks generated on a semiconductor wafer due to contact with a support boat or the like of a heat treatment apparatus.

  Hereinafter, a first embodiment of a semiconductor wafer manufacturing method of the present invention will be described with reference to the drawings. FIG. 1 is a flowchart showing the first half of the first embodiment of the semiconductor wafer manufacturing method of the present invention. FIG. 2 is a flowchart showing a continuation of the flow shown in FIG. FIG. 3 is a partial cross-sectional view showing the vicinity of the periphery of the semiconductor wafer 1 in which the chamfered surface 2 is formed at the periphery. FIG. 4 is a schematic diagram showing the semiconductor wafer 1 supported by the support boat 4.

First, a semiconductor wafer (hereinafter, also simply referred to as “wafer”) 1 having a chamfered surface 2 formed on the peripheral edge will be described with reference to FIG.
The wafer 1 is made of, for example, a silicon wafer or a gallium arsenide wafer.
The shape of the wafer 1 viewed in the thickness direction is generally a perfect circle, and its diameter is preferably 200 mm or more, more preferably 300 mm or more. Specifically, the diameter of the wafer 1 is, for example, 200 mm, 300 mm, or 450 mm. Here, the diameter of the wafer 1 is a target value in manufacturing, and includes a predetermined tolerance (allowable error) and the like. The shape of the wafer 1 viewed in the thickness direction may be an elliptical shape.
The thickness t (see FIG. 3) of the wafer 1 is, for example, 600 to 2000 μm, and preferably 700 to 1200 μm.

As shown in FIG. 3, a chamfered surface 2 is formed on the peripheral edge of the wafer 1 that has undergone the chamfering step S4 (details will be described later). The outer surface (front surface) of the wafer 1 includes a main surface 10 that is a flat surface and a chamfered surface 2. The main surface 10 includes a main surface 11 on which various processes are performed and a semiconductor device is formed, and a back surface 12 that is the opposite surface. Since the main surface 11 is a region where a semiconductor device is formed, flatness and reduction of particles are required at a higher level than the back surface 12.
The boundary between the main surface 10 (the main surface 11 and the back surface 12) and the peripheral edge portion (the chamfered surface 2) is referred to as a “boundary portion 3”. The boundary portion 3 is a line having substantially no area, and has a substantially circular shape when the wafer 1 is viewed in plan (when viewed in the thickness direction).

[First Embodiment]
Next, a method for manufacturing a semiconductor wafer according to the first embodiment of the present invention will be described with reference to FIGS. The semiconductor wafer manufacturing method of the first embodiment is a method of manufacturing a semiconductor wafer having a predetermined quality by performing various processes on the wafer 1 having the chamfered surface 2 as shown in FIG.

  As shown in FIG.1 and FIG.2, the manufacturing method of the semiconductor wafer of a 1st embodiment is equipped with following process S1-S18 and S21. In particular, the semiconductor wafer manufacturing method of the first embodiment includes a chamfering process S4 and a first mirror chamfering process S8 as a chamfering process, a heat treatment process S12, a second mirror chamfering process S14 as a boundary polishing process, A second double-side polishing step S15 and a second mirror-polishing step S16 as polishing steps are provided.

(S1) Ingot growth step S1
A semiconductor single crystal is pulled up by the Czochralski method (CZ method) to grow a single crystal semiconductor ingot. A semiconductor ingot can be grown by a floating zone method (FZ method).

(S2) Outline Grinding Step The semiconductor ingot grown through the ingot growth step S1 is cut at the front end and the end. Then, the peripheral surface of the unground semiconductor ingot is ground into a perfect circle. As a result, a semiconductor ingot having a perfect circular cross section is obtained. Orientation flats and notches are formed on the periphery of the semiconductor ingot as necessary.

(S3) Slicing Step The semiconductor ingot that has undergone the external grinding step S2 is sliced in a direction orthogonal to the central axis. For the slice, for example, a wire saw is used. Thereby, a semiconductor wafer is obtained.

(S4) Chamfering Step Chamfering is performed on the peripheral portion of the wafer obtained through the slicing step S3 in order to prevent chipping and chipping of the peripheral portion of the wafer. For example, the peripheral edge of the wafer is chamfered into a predetermined shape by a chamfering grindstone. Thereby, as shown in FIG. 3, a chamfered surface 2 having a predetermined angle is formed on the peripheral edge of the wafer 1.

(S5) Lapping process The unevenness of the main surface 10 in the wafer 1 generated in the slicing process S3 or the like is flattened by lapping with respect to the wafer 1 that has undergone the chamfering process S4. For example, the wafer 1 is disposed between lapping surface plates parallel to each other, and a lapping liquid that is a mixture of alumina abrasive grains, a dispersant, water, and the like is poured between the lapping surface plate and the wafer 1. Then, they are rotated with each other under pressure and rubbed together, and both the main surface 11 and the back surface 12 of the wafer 1 are lapped. Thereby, the flatness of the main surface 11 and the back surface 12 in the wafer 1 and the parallelism of the wafer 1 are increased.
In addition, it can replace with lapping process S5 and can also perform a double-headed grinding process.

(S6) Surface Grinding Step Surface grinding is performed on the wafer 1 that has undergone the lapping step S5 in order to further increase the flatness of the main surface 10 of the wafer 1. Surface grinding can be performed, for example, by holding one surface of the wafer 1 by vacuum suction and bringing the wafer 1 and a cup-shaped fine diamond grindstone into contact with each other while rotating.

(S7) Etching Step The wafer 1 that has undergone the surface grinding step S6 is dipped in an etching solution and subjected to an etching process. For example, an etching solution is supplied to the main surface 10 of the wafer 1 while spinning the wafer 1, and the supplied etching solution is spread over the entire main surface 10 of the wafer 1 by centrifugal force due to the spin, so that the entire main surface 10 of the wafer 1 is spread. The surface roughness Ra of the main surface 10 of the wafer is controlled to a predetermined surface roughness. In this manner, the work-affected layer generated by the machining process such as the chamfering step S4 and the lapping step S5 can be almost completely removed.

(S8) First Mirror Chamfering Step A mirror chamfering process is performed on the peripheral portion of the wafer 1 that has undergone the etching step S7. Thereby, the chamfered surface 2 of the wafer 1 is mirror-finished. For example, while supplying the polishing liquid to the chamfered surface 2 of the wafer 1, the chamfered surface 2 of the wafer 1 is pressed against the outer peripheral surface of the polishing cloth rotating around the axis to perform mirror chamfering.

(S9) First double-side polishing step For the main surface 11 and the back surface 12 of the wafer 1 that has undergone the first mirror chamfering step S8, using a double-side simultaneous polishing apparatus that simultaneously polishes the main surface 11 and the back surface 12, Are subjected to double-side polishing. Note that instead of the first double-side polishing step S9, the main surface 11 and the back surface 12 of the wafer 1 may be subjected to rough polishing one by one.

(S10) First Mirror Polishing Step Mirror polishing is performed using a double-sided simultaneous polishing apparatus that simultaneously polishes the main surface 11 and the back surface 12 with respect to the main surface 11 and the back surface 12 of the wafer 1 that has undergone the first double-side polishing step S9. Done. Instead of simultaneous double-side polishing, the main surface 11 and the back surface 12 of the wafer 1 may be mirror-polished one by one.

(S11) Pre-heat treatment cleaning step The wafer 1 that has undergone the first mirror polishing step S10 is cleaned. For example, the pre-heat treatment cleaning can be performed by, for example, HF cleaning in addition to RCA cleaning. Thereby, the outer surface of the wafer 1 immediately before the heat treatment step (surface modification step) S12 can be cleaned.

(S12) Heat treatment step (surface modification step)
The wafer 1 that has undergone the pre-heat treatment cleaning step S11 is subjected to heat treatment in an atmosphere of 900 ° C. or higher. The temperature of the atmosphere is preferably 1000 ° C. or higher, more preferably 1100 ° C. or higher. The temperature of the atmosphere is preferably 1350 ° C. or lower. The heat treatment is preferably performed for 10 minutes to 16 hours. In this way, the surface modification process is performed on the wafer 1. The surface modification treatment means that void (cavity) defects (V defects) generated by agglomeration of vacancies such as COP (Crystal Originated Particle) on the surface of the wafer 1 are eliminated.

As the atmospheric gas in the heat treatment, for example, argon gas, hydrogen gas, nitrogen gas, or a mixed gas of argon gas and hydrogen gas is used.
The heat treatment may be a process that does not substantially modify the surface of the wafer.
Further, in order to eliminate COP by injecting silicon between the lattices, after the heat treatment step S12, the atmosphere gas may be switched to O ₂ and the heat treatment may be performed, and then the oxide film may be peeled off.

(S13) First Thickness Measurement Step The thickness t of the wafer 1 that has undergone the heat treatment step (surface modification step) S12 is measured. Thereby, the thickness t of the wafer 1 before the second mirror chamfering step (boundary portion polishing step) S14 is confirmed.
In addition, 1st thickness measurement process S13 can also be performed between etching process S7 and heat processing process (surface modification process) S12. For example, the first thickness measurement step S13 can be performed between the first mirror polishing step S10 and the pre-heat treatment cleaning step S11.

(S14) Second mirror chamfering step (boundary polishing step)
Including the boundary portion 3 between the main surface 10 (the main surface 11 and the back surface 12) and the peripheral portion with respect to the main surface 10 and the peripheral portion (chamfered surface 2) of the wafer that has undergone the heat treatment step (surface modification step) S12. A mirror chamfering process is performed (ie across the boundary 3).
The area near the boundary 3 on the main surface 10 is mirror-polished to a width of 0.2 to 2 mm, for example, in the radial direction of the wafer 1.
Further, the area near the boundary 3 on the chamfered surface 2 is mirror chamfered with a width of 0.2 mm or more in the radial direction of the wafer 1, for example. Therefore, for example, a width of 0.2 mm or more may be chamfered from the boundary portion 3 on the back surface 12 side toward the center side of the back surface 12, and 0 from the boundary portion 3 on the back surface 12 side to the main surface 11 side. A width of 2 mm or more may be mirror chamfered.

Note that at least a region in the vicinity of the boundary portion 3 between the main surface 10 and the peripheral portion of the main surface 10 of the wafer 1 may be polished.
About the main surface 10, you may grind | polish both the main surface 11 and the back surface 12 simultaneously, or you may grind | polish each surface of the main surface 11 or the back surface 12 one by one. Moreover, about the main surface 10, you may grind | polish only the surface side which contacts the support boat 4 (refer FIG. 4) of a heat processing apparatus.
The mirror chamfering can be performed, for example, using the techniques described in JP 2006-156688 A and JP 9-183051 A (the same applies to the first mirror chamfering step S8).

(S15) Second double-side polishing step Similar to the first double-side polishing step S9, double-side polishing is performed on the main surface 11 and the back surface 12 of the wafer 1 that has undergone the second mirror chamfering step (boundary portion polishing step) S14. Is done.

(S16) Second Mirror Polishing Step The main surface 11 and back surface 12 of the wafer 1 that has undergone the second double-side polishing step S15 are subjected to mirror polishing similarly to the first mirror polishing step S10.

(S17) Cleaning process after heat treatment The wafer 1 that has undergone the second mirror polishing process S16 is cleaned. For this cleaning, for example, RCA cleaning is used. Thereby, the contamination of the wafer 1 in the heat treatment step (surface modification step) S12 and the polishing steps S14 to S16 can be cleaned.

(S18) Second thickness measurement step The thickness t of the wafer 1 that has undergone the post-heat treatment cleaning step S17 is measured. Thereby, the thickness t of the wafer 1 immediately after the post-heat treatment cleaning step S17 can be confirmed.

(S21) Finish cleaning step Finish cleaning is performed on the wafers that have undergone the respective steps S1 to S18. For the finish cleaning, for example, an RCA cleaning solution is used.

According to the semiconductor wafer manufacturing method of the first embodiment, for example, the following effects are exhibited.
In the method for manufacturing a semiconductor wafer according to the first embodiment, a region in the vicinity of the boundary portion 3 on the main surface 10 of the wafer 1 that has undergone the heat treatment step S12 in which heat treatment is performed on the wafer 1 in an atmosphere of 900 ° C. or higher is obtained. The boundary part polishing process S14 which polishes including is provided. Therefore, it is possible to further suppress the generation of particles due to contact marks generated on the wafer 1 due to contact with the support boat 4 (see FIG. 4) of the heat treatment apparatus.

  The reason why the generation of particles due to contact marks with the support boat 4 and the like can be suppressed by the semiconductor wafer manufacturing method of the first embodiment is considered as follows. Conventionally, particularly in a heat treatment apparatus equipped with a vertical heat treatment furnace, contact marks on the wafer 1 can be obtained by polishing the main surface 10 (main surface 11 and back surface 12) in the thickness direction of the wafer 1 (normal single-side polishing or It was thought that it could be erased if both sides were polished.

  However, in practice, in a heat treatment apparatus equipped with a batch type vertical heat treatment furnace that heat-treats a plurality of wafers 1 at a time, the wafer 1 in the in-plane direction of the wafer 1 is taken in and out of the heat treatment furnace. The wafer 1 was warped due to non-uniform temperature. Therefore, as shown in FIG. 4, the wafer 1 is in line contact with the support boat 4 in the region near the boundary portion 3 on the main surface 10. As a result, the contact mark was mainly generated in the area near the boundary portion 3 on the main surface 10. Since the boundary portion 3 is angular with respect to the main surface 10, a contact mark is deeply formed in the boundary portion 3. The contact marks formed on the boundary portion 3 were not polished by normal single-side polishing or double-side polishing, and many of the contact marks remained after polishing. For this reason, particles are generated from the remaining contact marks.

Such a phenomenon becomes more prominent because the warp tends to warp as the diameter of the wafer 1 increases. For example, it becomes remarkable in the wafer 1 having a diameter of 300 mm and 450 mm.
Such a phenomenon becomes more prominent because contact marks and distortions are more likely to spread as the temperature of the atmosphere in the heat treatment process increases. This is particularly noticeable in an atmosphere of 900 ° C. or higher where the dislocation movement speed increases.

  On the other hand, in the method for manufacturing a semiconductor wafer according to the first embodiment, the region in the vicinity of the boundary portion 3 on the main surface 10 is polished, so that the contact is larger than that in the case of polishing by normal single-side polishing or double-side polishing. Most of the marks can be removed. Therefore, the generation of particles due to contact marks with the support boat 4 or the like can be suppressed. Further, scratches due to contact marks are eliminated, the mechanical strength of the wafer 1 is improved, and cracking of the wafer 1 is less likely to occur.

  In addition, a second double-side polishing step S15 and a second mirror-polishing step S16 for polishing both main surfaces 10 (main surface 11 and back surface 12) of the wafer 1 that has undergone the second mirror chamfering step (boundary portion polishing step) S14, respectively. Since it is provided, it is possible to remove the roughness of both main surfaces 10 due to the second mirror chamfering step (boundary portion polishing step) S14, and it is possible to completely remove scratches on the boundary portion 3.

  Next, a second embodiment and a third embodiment, which are other embodiments of the semiconductor wafer manufacturing method of the present invention, will be described. About another embodiment, a different point from a 1st embodiment is mainly demonstrated, the same code | symbol is attached | subjected about the structure similar to a 1st embodiment, and description is abbreviate | omitted. The description about the first embodiment is applied as appropriate to points that are not specifically described regarding the other embodiments. In other embodiments, the same effects as in the first embodiment can be obtained.

[Second Embodiment]
FIG. 5 is a flowchart (corresponding to FIG. 2) showing the second half of the second embodiment of the semiconductor wafer of the present invention. As shown in FIG. 5, the wafer manufacturing method of the second embodiment is different from the wafer manufacturing method of the first embodiment in the second mirror chamfering step (boundary portion polishing step) S14 and the second double-side polishing step. The order with S15 is different. Other than that, it is the same as the first embodiment.

[Third embodiment]
FIG. 6 is a flowchart (corresponding to FIG. 2) showing the second half of the third embodiment of the semiconductor wafer of the present invention. As shown in FIG. 6, the wafer manufacturing method of the third embodiment is between the second double-side polishing step S <b> 15 and the second mirror polishing step S <b> 16 as compared to the wafer manufacturing method of the first embodiment. A third mirror chamfering step S22 is provided as a boundary portion polishing step. Since the third mirror chamfering step S22 is performed after the second mirror chamfering step S14, it is only necessary to perform simple polishing as compared with the second mirror chamfering step S14.

[Fourth Embodiment]
FIG. 7 is a flowchart (corresponding to FIG. 2) showing the second half of the fourth embodiment of the semiconductor wafer of the present invention. As shown in FIG. 7, in the wafer manufacturing method of the fourth embodiment, the first mirror chamfering is performed between the etching step S7 and the pre-heat treatment cleaning step S11 as compared with the wafer manufacturing method of the first embodiment. The difference is that chamfering processes such as the process S8, the first double-side polishing process S9, the first mirror polishing process S10, and the polishing process are not performed. Therefore, the wafer 1 that has undergone the etching step S7 is cleaned before heat treatment without being chamfered or polished, and then subjected to heat treatment.

  In the second embodiment and the third embodiment, as in the fourth embodiment, the first mirror chamfering step S8, the first double-side polishing step S9, between the etching step S7 and the pre-heat treatment cleaning step S11, A chamfering process such as the first mirror polishing process S10, a polishing process, or the like can be prevented from being performed.

As mentioned above, although the embodiment of the manufacturing method of the semiconductor wafer of this invention was described, this invention is not restrict | limited to the embodiment mentioned above.
For example, the double-side polishing step (second double-side polishing step S15 and second mirror polishing step S16) for polishing both the main surfaces 10 (main surface 11 and back surface 12) of the wafer 1 is the second in the above-described embodiment. Although it is performed after the mirror chamfering step (boundary portion polishing step) S14, the present invention is not limited to this and can be performed between the heat treatment step S12 and the boundary portion polishing step S14.
The member that contacts the wafer 1 in the heat treatment apparatus is not limited to the support boat 4.

  EXAMPLES Hereinafter, although an Example demonstrates this invention further in detail, this invention is not limited to these.

[Example 1]
In the ingot growth step S1, the single crystal silicon ingot is grown by pulling up the silicon single crystal by the Czochralski method. For this single crystal silicon ingot, external grinding step S2, slicing step S3, chamfering step S4, lapping step S5, surface grinding step S6, etching step S7, first mirror chamfering step S8, first double-side polishing step S9, Each of the one mirror polishing step S10 and the pre-heat treatment cleaning step S11 is sequentially performed to obtain a silicon wafer having a diameter of 300 mm. As the heat treatment step (surface modification step) S12, the obtained silicon wafer was subjected to a heat treatment for 60 minutes in an argon gas atmosphere at 1200 ° C. using a vertical heat treatment apparatus.

  Then, after performing 1st thickness measurement process S13, as the 2nd mirror chamfering process (boundary part grinding | polishing process) S14, the area | region of the main surface 10 in the silicon wafer near the boundary part 3 and the boundary part 3 in the chamfering surface 2 Mirror polishing (mirror chamfering) was performed by bringing a nearby region into contact with the polishing pad across the boundary 3. Since the main surface 11 is roughened by the abrasive used when performing this mirror polishing, the second double-side polishing step S15 and the second mirror-polishing step S16 are performed after the second mirror-chamfering step (boundary portion polishing step) S14. Thereafter, the post-heat treatment cleaning step S17, the second thickness measurement step S18, and the finish cleaning step S21 were sequentially performed.

  A 37 nm size LPD (Light Point Defect) was measured on the wafer 1 that had undergone the final cleaning step S21 using a surface defect inspection apparatus (Surscan SP2 manufactured by KLA-Tencor).

[Example 2]
Compared with Example 1, the temperature of the argon gas was 1150 ° C., and the heat treatment time was 240 minutes. The rest is the same as the first embodiment.

[Comparative Example 1]
Compared to Example 1, the second mirror chamfering step (boundary portion polishing step) S14 was not performed. The rest is the same as the first embodiment.

[Comparative Example 2]
Compared to Example 2, the second mirror chamfering step (boundary polishing step) S14 was performed before the heat treatment step (surface modification step) S12. The rest is the same as the first embodiment.

  Table 1 below shows the LPD measurement results for Example 1, Example 2, Comparative Example 1 and Comparative Example 2.

  From the comparison between Example 1 and Comparative Example 1 and the comparison between Example 2 and Comparative Example 2, the second mirror chamfering step (boundary polishing step) S14 is performed after the heat treatment step (surface modification step) S12. This shows that the amount of generated particles is small.

It is a flowchart which shows the first half of the 1st embodiment of the manufacturing method of the semiconductor wafer of this invention. 2 is a flowchart showing a continuation of the flow shown in FIG. 1. It is a fragmentary sectional view which shows the peripheral part vicinity in the semiconductor wafer 1 in which the chamfering surface 2 is formed in the peripheral part. FIG. 3 is a schematic diagram showing a semiconductor wafer 1 supported by a support boat 4. It is a flowchart (corresponding to FIG. 2) showing the second half of the second embodiment of the semiconductor wafer of the present invention. It is a flowchart (corresponding to FIG. 2) showing the second half of the third embodiment of the semiconductor wafer of the present invention. It is a flowchart (corresponding to FIG. 2) showing the second half of the fourth embodiment of the semiconductor wafer of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 2 Chamfering surface 3 Boundary part 10 Main surface 11 Main surface 12 Back surface S4 Chamfering process (chamfering process)
S8 First mirror chamfering process (chamfering process)
S12 Heat treatment step S14 Second mirror chamfering step (boundary polishing step)

Claims (4)

A chamfering process for forming a chamfered surface on the periphery of the semiconductor wafer;
A heat treatment step of performing a heat treatment in an atmosphere of 900 ° C. or higher on the semiconductor wafer that has undergone the chamfering step;
A boundary portion polishing step for polishing the region in the vicinity of the boundary portion between the main surface and the peripheral edge portion of the main surface of the semiconductor wafer that has undergone the heat treatment step, including the boundary portion. Semiconductor wafer manufacturing method.   2. The double-side polishing step of polishing both main surfaces of the semiconductor wafer between the heat treatment step and the boundary portion polishing step or after the boundary portion polishing step, respectively. Semiconductor wafer manufacturing method.   The semiconductor wafer manufacturing method according to claim 1, wherein a diameter of the semiconductor wafer that has undergone the boundary polishing step is 300 mm or more.   The method for producing a semiconductor wafer according to any one of claims 1 to 3, wherein the atmospheric gas in the heat treatment step is composed of argon gas, hydrogen gas, nitrogen gas, or a mixed gas of argon gas and hydrogen gas. .

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