JP2010040664A - Method of manufacturing of ferroelectric memory and test system of the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To carry out a test in consideration of imprint characteristics in a manufacturing step of a ferroelectric memory having a twin sense amplifier, and to prevent defects caused due to imprinting from occurring in a market. <P>SOLUTION: A ferroelectric memory having a first memory cell with a ferroelectric capacitor for storing a single logic level, a second memory cell with a pair of ferroelectric capacitors for storing complementary logic levels, and a twin sense amplifier connected to the first and second memory cells is produced. First, a first logic is written to the first and second memory cells, and the ferroelectric memory is left under a high temperature for progressing imprinting. Then, a second logic, which is inverse to the first logic, is written to the first memory cell. Furthermore, the logic held in the first memory cell is read out; and when the read logic is different from the second logic, defect of the ferroelectric memory is detected. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a ferroelectric memory having a memory cell composed of a ferroelectric capacitor.

  By using a ferroelectric capacitor that uses a ferroelectric as an insulating material as a variable capacitor and utilizing the fact that residual polarization remains even when the voltage applied to the ferroelectric capacitor is zero, Data can be retained even when power is not supplied. Utilizing this feature, the ferroelectric memory is used as a storage medium such as an IC card or an RFID tag.

The memory cells of the ferroelectric memory are classified into 1T1C type and 2T2C type. The 1T1C type memory cell has one transistor and one ferroelectric capacitor. The 2T2C type memory cell has two transistors and two ferroelectric capacitors, and holds complementary logic values in the two ferroelectric capacitors, respectively. Recently, a twin sense amplifier method has been proposed in which a read voltage from a 1T1C type memory cell is compared with a complementary read voltage from a 2T2C type memory cell (see, for example, Patent Document 1).
JP 2002-157876 A

  In general, a ferroelectric capacitor has imprint characteristics. Imprinting is a phenomenon in which a hysteresis loop indicating the characteristics of a ferroelectric capacitor shifts in the voltage axis direction. Imprinting occurs when a long time elapses after a logical value is written to a ferroelectric capacitor. Due to imprinting, the read margin of data held in the ferroelectric capacitor changes. For this reason, in the test process when manufacturing a ferroelectric memory, it is necessary to perform a test in consideration of imprinting. In particular, in a ferroelectric memory having a twin sense amplifier that uses a complementary read voltage from a 2T2C type memory cell as a reference voltage, it is necessary to consider the imprint characteristics of both the 1T1C type and 2T2C type memory cells. .

  An object of the present invention is to perform a test in consideration of imprint characteristics in a manufacturing process of a ferroelectric memory having a twin sense amplifier, and to prevent defects due to imprint from occurring in the market.

  In one aspect of the invention, a first memory cell having a ferroelectric capacitor that stores a single logic level, a second memory cell having a ferroelectric capacitor pair that stores a complementary logic level, and a ferroelectric A ferroelectric memory having a twin sense amplifier that generates a logic level according to the electric charge read from the capacitor is manufactured. The twin sense amplifier includes a first sense amplifier that differentially amplifies a voltage corresponding to the electric charge read from the ferroelectric capacitor and a voltage corresponding to the electric charge read from one of the ferroelectric capacitor pairs, and the ferroelectric capacitor. A second sense amplifier that differentially amplifies a voltage corresponding to the charge read and a voltage corresponding to the charge read from the other of the ferroelectric capacitor pair; In the manufacturing method, the first logic is written in the first and second memory cells. In order to proceed with the imprint of the ferroelectric capacitor and the ferroelectric capacitor pair, the ferroelectric memory is left at a high temperature. Next, the second logic opposite to the first logic is written in the first memory cell. Then, when the logic held in the first memory cell is read and the read logic is different from the second logic, a failure of the ferroelectric memory is detected.

  In a ferroelectric memory having a twin sense amplifier, a margin failure due to imprinting can be detected by writing reverse logic only to the first memory cell after imprinting has progressed due to high temperature exposure. As a result, it is possible to prevent defects due to imprinting from occurring in the market.

  Hereinafter, embodiments will be described with reference to the drawings. Double square marks in the figure indicate external terminals. The external terminal is, for example, a pad on a semiconductor chip or a lead of a package in which the semiconductor chip is stored. For the signal supplied via the external terminal, the same symbol as the terminal name is used. The same reference numerals as the signal names are used for signal lines through which signals are transmitted. A signal preceded by “/” indicates negative logic.

  FIG. 1 shows an example of a ferroelectric memory FM to be tested in one embodiment. For example, the ferroelectric memory FM is formed on a silicon substrate by using a CMOS process. The ferroelectric memory FM is used, for example, as a work memory for a wireless tag (RFID) such as an IC card or a work memory for a portable terminal such as a mobile phone. The ferroelectric memory FM has an address buffer ADB, a word decoder WDEC, a column decoder CDEC, a command buffer CMDB, a timing control circuit TCNT, a plate driver PD, a word driver WD, a memory core CORE, and a data input / output buffer IOB. . FIG. 1 mainly shows circuits necessary for the read operation. For this reason, the description of the bit line voltage control circuit and the like necessary for the write operation is omitted.

  The address buffer ADB receives the address signal AD via the address terminal, and outputs the received signal to the word decoder WDEC and the column decoder CDEC. The word decoder WDEC decodes the upper bits (row address RAD) of the address signal AD to generate a row decode signal, and outputs the generated signal to the word driver WD and the plate driver PD. The column decoder CDEC decodes the lower bits (column address CAD) of the address signal to generate a column decode signal, and outputs the generated signal to the data input / output buffer IOB and the like.

  The command buffer CMDB receives command signals such as a chip select signal / CS and a write enable signal / WE via a command terminal, decodes the received signals, and outputs a read control signal or a write control signal to the timing control circuit TCNT. To do. The timing control circuit TCNT receives a read control signal or a write control signal and outputs a timing signal for operating the plate driver PD, the word driver WD, the data input / output buffer IOB, the sense amplifier SA, and the like.

  The plate driver PD selects a predetermined plate line PL in response to the timing signal from the timing control circuit TCNT and the row decode signal from the word decoder WDEC. The selected plate line PL changes from a low level to a high level for a predetermined period. The word driver WD selects a predetermined word line WL in response to the timing signal from the timing control circuit TCNT and the row decode signal from the word decoder WDEC. The selected word line WL changes from a low level to a high level for a predetermined period.

  The memory core CORE includes a memory cell array ARY having 2T2C type memory cells and 1T1C type memory cells, a sense amplifier SA, and a twin sense amplifier TSA. Hereinafter, a 2T2C type memory cell is referred to as a 2T2C cell, and a 1T1C type memory cell is referred to as a 1T1C cell. The 2T2C cell is arranged along the vertical direction of the drawing and is connected to the complementary bit line pair BL1, / BL1. The 1T1C cells are arranged in a matrix. A column of 1T1C cells arranged in the vertical direction in the figure is connected to a bit line BL2 (or BL2,... BLn (n is 512, for example). 2T2C cells and 1T1C cells arranged in the horizontal direction in the figure are: The 2T2C cell and the 1T1C cell are connected to the common word line WL and the common plate line PL. User data received at the data input / output terminal I / O is written into the 2T2C cell and the 1T1C cell. The data read to the pair BL1, / BL1 is also used as a reference voltage for operating the twin sense amplifier TSA.

  The sense amplifier SA connected to the bit lines BL1 and / BL1 amplifies the voltage difference between the bit lines BL1 and / BL1, and outputs a sense amplifier output signal SOUT1 (read data) from a node corresponding to the bit line BL1. The twin sense amplifier TSA has two sense amplifiers SA. For example, in the twin sense amplifier TSA connected to the bit line BL2, one of the sense amplifiers SA amplifies the voltage difference between the bit lines BL1 and BL2. The other of the sense amplifiers SA amplifies the voltage difference between the bit lines / BL1 and BL2. The voltages of the bit lines BL1 and / BL1 are supplied to each twin sense amplifier TSA as a reference voltage corresponding to logic 0 or a reference voltage corresponding to logic 1 through the pre-sense amplifier PSA shown in FIG.

  The data input / output buffer IOB selects, for example, 16 bits from the plurality of bits of read data read from the memory core CORE according to the column decode signal, and outputs the selected read data to the data input / output terminal I / O. . The data input / output terminal I / O is, for example, 16 bits.

  FIG. 2 shows an example of the memory core CORE of the ferroelectric memory FM shown in FIG. The 2T2C cell has a transfer transistor (nMOS transistor) pair RT1, RT2 and a ferroelectric capacitor pair RF1, RF2. One end of the ferroelectric capacitor RF1 is connected to the bit line BL1 via the transfer transistor RT1, and the other end is connected to the plate line PL. One end of the ferroelectric capacitor RF2 is connected to the bit line / BL1 via the transfer transistor RT2, and the other end is connected to the plate line PL. The gates of the transfer transistors RT1 and RT2 are connected to a common word line WL. The ferroelectric capacitors RF1 and RF2 store different logic values (complementary logic levels). The capacitance values of the ferroelectric capacitors RF1 and RF2 differ depending on the logic of data to be stored. That is, the ferroelectric capacitors RF1 and RF2 can store electric charges according to the logic of data.

  The 1T1C cell has a transfer transistor (nMOS transistor) T1 and a ferroelectric capacitor F1 for storing a single logic level. In practice, a 2T2C cell is formed by arranging two 1T1C cells. That is, the layout pitches of the ferroelectric capacitors RF1, RF2, and F1 arranged in the horizontal direction in the figure are the same, and the layout pitches of the transfer transistors RT1, RT2, and T1 arranged in the horizontal direction in the figure are the same.

  The sense amplifier SA corresponding to the bit lines BL1, / BL1 has a flip-flop including pMOS transistors P1, P2 and nMOS transistors N1, N2. The sources of the pMOS transistors P1 and P2 are connected to the power supply line VDD via the pMOS transistors P3 and P4. The sources of the nMOS transistors N1 and N2 are connected to the ground line VSS via the nMOS transistors N3 and N4. The output node of the flip-flop is connected to the ground line VSS via the capacitors C1 and C2. One of the output nodes of the flip-flop is connected to the bit line BL1 via the nMOS transistor N5 and the pre-sense amplifier PSA. The other output node of the flip-flop is connected to bit line / BL1 via nMOS transistor N6 and pre-sense amplifier PSA.

  The pre-sense amplifier PSA has i pairs of pMOS transistors (source follower circuits) connected between the power supply line VDD and the ground line VSS. The pre-sense amplifier PSA changes the voltage of the output node (for example, SOUT1) according to the change of the voltage of the bit line (for example, BL1).

  When a read command is supplied to the ferroelectric memory FM, the read operation of the 2T2C cell is executed as follows. First, the word line WL and the plate line PL selected according to the row address RAD are sequentially changed from a low level to a high level. Due to the change of the plate line PL to the high level, charges are read from the ferroelectric capacitors RF1 and RF2 to the bit lines BL1 and / BL1, and the voltages of the bit lines BL1 and / BL1 change. The amount of charge read to the bit lines BL1 and / BL1 varies depending on the residual polarization values of the ferroelectric capacitors RF1 and RF2. The pre-sense amplifier PSA changes the voltage at the output node according to the change in the voltage of the bit lines BL1 and / BL1.

  After the pre-sense amplifier PSA starts operating, the control signal CK changes from the low level to the high level. The capacitors C1 and C2 of the sense amplifier SA accumulate electric charges according to the output signal of the pre-sense amplifier PSA, and generate voltages corresponding to electric charges read from the ferroelectric capacitors RF1 and RF2 at one end of each of the capacitors C1 and C2. .

  Next, the sense amplifier enable signal / SAE changes from high level to low level, and the sense amplifier enable signal SAE changes from low level to high level. As a result, the flip-flop of the sense amplifier SA is activated. The flip-flop differentially amplifies the voltages received at the complementary inputs, and generates the logic level of the data held in the 2T2C cell. That is, the output node SOUT1 changes to the power supply voltage VDD or the ground voltage VSS according to the logic of the data held in the 2T2C cell. The sense amplifier enable signals / SAE and SAE are generated by the timing control circuit TCNT.

  The read operation of the 1T1C cell is executed similarly to the read operation of the 2T2C cell. However, one of the inputs of each sense amplifier SA in the twin sense amplifier TSA receives a voltage change of the bit line BL1 or / BL1 via the pre-sense amplifier PSA. In the ferroelectric memory FM employing the twin sense amplifier TSA, one of the ferroelectric capacitors RF1 and RF2 of the 2T2C cell always stores logic 1, and the other always stores logic 0. Therefore, even when the ferroelectric capacitor F1 of the 1T1C cell stores either logic 1 or logic 0, the logic of data can be generated by one sense amplifier SA of the twin sense amplifier TSA. Therefore, the read margin of the 1T1C cell by the twin sense amplifier TSA can be made the same as the read margin of the 2T2C cell.

  FIG. 3 shows an example of the test system TSYS in one embodiment. In this example, the test system TSYS includes a thermostatic chamber TC for performing a high temperature storage test. First, a plurality of memories FM are formed on a semiconductor wafer WAF by a semiconductor manufacturing process. For example, the memory FM is tested by the LSI tester TEST before being cut out from the wafer WAF in the test process. Alternatively, in the test process, the packaged memory FM is tested by the LSI tester TEST. From the LSI tester TEST, signals / CS, / WE, AD, I / O, a power supply voltage VDD and a ground voltage VSS for controlling the access operation of the memory FM are supplied to the memory FM. The memory FM stored in the thermostat TC is connected to the LSI tester TEST via, for example, a test bus TBUS. In the figure, one memory FM is connected to the LSI tester TEST, but a plurality of memories FM (for example, four, sixteen or 256) may be connected to the LSI tester TEST at a time.

  The LSI tester TEST supplies a chip select signal / CS, a write enable signal / WE, an address signal AD, and a write data signal I / O to the memory FM, and receives a read data signal I / O from the memory FM. Then, in the test process in the manufacturing process, the memory FM is tested. Details of the test method are shown in FIG.

  FIG. 4 shows a hysteresis loop of the ferroelectric capacitor. The horizontal axis indicates the voltage V applied to the ferroelectric capacitor, and the vertical axis indicates the dielectric polarization value P of the ferroelectric capacitor. The voltage V indicates the voltage VCP (VCP−VBL) of the plate line PL with respect to the voltage VBL of the bit line BL. A black circle on the vertical axis indicates a remanent polarization value when no voltage is applied to the ferroelectric capacitor.

  The writing of logic 1 is performed by setting the bit line BL to a high level and the plate line PL to a low level. At this time, the polarization value of the ferroelectric capacitor changes from point F to point A. That is, the polarization value at point A indicates a logic one memory. On the other hand, writing of logic 0 is performed by setting the bit line BL to a low level and the plate line PL to a high level. At this time, the polarization value of the ferroelectric capacitor changes from point C to point D. That is, the polarization value at point D indicates a memory of logic 0.

  In the read operation of the ferroelectric memory FM, the plate line PL is set to a high level (VDD). When the ferroelectric capacitor holds logic 1, the amount of charge generated from the ferroelectric capacitor is J1 corresponding to the difference between the polarization value at point C and the residual polarization value at point A. When the ferroelectric capacitor holds logic 0, the amount of charge generated from the ferroelectric capacitor is J0 corresponding to the difference between the polarization value at point C and the residual polarization value at point D.

  The 2T2C cell stores complementary logic. For this reason, the sense amplifier SA connected to the bit line pair BL1, / BL1 shown in FIG. 2 amplifies the voltage difference between the bit line pair BL1, / BL1 corresponding to the charge amounts J0, J1, respectively. The twin sense amplifier TSA connected to the bit line BL2 shown in FIG. 2 has the voltage of the bit line BL2 corresponding to the charge amount J1 and the bit line corresponding to the charge amount J0 when the 1T1C cell stores logic 1. The difference from the voltage of BL1 (or / BL1) is amplified. On the other hand, when the 1T1C cell stores logic 0, the twin sense amplifier TSA has a voltage between the bit line BL2 corresponding to the charge amount J0 and the voltage of the bit line BL1 (or / BL1) corresponding to the charge amount J1. Amplify the difference.

  When the read operation of the ferroelectric capacitor having the remanent polarization value of the point A (logic 1) is executed, the polarization value is shifted to the point C via the point B due to the change to the high level of the plate line PL. . After the read operation, the polarization value shifts from point C to point D. This state corresponds to a logic 0 storage state. Therefore, the logic held in the memory cell is lost by reading logic 1 from the memory cell. In order to hold logic 1, a rewrite operation is required. For example, in the rewrite operation, the plate line PL is set from the high level to the low level while the bit line BL is set to the high level. Thereby, the polarization value of the ferroelectric capacitor moves to the point F through the point E. Thereafter, the bit line is set to the low level and the word line WL is set from the high level to the low level, whereby the polarization value returns to the point A, and the rewriting of the logic 1 is completed.

  FIG. 5 shows a hysteresis loop of a ferroelectric capacitor imprinted on the logic 1 side. The solid hysteresis loop NRML shows the state of FIG. 4 that is not imprinted. A dashed hysteresis loop INP1 indicates a state imprinted on the logic 1 side.

  When a long time TINP elapses after the logic 1 is written in the ferroelectric capacitor, the hysteresis loop shifts to the right side (plus side) as shown by the broken line. The remanent polarization value of the ferroelectric capacitor storing the logic 1 is smaller than that in FIG. Also, when logic 0 is written in the ferroelectric capacitor imprinted on the logic 1 side, the remanent polarization value becomes smaller than that in FIG.

  As the remanent polarization value decreases, the amount of charges J0 and J1 generated during the read operation increases as compared to FIG. For this reason, as shown on the left side of the figure, imprinting progresses as time T elapses, and the voltage VBL read to the bit line during the read operation gradually increases. Note that when the ferroelectric capacitor RF1 of the 2T2C cell is imprinted on the logic 1 side, the ferroelectric capacitor RF2 storing the opposite logic 0 is imprinted on the logic 0 side.

  FIG. 6 shows a hysteresis loop of a ferroelectric capacitor imprinted on the logic 0 side. The solid hysteresis loop NRML shows the state of FIG. 4 that is not imprinted. A one-dot chain line hysteresis loop INP0 indicates a state imprinted on the logic 0 side.

  When a long time TINP elapses after the logic 0 is written in the ferroelectric capacitor, the hysteresis loop shifts to the left side (minus side) in the figure as shown by the one-dot chain line. The remanent polarization value of the ferroelectric capacitor that stores logic 0 is larger than that in FIG. Also, when logic 1 is written in the ferroelectric capacitor imprinted on the logic 0 side, the remanent polarization value becomes larger than that in FIG.

  As the remanent polarization value increases, the charge amounts J0 and J1 generated during the read operation are smaller than those in FIG. For this reason, as shown on the left side of the figure, imprinting progresses as time T elapses, and the voltage VBL read to the bit line during the read operation gradually decreases.

  FIG. 7 shows an example of a hysteresis loop of 1T1C cell and 2T2C cell imprinted on the logic 1 side. The meaning of the line indicating the hysteresis loop is the same as in FIGS. The remanent polarization value of the ferroelectric capacitor F1 of the 1T1C cell is indicated by a black circle. The residual polarization value of the ferroelectric capacitor RF1 of the 2T2C cell is indicated by a shaded circle. The remanent polarization value of the ferroelectric capacitor RF2 of the 2T2C cell is indicated by a white circle. In this example, a read operation is performed without rewriting data in a state imprinted on the logic 1 side (INP1).

  The remanent polarization values of the ferroelectric capacitors F1 and RF1 imprinted on the logic 1 side are the same as those of the logic 1 in FIG. Since the ferroelectric capacitor RF2 stores the reverse logic (= “0”) of the logic 1, it is imprinted on the logic 0 side (INP0), and the remanent polarization value is the logic 0 of FIG. The same. In the read operation, the charge amount J1 generated from the ferroelectric capacitor F1 and the charge amount RJ1 generated from the ferroelectric capacitor RF1 are the same. The charge amounts J1 and RJ1 are larger than the charge amount in a state where no imprinting is performed. On the other hand, the charge amount RJ0 generated from the ferroelectric capacitor RF2 is smaller than the charge amount in a state where no imprinting is performed.

  In this example, the reference voltage when reading data from the 1T1C cell that stores logic 1 is generated according to the charge amount RJ0 generated from the ferroelectric capacitor RF2 that stores logic 0. The twin sense amplifier TSA amplifies a voltage difference corresponding to the charge amount difference D1 which is larger than when the imprint is not performed. For this reason, the read margin is improved in the imprint state shown in the drawing.

  The difference in the amount of charge when reading data from the 2T2C cell is also D1, which improves the read margin. Further, when the read operation is executed without rewriting data in a state imprinted on the logic 0 side, the difference in charge amount is D1, and the read margin is improved. After reading, the remanent polarization values (black circles and shaded circles) of the ferroelectric capacitors F1 and RF1 move to the logic 0 position indicated by Δ on the loop INP1. The remanent polarization value (white circle) of the ferroelectric capacitor RF2 returns to “0” in the figure. The ferroelectric capacitors F1 and RF1 return to the original position “1” via the loop INP1 by the above-described rewrite operation.

  FIG. 8 shows an example of a 1T1C cell and a 2T2C hysteresis loop imprinted on the logic 0 side. The meaning of the line indicating the hysteresis loop is the same as in FIGS. The marks of the remanent polarization values of the ferroelectric capacitors F1, RF1, and RF2 are the same as those in FIG. In this example, the reverse logic is written to the 1T1C cell and 2T2C while being imprinted on the logic 0 side, and the read operation is executed.

  The remanent polarization values of the ferroelectric capacitors F1 and RF1 are the same as the logic 1 in FIG. The ferroelectric capacitor RF2 is written with logic opposite to logic 1 (= “0”), and therefore the remanent polarization value is the same as the logic 0 in FIG. In the read operation, the charge amounts J1 and RJ1 generated from the ferroelectric capacitors F1 and RF1 are the same. The charge amounts J1 and RJ1 are smaller than the charge amount in a state where no imprinting is performed. On the other hand, the amount of charge RJ0 generated from the ferroelectric capacitor RF2 is larger than the amount of charge in an unimprinted state.

  Also in this example, the reference voltage when reading data from the 1T1C cell that stores logic 1 is generated according to the charge amount RJ0 generated from the ferroelectric capacitor RF2 that stores logic 0. The twin sense amplifier TSA amplifies the voltage difference corresponding to the charge amount difference D0 which is smaller than when the imprint is not performed. For this reason, in the imprint state shown in the figure, the read margin decreases. The difference in the amount of charge when reading data from the 2T2C cell is also D0, and the read margin decreases. However, since the read margin of the twin sense amplifier system and the 2T2C cell is originally large, the twin sense amplifier TSA and the sense amplifier SA output correct data.

  Further, when the read operation is executed after the reverse logic is written in the 1T1C cell and 2T2C in the state of being imprinted on the logic 1 side, the charge amount difference is D0 and the read margin is reduced. At this time, the remanent polarization value (black circle) of the ferroelectric capacitor F1 is located at logic 0 in the figure. The remanent polarization values (shaded circles and white circles) of the ferroelectric capacitors RF1 and RF2 are interchanged.

  FIG. 9 shows an example of a 1T1C cell and a 2T2C hysteresis loop imprinted on the logic 1 side. However, in this example, reverse logic (= “0”) is written only in the 2T2C cell, and the read operation is executed. The meaning of the line indicating the hysteresis loop is the same as in FIGS. The marks of the remanent polarization values of the ferroelectric capacitors F1, RF1, and RF2 are the same as those in FIG.

  The remanent polarization value of the ferroelectric capacitor F1 is the same as the logic 1 in FIG. 5, and decreases as the imprint progresses. For this reason, the amount of charge J1 generated from the ferroelectric capacitor F1 during the read operation and the voltage VBL generated on the bit line increase as the imprint progresses. The remanent polarization value of the ferroelectric capacitor RF1 is the same as the logic 0 of FIG. 5, and decreases as the imprint progresses. For this reason, the charge amount RJ0 generated from the ferroelectric capacitor RF1 during the read operation and the voltage VBL generated on the bit line increase as the imprint progresses. The remanent polarization value of the ferroelectric capacitor RF2 is the same as the logic 1 in FIG. 6, and increases as the imprint progresses. For this reason, the charge amount RJ1 generated from the ferroelectric capacitor RF2 during the read operation and the voltage VBL generated on the bit line decrease as the imprint progresses.

  In this example, the reference voltage when reading data from the 1T1C cell that stores logic 1 is generated according to the charge amount RJ0 generated from the ferroelectric capacitor RF1 that stores logic 0. The sense amplifier SA corresponding to the bit line BL1 in the twin sense amplifier TSA amplifies the voltage difference corresponding to the charge amount difference D1. The sense amplifier SA corresponding to the bit line / BL1 in the twin sense amplifier TSA amplifies the voltage difference corresponding to the charge amount difference D11. Here, the voltage VBL of the bit line corresponding to the ferroelectric capacitor F1 storing logic 1 is always higher than the voltage VBL of the bit line corresponding to the ferroelectric capacitor RF2 storing logic 1. Therefore, the sense amplifier SA corresponding to the bit line / BL1 (RF2) in the twin sense amplifier TSA always determines that the logic stored in the 1T1C cell is “1”. In other words, in the imprint state shown in the figure, no malfunction occurs even if the read margin decreases.

  FIG. 10 shows an example of a 1T1C cell and a 2T2C hysteresis loop imprinted on the logic 0 side. However, in this example, the reverse logic (= “1”) is written only in the 2T2C cell, and the read operation is executed. The meaning of the line indicating the hysteresis loop is the same as in FIGS. The marks of the remanent polarization values of the ferroelectric capacitors F1, RF1, and RF2 are the same as those in FIG.

  The remanent polarization value of the ferroelectric capacitor F1 is the same as the logical 0 in FIG. 6, and increases as the imprint progresses. The amount of charge J0 generated from the ferroelectric capacitor F1 during the read operation and the voltage VBL generated on the bit line decrease as the imprint progresses. The remanent polarization value of the ferroelectric capacitor RF1 is the same as the logic 1 in FIG. 6, and increases as the imprint progresses. The amount of charge RJ1 generated from the ferroelectric capacitor RF1 and the voltage VBL generated on the bit line during the read operation decrease as the imprint progresses. The remanent polarization value of the ferroelectric capacitor RF2 is the same as the logic 0 in FIG. 5, and decreases as the imprint progresses. The charge amount RJ0 generated from the ferroelectric capacitor RF2 during the read operation and the voltage VBL generated on the bit line increase as the imprint progresses.

  In this example, the reference voltage when reading data from the 1T1C cell that stores logic 0 is generated according to the charge amount RJ1 generated from the ferroelectric capacitor RF1 that stores logic 1. The sense amplifier SA corresponding to the bit line BL1 in the twin sense amplifier TSA amplifies the voltage difference corresponding to the charge amount difference D0. The sense amplifier SA corresponding to the bit line / BL1 in the twin sense amplifier TSA amplifies the voltage difference corresponding to the charge amount difference D00. Here, the voltage VBL of the bit line corresponding to the ferroelectric capacitor F1 storing logic 0 is always lower than the voltage VBL of the bit line corresponding to the ferroelectric capacitor RF2 storing logic 0. Therefore, the sense amplifier SA corresponding to the bit line / BL1 (RF2) in the twin sense amplifier TSA always determines that the logic stored in the 1T1C cell is “0”. In other words, in the imprint state shown in the figure, no malfunction occurs even if the read margin decreases.

  FIG. 11 shows an example of a 1T1C cell and a 2T2C hysteresis loop imprinted on the logic 1 side. However, in this example, the reverse logic (= “0”) is written only in the 1T1C cell, and the read operation is executed. The meaning of the line indicating the hysteresis loop is the same as in FIGS. The marks of the remanent polarization values of the ferroelectric capacitors F1, RF1, and RF2 are the same as those in FIG.

  The remanent polarization value of the ferroelectric capacitor F1 is the same as the logic 0 in FIG. 5, and decreases as the imprint progresses. The amount of charge J0 and the voltage VBL generated on the bit line increase as the imprint progresses. The remanent polarization value of the ferroelectric capacitor RF1 is the same as the logic 1 in FIG. 5, and decreases as the imprint progresses. The charge amount RJ1 and the voltage VBL generated on the bit line increase as the imprint progresses. The remanent polarization value of the ferroelectric capacitor RF2 is the same as the logic 0 of FIG. 6, and increases as the imprint progresses. The charge amount RJ0 and the voltage VBL generated on the bit line decrease as the imprint progresses.

  In this example, the sense amplifier SA corresponding to the bit line BL1 (RF1) in the twin sense amplifier TSA amplifies the voltage difference corresponding to the charge amount difference D1. The sense amplifier SA corresponding to the bit line / BL1 (RF2) in the twin sense amplifier TSA amplifies the voltage difference corresponding to the charge amount difference D00. Here, the voltage VBL of the bit line corresponding to the ferroelectric capacitor F1 storing logic 0 is always higher than the voltage VBL of the bit line corresponding to the ferroelectric capacitor RF2 storing logic 0. For this reason, when the imprint progresses and the charge amount D00 becomes larger than the charge amount D1, the twin sense amplifier TSA reads the logic 0 stored in the 1T1C cell as the logic 1. That is, a malfunction ERR occurs due to the progress of imprint. The conventional ferroelectric memory test method cannot detect the read margin defect shown in FIG.

  FIG. 12 shows an example of a 1T1C cell and a 2T2C hysteresis loop imprinted on the logic 0 side. However, in this example, reverse logic (= “1”) is written only in the 1T1C cell, and the read operation is executed. The meaning of the line indicating the hysteresis loop is the same as in FIGS. The marks of the remanent polarization values of the ferroelectric capacitors F1, RF1, and RF2 are the same as those in FIG.

  The remanent polarization value of the ferroelectric capacitor F1 is the same as the logic 1 in FIG. 6, and increases as the imprint progresses. The amount of charge J1 and the voltage VBL generated on the bit line decrease as the imprint progresses. The remanent polarization value of the ferroelectric capacitor RF1 is the same as the logic 0 of FIG. 6, and increases as the imprint progresses. The charge amount RJ0 and the voltage VBL generated on the bit line decrease as the imprint progresses. The remanent polarization value of the ferroelectric capacitor RF2 is the same as the logic 1 in FIG. 5, and decreases as the imprint progresses. The charge amount RJ1 and the voltage VBL generated on the bit line increase as the imprint progresses.

  In this example, the sense amplifier SA corresponding to the bit line BL1 (RF1) in the twin sense amplifier TSA amplifies the voltage difference corresponding to the charge amount difference D0. The sense amplifier SA corresponding to the bit line / BL1 (RF2) in the twin sense amplifier TSA amplifies the voltage difference corresponding to the charge amount difference D11. Here, the voltage VBL of the bit line corresponding to the ferroelectric capacitor F1 storing logic 1 is always lower than the voltage VBL of the bit line corresponding to the ferroelectric capacitor RF2 storing logic 1. Therefore, when imprinting proceeds and the charge amount D11 becomes larger than the charge amount D0, the twin sense amplifier TSA reads the logic 1 stored in the 1T1C cell as the logic 0. That is, a malfunction ERR occurs due to the progress of imprint. The conventional ferroelectric memory test method cannot detect the read margin defect shown in FIG.

  FIG. 13 shows a test method of the ferroelectric memory FM by the test system TSYS shown in FIG. The flow shown in FIG. 13 is performed in a test process after the wafer process of the ferroelectric memory FM is completed. The test process is included in the manufacturing process of the ferroelectric memory FM.

  First, in operation 100, checker patterns are written to the 1T1C cell and the 2T2C cell. The checker pattern is a test pattern in which logics opposite to each other are written in a target memory cell and a memory cell adjacent to the target memory cell. For example, in FIG. 2, logic 1 is written to the ferroelectric capacitor RF1 of the 2T2C cell and the ferroelectric capacitor F1 of the 1T1C cell, and logic 0 is written to the ferroelectric capacitor RF2 of the 2T2C cell (positive pattern). Since the checker pattern is written in the memory cell, the reverse logic is written in the column of the ferroelectric capacitors F1, RF1, and RF2 adjacent to the column of the ferroelectric capacitors F1, RF1, and RF2. The checker pattern is written in the memory cell by the LSI tester TEST shown in FIG. 3 executing the test program TPRG. The test program TPRG is stored in a magnetic medium or a magneto-optical medium.

  Next, in operation 102, the ferroelectric memory FM in the thermostat TC is left for several hours at a high temperature of, for example, 200 ° C. to 300 ° C. in order to proceed with imprinting. During the high temperature state, the LSI tester TEST stops supplying the power supply voltage VDD and the signal to the ferroelectric memory FM. Note that the LSI tester TEST may continue to supply the power supply voltage VDD to the ferroelectric memory FM and keep the ferroelectric memory FM in a standby state. When left at a high temperature, the ferroelectric capacitors F1 and RF1 that store logic 1 are imprinted on the logic 1 side as shown in FIG. The ferroelectric capacitor RF2 that stores logic 0 is imprinted on the logic 0 side as shown in FIG. Further, the residual polarization values of the ferroelectric capacitors F1, RF1, and RF2 are reduced (depolarization), and the hysteresis loop is reduced.

  Next, in operation 104, the logic written in the 1T1C cell and the 2T2C cell is read to confirm that the data is correctly held. A ferroelectric memory FM from which correct logic cannot be read is treated as a defective product. That is, an evaluation test of data retention characteristics can be performed together with an imprint evaluation test. Operation 104 is performed by the LSI tester TEST executing the test program TPRG. Note that the operation 104 can be omitted when the data retention characteristics of the ferroelectric memory FM are evaluated in advance.

  Next, in operation 106, the inverse pattern of the checker pattern is written into the ferroelectric capacitor F1 of the 1T1C cell, and the positive pattern of the checker pattern is written into the ferroelectric capacitors RF1 and RF2 of the 2T2C cell. Operation 106 is performed by the LSI tester TEST executing the test program TPRG. Operation 106 also serves to write a reverse pattern (back pattern) of the 1T1C cell. For this reason, in the back pattern test (operations 112 to 120), which will be described later, the process of writing the reverse pattern before leaving at high temperature can be omitted.

  Specifically, for example, logic 0 is written in the ferroelectric capacitor F1 imprinted on the logic 1 side. Logic 1 is written in the ferroelectric capacitor RF1 imprinted on the logic 1 side. Logic 0 is written in the ferroelectric capacitor RF2 imprinted on the logic 0 side. That is, the row of the ferroelectric capacitors F1, RF1, and RF2 of interest is in the imprint state of FIG. The opposite logic is written in the column of the ferroelectric capacitors F1, RF1, and RF2 adjacent to the column of the ferroelectric capacitors F1, RF1, and RF2 of interest. For this reason, the imprint state shown in FIG.

  When the write operation of the 1T1C cell does not affect the logic held in the 2T2C cell, that is, when the positive pattern held in the 2T2C cell is not destroyed, it is not necessary to write the positive pattern in the 2T2C cell. For example, when the bit lines BL1 and / BL are set to the high level together with the plate line PL, the positive pattern of the 2T2C cell is maintained without being destroyed.

  Next, in operation 108, a wait time is inserted (eg, 1 second). Operation 108 is performed by the LSI tester TEST executing the test program TPRG. By the wait time, the electrodes of the ferroelectric capacitors F1, RF1, and RF2 can be reliably discharged, and the imprint state can be correctly evaluated. It should be noted that the operation 108 can be omitted when it is estimated in advance that the battery is discharged without inserting a wait time.

  Next, in operation 110, the reverse pattern written in the 1T1C cell and the normal pattern written in the 2T2C cell are read in order to confirm that the data is correctly held. A ferroelectric memory FM from which correct logic cannot be read is handled as a defective product with insufficient read margin. That is, by the operation 110, the ferroelectric capacitor F1 having a deteriorated read margin shown in FIGS. 11 and 12 can be detected. The operation 110 is performed by the LSI tester TEST executing the test program TPRG.

  Next, in operation 112, as in operation 102, the ferroelectric memory FM in the thermostat TC is left for several hours in a high temperature state. Each ferroelectric capacitor F1 in which a reverse pattern is written by being left at a high temperature is imprinted on the logic 1 side or the logic 0 side. Next, in operation 114, as in operation 104, the logic written in the 1T1C cell and the 2T2C cell is read to confirm that the data is correctly retained. The operation 114 can be omitted in the same manner as the operation 104.

  Next, in operation 116, as in operation 106, the positive pattern of the checker pattern is written in the ferroelectric capacitors F1, RF1, and RF2. In other words, the reverse logic data is written only in the ferroelectric capacitor F1 of the 1T1C cell. As a result, a certain row of the ferroelectric capacitors F1, RF1, and RF2 is in the imprint state of FIG. A column adjacent to a column of certain ferroelectric capacitors F1, RF1, and RF2 is in the imprint state of FIG. The writing of the positive pattern to the 2T2C cell can be omitted as in the operation 106.

  Next, in operation 118, a wait time is inserted (for example, 1 second) as in operation 108. Note that operation 118 can be omitted in the same manner as operation 108. Next, in operation 120, as in operation 110, the positive patterns written in the 1T1C cell and the 2T2C cell are read in order to confirm that the data is correctly held. A ferroelectric memory FM from which correct logic cannot be read is treated as a defective product. That is, by the operation 120, the ferroelectric capacitor F1 with the read margin shown in FIGS. 11 and 12 deteriorated can be detected. In this way, the ferroelectric memory FM is manufactured by discriminating between good products and defective products.

  As described above, in this embodiment, a margin defect caused by imprinting can be detected by performing the test flow shown in FIG. 13 in the manufacturing process (test process) of the ferroelectric memory FM. As a result, it is possible to prevent the occurrence of defects due to imprinting in the market and improve the reliability.

  FIG. 14 shows a test method of the ferroelectric memory FM by the test system TSYS in another embodiment. The same elements as those described in the embodiment described above are denoted by the same reference numerals, and detailed description thereof will be omitted. The flow shown in FIG. 14 is performed in a test process after the wafer process of the ferroelectric memory FM shown in FIG. 1 is completed. The test process is included in the manufacturing process of the ferroelectric memory FM.

  In this embodiment, operations 111 and 121 are added to the test flow of FIG. However, the LSI tester TEST performs the write operation of operations 100, 106, and 116 at the normal power supply voltage VDD (Typ.), And performs the read operation of operations 104, 110, 114, and 120 at a power supply voltage VDD (High) higher than normal. ). The other test flow is the same as FIG. Operations 100, 104, 106, 108, 110, 111, 114, 116, 118, 120, and 121 are performed by the LSI tester TEST executing the test program TPRG.

  The power supply voltage VDD is used as a high level voltage of the bit line BL (BL1, / BL1, BL2, etc.) and the plate line PL. Note that the power supply voltage VDD during the write operation may be executed using a power supply voltage VDD (Low) lower than normal. Note that the power supply voltage VDD during the write operation may be executed using a power supply voltage VDD (Low) lower than normal.

  For example, when a storage node of a 1T1C cell is short-circuited to a corresponding word line WL via a high resistance component, the word line WL is transferred to the storage node during a high level period of the word line WL (during access to the 1T1C cell). Charge is supplied. As a result, the amount of charge transferred from the storage node to the bit line BL increases, and the peak voltage of the bit line BL becomes higher than when there is no leak. Here, the storage node is a node between the ferroelectric capacitor F1 and the transfer transistor T1, and is a node from which charges are read from the ferroelectric capacitor F1 during a read operation.

  In operations 104, 110, 114, and 120, the power supply voltage VDD is high during the read operation, and the high level voltage of the word line WL is high. For this reason, in the read operation, the voltage of the bit line BL of the 1T1C cell in which a high resistance leak exists between the corresponding word lines becomes higher than when there is no leak. Details of this read operation are shown in FIG.

  On the other hand, when the storage node of the 1T1C cell is short-circuited with the non-corresponding word line WL via the high resistance component, the non-corresponding word line WL is set to the low level during the read operation of the 1T1C cell. At this time, since charge is supplied from the storage node to the non-corresponding word line, the amount of charge transferred from the storage node to the bit line BL decreases. The peak voltage of the bit line BL is lower than when there is no leak.

  In operation 111, the reverse pattern written in the 1T1C cell and the normal pattern written in the 2T2C cell are read using the power supply voltage VDD (Low) lower than normal. In operation 121, the positive pattern written in the 1T1C cell and the 2T2C cell is read using the power supply voltage VDD (Low) lower than normal. In operations 111 and 121, the power supply voltage VDD during the read operation is low, and the high level voltage of the word line WL is low. For this reason, in the read operation, the voltage of the bit line BL of the 1T1C cell in which a high resistance leak exists between the corresponding word lines is lower than when there is no leak. Details of this read operation are shown in FIG.

  FIG. 15 shows the voltage VBL of the bit line BL when the storage node of the 1T1C cell is short-circuited to the high level node. As in FIG. 11, the 1T1C cell is imprinted on the logic 1 side, and logic 0 is written. The left side of the figure shows the characteristics of the bit line voltage when the power supply voltage VDD during the read operation is standard (Typ.) (For example, operations 104, 110, 114, and 120 in FIG. 13). The right side of the drawing shows the characteristics of the bit line voltage when the power supply voltage VDD during the read operation is high (Operation 104, 110, 114, 120 in FIG. 14).

  The thick broken line in the figure indicates the bit line voltage of the 1T1C cell in which the storage node leaks to the high level node. The rate of increase in the voltage of the bit line BL is higher than when there is no leak. For this reason, the charge amount difference D00 is likely to be larger than the difference D1, and a defect is easily detected. In particular, when the power supply voltage VDD during the read operation is high (High), the defect is more easily detected. As shown on the left side of the figure, even when the power supply voltage VDD during the read operation is standard (Typ.), It is possible to detect a defect in the 1T1C cell in which the storage node leaks to the high level node.

  FIG. 16 shows the voltage VBL of the bit line BL when the storage node of the 1T1C cell is short-circuited to the low level node. As in FIG. 12, the 1T1C cell is imprinted on the logic 0 side, and logic 1 is written. The left side of the figure shows the characteristics of the bit line voltage when the power supply voltage VDD during the read operation is standard (Typ.) (For example, operations 104, 110, 114, and 120 in FIG. 13). The right side of the figure shows the characteristics of the bit line voltage when the power supply voltage VDD during the read operation is low (Low) (operations 111 and 121 in FIG. 14).

  The thick broken line in the figure indicates the bit line voltage of the 1T1C cell in which the storage node leaks to the low level node. The rate of increase in the voltage of the bit line BL is lower than when there is no leak. For this reason, the charge amount difference D11 is likely to be larger than the difference D0, and a defect is easily detected. In particular, when the power supply voltage VDD during the read operation is low (Low), a defect is more easily detected. As shown on the left side of the figure, even when the power supply voltage VDD during the read operation is standard (Typ.), A defect in the 1T1C cell in which the storage node leaks to the low level node can be detected.

  Further, for example, it is assumed that the storage node of the 2T2C cell that is imprinted on the logic 0 side and in which the logic 0 is written leaks to the low level node. At this time, by lowering the power supply voltage VDD during the read operation, the difference D00 shown in FIG. 15 can be relatively increased, and a defective 2T2C cell can be easily detected. Further, it is assumed that the storage node of the 2T2C cell that is imprinted on the logic 1 side and in which logic 1 is written leaks to the high level node. At this time, by increasing the power supply voltage VDD during the read operation, the difference D11 shown in FIG. 16 can be relatively increased, and a defective 2T2C cell can be easily detected.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Further, in this embodiment, when at least one of the 1T1C cell or the 2T2C cell is leaking to the high level node or the low level node, it is possible to detect a leak failure together with the imprint evaluation test. In other words, a memory cell having a leak failure can be detected as a margin failure due to imprint. The leakage current due to the high resistance component may gradually increase with the use of the ferroelectric memory FM, causing a reliability failure. Reliability can be improved by reliably failing the ferroelectric memory FM having a high-resistance leak failure.

  FIG. 17 shows a test method of the ferroelectric memory FM by the test system TSYS in another embodiment. The same elements as those described in the embodiment described above are denoted by the same reference numerals, and detailed description thereof will be omitted. The flow shown in FIG. 17 is performed in a test process after the wafer process of the ferroelectric memory FM shown in FIG. 1 is completed. The test process is included in the manufacturing process of the ferroelectric memory FM.

  This embodiment is effective when it is known in advance by reliability evaluation that the logic 1 imprint is easy to progress and the logic 0 imprint is difficult to progress. As in FIG. 14, the write operation is executed at the normal power supply voltage VDD (Typ.). The read operation is executed at a power supply voltage VDD (High) higher than normal except for the operation 122A. Operations 100A, 104, 106A, 108, 110, 122A are performed by the LSI tester TEST executing the test program TPRG.

  When the logic 1 imprint is dominant, first, in operation 100A, ALL “1” (positive pattern) is written in the 1T1C cell and the 2T2C cell. At this time, logic 0 which is difficult to proceed with imprinting is written in the ferroelectric capacitor RF2 of the 2T2C cell. Next, as in FIG. 14, operations 102 and 104 are performed.

  Next, in operation 106A, ALL “0” (reverse pattern) is written only in the 1T1C cell. After the wait time is inserted, in operation 110, the reverse pattern (logic 0) written in the 1T1C cell and the normal pattern (logic 1) written in the 2T2C cell are read out as in FIG. A ferroelectric memory FM from which correct logic cannot be read is treated as a defective product.

  Thereafter, in operation 122A, ALL “0” (reverse pattern) is written into the 1T1C cell and the 2T2C cell at a power supply voltage VDD (Low) lower than normal. This prevents the logic 1 imprint from proceeding. In the write state of ALL “0”, the ferroelectric capacitor RF2 of the 2T2C cell holds the logic 1, and the imprint is likely to proceed. However, in this example, only the charge amount RJ1 of the ferroelectric capacitor RF2 increases as the logic 1 imprint progresses. Therefore, the read margin is increased and no reliability failure occurs after the operation 122A.

  In this embodiment, the read operation is performed at a power supply voltage VDD (High) higher than normal. However, the read operation may be executed with the normal power supply voltage VDD (Typ.). At this time, the operation 122A may be omitted. Similarly to FIG. 13, the writing of the positive pattern to the 2T2C cell in operations 104 and 108 and operation 106A can be omitted.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Furthermore, in this embodiment, when the imprint characteristics are known in advance, it is possible to omit either the normal pattern or the reverse pattern at high temperature (imprint progress) and the read check. As a result, the test method can be simplified and the test cost can be reduced.

  FIG. 18 shows a test method of the ferroelectric memory FM by the test system TSYS in another embodiment. The same elements as those described in the embodiment described above are denoted by the same reference numerals, and detailed description thereof will be omitted. The flow shown in FIG. 18 is performed in a test process after the wafer process of the ferroelectric memory FM shown in FIG. 1 is completed. The test process is included in the manufacturing process of the ferroelectric memory FM.

  This embodiment is effective when it is known in advance by reliability evaluation that logic 0 imprinting is easy to proceed and logic 1 imprinting is difficult to proceed. As in FIG. 14, the write operation is executed at the normal power supply voltage VDD (Typ.). The read operation is executed at a power supply voltage VDD (High) higher than normal except for the operation 122B. Operations 100B, 104, 106B, 108, 110, and 122B are performed by the LSI tester TEST executing the test program TPRG.

  When the logic 0 imprint is dominant, first, in operation 100B, ALL “0” (positive pattern) is written in the 1T1C cell and the 2T2C cell. At this time, logic 1 which is difficult to proceed with imprinting is written in the ferroelectric capacitor RF2 of the 2T2C cell. Next, as in FIG. 14, operations 102 and 104 are performed.

  Next, in operation 106B, ALL “1” is written only in the 1T1C cell. After the wait time is inserted, in operation 110, the reverse pattern (logic 1) written in the 1T1C cell and the normal pattern (logic 0) written in the 2T2C cell are read out as in FIG. A ferroelectric memory FM from which correct logic cannot be read is treated as a defective product.

  Thereafter, in operation 122B, ALL “1” (reverse pattern) is written into the 1T1C cell and the 2T2C cell at the power supply voltage VDD lower than normal. This prevents the logic 0 imprint from proceeding. In the write state of ALL “1”, the ferroelectric capacitor RF2 of the 2T2C cell holds the logic 0, and imprinting easily proceeds. However, in this example, only the charge amount RJ1 of the ferroelectric capacitor RF2 decreases as the logic 0 imprint progresses. Therefore, the read margin is increased and no reliability failure occurs after the operation 122A.

  In this embodiment, the read operation is performed at a power supply voltage VDD (High) higher than normal. However, the read operation may be executed with the normal power supply voltage VDD (Typ.). At this time, the operation 122B may be omitted. Similarly to FIG. 13, the writing of the positive pattern to the 2T2C cell in operations 104 and 108 and operation 106B can be omitted. As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained.

  FIG. 19 shows an example of a test system TSYS in another embodiment. In this example, the test system TSYS has a thermostatic chamber TC for performing a high temperature standing test independently of the LSI tester TEST. Other configurations are the same as those in FIG.

  When left at a high temperature as shown in operation 102 in FIG. 13 and the like, each ferroelectric memory FM is removed from the LSI tester TEST and stored in the thermostat TC. The movement of the ferroelectric memory FM between the LSI tester TEST and the thermostat TC is performed using, for example, an automatic transfer system.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Furthermore, in this embodiment, even in the test system TSYS in which the LSI tester TEST and the thermostatic chamber TC are installed independently from each other, it is possible to detect a margin defect caused by imprinting, and that a defect due to imprinting occurs in the market. Can be prevented.

  FIG. 20 shows another example of a ferroelectric memory FM to be tested. The same elements as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. In this embodiment, the memory cell array ARY has redundant bit lines RBL and redundant memory cells RMC (redundant 1T1C cells) connected to the redundant bit lines RBL. The redundant bit line RBL is connected to the twin sense amplifier TSA via the pre-sense amplifier PSA similarly to the 1T1C cell of FIG. The ferroelectric memory FM includes a program unit PRG, an address comparison unit ACMP, and a redundancy control circuit REDCNT. Other configurations are the same as those of the first embodiment.

  The program unit PRG has a nonvolatile element such as a fuse or a ferroelectric memory cell. The program unit PRG stores the address of the defective bit line BL (such as BL2) connected to the 1T1C cell by programming the nonvolatile element, and outputs it as the redundant column address RCAD. The address comparison unit ACMP activates the coincidence signal COIN when the column address CAD coincides with the redundant column address RCAD.

  The redundancy control circuit REDCNT selects the normal bit line BL while the coincidence signal COIN is inactive, and selects the redundant bit line RBL while the coincidence signal COIN is active. Thereby, the defective bit line BL is replaced with the redundant bit line RBL, and the defect is relieved. Further, the redundancy control circuit REDCNT forcibly selects the redundancy bit line RBL regardless of the logic of the coincidence signal COIN during the activation of the test signal TEST. The test signal TEST may be supplied via an external terminal, or may be supplied from the outside of the ferroelectric memory FM as a test command.

  The ferroelectric memory FM shown in FIG. 20 is manufactured using the test method shown in FIG. 13, FIG. 14, FIG. 17 or FIG. At this time, the 1T1C cell in the flow of the figure includes the redundant memory cell RMC. However, in order to evaluate the imprint of the redundant memory cell RMC, the flow shown in the drawing is executed not only in a state where the test signal TEST is deactivated but also in a state where the test signal TEST is activated. Thereby, the redundant memory cell RMC can be accessed regardless of the program state of the program unit PRG. Further, FIG. 20 shows the redundant bit line RBL, and the operation of the above circuit is described. However, the same circuit mounting and operation can be performed for the redundant word line.

  FIG. 21 shows another example of a ferroelectric memory FM to be tested. The same elements as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. In this embodiment, the memory cell array ARY includes a parity bit line PBL and a parity memory cell PMC (parity 1T1C cell) connected to the parity bit line PBL. The parity bit line PBL is connected to the twin sense amplifier TSA via the pre-sense amplifier PSA similarly to the 1T1C cell of FIG. The parity memory cell PMC stores parity data of data written to the 2T2C cell and the 1T1C cell. The ferroelectric memory FM has a parity control circuit PARCNT. Other configurations are the same as those of the first embodiment.

  The parity control circuit PARCNT generates parity data of data to be written in the 2T2C cell and 1T1C cell during the write operation, and writes the generated parity data in the parity memory cell PMC. In addition, the parity control circuit PARCNT detects an error in data read from the 2T2C cell and the 1T1C cell by using data read from the parity 1T1C cell during the read operation. When the parity control circuit PARCNT detects an error, the parity control circuit PARCNT corrects the error in the read data and outputs it to the data input / output buffer IOB.

  The parity control circuit PARCNT forcibly selects the parity bit line PBL instead of any of the normal bit lines BL during the activation of the test signal TEST. The test signal TEST may be supplied via an external terminal, or may be supplied from the outside of the ferroelectric memory FM as a test command.

  The ferroelectric memory FM shown in FIG. 21 is manufactured using the test method shown in FIG. 13, FIG. 14, FIG. 17 or FIG. At this time, the 1T1C cell in the flow of the figure includes the parity memory cell PMC. However, in order to evaluate the imprint of the parity memory cell PMC, the flow shown in the drawing is executed not only in a state where the test signal TEST is deactivated but also in a state where the test signal TEST is activated. Thereby, the parity 1T1C cell (PMC) can be accessed as a normal 1T1C cell. That is, any logic can be written in the parity 1T1C cell regardless of the logic written in the 1T1C cell and the 2T2C cell. Furthermore, any logic can be read from the parity 1T1C cell regardless of the logic read from the 1T1C cell and the 2T2C cell.

  FIG. 22 shows another example of the ferroelectric memory FM to be tested. The same elements as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. In this embodiment, the twin sense amplifier TSA receives 2T2C cell read data output via the pre-sense amplifier PSA. The pre-sense amplifier PSA is the pre-sense amplifier shown in FIG. 2 or the bit line GND sense type pre-sense amplifier (BGS amplifier). Other configurations are the same as those of the first embodiment.

  The BGS amplifier has, for example, a charge transfer circuit called a charge transfer, a charge storage circuit, and a voltage generation circuit. The BGS amplifier operates as follows during a read operation. First, when a voltage is applied to the plate line PL, the charge transfer circuit causes the bit line BL (BL1, / BL1, BL2,... BLn) not to fluctuate from the ferroelectric capacitor to the bit line. The charge read to BL is transferred to the charge storage circuit. The voltage generation circuit generates a voltage according to the amount of charge transferred to the charge storage circuit, and outputs the generated voltage to the sense amplifier SA and the twin sense amplifier TSA.

Regarding the above embodiment, the following additional notes are disclosed.
(Appendix 1)
A first memory cell having a ferroelectric capacitor for storing a single logic level, a second memory cell having a ferroelectric capacitor pair for storing a complementary logic level, and a charge read from the ferroelectric capacitor. And a twin sense amplifier that generates a logic level according to the voltage according to the electric charge read from the ferroelectric capacitor and the electric charge read from one of the ferroelectric capacitor pairs. A first sense amplifier for differentially amplifying a voltage; a first amplifier for differentially amplifying a voltage corresponding to a charge read from the ferroelectric capacitor and a voltage corresponding to a charge read from the other of the ferroelectric capacitor pair; A method of manufacturing a ferroelectric memory having two sense amplifiers,
Writing a first logic to the first and second memory cells;
In order to proceed the imprint of the ferroelectric capacitor and the ferroelectric capacitor pair, the ferroelectric memory is left under high temperature,
Writing a second logic opposite to the first logic in the first memory cell;
Reading the logic held in the first memory cell;
A method of manufacturing a ferroelectric memory, comprising: detecting a defect of the ferroelectric memory when a logic to be read is different from the second logic.
(Appendix 2)
In the method for manufacturing a ferroelectric memory according to appendix 1,
In order to proceed the imprint of the ferroelectric capacitor and the ferroelectric capacitor pair, the ferroelectric memory is left under high temperature,
Writing the first logic to the first memory cell;
Reading the logic held in the first memory cell;
A method of manufacturing a ferroelectric memory, comprising: detecting a defect of the ferroelectric memory when a logic to be read is different from the first logic.
(Appendix 3)
In the method for manufacturing a ferroelectric memory according to appendix 1 or appendix 2,
Manufacturing a ferroelectric memory, wherein a power supply voltage at the time of reading logic held in the first memory cell is different from a power supply voltage at the time of writing logic to the first and second memory cells. Method.
(Appendix 4)
In the method for manufacturing a ferroelectric memory according to any one of appendices 1 to 3,
The first memory cell includes a normal memory cell and a redundant memory cell for relieving a defect of the normal memory cell,
A method for manufacturing a ferroelectric memory, comprising: detecting a defect in a ferroelectric memory when logic read from the normal memory cell and the redundant memory cell is different from the logic written immediately before.
(Appendix 5)
In the method for manufacturing a ferroelectric memory according to any one of appendices 1 to 3,
The first memory cell includes a normal memory cell and a parity memory cell that stores a parity bit of the normal memory cell;
A method of manufacturing a ferroelectric memory, comprising: detecting a defect of a ferroelectric memory when logic read from the normal memory cell and the parity memory cell is different from the logic written immediately before.
(Appendix 6)
In the method for manufacturing a ferroelectric memory according to any one of appendices 1 to 5,
A method of manufacturing a ferroelectric memory, wherein the same logic as that before being left at high temperature is written into the second memory cell when writing the reverse logic to the first memory cell before being left at high temperature. .
(Appendix 7)
In the method for manufacturing a ferroelectric memory according to any one of appendices 1 to 6,
Read the logic held in the first and second memory cells before writing the opposite logic to the logic held in the first memory cell;
A method of manufacturing a ferroelectric memory, comprising: detecting a defect of the ferroelectric memory when the logic to be read is different from the logic written before being left at high temperature.
(Appendix 8)
In the method for manufacturing a ferroelectric memory according to any one of appendices 1 to 7,
Inserting a wait time in order to discharge the charges of the ferroelectric capacitor and the electrode of the ferroelectric capacitor pair after writing a logic opposite to that before leaving the first memory cell at a high temperature. A method of manufacturing a ferroelectric memory characterized by the following.
(Appendix 9)
A first memory cell having a ferroelectric capacitor for storing a single logic level, a second memory cell having a ferroelectric capacitor pair for storing a complementary logic level, and a charge read from the ferroelectric capacitor. And a twin sense amplifier that generates a logic level according to the voltage according to the electric charge read from the ferroelectric capacitor and the electric charge read from one of the ferroelectric capacitor pairs. A first sense amplifier for differentially amplifying a voltage; a first amplifier for differentially amplifying a voltage corresponding to a charge read from the ferroelectric capacitor and a voltage corresponding to a charge read from the other of the ferroelectric capacitor pair; A test system for performing an operation test of a ferroelectric memory having two sense amplifiers,
The test system includes:
Writing a first logic to the first and second memory cells;
In order to proceed the imprint of the ferroelectric capacitor and the ferroelectric capacitor pair, the ferroelectric memory is left under high temperature,
Writing a second logic opposite to the first logic in the first memory cell;
Reading the logic held in the first memory cell;
A test system for detecting a failure of a ferroelectric memory when a logic to be read is different from the second logic.
(Appendix 10)
In the test system according to appendix 9,
The test system includes:
In order to proceed the imprint of the ferroelectric capacitor and the ferroelectric capacitor pair, the ferroelectric memory is left under high temperature,
Writing the first logic to the first memory cell;
Reading the logic held in the first memory cell;
A test system for detecting a failure of a ferroelectric memory when a logic to be read is different from the first logic.
(Appendix 11)
In the test system according to appendix 9 or appendix 10,
The test system is characterized in that a power supply voltage at the time of reading logic held in the first memory cell is different from a power supply voltage at the time of writing logic to the first and second memory cells. system.
(Appendix 12)
In the test system according to any one of appendix 9 to appendix 11,
The first memory cell includes a normal memory cell and a redundant memory cell for relieving a defect of the normal memory cell,
The test system detects a defect in a ferroelectric memory when the logic read from the normal memory cell and the redundant memory cell is different from the logic written immediately before.
(Appendix 13)
In the test system according to any one of appendix 9 to appendix 11,
The first memory cell includes a normal memory cell and a parity memory cell that stores a parity bit of the normal memory cell;
The test system detects a defect of a ferroelectric memory when the logic read from the normal memory cell and the parity memory cell is different from the logic written immediately before.
(Appendix 14)
In the test system according to any one of appendix 9 to appendix 13,
The test system writes the same logic as before writing to the second memory cell at a high temperature when writing the reverse logic to the first memory cell at a high temperature. .
(Appendix 15)
In the test system according to any one of appendix 9 to appendix 14,
The test system includes:
Read the logic held in the first and second memory cells before writing the opposite logic to the logic held in the first memory cell;
A test system for detecting a failure of a ferroelectric memory when a logic to be read is different from a logic written before being left at high temperature.
(Appendix 16)
In the test system according to any one of appendix 9 to appendix 15,
The test system has a wait time for discharging the charges of the electrodes of the ferroelectric capacitor and the ferroelectric capacitor pair after writing a reverse logic to the first memory cell before being left at high temperature. A test system characterized by inserting a.

  From the above detailed description, features and advantages of the embodiment will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Further, any person having ordinary knowledge in the technical field should be able to easily come up with any improvements and changes, and there is no intention to limit the scope of the embodiments having the invention to those described above. It is also possible to rely on suitable improvements and equivalents within the scope disclosed in.

Fig. 4 illustrates an example of a ferroelectric memory to be tested in one embodiment. 2 shows an example of a memory core of the ferroelectric memory shown in FIG. 1 illustrates an example of a test system in one embodiment. 3 shows a hysteresis loop of a ferroelectric capacitor. 3 shows a hysteresis loop of a ferroelectric capacitor imprinted on the logic 1 side. A hysteresis loop of a ferroelectric capacitor imprinted on the logic 0 side is shown. An example of a hysteresis loop of a 1T1C cell and a 2T2C cell imprinted on the logic 1 side is shown. An example of a 1T1C cell and a 2T2C hysteresis loop imprinted on the logic 0 side is shown. An example of a 1T1C cell imprinted on the logic 1 side and a 2T2C hysteresis loop is shown. An example of a 1T1C cell and a 2T2C hysteresis loop imprinted on the logic 0 side is shown. An example of a 1T1C cell imprinted on the logic 1 side and a 2T2C hysteresis loop is shown. An example of a 1T1C cell and a 2T2C hysteresis loop imprinted on the logic 0 side is shown. 4 shows a ferroelectric memory test method using the test system TSYS shown in FIG. 3. 3 shows a method for testing a ferroelectric memory by a test system in another embodiment. The voltage of the bit line when the storage node of the 1T1C cell is shorted to the high level node is shown. The voltage of the bit line when the storage node of the 1T1C cell is shorted to the low level node is shown. 3 shows a method for testing a ferroelectric memory by a test system in another embodiment. 3 shows a method for testing a ferroelectric memory by a test system in another embodiment. 3 shows an example of a test system in another embodiment. 3 shows another example of a ferroelectric memory to be tested. 3 shows another example of a ferroelectric memory to be tested. 3 shows another example of a ferroelectric memory to be tested.

Explanation of symbols

  ACMP: Address comparison unit; ADB: Address buffer; ARY: Memory cell array; BL1, / BL1, BL2: Bit lines; CDEC: Column decoder; CMDB: Command buffer; COIN: Match signal; Ferroelectric memory; IOB Data input / output buffer; TCNT Timing control circuit; PARCNT Parity control circuit; PBL Parity bit line; PD Plate driver; PL Plate line; PMC Parity memory cell PRG Program unit; PSA Pre-sense amplifier; RBL Redundant bit line; REDCNT Redundant control circuit; RF1, RF2 Ferroelectric capacitor; RMC Redundant memory cell; RT1, RT2 Transfer transistor; 1 ‥ transfer transistor; TC ‥ thermostatic bath; TSA ‥ twin sense amplifier; TSYS ‥ test system; WAF ‥ semiconductor wafer; WD ‥ word driver; WDEC ‥ word decoder; WL ‥ word line

Claims (6)

A first memory cell having a ferroelectric capacitor for storing a single logic level, a second memory cell having a ferroelectric capacitor pair for storing a complementary logic level, and a charge read from the ferroelectric capacitor. And a twin sense amplifier that generates a logic level according to the voltage according to the electric charge read from the ferroelectric capacitor and the electric charge read from one of the ferroelectric capacitor pairs. A first sense amplifier for differentially amplifying a voltage; a first amplifier for differentially amplifying a voltage corresponding to a charge read from the ferroelectric capacitor and a voltage corresponding to a charge read from the other of the ferroelectric capacitor pair; A method of manufacturing a ferroelectric memory having two sense amplifiers,
Writing a first logic to the first and second memory cells;
In order to proceed the imprint of the ferroelectric capacitor and the ferroelectric capacitor pair, the ferroelectric memory is left under high temperature,
Writing a second logic opposite to the first logic in the first memory cell;
Reading the logic held in the first memory cell;
A method of manufacturing a ferroelectric memory, comprising: detecting a defect of the ferroelectric memory when a logic to be read is different from the second logic. The method of manufacturing a ferroelectric memory according to claim 1.
In order to proceed the imprint of the ferroelectric capacitor and the ferroelectric capacitor pair, the ferroelectric memory is left under high temperature,
Writing the first logic to the first memory cell;
Reading the logic held in the first memory cell;
A method of manufacturing a ferroelectric memory, comprising: detecting a defect of the ferroelectric memory when a logic to be read is different from the first logic. 3. The method for manufacturing a ferroelectric memory according to claim 1, wherein:
Manufacturing a ferroelectric memory, wherein a power supply voltage at the time of reading logic held in the first memory cell is different from a power supply voltage at the time of writing logic to the first and second memory cells. Method. 4. The method of manufacturing a ferroelectric memory according to claim 1, wherein:
The first memory cell includes a normal memory cell and a redundant memory cell for relieving a defect of the normal memory cell,
A method for manufacturing a ferroelectric memory, comprising: detecting a defect in a ferroelectric memory when logic read from the normal memory cell and the redundant memory cell is different from the logic written immediately before. 4. The method of manufacturing a ferroelectric memory according to claim 1, wherein:
The first memory cell includes a normal memory cell and a parity memory cell that stores a parity bit of the normal memory cell;
A method of manufacturing a ferroelectric memory, comprising: detecting a defect of a ferroelectric memory when logic read from the normal memory cell and the parity memory cell is different from the logic written immediately before. A first memory cell having a ferroelectric capacitor for storing a single logic level, a second memory cell having a ferroelectric capacitor pair for storing a complementary logic level, and a charge read from the ferroelectric capacitor. And a twin sense amplifier that generates a logic level according to the voltage according to the electric charge read from the ferroelectric capacitor and the electric charge read from one of the ferroelectric capacitor pairs. A first sense amplifier for differentially amplifying a voltage; a first amplifier for differentially amplifying a voltage corresponding to a charge read from the ferroelectric capacitor and a voltage corresponding to a charge read from the other of the ferroelectric capacitor pair; A test system for performing an operation test of a ferroelectric memory having two sense amplifiers,
The test system includes:
Writing a first logic to the first and second memory cells;
In order to proceed the imprint of the ferroelectric capacitor and the ferroelectric capacitor pair, the ferroelectric memory is left under high temperature,
Writing a second logic opposite to the first logic in the first memory cell;
Reading the logic held in the first memory cell;
A test system for detecting a failure of a ferroelectric memory when a logic to be read is different from the second logic.

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