JP2010039648A - Reference voltage generating circuit and semiconductor element having the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a reference voltage generating circuit which operates with lower voltage than a band gap voltage and low-power consumption and generates high precision reference voltage. <P>SOLUTION: The difference voltage V<SB>S</SB>which has a positive temperature dependency is converted into the second current I<SB>2</SB>, by performing feeding back using the differential amplifier A1 so as to apply a same voltage to both ends of the first diode Da and to the point between the second diode Db and the first resistor R<SB>1</SB>which are series-connected. The forward voltage which has a negative temperature dependency is converted into the third current I<SB>3</SB>, by connecting the third resistor R<SB>3A</SB>to the second diode Db and connecting the fourth resistor R<SB>3B</SB>to the first diode Da. Then, the first current I<SB>1</SB>which has no temperature dependencies is generated by combining the second current I<SB>2</SB>and the third current I<SB>3</SB>. Further, the output voltage Vout is generated by connecting the third resistor R<SB>3A</SB>and the fourth resistor R<SB>3B</SB>to the output node N3 and by flowing a current I<SB>1</SB>+I<SB>3</SB>×2 through the second resistor R<SB>2</SB>. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a reference voltage generation circuit that generates a desired reference voltage and a semiconductor device including the same, and more particularly to a reference voltage generation circuit that operates at a power supply voltage that is lower than the band gap voltage of silicon and a semiconductor device including the same. Is.

  In a semiconductor element such as a semiconductor chip, it is necessary to adjust a node in the circuit to a desired voltage in order to operate the internal circuit properly. Particularly in an analog circuit, the accuracy of the voltage is important. It becomes.

  For this reason, a reference voltage generating circuit for generating a desired reference voltage is usually formed in the semiconductor element.

  As this reference voltage generation circuit, two diodes Da and Db having different current densities are used to extract a voltage having a positive temperature dependency, and this voltage and a forward voltage of a PN junction having a negative temperature dependency are appropriately used. There is a circuit that generates a reference voltage that does not depend on temperature by adding at a proper ratio.

That is, since the differential voltage V _S between the two diodes Da and Db having different current densities has a positive temperature dependency and the forward voltage V _BE of the diodes Da and Db has a negative temperature dependency, these voltages Are added at an appropriate ratio to generate a temperature independent reference voltage.

For example, when the temperature rises, the voltage corresponding to the decrease in the forward voltage V _BE having the negative temperature dependency is represented by ΔV _BE and the voltage ΔV _{S corresponding} to the increase in the differential voltage V _S having the positive temperature dependency. By appropriately adjusting the ratio α, ΔV _BE + αΔV _S = 0. Thereby, it is possible to generate a highly accurate reference voltage having no temperature dependency.

  However, the semiconductor element of the advanced process of 90 nm or later cannot be operated with the above-described conventional configuration because the power supply voltage is a voltage lower than the band gap voltage (for example, 1.2 V).

  Therefore, Patent Document 1 below discloses a reference voltage generation circuit capable of generating a highly accurate reference voltage even when the power supply voltage is a voltage equal to or lower than the band gap voltage.

The reference voltage generation circuit of Patent Document 1 converts the differential voltage V _S having a positive temperature dependency into a current, converts the forward voltage V _BE having a negative temperature dependency into a current, and converts these currents into currents. After the addition, the reference voltage Vout is generated by converting the voltage into a voltage.

  FIG. 4 shows a configuration of the reference voltage generating circuit 100 described in Patent Document 1.

The diode Db has an emitter area N times that of the diode Da (N> 1), and the forward voltage differential voltage V _S1 when the same current I _11A is passed through these is expressed by the following equation (10). Can be expressed as: Here, k is a Boltzmann constant, T is an absolute temperature, q is an electron charge amount, and log is a natural logarithm.
V _S1 = kT / qlogN (10)

A resistance element R ₁₁ is connected in series to the diode Db, and a differential amplifier circuit A 10 and PMOS transistors M ₁₁ and M ₁₂ are used so that the voltages V 10 a and V 10 b at the two nodes N 10 and N 11 are equal. Feedback is on.

Thus node N10, N11 of the voltage V10a, since V10b are equal, the diode Da, the differential voltage V _S1 of Db becomes the same voltage as the voltage across the resistor element R _11, diode Da, the current flowing through the Db I _11A Can be expressed as in the following formula (11).
I _11A = kT / (R ₁₁ q) log N (11)

Therefore, it can be seen that the current I _11A flowing through the diodes Da and Db is a current having a positive temperature dependency in which the current increases as the temperature rises.

On the other hand, resistance elements R _13A and R _13B having the same resistance value R ₁₃ are connected between nodes N10 and N11 and the ground node, respectively. Since these resistors R _13A and R _13B are respectively applied with the same voltage as the forward voltage V _BE of the diode Da, a current I _11B flowing through these resistors R _13A and R _13B is expressed by the following equation (12). It can be expressed as
I _11B = V _BE / R ₁₃ (12)

Forward voltage V _BE in the above formula (12), since a voltage having a negative temperature dependency that the voltage drops in response to the temperature rise, the resistance element R _13A, current I _11B flowing through the R _13B is negative It can be seen that the current has temperature dependence.

Since the sum I ₁₀ (= I _11A + I _11B ) of these currents flows through the PMOS transistors M ₁₁ and M ₁₂ , by appropriately selecting the resistance values of the resistance elements R ₁₁ , R _13A and R _13B , The ratio of these currents I _11A and I _11B having positive and negative temperature dependence can be adjusted. Thus, when designed in optimal ratio, so that it is possible to generate a current I ₁₀ having no temperature dependency.

Then, by causing the same current I ₁₀ to flow from the PMOS transistor M ₁₃ to the resistance element R ₁₂ , an output voltage Vout having no temperature dependency can be generated and output from the output node N12.

Japanese Patent No. 3586073

However, in the technique of the above-mentioned Patent Document 1, extra current is consumed by the resistance elements R _13A and R _13B in order to generate the current I _11A having a positive temperature dependency.

  On the other hand, severe low power consumption is required for portable devices and the like, and it is desired to reduce current consumption as much as possible.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a highly accurate reference voltage generating circuit that operates with a power supply voltage lower than the band gap voltage and that consumes less power than in the prior art.

  In order to achieve the above object, according to the first aspect of the present invention, there is provided a first PMOS transistor and a first PN junction connected in series between a power supply node and a ground node, and a power supply node and a ground node. A second PMOS transistor, a first resistance element and a second PN junction connected in series between the power supply node and the ground node, and a third PMOS transistor and a second PMOS transistor connected in series between the power supply node and the ground node. A first voltage depending on the characteristics of the resistance element, the first PN junction, and a second voltage depending on the characteristics of the second PN junction are input, and the first voltage and the second voltage are input. A differential amplifier circuit for supplying an output voltage corresponding to the difference between the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor to the gates of the first PMOS transistor, the drain of the first PMOS transistor, and the third PMOS transistor. PMOS A third resistance element connected between the transistor and the output node between the second resistance element and a fourth resistance element connected between the drain of the second PMOS transistor and the output node. And a resistance element.

  According to a second aspect of the present invention, in the first aspect of the invention, the first voltage is a voltage generated at a connection point between the first PMOS transistor and the first PN junction. The second voltage is a voltage generated at a connection point between the second PMOS transistor and the first resistance element.

  According to a third aspect of the present invention, in the first or second aspect of the present invention, the second PN junction is composed of a plurality of PN junctions connected in parallel.

  According to a fourth aspect of the present invention, in the first or second aspect of the present invention, the second PMOS transistor includes a plurality of PMOS transistors connected in parallel, and the fourth PMOS transistor The resistance value of the resistance element is set to N times the resistance value of the third resistance element, and the first PN junction is formed in the same size as the first PN junction.

  According to a fifth aspect of the present invention, a reference voltage generation circuit for generating a predetermined reference voltage is provided therein, and the reference voltage generation circuit is a first connected in series between a power supply node and a ground node. A PMOS transistor and a first PN junction, a second PMOS transistor, a first resistance element and a second PN junction connected in series between a power supply node and a ground node, a power supply node and a ground node, A third PMOS transistor and a second resistance element connected in series between the first and second PN junctions, a first voltage that depends on the characteristics of the first PN junction, and a second voltage that depends on the characteristics of the second PN junction. And a differential amplifier circuit that supplies an output voltage corresponding to a difference between the first voltage and the second voltage to each gate of the first, second, and third PMOS transistors, Further comprising A third resistance element connected between a drain of one PMOS transistor and an output node between the third PMOS transistor and the second resistance element; a drain of the second PMOS transistor; And a fourth resistance element connected to the output node.

  According to the present invention, it is possible to provide a highly accurate reference voltage generating circuit that operates with a power supply voltage lower than the band gap voltage and that consumes less power than in the past.

  A semiconductor device according to an embodiment of the present invention operates with a power supply voltage lower than a band gap voltage, and includes a reference voltage generation circuit with low power consumption and high accuracy.

In this reference voltage generation circuit, the differential voltage between the first diode and the second diode having different current densities has a positive temperature dependency, and the forward voltage V _{BE of} the first and second diodes has a negative temperature dependency. Therefore, a highly accurate reference voltage is generated using these.

  Then, in order to operate with a power supply voltage lower than the band gap voltage, it is converted into a current once without directly adding the differential voltage having a positive temperature dependency and the forward voltage having a negative temperature dependency. Then, after adding with the current, it is converted into a voltage to generate a reference voltage.

  That is, feedback is applied by the differential amplifier circuit so that the same voltage is applied to the first diode, the second diode connected in series, and the first resistance element, and a differential voltage having a positive temperature dependence is applied to the first diode. It converts into the 1st electric current which flows into 1 diode or 2nd diode.

  Further, a third resistance element is connected to the first diode, a fourth resistance element is connected to the second diode, and a forward voltage having a positive temperature dependency is applied to the third and fourth resistance elements. It converts into the 2nd electric current which flows.

  Since the first current is a current having a positive temperature dependency and the second current is a current having a negative temperature dependency, a third current having no temperature dependency is obtained by adding these. be able to. And the voltage which does not have temperature dependence is produced | generated by flowing this 3rd electric current through a 2nd resistive element.

  Furthermore, in the reference voltage generation circuit according to the present embodiment, the third and fourth resistance elements are connected to the output node that outputs the reference voltage.

In the technique of Patent Document 1, the resistance element R _13B is the third and fourth resistive elements, because it was to connect the R _13A to the ground node, but the power consumption had been wasted, the present embodiment In the reference voltage generating circuit, a current flowing through the third and fourth resistance elements is used to generate a reference voltage by flowing through the second resistance element.

  Therefore, power consumption can be suppressed, and low power consumption can be achieved by applying to a device such as a portable device that requires severe low power consumption.

  Hereinafter, a reference voltage generating circuit formed in a semiconductor device according to an embodiment of the present invention will be specifically described with reference to the drawings. 1 and 2 are configuration diagrams of a reference voltage generating circuit according to an embodiment of the present invention.

The reference voltage generation circuit 1 includes first to third PMOS transistors M _{1 to} M ₃ , first and second diodes Da and Db (an example of a first PN junction and a second PN junction), A fourth resistor element R ₁ , R ₂ , R _3B , R _3A , and a differential amplifier circuit A1 are included.

As shown in FIG. 1, the first PMOS transistor M ₁ and the first diode Da are connected in series to the power supply node and the ground node, and the second PMOS transistor M ₂ , the second diode Db, and the first resistor are connected. Element R ₁ is connected in series between the power supply node and the ground node. The second diode Db and a first arrangement of the resistance elements R ₁ is not limited to ground the first resistance element R _1, arranged so as to ground the second diode Db as shown in FIG. 2 May be.

The first and second PMOS transistors M ₁ and M ₂ are formed with the same size, and both receive the output voltage of the differential amplifier circuit A1. Therefore, the first and second PMOS transistors M ₁ and M ₂ supply current I ₂ equal to the first diode Da and the second diode Db as current sources.

Further, the node N1 to the first drain of the PMOS transistor M ₁ and the first diode Da is connected, and a node N2 and the drain of the second PMOS transistor M ₂ and the second diode Db is connected A feedback loop is formed by connecting to the input node of the differential amplifier circuit A1. Therefore, feedback is applied so that the voltage Va (first voltage) at the node N1 and the voltage Vb at the node N2 are equal. More specifically, the differential amplifier circuit A1 includes a voltage Va (first voltage) that depends on the characteristics of the first diode Da and a voltage Vb (second voltage) that depends on the characteristics of the second diode Db. ) Is entered. The differential amplifier circuit A1 supplies an output voltage corresponding to the difference between the voltage Va and the voltage Vb to the gates of the first and second PMOS transistors M ₁ and M ₂ . Incidentally, the differential amplifier circuit A1, the output voltage corresponding to the difference between the voltage Va and the voltage Vb is also fed to the third PMOS transistor M _3, the third PMOS transistor M ₃ are first PMOS transistor They are formed in the same size as the M _1. Therefore, the current supplied from the third PMOS transistor M ₃ is the same as the current I ₁ supplied from the first and second PMOS transistors M ₁ and M ₂ .

  In addition, since the second diode Db has N diodes of the same size as the first diode Da connected in parallel, the forward voltage of the second diode Db is equal to the forward voltage of the first diode Da. On the other hand, the voltage decreases by kT / qlogN.

Since the resistance element R ₁ is connected to the second diode Db, the differential voltage V _S between the forward voltages of the two diodes Da and Db is equal to the voltage across the resistance element R ₁ . That is, to become equal to the voltage as described above and the voltage Vb of the voltage Va and the node N2 of the node N1, the voltage across the resistor element R ₁ is the order of the second diode Db from the forward voltage of the first diode Da The voltage V _S is obtained by subtracting the direction voltage.

Further, the reference voltage generation circuit 1 of the present embodiment includes a fourth resistance element R _3B connected between the node N1 and the output node N3, and a first resistor connected between the node N2 and the output node N3. third resistive element and a R _3A. The two resistance elements R _3A and R _3B have the same resistance value R ₃ .

As described above, since the voltage Va at the node N1 and the voltage Vb at the node N2 are equal, the voltages applied to the resistance elements R _3A and R _3B are equal and the same current I ₃ flows.

Since the currents I ₂ flowing through the first and second diodes Da and Db are both I ₁ -I ₃ , the relationship represented by the following formula (1) can be derived. However, the thermal voltage V _T = kT / q.
R ₁ × (I ₁ −I ₃ ) = V _T log (N) (1)

Between the power supply node and the ground node, a third PMOS transistor M ₃ and the second resistive element R ₂ are connected, the third PMOS transistor M ₃ second resistive element in series with R ₂ current supplied to becomes I _1. Further, currents supplied from the third resistance elements R _3A and R _3B to the second resistance element R ₂ are currents I ₃ , respectively. Therefore, the current flowing through the second resistance element R ₂ is I ₁ + 2I ₃ , and the voltage Vout at the output node N3 can be expressed by the following equation (2).
Vout = R ₂ × (I ₁ + 2I ₃ ) (2)

Further, since the current flowing through the third resistance elements R _3A and R _3B is the current I ₃ , the following relational expression can be derived when V _BE is the forward voltage of the diode Da.
V _BE −Vout = R ₃ × I ₃ (3)

When the currents I ₁ and I ₃ are eliminated from the above equations (1), (2), and (3), the output voltage Vout can be expressed by the following equation (4).
Vout = 3R ₂ / (R ₃ + 3R ₂ ) {R ₃ / (3R ₁ ) * V _T log (N) + V _BE } (4)

Here, in curly brackets {} in the equation (4), the sum of the thermal voltage V _T and the forward voltage V _BE of the diode is taken. When this sum becomes a voltage equal to the band gap voltage of silicon, the output voltage Vout has no temperature dependence.

Here, since 3R ₂ / (R ₃ + 3R ₂ ) is applied outside the curly braces, the actual output voltage Vout can be made lower than the band gap voltage of silicon.

Moreover, in the technique disclosed in Patent Document 1, a wasteful current is passed to the ground via the resistance elements R _13A and R _13B connected to the nodes N10 and N11. However, in the reference voltage generation circuit 1, the nodes N1 and N2 are supplied. No current flows to the ground via the third and fourth resistance elements R _3A and R _3B to be connected. That is, the current I ₃ flowing through the third and fourth resistance elements R _3A and R _3B flows through the second resistance element R ₂ and is used to generate the reference voltage. Therefore, in the reference voltage generation circuit 1 according to the present embodiment, power consumption can be reduced as compared with the technique of Patent Document 1.

  Here, the points to be noted in the actual design of the reference voltage generation circuit 1 will be described.

In actual design, it is important that the PMOS transistors M _{1 to} M ₃ operate as constant current sources. Therefore, the source-drain voltage of the PMOS transistor M ₁ ~M ₃ is selected equal such circuit constants as possible.

The forward voltage of the first diode Da is about 0.82 V at −40 ° C. and about 0.55 V at 125 ° C. Therefore, when the temperature changes, the source / drain voltages of the PMOS transistors M ₁ and M ₂ change by this amount.

On the other hand, the output voltage Vout has no temperature dependence. Therefore, it is desirable to set the output voltage Vout near 0.7V as an intermediate voltage between 0.82V and 0.55V. At this time, by appropriately selecting 3R ₂ / (R ₃ + 3R ₂ ), it is possible to set it to around 0.7V.

Further, the PMOS transistors M _{1 to} M ₃ are designed to operate in a saturated state, so that even if there is a slight difference between the source and drain voltages, the flowing current can be hardly changed.

In this way, the minimum operating voltage when the output voltage Vout is set to around 0.7 V is that the PMOS transistors M ₁ and M ₂ are low when the forward voltage of the first diode Da is as high as 0.82 V at a low temperature. It is determined by the limit voltage that can operate in a saturated state as a current source. Therefore, even in the worst case, the reference voltage generating circuit 1 can operate if the power supply voltage is 1.0 V or higher.

  Next, a modification of the reference voltage generating circuit 1 will be described with reference to FIG. FIG. 3 is a diagram showing a configuration of another reference voltage generating circuit 1 'according to an embodiment of the present invention.

Reference voltage generating circuit 1 'shown in FIG. 3, the first and second diode Da, a size of Db is the same size, the current flowing in the current flowing through the second PMOS transistor M ₂ to the first PMOS transistor _{M 1} 1 / N.

In order to reduce the current flowing through the second PMOS transistor M ₂ to 1 / N of the current flowing through the first PMOS transistor M ₁ , N PMOS transistors having the same size as the _second MOS transistor M ₂ are connected in parallel. This can be realized by using the first and third PMOS transistors M ₁ and M ₃ .

Also in the reference voltage generation circuit 1 ′, the forward voltage of the second diode Db is smaller by kT / qlog (N) than the forward voltage of the first diode Da. The same. This is because the current flowing through the second PMOS transistor M ₂ is 1 / N of the current flowing through the first PMOS transistor M ₁ .

The value of the fourth resistance element R _3B is set to N times the resistance value R _3. As a result, the current flowing through the fourth resistance element R _3B can be reduced to 1 / N times the current flowing through the third resistance element R _3A .

The output voltage Vout of the reference voltage generation circuit 1 ′ can be expressed as the following equation (5).
Vout =
_{{(2N + 1) R 2} } / {NR 3 + (2N + 1) R 2} [{N 2 / (2N + 1) R 3 / R 1 V T log (N) + V BE}]
... (5)

  Therefore, even with this reference voltage generation circuit 1 ′, a highly accurate reference voltage can be generated as with the reference voltage generation circuit 1.

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

It is a block diagram of the reference voltage generation circuit which concerns on one Embodiment of this invention. It is a block diagram of the reference voltage generation circuit which concerns on one Embodiment of this invention. It is a block diagram of another reference voltage generation circuit according to an embodiment of the present invention. It is a figure which shows the structure of the conventional reference voltage generation circuit.

Explanation of symbols

1, 1 ′ reference voltage generation circuit M ₁ first PMOS transistor M ₂ second PMOS transistor M ₃ third PMOS transistor Da first diode (first PN junction)
Db second diode (second PN junction)
R ₁ first resistor element R ₂ second resistor elements R _3A , R _3B third resistor element A 1 differential amplifier circuit

Claims (5)

A first PMOS transistor and a first PN junction connected in series between a power supply node and a ground node;
A second PMOS transistor, a first resistance element and a second PN junction connected in series between the power supply node and the ground node;
A third PMOS transistor and a second resistance element connected in series between the power supply node and the ground node;
The first voltage depending on the characteristics of the first PN junction and the second voltage depending on the characteristics of the second PN junction are input, and according to the difference between the first voltage and the second voltage. A differential amplifier circuit for supplying the output voltage to the gates of the first, second and third PMOS transistors,
A third resistance element connected between the drain of the first PMOS transistor and an output node between the third PMOS transistor and the second resistance element;
A reference voltage generation circuit comprising a fourth resistance element connected between the drain of the second PMOS transistor and the output node.   The first voltage is a voltage generated at a connection point between the first PMOS transistor and the first PN junction, and the second voltage is the second PMOS transistor and the first resistor. 2. The reference voltage generation circuit according to claim 1, wherein the reference voltage generation circuit is a voltage generated at a connection point with the element.   The reference voltage generation circuit according to claim 1, wherein the second PN junction includes a plurality of PN junctions connected in parallel. The second PMOS transistor is composed of a plurality of PMOS transistors connected in parallel,
The resistance value of the fourth resistance element is set to N times the resistance value of the third resistance element,
The reference voltage generation circuit according to claim 1, wherein the first PN junction is formed in the same size as the first PN junction. A reference voltage generation circuit for generating a predetermined reference voltage is provided inside,
The reference voltage generation circuit includes:
A first PMOS transistor and a first PN junction connected in series between a power supply node and a ground node;
A second PMOS transistor, a first resistance element and a second PN junction connected in series between the power supply node and the ground node;
A third PMOS transistor and a second resistance element connected in series between the power supply node and the ground node;
The first voltage depending on the characteristics of the first PN junction and the second voltage depending on the characteristics of the second PN junction are input, and according to the difference between the first voltage and the second voltage. A differential amplifier circuit for supplying the output voltage to the gates of the first, second and third PMOS transistors,
A third resistance element connected between the drain of the first PMOS transistor and an output node between the third PMOS transistor and the second resistance element;
A semiconductor element comprising a fourth resistance element connected between the drain of the second PMOS transistor and the output node.

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