JP2010039400A - Display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make an amplitude of a driving clock large, without increasing load of a transistor, in a display including a single channel shift register. <P>SOLUTION: The display includes a display panel including a plurality of pixels and a driving circuit for driving each pixel, wherein the driving clock which changes between voltage levels of a voltage level VH and a voltage level VL is input to the driving circuit, and the driving circuit takes the clock when it is in an ON state, and outputs it from an output terminal. The display includes: a transistor in which the driving clock is input to a first electrode; a first protection transistor which is connected between a second electrode and a terminal of the transistor, and in which a control electrode is connected to the control electrode of the transistor; a second protection transistor in which the driving clock is input to the second electrode, and a voltage VDD is input to the control electrode; and a third protection transistor of diode connection, which is connected between the first electrode of the second protection transistor, and the second electrode of the transistor, and VL<VDD<VH is satisfied. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a display device, and more particularly to a technique effective when applied to a display device having a shift register.

For example, an active matrix type liquid crystal display device using a thin film transistor (TFT) as an active element extends in the x direction on the liquid crystal side surface of one of the substrates opposed to each other through the liquid crystal. And a pixel region surrounded by scanning lines arranged in parallel in the y direction and video lines extending in the y direction and arranged in parallel in the x direction. The pixel region includes a thin film transistor (TFT) that operates by supplying a scanning signal from a scanning line.
The liquid crystal display device has a scanning line driving circuit that supplies a scanning signal to each of the scanning lines, and a video line driving circuit that supplies a video signal to each of the video lines, and at least one of these driving circuits is shifted It has a register.
On the other hand, a polysilicon type liquid crystal display device is also known in which the semiconductor layer of the thin film transistor constituting the active element is formed of polycrystalline silicon (polysilicon). In such a polysilicon type liquid crystal display device, the thin film transistor (for example, MIS transistor) constituting the scanning line driving circuit and the video line driving circuit is also the same as the thin film transistor constituting the active element in the same process. Formed on the surface.
As this scanning line driving circuit, a liquid crystal display device including a single channel (n-MOS) shift register is described in, for example, Patent Document 1 and Patent Document 2 below.

In the single channel shift register described in Patent Document 1, the gate of the transistor that connects the floating node of the non-selected stage to the bias power supply (Vss) is a floating memory node in order to maintain stable operation. Yes.
The writing to the floating memory node is configured to perform writing (refresh) once per scan, reflecting the scanning state of each stage. Therefore, the leakage current of the floating memory node affects the operation stability. In particular, when the threshold voltage Vth of the resetting transistor of the floating memory node is low, the leakage current of the resetting transistor increases, so that stable operation is achieved. As a result, the likelihood of the threshold may be reduced.
Accordingly, the present applicant has developed a liquid crystal display device having a single channel (n-MOS) shift register in which the number of times of writing to the floating memory node is increased to improve the time likelihood with respect to the leakage current of the floating memory node. Have already been filed. (See Patent Document 3 below)

As prior art documents related to the invention of the present application, there are the following.
JP 2002-215118 A JP 2006-10784 A Japanese Patent Application No. 2008-53314

In a liquid crystal display device, it is possible to improve image quality by adopting a dot inversion driving method as an AC driving method.
In the dot inversion driving method, it is necessary to increase the amplitude of the scanning voltage, but in order to increase the amplitude of the scanning voltage, it is necessary to increase the amplitude of the driving clock input to the shift register that outputs the scanning voltage to the scanning line. There is.
However, when the amplitude of the drive clock is increased, the drain-source voltage (Vds) of the transistors constituting the shift register is increased, the load on the transistors is increased, the dielectric film that forms the capacitance is destroyed, or the circuit Reliability degradation becomes a problem.
The present invention has been made to solve the above-described problems of the prior art, and an object of the present invention is to increase the amplitude of the drive clock without increasing the transistor load in a display device having a single channel shift register. It is to provide a technique that can increase the size of the image.

Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
(1) A display panel having a plurality of pixels (for example, a liquid crystal display panel) and a drive circuit for driving each pixel are provided. The drive circuit has a voltage level of VH and a voltage level of VL. A drive clock that changes between the first and second electrodes, and the drive circuit captures the clock when in an on state and outputs the clock from an output terminal, wherein the drive clock is input to a first electrode; A first protection transistor connected between the second electrode and the terminal of the transistor, a control electrode connected to the control electrode of the transistor, and the drive clock input to a second electrode; A die connected between a second protection transistor to which a voltage of VDD is input, a first electrode of the second protection transistor, and the second electrode of the transistor And a third protection transistor over de connection satisfies VL <VDD <VH.

(2) A display panel having a plurality of pixels (for example, a liquid crystal display panel) and a drive circuit for driving the pixels are provided. The drive circuit includes a shift register, and the shift register includes VH A first drive clock that changes between a voltage level and a voltage level of VL, and a second drive clock that has a phase different from that of the first drive clock and changes between a voltage level of VH and a voltage level of VL. The shift register is configured by a plurality of basic circuits, and each basic circuit captures and outputs the first drive clock or the second drive clock when transfer data from the previous stage is input. A display device that outputs as a shift output of its own stage from a terminal and transfers it as transfer data to a basic circuit of the next stage, wherein each basic circuit is connected to a control electrode from the previous stage. A first transistor to which transfer data is input; a first protection transistor connected between a second electrode of the first transistor and the output terminal; and a control electrode connected to a control electrode of the first transistor; A diode-connected third protection transistor connected between a second protection transistor having a VDD voltage input to the control electrode, a first electrode of the second protection transistor, and the second electrode of the first transistor In the odd-numbered basic circuit, the first drive clock is input to the first electrode of the first transistor and the second electrode of the second protection transistor. The second driving clock is input to the first electrode of the first transistor and the second electrode of the second protection transistor, and VL <VDD < To satisfy the H.

In the present invention, each of the basic circuits includes a diode-connected second transistor to which transfer data from the previous stage is input, and a first capacitor connected between the control electrode of the first transistor and the output terminal. A third transistor connected between the element, the first electrode of the second transistor and the control electrode of the first transistor, and a voltage of VDD is input to the control electrode; and a diode connection of the output terminal and the next stage A fourth protection transistor connected between the second transistor and the second transistor.
In the present invention, each of the basic circuits includes a first reset transistor connected between the output terminal and a reference voltage, a series circuit of a fifth protection transistor, and a first of the diode-connected second transistor. A second reset transistor connected between the electrode and the reference voltage, and the second drive clock is input to the control electrode of the first reset transistor of the odd-numbered basic circuit, The first drive clock is input to the control electrode of the first reset transistor of the basic circuit, the voltage of VDD is input to the control electrode of the fifth protection transistor, and the control electrode of the second reset transistor is input to the control electrode of the second reset transistor. The reset signal of the previous stage is input.

In the present invention, each of the basic circuits includes a diode-connected fourth transistor, the fifth transistor, a second capacitor connected between the second electrode and the control electrode of the fifth transistor, A third reset transistor connected between a first electrode of the fifth transistor and a reference voltage, a control electrode connected to the first electrode of the second transistor; a second electrode of the fifth transistor; A sixth protection transistor connected between the first electrode of the fourth diode-connected transistor and a voltage of VDD being input to the control electrode; a first electrode connected to the control electrode of the fifth transistor; A seventh protection transistor to which a voltage of VDD is input to the output terminal, a fourth reset transistor connected between the output terminal and a reference voltage, and a direct connection of the eighth protection transistor. A voltage of VDD is input to a control electrode of the eighth protection transistor, and a voltage of the first electrode of the fifth transistor is set as a reset signal to the control electrode of the fourth reset transistor, The second drive clock is input to the control electrode and the second electrode of the fourth transistor in the odd-numbered basic circuit, and the second drive clock is input to the control electrode of the second reset transistor of the next basic circuit. The first drive clock is input to the second electrode of the seventh protection transistor, and the first drive clock is input to the control electrode and the second electrode of the fourth transistor in the even-numbered basic circuit. The second drive clock is input to the second electrode of the seventh protection transistor.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
According to the present invention, in a display device having a single channel shift register, it is possible to increase the amplitude of a drive clock without increasing the load of a transistor.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
In all the drawings for explaining the embodiments, parts having the same functions are given the same reference numerals, and repeated explanation thereof is omitted.
[Example]
FIG. 1 is a circuit diagram showing an equivalent circuit of a liquid crystal display panel of an active matrix liquid crystal display device according to Embodiment 1 of the present invention.
As shown in FIG. 1, the liquid crystal display panel of this embodiment has an n-type parallel arrangement in the y direction on the liquid crystal side surface of one of a pair of substrates that are arranged to face each other via a liquid crystal. X scanning lines (also referred to as gate lines) (X1, X2,..., Xn) and m video lines (also referred to as source lines or drain lines) extending in the y direction in parallel with the x direction (Y1, Y2,..., Ym).
A region surrounded by the scanning line and the video line is a pixel region. In one pixel region, a gate is a scanning line, a drain (or source) is a video line, and a source (or drain) is a pixel. An active element (thin film transistor) (Tnm) connected to the electrode is provided.
In addition, a storage capacitor (Cnm) is provided between the pixel electrode and the counter electrode (also referred to as a common electrode) (CT). Since liquid crystal is interposed between the pixel electrode and the counter electrode (CT), a liquid crystal capacitor (Clc) is also formed between the pixel electrode and the counter electrode (CT).
Each scanning line (X1, X2,..., Xn) is connected to a scanning line driving circuit (XDV), and the scanning line driving circuit (XDV) sends a selection scanning signal from the X1 to the Xn scanning line. Alternatively, they are sequentially supplied from Xn to the scanning line X1.
Each video line (Y1, Y2,..., Ym) is connected to a video line drive circuit (YDV) via an RGB switch circuit (S-RGB). The video line driving circuit (YDV) outputs R, G, and B gradation voltages within one horizontal scanning period, and the RGB switch circuit (S-RGB) is output from the video line driving circuit (YDV). The R, G, and B gradation voltages are output to the R, G, and B video lines, respectively.

The liquid crystal display panel of this embodiment includes a first substrate (also referred to as a TFT substrate or an active matrix substrate) (not shown) provided with pixel electrodes, thin film transistors, and the like, and a second substrate on which color filters and the like are formed. (Also referred to as a counter substrate) (not shown) are overlapped with a predetermined gap therebetween, and both substrates are bonded together by a seal material provided in a frame shape in the vicinity of the peripheral edge between the two substrates. A liquid crystal is sealed and sealed inside a sealing material between both substrates from a liquid crystal sealing port provided in a part of the substrate, and a polarizing plate is attached to the outside of both substrates.
Thus, the liquid crystal display panel of this embodiment has a structure in which liquid crystal is sandwiched between a pair of substrates. The counter electrode is provided on the second substrate (counter substrate) side in the case of a TN liquid crystal display panel or a VA liquid crystal display panel. In the case of the IPS system, it is provided on the first substrate (TFT substrate) side. In the present invention, since it is not related to the internal structure of the liquid crystal panel, a detailed description of the internal structure of the liquid crystal panel is omitted. Furthermore, the present invention can be applied to a liquid crystal panel having any structure.
In this embodiment, each transistor of the scanning line driving circuit (XDV) and the video line driving circuit (YDV) is formed in the same process as a thin film transistor that forms an active element, with a semiconductor layer formed of polycrystalline silicon (polysilicon). , Formed on one substrate surface.

[Conventional shift register circuit configuration]
The scan line driver circuit (XDV) illustrated in FIG. 1 includes a shift register.
FIG. 2 is a circuit diagram showing a circuit configuration of a conventional single channel (n-MOS) shift register.
The shift register shown in FIG. 2 includes a plurality of basic circuits. In FIG. 2, the basic circuit is indicated by a dotted line rectangle.
Each basic circuit includes an n-type field effect transistor (n-type MOS transistor; hereinafter, simply referred to as a transistor) whose semiconductor layer is made of polysilicon formed on a first substrate.
Each basic circuit includes a transistor (first transistor of the present application) (T3 *) (where * = 1, 2, 3, 4,...) And a gate and a drain of the transistor (T3 *). Capacitance element (bootstrap capacitance) (C1 *) to be connected, diode-connected transistor (second transistor of the present application) (T1 *) to which the previous shift output is input, source and transistor of transistor (T1 *) A transistor (third transistor of the present application) (T2 *) which is connected between the gate of (T3 *) and to which the voltage of Vdd is input to the gate.
Further, a diode-connected transistor (fourth transistor of the present application) (T5 *), a transistor having a drain connected to the source of the transistor (T5 *) (the fifth transistor of the present application) (T6 *), and a transistor (T6 *) *) And a capacitive element (bootstrap capacitor) (C2 *) connected between the gate and drain.
Further, a transistor (first reset transistor of the present application) (T8 *) and a transistor (fourth reset transistor of the present application) (T4 *) connected between the drain of the transistor (T3 *) and the reference voltage (VSS) The transistor (second reset transistor of the present application) (T9 *) connected between the source of the transistor (T1 *) and the reference voltage (VSS), the source of the transistor (T6 *), and the reference voltage (VSS) (A third reset transistor of the present application) (T7 *) connected between the two transistors. In the first-stage basic circuit, the transistor (T2) and the transistor (T9) are omitted. In addition, a start pulse (ΦIN) is input to the transistor (T1) of the first-stage basic circuit.

In the shift register shown in FIG. 2, a shift output (selected scanning voltage) G (*) is output from the drain of the transistor (T3 *).
In the odd-numbered basic circuit, the first drive clock (CK1) is input to the source of the transistor (T3 *) and the gate of the transistor (T6 *). The second driving clock (CK2) is input to the drain and gate of the transistor (T5 *) and the gate of the transistor (T8 *). Here, the first drive clock (CK1) and the second drive clock (CK2) are clocks having a phase difference of 180 °.
In the even-numbered basic circuit, the second drive clock (CK2) is input to the source of the transistor (T3 *) and the gate of the transistor (T6 *). The first driving clock (CK1) is input to the drain and gate of the transistor (T5 *) and the gate of the transistor (T8 *).
In each basic circuit, the gate of the transistor (T7 *) is connected to the source of the transistor (T1 *), and the gate of the transistor (T4 *) is connected to the source of the transistor (T6 *). The gate of the transistor (T9 *) is connected to the source of the transistor (T6 *) of the previous basic circuit.
A start pulse (ΦIN) is input to the gate of the transistor (T31) and the gate of the transistor (T71) of the first basic circuit through the transistor (T11). Here, the second drive clock (CK2) is input to the gate of the transistor (T11).

FIG. 3 is a timing chart showing voltage changes at each node shown in FIG.
Hereinafter, an operation of the shift register illustrated in FIG. 2 will be described.
(1) Since the transistor (T11) is turned on when the second drive clock (CK2) becomes H level during the period t4 while the start pulse (ΦIN) is at High level (hereinafter referred to as H level), the node (N11) becomes H level. Accordingly, the transistor (T71) is turned on, and the node (N21) becomes the reference voltage (VSS).
(2) Next, in the period t5, when the second drive clock (CK2) becomes the L level and the first drive clock (CK1) becomes the H level, the node (N31) becomes the H level through the transistor (T31), Thereby, the voltage of the node (N11) is further boosted by the bootstrap effect by the capacitive element (C11).
At this time, by setting the bootstrap capacitor (C1 *) so that the H level of the node (N3 *) is equal to the H level of the first and second drive clocks (CK1, CK2), the node (N31) Outputs a first drive clock having no voltage drop, which becomes a shift output G (1).
Further, since the transistor (T12) is turned on, the node (N72) is also at the H level (strictly speaking, VH−Vth). Accordingly, the transistor (T72) is turned on, and the node (N22) becomes the reference voltage (VSS). Here, VH is an H level voltage of the first drive clock (CK1) and the second drive clock (CK2), and Vth is a threshold voltage of the transistor (T1 *).
In this period, the transistor (T61) is also turned on, but the on state of the transistor (T71) is strengthened (becomes low resistance) by boosting the node (N11), so that the node (N21) has the reference voltage ( VSS).

(3) Next, in the period t6, when the first drive clock (CK1) becomes L level and the second drive clock (CK2) becomes H level, the node (N32) becomes H level through the transistor (T32), Thereby, the voltage of the node (N12) is further boosted by the bootstrap effect by the capacitive element (C12). As a result, the second drive clock having no voltage drop is output to the node (N32), which becomes the shift output G (2).
Further, since the transistor (T13) is turned on, the node (N73) is also at the H level (strictly speaking, VH−Vth). Accordingly, the transistor (T73) is turned on and the node (N23) becomes the reference voltage (VSS). At the same time, the transistor (T81) to which the first drive clock (CK1) is input is turned on, and the node (N31) becomes the reference voltage (VSS).
During this period, the transistor (T62) is also turned on, but the on-state of the transistor (T72) is strengthened (becomes low resistance) by boosting the node (N12), so that the node (N22) has the reference voltage ( VSS).
Further, since the node (N11) is at an L level, the transistor (T71) is turned off and the node (N21) is in a floating state. Further, the node (N61) is at the H level via the transistor (T51).

(4) Next, in the period t7, when the second drive clock (CK2) becomes the L level and the first drive clock (CK1) becomes the H level, the node (N33) becomes the H level through the transistor (T33), Thereby, the voltage of the node (N13) is further boosted by the bootstrap effect by the capacitive element (C13). As a result, the first drive clock having no voltage drop is output to the node (N33), which becomes the shift output G (3).
Further, since the transistor (T14) is turned on, the node (N74) is also at the H level (strictly speaking, VH−Vth). Accordingly, the transistor (T74) is turned on, and the node (N24) becomes the reference voltage (VSS). At the same time, the transistor (T82) to which the first driving clock (CK1) is input is turned on, and the node (N32) becomes the reference voltage (VSS).
During this period, the transistor (T63) is also turned on, but the on state of the transistor (T73) is strengthened (becomes low resistance) by boosting the node (N13), so that the node (N23) has the reference voltage ( VSS).
In addition, when the first driving clock (CK1) is at the H level, the potential of the node (N61) is boosted and the transistor (T61) is turned on by the bootstrap effect of the capacitor (C21). Accordingly, the node (N21) and the node (N61) are connected, and the charge charged in the capacitor (C2 *) moves to the node (N21). The voltage of the node (N21) at this time depends on the parasitic capacitance ratio between the node (N21) and the node (N61). That is, the capacitor (C2 *), the transistor (T5 *), the transistor (T6 *), the transistor (T), and the transistor (T4 *) and the transistor (T9 *) are turned on with a desired on-resistance. It is possible to set constants for T4 *), transistor (T9 *), and transistor (T7 *).

The voltage of the node (N21) turns on the transistor (T41) and the transistor (T92), whereby the node (N31) and the node (N72) become the reference voltage (VSS).
Thereafter, if the voltage of the node (N21) does not decrease, the node (N31) and the node (N72) are connected to the reference voltage (VSS) until the node (N31) changes from the L level to the H level again. In this first stage, since there are no floating nodes, the operation is stable regardless of disturbance.
Further, since the node (N72) is at an L level, the transistor (T72) is turned off and the node (N22) is in a floating state. Further, the node (N62) is at the H level via the transistor (T52).
Thereafter, similar operations are repeated, but the operation of the node (N3 *) and the node (N7 *) will be further described.

(5) Next, in the period t8, when the first drive clock (CK1) is at the L level and the second drive clock (CK2) is at the H level, the transistor (T51) is turned on again, and the node (N61) , H level (strictly, VH−Vth).
(6) Next, in the period t9, when the second drive clock (CK2) becomes the L level and the first drive clock (CK1) becomes the H level, the bootstrap effect by the capacitor (C21) causes the node (N61) The potential is boosted and the transistor (T61) is turned on. Accordingly, the node (N61) and the node (N21) are connected, and the charge charged in the capacitor (C21) moves to the node (N21).
Since this operation is repeated, the node (N21) gradually approaches the voltage of (VH−Vth). Therefore, the on state of the transistor (T41) and the transistor (T92) is maintained, and the voltage of the node (N31) and the node (N72) becomes the reference voltage (VSS).
Further, in this period, the transistor (T52) is turned on again, and the node (N62) is again at the H level (strictly, VH−Vth).
(7) Next, in the period t10, when the first drive clock (CK1) is at the L level and the second drive clock (CK2) is at the H level, the bootstrap effect by the capacitor (C22) causes the node (N62) The potential is boosted and the transistor (T62) is turned on. Accordingly, the node (N62) and the node (N22) are connected, and the charge charged in the capacitor (C22) moves to the node (N22).
Since this operation is repeated, the node (N22) gradually approaches the voltage of (VH−Vth). Accordingly, the on state of the transistor (T42) and the transistor (T93) is maintained, and the voltage of the node (N32) and the node (N73) becomes the reference voltage (VSS).

As described above, in the shift resist circuit shown in FIG. 2, the transistors (T4 *) for connecting the inactive stage floating nodes (N3 *, N7 *) to the reference voltage (VSS) for stable operation. , T9 *), the node (N2 *) connected to the gate is reinforced by the bootstrap effect in accordance with one of the periods of the first and second drive clocks (CK1, CK2).
Therefore, in the shift resist circuit shown in FIG. 2, the stable operation with respect to the leakage current of the reset transistor (T7 *) is much more robust than writing to the memory node (N2 *) once in one cycle. Become.
In the circuit shown in FIG. 2, the gate of the transistor (third transistor of the present application) (T2 *) inserted between the source of the transistor (T1 *) of each basic circuit and the gate of the transistor (T3 *). Is supplied with a fixed bias voltage (Vdd) of H level.
The role of the transistor (T2 *) is the bootstrap effect, which prevents the voltage of the node (N7 *) from being boosted to approximately (VDD−Vth) or higher even when the voltage of the node (N1 *) rises. As a result, an increase in drain voltage when the transistor (T9 *) is turned off is suppressed, and the likelihood of unstable operation due to a leakage current due to the source-drain breakdown voltage (Bvds) is improved.

[Circuit Configuration of Shift Register of This Example]
As described above, in the liquid crystal display device, it is possible to improve the image quality by adopting the dot inversion driving method as the AC driving method.
On the other hand, in the dot inversion driving method, it is necessary to increase the amplitude of the scanning voltage. In order to increase the amplitude of the scanning voltage, the driving clocks (CK1, CK2) input to the shift register that outputs the scanning voltage to the scanning line. It is necessary to increase the amplitude of.
However, when the amplitude of the drive clocks (CK1, CK2) is increased, the drain-source voltage (Vds) of the transistors constituting the shift register increases, which causes destruction of the insulating film forming the capacitor and lowering of circuit reliability. It becomes a problem. Therefore, in this embodiment, a protection circuit for high voltage driving is added to the shift register.
FIG. 4 is a circuit diagram showing a circuit configuration of the shift register of the present embodiment. The shift register of this embodiment is also configured by connecting the basic circuits surrounded by the dotted frame in multiple stages. FIG. 4 shows the (n−1) th and Nth basic circuits.
In FIG. 4, the transistors added in this embodiment to the circuit shown in FIG. In the present embodiment, basically, a transistor (protection transistor of the present invention; T10 * to T17 *) in which the voltage of Vdd is input to the gate is arranged at each input node, thereby limiting the input voltage and the circuit. Is driving.
For example, in the transistor (T13 *) (the fourth protection transistor of the present invention), when the shift output G (n−1) is output, the voltage of the drain and gate of the transistor (T1n) is (Vdd−Vth). The voltage is limited to
Further, the transistor (T15 *) (the sixth protection transistor of the present invention) and the transistor (T16 *) (the seventh protection transistor of the present invention) include the first drive clock (CK1) or the second drive clock (CK2). When H is at the H level, the drain and gate voltages of the transistor (T6n) are limited to a voltage of (Vdd−Vth).
Further, the transistor (T14 *) (the fifth protection transistor of the present invention) and the transistor (T17 *) (the eighth protection transistor of the present invention) are turned off when the shift output G (n-1) is output. The drain voltage of the transistor (T4n) and the transistor (T8n) is limited to a voltage of (Vdd−Vth).
Other operations are the same as those in FIG.

However, since it is necessary to directly input the high-voltage drive clocks (CK1, CK2) to the transistor (T3 *) that outputs the high-voltage scan voltage, the output buffer protection circuit (S-COM) indicated by the thick dotted line Has been added.
The output buffer protection circuit (S-COM) will be described below.
N4 * is a node between the transistor (T3 *) and the transistor (T10 *) (the first protection transistor of the present invention). The transistor (T3 *) and the transistor (T10 *) are both output transistors.
A series circuit of a transistor (T11n) and a transistor (T12n) is connected to the node (N4n), and the second drive clock (CK2) is input to the drain of the transistor (T11n).
The transistor (T11 *) (second protection transistor of the present invention) is a voltage limiting transistor, and the transistor (T12 *) (third protection transistor of the present invention) is a diode-connected transistor. With this configuration, when the node (N1 *) is at the L level, the voltage of (Vdd−2Vth) having the same phase as that of the second drive clock (CK2) is applied to the node (N4 *).

That is, since the voltage of the second drive clock (CK2) is limited by the transistor (T11 *), the voltage of the node (N5 *) becomes (Vdd−Vth), and further passes through the transistor (T12 *). Thus, the voltage of (Vdd−2Vth) becomes the input voltage to the node (N4 *).
FIG. 5 is a diagram in which the portion of the output buffer protection circuit shown in FIG. 4 is extracted. FIG. 6 is a diagram for explaining the voltages of the respective parts when the node (N1n) is at the L level in FIG. is there.
As shown in FIG. 6, when the node (N1n) is at the L level, the voltage at the node (N3n) becomes GND. At this time, when the second drive clock (CK2) is at the H level voltage VHH, N4 *) is a voltage of (Vdd-Vth).
As described above, when the node (N1n) is at the L level, the voltage applied to both ends of the transistor (T3n) is reduced in a stepwise manner from the H level of the second drive clock (CK2) to the GND voltage. {VHH− (Vdd−Vth)}, the voltage applied to both ends of the transistor (T10n) is (Vdd−Vth), and the drain-source voltage (Vds) of the transistor (T3n, T10n) can be reduced. .
Further, it can be seen from FIG. 6 that the shift output G (n) can be output up to twice the upper limit of the drain-source voltage (Vds) of the transistor (T3n).

FIG. 7 is a timing chart showing voltage changes at each node shown in FIG.
Hereinafter, an operation of the output buffer protection circuit (S-COM) will be described.
(1) In the period t1, when the second drive clock (CK2) becomes L level, the first drive clock (CK1) becomes H level, and the previous shift output G (n−1) is output, the node (N1n ) Becomes H level, and the capacitor (C1n) is charged.
(2) In the period t2, when the first drive clock (CK1) becomes L level and the second drive clock (CK2) becomes H level, the voltage of the node (N1n) is further boosted by the bootstrap effect.
Accordingly, the on-resistance of the transistors (T3n, T10n) is decreased, and the node (N4n) and the node (N3n) are at the H level. At the same time, the voltage of (Vdd−Vth) is applied to the node (N5n). However, since the node (N4n) is higher in potential than the node (N5n), the connection is cut off by the transistor (T12n), and the node (N4n) And node (N5n) are prevented from being short-circuited.
(3) In the period t3, when the second drive clock (CK2) becomes L level and the first drive clock (CK1) becomes H level, the node (N4n) also becomes L level. Similarly to the circuit before the addition of the output buffer protection circuit (S-COM), the node (N1n) is fixed to the L level during the non-selection period by the preceding node (N2n-1).
(4) In the period t4, the second drive clock (CK1) is fixed at the L level, the second drive clock (CK2) is fixed at the H level, that is, the node (N1n) is fixed at the L level. When (CK2) becomes H level, a voltage of (Vdd−2Vth) is applied to the node (N4n).
Thereafter, the voltage of (Vdd−2Vth) is applied to the node (N4n) at the same timing as the second driving clock (CK2) until the node (N1n) becomes H level again, and the transistors (T3n, T10n) The drain-source voltage (Vds) can be reduced.

In the above description, the case where the drive clock is a high voltage has been described. However, even when the drive clock is a normal voltage, the output voltage can be set by setting the voltage of Vdd to be lower than the input voltage. Is the same voltage as the input voltage, but the circuit can be driven with an amplitude of Vdd, so that the reliability can be improved.
In the above description, the case where all the transistors are configured by n-type MOS transistors has been described. However, by reversing the power supply voltage and the H level and the L level of the drive clock, all the transistors are made p-type. It is also possible to configure with MOS transistors.
In addition, it is possible to use a MIS transistor instead of a MOS transistor. Further, the above-described shift register can be constituted by a transistor whose semiconductor layer is made of silicon, and can be a circuit in a semiconductor chip. is there.
Further, in the above-described embodiment, the embodiment in which the present invention is applied to the shift register of the liquid crystal display device has been described. However, the present invention is not limited to this, and the present invention can be applied to, for example, an organic EL display device. The present invention can also be applied to a shift register used in other display devices.
As mentioned above, the invention made by the present inventor has been specifically described based on the above embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Of course.

It is a circuit diagram which shows the equivalent circuit of the liquid crystal display panel of the active matrix type liquid crystal display device of the Example of this invention. It is a circuit diagram which shows the circuit structure of the conventional single channel shift register. FIG. 3 is a timing chart showing voltage changes at each node shown in FIG. 2. FIG. It is a circuit diagram which shows the circuit structure of the single channel shift register of the Example of this invention. FIG. 5 is a diagram in which a portion of the output buffer protection circuit shown in FIG. 4 is extracted. In FIG. 5, when the node (N1n) is L level, it is a figure for demonstrating the voltage of each part. 5 is a timing chart showing voltage changes at each node shown in FIG. 4.

Explanation of symbols

X1, X2, ..., Xn Scan lines (gate lines)
Y1, Y2, .., Ym Video line (source line or drain line)
XDV scanning line drive circuit YDV video line drive circuit Tnm active element (thin film transistor)
Cnm Retention capacitance Clc Liquid crystal capacitance CT Counter electrode (common electrode)
S-COM output buffer protection circuit CK1, CK2 drive clock ΦIN start pulse T1 * to T17 * n-type MOS transistor C1 *, C2 * capacitive element N1 * to N7 * node

Claims (10)

A display panel having a plurality of pixels;
A drive circuit for driving each pixel;
The drive circuit receives a drive clock whose voltage level changes between a voltage level of VH and a voltage level of VL,
The drive circuit is a display device that takes in the clock when it is in an on state and outputs it from an output terminal,
A transistor in which the drive clock is input to the first electrode;
A first protection transistor connected between the second electrode of the transistor and the terminal, the control electrode being connected to the control electrode of the transistor;
A second protection transistor in which the drive clock is input to the second electrode and a voltage of VDD is input to the control electrode;
A diode-connected third protection transistor connected between the first electrode of the second protection transistor and the second electrode of the transistor;
A display device satisfying VL <VDD <VH. A display panel having a plurality of pixels;
A drive circuit for driving each of the pixels,
The drive circuit has a shift register;
The shift register includes a first drive clock that changes between a voltage level of VH and a voltage level of VL, and the phase of the first drive clock is different between the voltage level of VH and the voltage level of VL. And a second driving clock that changes,
The shift register includes a plurality of basic circuits,
Each of the basic circuits takes in the first drive clock or the second drive clock when transfer data from the previous stage is input, and outputs it as a shift output of its own stage from an output terminal, and also transfers the next stage as transfer data. A display device for transferring to the basic circuit of
Each of the basic circuits includes a first transistor in which transfer data from the previous stage is input to the control electrode;
A first protection transistor connected between the second electrode of the first transistor and the output terminal, the control electrode being connected to the control electrode of the first transistor;
A second protection transistor in which a voltage of VDD is input to the control electrode;
A diode-connected third protection transistor connected between the first electrode of the second protection transistor and the second electrode of the first transistor;
In the odd-numbered basic circuit, the first drive clock is input to the first electrode of the first transistor and the second electrode of the second protection transistor,
In the even-numbered basic circuit, the second drive clock is input to the first electrode of the first transistor and the second electrode of the second protection transistor,
A display device satisfying VL <VDD <VH. Each of the basic circuits includes a diode-connected second transistor to which transfer data from the previous stage is input;
A first capacitive element connected between a control electrode of the first transistor and the output terminal;
A third transistor connected between a first electrode of the second transistor and a control electrode of the first transistor, and a voltage of VDD is input to the control electrode;
The display device according to claim 2, further comprising a fourth protection transistor connected between the output terminal and a second diode-connected second transistor. Each basic circuit includes a first reset transistor connected between the output terminal and a reference voltage, and a series circuit of a fifth protection transistor,
The second drive clock is input to the control electrode of the first reset transistor of the odd-numbered basic circuit,
The first drive clock is input to the control electrode of the first reset transistor of the even-numbered basic circuit,
The display device according to claim 3, wherein a voltage of VDD is input to a control electrode of the fifth protection transistor. Each of the basic circuits includes a second reset transistor connected between the first electrode of the diode-connected second transistor and the reference voltage;
The display device according to claim 4, wherein a reset signal of a previous stage is input to the control electrode of the second reset transistor. Each of the basic circuits includes a diode-connected fourth transistor;
The fifth transistor;
A second capacitor connected between the second electrode and the control electrode of the fifth transistor;
A third reset transistor connected between the first electrode of the fifth transistor and a reference voltage, and a control electrode connected to the first electrode of the second transistor;
A sixth protection transistor connected between the second electrode of the fifth transistor and the first electrode of the diode-connected fourth transistor, and the voltage of VDD being input to the control electrode;
A seventh protection transistor having a first electrode connected to a control electrode of the fifth transistor and a voltage of VDD input to the control electrode;
A fourth reset transistor connected between the output terminal and a reference voltage; and a series circuit of an eighth protection transistor;
A VDD voltage is input to the control electrode of the eighth protection transistor,
The voltage of the first electrode of the fifth transistor is input as a reset signal to the control electrode of the fourth reset transistor and to the control electrode of the second reset transistor of the next basic circuit,
In the odd-numbered basic circuit, the second drive clock is input to the control electrode and the second electrode of the fourth transistor,
The first drive clock is input to the second electrode of the seventh protection transistor,
In the even-numbered basic circuit, the first drive clock is input to the control electrode and the second electrode of the fourth transistor,
The display device according to claim 5, wherein the second drive clock is input to the second electrode of the seventh protection transistor.   The display device according to claim 6, wherein each of the transistors is an n-type field effect transistor.   The display device according to claim 6, wherein each of the transistors is a p-type field effect transistor.   9. The display device according to claim 7, wherein each of the transistors is formed of polysilicon having a semiconductor layer formed on a substrate.   The display device according to claim 9, wherein the display device is a liquid crystal display device.

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