JP2010034124A - Solar battery apparatus and production process therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To adopt a configuration which leads sunlight to a depletion layer or an intrinsic layer with no electrode layer interposed therebetween, and to attain the configuration by using a cheap glass substrate. <P>SOLUTION: An intrinsic semiconductor layer is formed on a transparent amorphous substrate, and materials having different work functions are bonded to the surface of the semiconductor layer. The different materials are impurity diffusion layers of p-type conductivity and n-type conductivity which are formed contiguously to each other or separately from each other. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  In the present invention, a material having a different work function, for example, a p-type or n-type electrode is formed on one surface, and an intrinsic crystal is exposed on the other surface, so that the work function can be achieved without passing sunlight through an electrode layer. The present invention relates to a solar cell device to be introduced into an internal electric field layer generated by the difference between the two and a manufacturing method thereof.

  Conventionally, a solar cell using a silicon pn junction which is a junction of materials having different work functions has been generally used. The open-circuit voltage that can be generated in a solar cell having such a structure is a Fermi level energy difference, that is, a potential difference corresponding to a work function difference that electrons receive.

  In this type of solar cell, a thin (thickness of 1 μm or less) n-type diffusion layer is formed on the surface of a p-type silicon substrate having a thickness of 200 to 400 μm, and this is used as a surface electrode. In such solar cells, the silicon substrate absorbs sunlight and generates charges of electrons and holes, but those that diffuse and reach the electrodes contribute to power generation, so whether it can be converted into electrical energy Depends on the location of solar absorption and charge generation.

  FIG. 17 is a schematic cross-sectional view of a typical conventional silicon pn junction solar cell. Here, the transparent electrode on the front surface and the metal electrode on the back surface are not shown. As shown in FIG. 17, an n-type layer 11 is formed on the surface of the p-type layer 12, a depletion layer 13 is formed at the interface between the n-type layer 11 and the p-type layer 12, and an internal electric field is generated in the depletion layer 13. . Sunlight is introduced from the surface of the n-type layer 11.

  Sunlight is generally reflected at the interface of materials with different refractive indices depending on the wavelength. The n-type layer 11 contains majority carrier electrons. For this reason, the surface of this layer becomes the reflecting surface 1, and sunlight is reflected. As a result, the intensity of the incoming sunlight 1a is attenuated by the reflecting surface 1. Moreover, the approaching sunlight 1b that has passed through the reflecting surface 1 reaches the reflecting surface 2 while being attenuated. However, since the majority carrier densities of the depletion layer 13 and the n-type layer 11 are different, the refractive indexes are different, causing reflection, and the incoming sunlight 1 b is attenuated by the reflection surface 2.

  Moreover, the approaching sunlight 1c that has passed through the depletion layer 13 reaches the reflection surface 3 that is the interface between the depletion layer 13 and the p-type layer 12, and is reflected and attenuated by the reflection surface 3 due to the difference in refractive index. On the other hand, the approaching sunlight that has passed through the reflecting surface 3 reaches the inside of the p-type layer 12. As described above, since sunlight is reflected at the interface of layers having different refractive indexes with respect to sunlight, the incoming sunlight is attenuated by reflection on the reflection surfaces 1, 2, and 3 and by absorption of transition between silicon bands. Along with this, the p-type layer is reached.

  In order to utilize the reflection due to the difference in refractive index, in conventional solar cells, a long optical path length is secured by reflecting the sunlight by forming irregularities on the substrate or electrodes on the substrate, and improving the photoelectric conversion efficiency (For example, refer to Patent Document 1).

  When the depletion layer 13 absorbs sunlight, electrons and holes are generated. The generated electrons and holes are accelerated by an internal electric field in the depletion layer 13 and reach the n-type layer 11 and the p-type layer 12 to generate a voltage to produce electric energy.

  Furthermore, the holes and electrons generated by absorption of sunlight in the range of the minority carrier (hole) diffusion length Lp of the n-type layer 11 and the minority carrier (electron) diffusion length Ln of the p-type layer 12 are also depleted by diffusion. It reaches the layer 13 and is accelerated and moved by the electric field of the depletion layer 13 to be converted into electric energy.

  In general, since the n-type layer 11 is highly doped, the recombination time of electrons and holes is short, and Lp is small. In addition, there is also optical attenuation, so this layer needs to be designed thin. That is, in order to increase the power generation efficiency, it is desirable to guide sunlight to the depletion layer 13 without passing through the n-type layer 11.

  It has been stated that sunlight that contributes to power generation is sunlight absorbed by the depletion layer 13 and the Ln and Lp regions sandwiching it, but when the semiconductor is a crystal, Ln and Lp have a constant value. Therefore, this region serves as a region that can contribute to power generation. However, if the semiconductor layer is amorphous or a polycrystal having many crystal defects, the minority carrier Ln and Lp become short, and the region that can contribute to power generation becomes narrow.

A structure for solving this is a pin diode junction structure. This cross-sectional structure is shown in FIG. This pin diode junction has a structure in which an intrinsic amorphous layer 14 is sandwiched between an n-type amorphous layer 15 and a p-type amorphous layer 16. The n-type amorphous layer 15 and the p-type amorphous layer 16 serving as electrodes are layers that cannot contribute to power generation because of a short minority carrier lifetime, and are mainly absorbed by the intrinsic amorphous layer 14 having an internal electric field. Contributes to power generation. Therefore, it is desirable to guide sunlight to the intrinsic amorphous layer 14 without passing through the n-type amorphous layer 15 in order to increase the power generation efficiency.
JP 2006-19481 A

  Here, the problems associated with the reflection of sunlight are organized. The reflection of the approaching sunlight 1a generated on the reflection surface 1 is a reflection that depends on the majority carriers of the low-resistance diffusion layer. The reflection also depends on the thickness of the layer. When the wavelength of visible light is 600 to 400 nm, interference occurs when the thickness of the n-type layer 11 is about 1 μm or less. In fact, this interference can be used to measure the layer thickness. Thus, reflection and penetration (transmission) occur depending on the carrier concentration and thickness of the n-type layer 11, but in order to obtain high photoelectric conversion efficiency, high resistance is obtained without passing through this layer. It is necessary to direct sunlight to the depletion layer 13 or the intrinsic amorphous layer 14.

  Incoming sunlight 1b is reflected on the reflecting surface 2 which is the interface between the n-type layer 11 and the depletion layer 13 or on the reflecting surface 2 which is the interface between the n-type layer 11 and the intrinsic amorphous layer 14 which is intrinsically high resistance. Arise. Due to this reflection, the intensity of the incoming sunlight 1b is attenuated.

  In the reflective surface 3 that is an interface between the depletion layer 13 and the p-type layer 12 or the reflective surface 3 that is an interface between the intrinsic amorphous layer 14 and the p-type amorphous layer 16 that is intrinsically high resistance, the incident sunlight 1c Reflection occurs. At this time, since reflected sunlight returns to the depletion layer 13 or the intrinsic amorphous layer 14, the loss of electric energy conversion of the approaching sunlight 1c is reduced. Therefore, in order to reduce the attenuation of sunlight until reaching the depletion layer 13 or the intrinsic amorphous layer 14, it is necessary to direct sunlight directly to the depletion layer 13 or the intrinsic amorphous layer 14 without passing through the electrode layer. It is.

  Accordingly, the present invention has been made in view of the above circumstances, and employs a configuration in which sunlight is guided to a depletion layer or an intrinsic layer without an electrode layer, and a solar cell that realizes this with an inexpensive glass substrate. An object is to provide an apparatus and a method for manufacturing the same.

  The present invention proposes the following items in order to solve the above-described problems.

(1) The present invention proposes a solar cell device in which an intrinsic semiconductor layer is formed on a transparent amorphous substrate and materials having different work functions are joined to the surface of the semiconductor layer.
The “intrinsic (i-type) semiconductor” used in the present invention is used in comparison with a p-type semiconductor and an n-type semiconductor, as used in the expression of an actually manufactured pin diode. Does not mean any p-type or n-type impurity, or does not mean a “intrinsic semiconductor” in the narrow sense of theory that the Fermi level is at the center of the band gap. One of the molds is used to mean a semiconductor material that is not subjected to impurity doping for determining the conductivity type.

  (2) The present invention relates to the solar cell device of (1), wherein the different materials are p-type and n-type conductive diffusion layers in which impurities are diffused, and are formed adjacent to or isolated from each other. Has been proposed.

  (3) The present invention proposes a solar cell device according to (1) or (2), wherein the transparent amorphous substrate is made of glass, resin or plastic.

  (4) In the solar cell device according to (1) to (3), the present invention is characterized in that the transparent amorphous substrate is a substrate in which a transparent thin film different from them is placed on glass, resin or plastic. A solar cell device is proposed.

  (5) The present invention proposes a solar cell device according to (1) to (4), wherein the semiconductor layer is intrinsic silicon.

  (6) The present invention proposes a solar cell device according to (1) to (4), wherein the semiconductor layer contains silicon and carbon.

  (7) The present invention proposes a solar cell device according to (1) to (6), wherein the semiconductor layer has a composition in which an energy band gap increases as it is closer to the substrate. Yes.

  (8) The present invention proposes a solar cell device characterized by introducing sunlight into the intrinsic semiconductor layer from the transparent amorphous substrate side with respect to the solar cell devices of (1) to (7). ing.

  (9) The present invention provides a line shape from a gas injection port placed on the surface of the substrate placed on a support table so that a gas heated to a temperature higher than the support table temperature of the substrate is opposed to the substrate surface. A method for manufacturing a solar cell device is proposed in which the surface is heated by spraying on the surface.

  (10) In the method for manufacturing a solar cell device according to (9), the gas includes any of nitrogen, oxygen, hydrogen, Ar, He, or a mixed gas thereof. The manufacturing method is proposed.

  (11) The present invention relates to the method of manufacturing a solar cell device according to (9) or (10), wherein a gas heated to a temperature higher than the temperature of the substrate is placed on the surface of the substrate placed on the substrate. Proposing a method for manufacturing a solar cell device, characterized in that a semiconductor layer is formed on the substrate by heating the surface by spraying a line from two or more different gas injection ports placed opposite to the surface. ing.

  (12) The present invention relates to the method for manufacturing a solar cell device according to (11), wherein a gas containing silicon, carbon, or both is introduced from a gas injection port sandwiched between different gas injection ports. A method for manufacturing a battery device.

  (13) The present invention relates to the method for manufacturing a solar cell device according to (9) or (10), wherein a gas heated above the temperature of the support base of the substrate is heated from above the substrate placed on the support base. A method of manufacturing a solar cell device is proposed in which an insulating film is grown on a surface by spraying in a line form from two or more different gas injection ports placed facing the substrate.

(14) In the method for manufacturing a solar cell device according to (13), the present invention provides that the gas injected from one of the two or more different gas injection ports is silane (SiH ₄ , Si _2). H ₆ ) or a halogenated silane, and a gas injected from another gas injection port is any of N ₂ O, NO _2, an oxidizing gas containing water, oxygen, and a nitriding gas containing NH ₃ that react with the gas In addition, a method for manufacturing a solar cell device is proposed in which an insulating film is grown on a substrate.

  (15) The present invention provides the method for manufacturing a solar cell device according to (11), wherein an oxide film is formed by introducing an oxidizing gas containing oxygen or water and oxidizing the surface of the semiconductor layer. A method for manufacturing a solar cell device is proposed.

  (16) The present invention relates to a method for manufacturing a solar cell device according to (9) or (10), wherein a gas containing impurities is introduced and the impurities are diffused to form a diffusion layer. A method for manufacturing a device is proposed.

  (17) The present invention proposes a method for manufacturing a solar cell device according to (16), wherein the impurity is an element that makes the semiconductor layer n-type or p-type. Yes.

  (18) In the method of manufacturing a solar cell device according to (9) to (17), the present invention is substantially perpendicular to the surface of the substrate on which the gas injected from the gas injection port is placed on the support base. The manufacturing method of the solar cell device characterized by being sprayed on is proposed.

  According to the present invention, a high-temperature heated gas beam is blown so as to collide with a glass substrate or a plastic substrate almost vertically, so that only the surface of the substrate can be heated to a high temperature, and the inside of the substrate and its back surface are maintained at a constant low temperature. However, it is necessary to heat treat only the surface at a temperature higher than that of the substrate for thermal diffusion of impurities, and to use a manufacturing method for growing a high-temperature thermal CVD material such as a silicon oxide film, a silicon nitride film, or polysilicon. There is an effect that it becomes possible.

  Further, by the above manufacturing method, a solar cell having a lateral pin / i junction structure in which an intrinsic semiconductor layer is grown and an n-type diffusion layer electrode and a p-type diffusion layer electrode are spaced apart from each other on the surface is formed on a glass substrate or There is an effect that it is possible to manufacture on a substrate that needs to be held at a temperature lower than the softening point (300 ° C.).

  Furthermore, since sunlight hits the intrinsic semiconductor layer directly without passing through the electrode layer from the glass substrate, the loss is reduced, and a solar cell with high conversion efficiency can be manufactured. In addition, the intrinsic semiconductor layer can be formed into a step-type junction or a gradient composition of layers having different band gaps, which has an effect of enabling a structure that can widely use the sunlight spectrum.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
Note that the constituent elements in the present embodiment can be appropriately replaced with existing constituent elements and the like, and various variations including combinations with other existing constituent elements are possible. Therefore, the description of the present embodiment does not limit the contents of the invention described in the claims.

<Structure of solar cell device>
As already described with reference to FIGS. 17 and 18, in order to reduce the loss of sunlight, the reflective surface 1, the n-type layer 11, the depletion layer 13, or the intrinsic amorphous layer on the surface of the n-type layer 11 is used. It is necessary to reduce or eliminate the reflective surface 2 at the interface with the surface 14, the reflective surface 3 at the interface between the depletion layer 13 or the intrinsic amorphous layer 14 and the p-type layer 12 or the p-type amorphous layer 16. Hereinafter, both the depletion layer 13 or the intrinsic amorphous layer 14 in which an internal electric field exists may be collectively referred to as an internal electric field region that collects carriers in a diffusion layer.

  Here, FIG. 1 shows a structure of a conventional light receiving element for optical communication having a pin diode structure. In FIG. 1, the intrinsic layer 23 is an internal electric field region. As described above, when sunlight is incident through the electrode and the n-type diffusion layer 21 shown in FIG. 1, the reflection surface on the surface of the n-type diffusion layer 21 and the reflection surface on the interface between the n-type diffusion layer 21 and the intrinsic layer 23. In addition, since sunlight is unattenuated by the reflection surface at the interface between the intrinsic layer 23 and the p-type diffusion layer 22, it is necessary to directly introduce sunlight into the intrinsic layer 23 in order to avoid this.

  One possible method is to introduce sunlight from a direction perpendicular to the paper surface of FIG. 1. In this case, the intrinsic layer 23 has a small cross-sectional area, and the light receiving element for communication achieves its purpose. Even if it is possible, there is a problem that it cannot be applied to solar cells.

  Therefore, the present invention in which this is applied to a solar cell will be described in detail with reference to FIGS.

  First, FIG. 2 shows the intrinsic layer 23 having the pin diode structure shown in FIG. 1 separated in the XX direction. In FIG. 2, the left side is the ni junction 25 of the n-type diffusion layer 21 and the intrinsic layer 23 (i layer), and the right side is the ip junction 26 of the i layer and the p-type diffusion layer 22.

  Next, FIG. 3 shows a structure in which the separated parts are joined at the end face of ZZ. By doing so, a structure in which the n-type diffusion layer 21 and the p-type diffusion layer 22 are arranged on the intrinsic layer 23 with the intrinsic layer 23 interposed therebetween is completed.

  4, an intrinsic semiconductor layer 33 is formed on a transparent substrate 30 as shown in FIG. 3, and an n-type diffusion layer 21 and a p-type diffusion layer 22 are formed on the intrinsic semiconductor layer 33. 33 is arranged with a separation. According to this figure, sunlight can be directly applied to the intrinsic semiconductor layer 33 from below.

  That is, in the solar cell device of this embodiment, an intrinsic semiconductor layer (intrinsic semiconductor layer 33) is formed on a transparent amorphous substrate (transparent substrate 30), and materials having different work functions are joined to the surface of the semiconductor layer. It has a structure. Further, the different materials are conductive diffusion layers (n-type diffusion layer 21 and p-type diffusion layer 22) in which p-type and n-type impurities are diffused, and are formed adjacent to or separated from each other. Features.

  According to such a structure, it is possible to realize a structure in which the reflection surfaces 1 and 2 that have conventionally caused attenuation of light intensity are not present. In addition, although the conventional reflective surface 3 exists, since the n-type diffused layer 21 and the p-type diffused layer 22 exist in isolation, the ratio decreases relatively. Therefore, the sunlight reflected by the reflecting surface 3 re-enters the intrinsic semiconductor layer 33 having the electric field region, and can contribute to power generation again. Here, this structure is referred to as a lateral pin / i structure in which the n-type diffusion layer 21 and the p-type diffusion layer 22 are spaced apart from each other on the intrinsic semiconductor layer 33.

Next, the operation when sunlight is applied to the i layer of the lateral pin / i structure will be described.
FIG. 4 is a schematic diagram of the structure of a lateral pin / i junction solar cell. A lateral pin / i junction 31 is formed on the transparent substrate 30. In the lateral pin / i junction solar cell shown in FIG. 4, sunlight enters directly into the intrinsic semiconductor layer 33. Then, electrons 34 and holes 35 are generated in the intrinsic semiconductor layer 33.

  Electrons 34 and holes 35 generated by sunlight are accelerated by the electric field in the electric field region and collected by the n-type diffusion layer 21 and the p-type diffusion layer 22, and a voltage is generated between both diffusion layers. . Then, the voltage is taken out from the metal electrode 36 attached to the n-type diffusion layer 21 and the p-type diffusion layer 22 through the window of the insulating film 24 and used. In FIG. 4, the n-type diffusion layer 21 and the p-type diffusion layer 22 are spaced apart from each other, but may be adjacent to each other so as to form a pn junction.

  The intrinsic semiconductor layer 33 may be crystalline, polycrystalline, or amorphous, and may be a semiconductor regardless of the type of organic / inorganic material. The types may be superimposed or the composition may be changed by inclining. In particular, due to the industrial maturity of manufacturing technology, intrinsic silicon or one containing silicon and carbon is desirable.

  However, when changing the composition, it is desirable that the energy band cap be larger as it is closer to the sunlight incident side, that is, closer to the transparent substrate 30. This is because, in the solar spectrum, high-energy sunlight is absorbed by high-energy bandgap semiconductors, and low-energy solar light is low-energy bandgap semiconductors that pass deep through the layer. This is because it is absorbed so that sunlight in a wide spectral range can be used.

  FIG. 5 schematically shows the structure of the solar cell of the lateral pin / i junction 31 of the intrinsic semiconductor layers 41, 42, and 43 having different band gaps. Here, assuming that the band gaps of the intrinsic semiconductor layers 41, 42, and 43 are Eg1, Eg2, and Eg3, respectively, a relationship of Eg1 <Eg2 <Eg3 is established therebetween, and the transparent substrate 40 on which sunlight is incident is formed. The band gap is getting bigger.

  Here, the electrons 34 generated by absorbing the sunlight enter the n-type diffusion layer 21 along the inclination of the conduction band formed from the intrinsic semiconductor layer 43 having a high gap energy toward the intrinsic semiconductor layer 41 having a low gap energy. get together. On the other hand, the holes 35 generated by absorbing sunlight gather in the p-type diffusion layer 22 along the slope of the valence band formed from the intrinsic semiconductor layer 43 having a high gap energy toward the intrinsic semiconductor layer 41 having a low gap energy. This will be described with reference to a band diagram shown in FIG.

Band diagrams of the NN cross section and the PP cross section in FIG. 5 are shown in FIGS. 6 and 7, respectively.
As shown in FIGS. 6 and 7, intrinsic semiconductor layers 43, 42, and 41 having band gaps Eg 3, Eg 2, and Eg 1 are stacked on a transparent substrate 40. As shown in FIG. 6, in the NN cross section, sunlight is incident from the transparent substrate 40 side, and electrons 34 and holes 35 are generated by photoexcitation 51. The generated electrons 34 have a potential difference along the conduction band, reach the n-type diffusion layer 21, and carry a negative charge to the metal electrode. On the other hand, the holes 35 in the valence band increase the potential difference via the intrinsic semiconductor layer 41 and reach the p-type diffusion layer 22, and carry positive charges to the metal electrode.

  Further, as shown in FIG. 7, in the pp section, sunlight is incident from the transparent substrate 40 side, and electrons 34 and holes 35 are generated by photoexcitation 51. The generated holes 35 rise in potential along the valence band, reach the p-type diffusion layer 22, and carry positive charges to the metal electrode. On the other hand, the electrons 34 in the conduction band descend the potential difference via the intrinsic semiconductor layer 41, reach the n-type diffusion layer 21, and carry negative charges to the metal electrode.

  Therefore, an intrinsic semiconductor having a large energy gap on the side on which sunlight is incident acts as an emitter of electrons 34 and holes 35. Further, the sunlight that has passed through the n-type diffusion layer 21 and the p-type diffusion layer 22 and the sunlight that has passed between the n-type diffusion layer 21 and the p-type diffusion layer 22 are reflected by the metal electrode and again in the electric field region. Electrons 34 and holes 35 are generated to contribute to power generation.

  As described above, according to the structure of the solar cell device of the present invention, the lateral pin / i junction 31 is used for attenuation caused by reflection when sunlight is incident through the conventional diffusion layer. This can be prevented. In addition, by adopting this structure, an intrinsic semiconductor emitter layer of electrons and holes, which was not possible with the conventional pn junction structure or pin junction structure, can be disposed on all surfaces on the side where sunlight enters. . Furthermore, by providing a material having a composition that increases the energy band gap in the direction in which sunlight enters as the emitter layer, a structure that effectively contributes to a wide spectrum of sunlight for power generation is possible.

<Method for Manufacturing Solar Cell Device>
This structure in which p-type diffusion layers and n-type diffusion layers having different work functions are arranged in an array in a lateral direction on one side surface is composed of a p-type diffusion layer and an n-type diffusion layer that need to transmit sunlight. It enables performance that was not possible with conventional structures with layers stacked vertically.

  That is, since it is not necessary to transmit sunlight as an electrode material having a different work function, for example, a metal can be selected in this structure. Here, the junction between the semiconductor and the metal is called a Schottky junction, but the necessary junction may be this Schottky junction.

  Therefore, when a material with a different work function is joined to an intrinsic semiconductor, electron movement occurs through the semiconductor until there is no difference in Fermi level, and in principle, a potential difference corresponding to the difference between the work functions of the two materials. Occurs in the material. Note that, as an electrode material to be bonded to the semiconductor, materials having different work functions can be selected as long as the manufacturing method allows. However, the potential difference generated by the Schottky junction of metals having different work functions depends on the band curvature depending on the interface state of the surface. Since control of this interface state is difficult in manufacturing, a method of forming stable p-type and n-type diffusion layers that form a junction inside the semiconductor is preferable.

  Here, since formation of a diffusion layer requires high temperature, the method is demonstrated below. In general, when a heated gas is blown perpendicularly to the surface of the substrate, the temperature of the gas can be transmitted to the substrate. Here, if the hot gas is squeezed into a beam shape and incident or collides perpendicularly instead of parallel to the substrate, the stagnant layer as the stagnation layer becomes thin. Or it can be made the grade which a stagnant layer is not formed substantially relatively. Here, if the stagnant layer is thin, the gas temperature can be efficiently transmitted to the substrate. In other words, only the surface can be heated because the surface of the substrate efficiently receives heat from a hot gas beam incident vertically.

  Further, when the back surface of the substrate is cooled, since the heat sink has a certain heat capacity, the temperature rises and reaches the gas temperature is limited to the substrate surface. Using this principle, only the substrate surface can be heated and the back surface and the inside of the substrate can be maintained at a certain temperature or lower.

  FIG. 8 schematically shows an example of a structure that realizes this state. In the following, a glass substrate will be described as an example of a transparent substrate. However, the present invention is not limited to this, and a resin substrate, a plastic substrate, or the like may be used.

  In the structure of FIG. 8, the heated gas beams 61 and 62 collide and enter the glass substrate 60 almost vertically. The glass substrate 60 is held on a cooled support base (not shown), and the substrate back surface temperature is held constant by the coolant.

  On the other hand, by controlling the heating power of the gas heater 65, the temperature of the gas beams 61 and 62 can be increased to 300 ° C. or higher. As the gas passed through the gas heater 65, one kind can be appropriately selected from nitrogen, oxygen, hydrogen, helium, argon, and the like, or a mixture of two or more can be used. When the temperature of the gas beams 61 and 62 is 800 ° C., it is possible to perform thermal diffusion of impurities in the silicon semiconductor process with respect to silicon. In addition, when there is an atmosphere of moisture, the silicon surface can be thermally oxidized. When oxygen is selected as the gas, the heater 65 needs to be made of a material that does not oxidize and burn, or a material that does not oxidize and become a gas.

Furthermore, polysilicon can be grown from 600 ° C. thermal decomposition of silane. When nitrogen oxide N ₂ O or water is introduced as an oxidizing gas together with silane, the thermal reaction oxide film grows at a gas beam temperature of 700 to 800 ° C. Is possible. When ammonia NH ₃ gas is introduced together with silane, a silicon nitride film can be formed at a gas beam temperature of 700 ° C. In place of silane, halogenated silane (SiH ₂ Cl ₂ or the like) may be used.

Here, the structure of FIG. 8 and each role will be described.
In FIG. 8, heating gas beams 61 and 62 are arranged so as to sandwich a gas introduction pipe 63 that introduces them without heating so as to be suitable for growing a semiconductor layer. In addition, since the process of heating only the surface with a gas beam is not particularly limited, only one beam may be used.

  In order to grow a film, heat is confined to create a high-temperature space (room), the gas to be pyrolyzed stays in the room for a long time, and reactive decomposition species are generated, which is efficiently transferred to the substrate. A structure that can replenish is necessary. For that purpose, in order to make a room, it is effective to inject gas of a high-temperature linear beam to be sprayed from two places. Here, a room surrounded by the high temperature gas, which is a space surrounded by the heated gas beams 61 and 62, is called a high temperature gas room 66.

  When, for example, silane is selected and introduced from the gas inlet pipe 63 that is not heated, thermal decomposition proceeds in the high temperature gas room 66 to generate active species, which diffuses the stagnant layer and deposits the silicon film on the glass substrate 60. Grow. If the heating beams 61 and 62 are selected so as to contain a gas that undergoes an oxidation reaction, a thermal decomposition reaction occurs with the silane stagnating in the high temperature gas room 66, and an oxide film grows.

  If there are no nuclei of different substances in the gas phase, natural nucleation will not occur below a certain concentration. Under the high temperature gas room 66, there is a glass substrate 60 as a giant nucleus which is a different kind of material having a low temperature. Since the substrate surface, which is a foreign material, has a low temperature, film growth starts from the nucleus growth. This is the principle of causing thermal CVD to occur on the substrate surface by contacting a gas having a temperature higher than that of the substrate while keeping the temperature of the glass substrate 60 low.

When, for example, acetylene C ₂ H ₂ is introduced together with silane from the gas introduction pipe 63, a polycrystalline film of a mixed crystal with silicon carbide or silicon can be grown. Further, when the silicon carbide composition having a large band gap is formed on the side close to the glass substrate 60 and the composition is changed to silicon stepwise or inclined, the surface is silicon, and the glass substrate 60 side has a band gap. An intrinsic semiconductor layer having a composition of large silicon carbide can be grown. However, at this time, in order to prevent the metal impurities from diffusing from the glass substrate, it is desirable to grow the oxide film by the method described above. Note that the conductive oxide film may be a transparent one such as zinc oxide. In addition, applying a metal oxide by another method, for example, a sputtering method is also effective for preventing impurity diffusion, but when excess metal is contained, it is oxidized by the oxidation method of the present invention described above. Thus, it is possible to improve the transparency.

  As described above, according to the method for manufacturing a solar cell device of the present invention, only the surface of the substrate 60 is blown by spraying the high-temperature heating gases 61 and 62 so as to collide with the glass substrate 60 almost vertically. The substrate can be heated to a high temperature, while maintaining the inside and back of the substrate at a constant temperature according to the cooling effect, heat treatment is performed only on the surface at a temperature higher than the substrate, and impurity thermal diffusion is performed, and a silicon oxide film or a silicon nitride film, It is possible to use a manufacturing method for growing a high temperature thermal CVD material such as polysilicon.

  Therefore, by this manufacturing method, a solar cell device having a lateral pin / i junction structure is manufactured on a glass substrate or a transparent amorphous substrate that needs to be maintained at a temperature lower than its softening point (300 ° C.). Is possible.

<Method for Manufacturing Lateral Pin / i Junction Solar Cell>
In the above, the structure of the solar cell device according to the present invention and the method for manufacturing the solar cell device have been described. Hereinafter, the embodiment of the present invention will be described in detail with reference to the drawings and the method for manufacturing a lateral pin / i junction solar cell. explain. In the accompanying drawings, the same or corresponding parts are denoted by the same reference numerals.

9 to 14 are diagrams schematically showing a method for manufacturing a lateral pin / i-junction solar cell.
FIG. 9 is a schematic diagram of a process of growing an intrinsic semiconductor crystal layer 67 (Si _(1-X) C _X ) on the glass substrate 60. Since the glass substrate 60 contains metal impurities, an oxide film 71 is grown to 100 nm to prevent this diffusion.

First, silane is introduced from the gas inlet 63 and nitrogen gas containing an oxidizing gas N ₂ O gas is introduced from the gas inlets 61 and 62. This may be a plasma CVD oxide film.

Next, the surface temperature of the support of the glass substrate 60 is set to 300 ° C., then the set temperature of the gas heater 65 is set in the range of 650 ° C. to 750 ° C., and a nitrogen gas beam (N ₂ gas beam) 61, The high temperature gas chamber 66 is formed by colliding 62 with the substrate. At the same time, without heating silane SiH ₄ diluted with nitrogen to 1% and acetylene C ₂ H ₂ through the quartz gas inlet 63, a space between the nitrogen gas beams 61 and 62 emitted from the gas inlet is obtained. Injection into the hot gas room 66. Silane SiH ₄ and acetylene C ₂ H ₂ are exemplified because the thermal decomposition temperature is lower than other gases.

  When SiC having a high energy band gap value is grown, the set temperature is set to 750 ° C. Here, since silicon carbide has a stable Si—C bond, silicon carbide has a strong property of continuous bonding in the film thickness direction on the oxide film, such as Si—C—Si—C. In the face-centered cubic crystal, since this direction is the <111> axis, it has a property of becoming a film with <111> preferential orientation.

Because of these properties, it is suitable to grow a SiC film first for the purpose of aligning the axes of the polycrystal. However, since there is a property that SiC nucleation does not easily occur on the silicon oxide film, it is preferable to nucleate the silicon film with silane alone to easily cause the SiC growth. When growing a polycrystalline silicon layer, the temperature is set to 650 ° C. Then, by changing the set temperature between 750 ° C. and 650 ° C. while reducing the ratio of acetylene, a polycrystalline and intrinsic semiconductor crystal layer 67 of the film Si _(1-X) C _X whose composition changes in the thickness direction is formed. A 300 nm thickness is grown on the glass substrate 60.

  At this time, the side close to the glass substrate 60 is mainly composed of SiC, and the surface is polycrystalline silicon. When acetylene is not introduced, a polycrystalline silicon film grows. The growth region can be expanded by reciprocating the glass substrate 60 in the lateral direction.

  FIG. 10 shows a schematic diagram of a separation process by etching a polycrystalline and intrinsic semiconductor crystal layer. Here, a resist 68 is coated on the upper surface of the polycrystalline and intrinsic semiconductor crystal layer 67, a resist separation pattern is formed by exposure and development, and the polycrystalline and intrinsic semiconductor crystal layer 67 is separated using a dry etching method. To do.

FIG. 11 is a schematic diagram showing a process of growing an insulating film on the separated polycrystalline and intrinsic semiconductor crystal layer 67. It is possible to grow the silicon oxide film 72 by introducing silane from the gas inlet 63 and introducing nitrogen gas containing an oxidizing gas N ₂ O gas from the gas inlets 61 and 62 at a temperature of 700 ° C. It becomes.

  Alternatively, the silicon oxide film 72 can be formed by introducing TEOS gas from the gas inlet 63 and then introducing it into the high temperature gas room 66 and thermally decomposing it. At this time, the surface of the semiconductor layer forms a recombination level. In order to control and reduce this, if a thermal silicon oxide film is formed in advance before forming the CVD film by irradiating a nitrogen gas beam containing water at 800 ° C., it is effective in dealing with the required quality for preventing aging deterioration.

  FIG. 12 is a schematic diagram of a process for forming an n-type impurity diffusion layer. Using the resist diffusion layer pattern transfer and dry etching methods, the silicon oxide film 72 where the n-type diffusion layer 73 is to be formed is opened. Next, nitrogen gas containing phosphine gas is introduced from the gas inlet 63 as an impurity, a nitrogen gas beam is introduced from the gas inlets 61 and 62 at a set temperature of 800 ° C., and phosphorus is removed from the opening of the silicon oxide film 72. An n-type diffusion layer 73 is formed by thermal diffusion. Note that phosphorus may be diffused by growing amorphous silicon containing phosphorus by another method, for example, plasma CVD, and annealing the amorphous silicon by the gas beam heating method of this embodiment.

  FIG. 13 is a schematic diagram of a process for forming a p-type impurity diffusion layer. The silicon oxide film 72 is additionally grown by the same method as that for forming the silicon oxide film 72 to close the opening of the n-type diffusion layer 73. The silicon oxide film 72 where the p-type diffusion layer 74 is to be formed is opened by transferring the p-type diffusion layer pattern of the resist and using a dry etching method. Next, nitrogen gas containing diborane gas is introduced as an impurity from the gas inlet 63, and a nitrogen gas beam is further introduced from the gas inlets 61 and 62 at a set temperature of 800 ° C., so that the p-type diffusion layer of the silicon oxide film 72 is introduced. The p-type diffusion layer 74 is formed by thermally diffusing boron from the opening. Alternatively, boron may be diffused by growing amorphous silicon containing boron by another method, such as plasma CVD, and annealing the amorphous silicon by the gas beam heating method of this embodiment.

  FIG. 14 is a schematic diagram of a process of forming an aluminum metal electrode. Again, the electrode pattern connected to the n-type diffusion layer 73 of the resist is transferred, the oxide film on the n-type diffusion layer 73 is removed by etching, and the n-type diffusion layer 73 and the p-type diffusion layer 74 are connected. A connection hole is opened in the oxide film 72. Next, an aluminum film is grown by sputtering, and a pattern of the aluminum electrode 75 is formed using a resist metal electrode layer pattern transfer and dry etching method.

  FIG. 15 is a diagram showing a series connection of lateral pin / i junction solar cells. The n-type diffusion layer 73 of the lateral pin / i junction 81 and the p-type diffusion layer 74 of the lateral pin / i junction 82 are connected by an aluminum electrode 75. Here, when sunlight 80 is irradiated, a voltage Vs (= Vout1 + Vout2), which is the sum of the generated voltage Vout1 of the lateral pin / i junction 81 and the generated voltage Vout2 of the lateral pin / i junction 82, is the lateral pin / i junction. It occurs between the n-type diffusion layer 73 of 81 and the p-type diffusion layer 74 of the lateral pin / i junction 82. A higher voltage can be generated by performing this connection in multiple stages.

  FIG. 16 shows an example in which a lateral pin / i-junction solar cell is fabricated on a glass substrate 90 whose surface has been processed with irregularities. In this example, the period of the unevenness and the period of the lateral pin / i junction solar cell are matched, but it is not necessary to match. The unevenness allows sunlight to enter the intrinsic semiconductor crystal layer 67 efficiently.

  By using the structure of the solar cell device of the present invention, sunlight can be introduced from the entire surface of the glass substrate, and sunlight can be introduced into the internal electric field region of the intrinsic semiconductor layer on the entire surface without interposing the electrode layer. This structure is a structure in which materials having different energy band gaps are continuously connected without being connected via an electrode. Therefore, the solar energy spectrum can be used effectively. Since the structure of the solar cell device of the present invention does not use a transparent electrode using rare metal indium, it also solves the economical problem of resources.

  In addition, the manufacturing method that enables the structure of the solar cell device of the present invention is a method for growing a crystalline semiconductor while keeping an inexpensive glass substrate at a low temperature. Realize a world where you can change and use more energy while protecting the global environment.

  The embodiments of the present invention have been described in detail with reference to the drawings. However, the specific configuration is not limited to the embodiments, and includes designs and the like that do not depart from the gist of the present invention.

It is a schematic diagram of a pin junction diode structure. It is the schematic diagram which divided | segmented the pin junction diode of FIG. 1 by XX. FIG. 3 is a schematic diagram of a diode in which the pi junction and the in junction of FIG. 1 are laterally joined on the ZZ plane. It is the figure which showed typically the structure of the lateral pin / i junction diode solar cell. It is the figure which showed typically the structure of the semiconductor intrinsic layer lateral pin / i junction solar cell from which a band gap differs. In the schematic diagram of the semiconductor intrinsic layer lateral pin / i junction in which band gaps differ, it is a figure which shows the band diagram of a NN cross section. In the schematic diagram of the semiconductor intrinsic layer lateral pin / i junction in which band gaps differ, it is a figure which shows the band diagram of PP cross section. It is the schematic diagram which showed the structure of the film forming apparatus which heats only the surface of a glass substrate. In the manufacturing process of a lateral pin / i junction solar cell, it is the schematic diagram which showed the process of growing intrinsic semiconductor crystalline layer Si _{(1-X) CX} on a glass substrate. It is the schematic diagram which showed the etching separation process of the intrinsic semiconductor crystal layer in the manufacturing process of the lateral pin / i junction solar cell. It is a schematic diagram which shows the silicon oxide film growth process to the isolate | separated intrinsic semiconductor crystal layer in the manufacturing process of a lateral pin / i junction solar cell. It is a schematic diagram which shows the formation process of an n-type impurity diffusion layer in the manufacturing process of a lateral pin / i junction solar cell. It is a schematic diagram which shows the formation process of a p-type impurity diffusion layer in the manufacturing process of a lateral pin / i junction solar cell. It is a schematic diagram which shows the formation process of an aluminum electrode in the manufacturing process of a lateral pin / i junction solar cell. It is a schematic diagram of the serial connection of a lateral pin / i junction solar cell. It is a schematic diagram of the lateral pin / i junction solar cell manufactured on the board | substrate with an unevenness | corrugation on the surface. It is a cross-sectional schematic diagram of a conventional pn diode. It is a cross-sectional schematic diagram of a conventional pin diode.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... n-type layer 12 ... p-type layer 13 ... depletion layer 14 ... intrinsic amorphous layer 15 ... n-type amorphous layer 16 ... p-type amorphous layer 21 ... n-type diffusion Layer 22 ... p-type diffusion layer 23 ... intrinsic layer 24 ... insulating film 25 ... ni junction 26 ... ip junction 30 ... transparent substrate 31 ... lateral pin / i junction 33. .... Intrinsic semiconductor layer 34 ... Electrons generated by sunlight 35 ... Holes generated by sunlight 36 ... Metal electrode 40 ... Transparent substrate 41 ... Intrinsic semiconductor layer 42 ... Intrinsic Semiconductor layer 43 ... Intrinsic semiconductor layer 51 ... Photo-excitation 60 ... Glass substrate 61, 62 ... Gas beam 63 ... Unheated gas introduction tube 65 ... Gas heater 66 ... High temperature gas Room 67 ... Intrinsic semiconductor crystal layer 68 -Resist 71 ... Oxide film 72 ... Silicon oxide film 73 ... N-type diffusion layer 74 ... P-type diffusion layer 75 ... Aluminum film 80 ... Sunlight 81 ... Lateral pin / i-junction 82 ... lateral pin / i-junction 90 ... glass substrate with uneven surface

Claims (18)

  A solar cell device in which an intrinsic semiconductor layer is formed on a transparent amorphous substrate, and materials having different work functions are joined to the surface of the semiconductor layer.   2. The solar cell device according to claim 1, wherein the different materials are p-type and n-type conductivity type diffusion layers in which impurities are diffused, and are formed adjacent to or separated from each other.   The solar cell device according to claim 1, wherein the transparent amorphous substrate is made of glass, resin, or plastic.   The solar cell device according to any one of claims 1 to 3, wherein the transparent amorphous substrate is a substrate on which a transparent thin film different from them is placed on glass, resin, or plastic.   The solar cell device according to any one of claims 1 to 4, wherein the semiconductor layer is intrinsic silicon.   The solar cell device according to any one of claims 1 to 4, wherein the semiconductor layer contains silicon and carbon.   The solar cell device according to any one of claims 1 to 6, wherein the semiconductor layer has a composition in which an energy band gap increases as it is closer to the substrate.   The solar cell device according to any one of claims 1 to 7, wherein sunlight is introduced into the intrinsic semiconductor layer from the transparent amorphous substrate side.   A gas heated to a temperature higher than the support table temperature of the substrate is sprayed in a line form on the surface of the substrate placed on the support table from a gas injection port placed opposite to the substrate surface to heat the surface. A method for manufacturing a solar cell device.   The method for manufacturing a solar cell device according to claim 9, wherein the gas includes any one of nitrogen, oxygen, hydrogen, Ar, and He, or a mixed gas thereof.   The surface of the substrate placed on a support table is sprayed in a line from two or more different gas injection ports placed opposite to the substrate surface with a gas heated to a temperature higher than the substrate support table temperature. The method of manufacturing a solar cell device according to claim 9, wherein a semiconductor layer is formed on the substrate by heating the substrate.   12. The method for manufacturing a solar cell device according to claim 11, wherein a gas containing silicon or carbon, or both is introduced from a gas injection port sandwiched between different gas injection ports.   A gas heated to a temperature higher than the temperature of the support table of the substrate is sprayed from above the substrate placed on the support table in a line form from two or more different gas injection ports placed facing the substrate. 11. The method for manufacturing a solar cell device according to claim 9, wherein an insulating film is grown on the surface. Of the two or more different gas injection ports, the gas injected from one gas injection port contains silane (SiH ₄ , Si ₂ H ₆ ) or halogenated silane, and is injected from another gas injection port. The gas includes any one or both of N ₂ O, NO _2, an oxidizing gas containing water and oxygen, a nitriding gas containing NH ₃ that reacts with the gas, and an insulating film is grown on the substrate. The manufacturing method of the solar cell apparatus of Claim 13.   The method for manufacturing a solar cell device according to claim 11, wherein an oxide film is formed by introducing an oxidizing gas containing oxygen or water to oxidize the surface of the semiconductor layer.   The method for manufacturing a solar cell device according to claim 9 or 10, wherein a diffusion layer is formed by introducing a gas containing impurities and diffusing the impurities.   The method for manufacturing a solar cell device according to claim 16, wherein the impurity is an element that makes the semiconductor layer n-type or p-type.   18. The solar cell device according to claim 9, wherein a gas ejected from the gas ejection port is sprayed substantially perpendicularly onto a surface of the substrate placed on the support base. Method.

Images