JP2010033420A - Cache circuit and cache memory control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce an access frequency to an external memory to reduce a processing time, when reading image data. <P>SOLUTION: In this cache circuit, one area of a cache memory is selected. One selection address is selected from a plurality of input addresses. It is decided whether data on a pixel shown by the selection address are stored in the cache memory or not. When the data on the pixel shown by the selection address are stored in the cache memory, data stored in a plurality of areas of the cache memory are received, and are written into the area selected by a selection signal. When the data on the pixel shown by the selection address are not stored in the cache memory, the data shown by the selection address are read from the external memory provided outside the cache circuit as read data, and are written into the area selected by the selection signal. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a cache circuit and a cache memory control method, and more particularly to a cache circuit used for image data processing and a cache memory control method suitable for use in the cache circuit.

  The image data processing circuit will be described with reference to FIG. FIG. 1 is a schematic diagram for explaining an image data processing circuit. The image data processing circuit includes an address calculation unit 10, an external memory 20, an image data processing unit 30, and a cache circuit 100.

  This image data processing circuit is used for a process of drawing a destination image after image processing by performing image processing such as rotation on the source image. For example, when the source image is rotated, data for four pixels of the source image is required to generate data for one pixel of the destination image.

  The relationship between the source image and the destination image will be described with reference to FIG. FIG. 2 is a schematic diagram for explaining the relationship between the source image and the destination image.

  The data of the pixel a of the destination image is generated by the data of the pixels 1-1, 2-1, 1-2, and 2-2 of the source image. Similarly, the data of the pixel b of the destination image is generated by the data of the pixels 1-2, 2-2, 1-3, and 2-3 of the source image, and the data of the pixel c of the destination image is the source image. Are generated with the data of the pixels 2-3, 3-3, 2-4 and 3-4.

  The address calculation means 10 receives an address (destination address) of one pixel of the destination image. The address calculation means 10 calculates input addresses 1 to 4 necessary for generating data indicated by the destination address. The input addresses 1 to 4 are sent to the cache circuit 100.

  The cache circuit 100 reads pixel data indicated by the input addresses 1 to 4 from the internal cache memory or the external memory 20. The cache circuit 100 sends the read data (output data 1 to 4) to the image data processing means 30.

  For reading data from an external memory, a method of reading data of a plurality of pixels as one block has been proposed (for example, see Patent Document 1).

The image data processing means 30 calculates the pixel data indicated by the destination address using the output data 1 to 4 and sends it to the drawing means (not shown) as processed data.
Japanese Patent Laid-Open No. 5-53909

  However, in the conventional configuration described with reference to FIG. 1, it is necessary to read data from an external memory four times for one destination address according to input addresses 1 to 4. Here, when the external memory 20 is configured by using a FlashROM, SDRAM, or the like, the FlashROM and SDRAM require a longer time to read data than the cache memory that the cache circuit 100 has.

  Therefore, when the inventor of this application conducted intensive research, when data at the same address that was once read from the external memory was used again, it was stored in the cache memory without accessing the external memory. It has been found that by efficiently performing the operation of referring to data, the number of accesses to the external memory can be reduced, and the processing time can be reduced.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a cache circuit that can reduce the number of accesses to an external memory and can shorten the processing time. It is.

  In order to achieve the above-described object, the cache circuit of the present invention has a cache memory in which a pixel data indicated by an address and an address is stored in each of a plurality of areas, and each of a plurality of inputted input addresses indicates Pixel data is read from the cache memory and output.

  The cache circuit includes a read control unit, an address selection unit, a cache hit determination unit, a cache hit data selection unit, a memory control unit, a write data determination unit, and a write area selection unit.

  The read control unit generates a selection signal for selecting one area of the cache memory. The address selection unit selects one selected address from a plurality of input addresses. The cache hit determination unit determines whether or not the pixel data indicated by the selected address is stored in the cache memory, and outputs a cache hit determination signal indicating the determination result and a cache hit signal indicating the stored area. Generate. When the pixel data indicated by the selected address is stored in the cache memory, the cache hit data selection unit selects the data in the area indicated by the cache hit signal as the cache hit data. When the pixel data indicated by the selected address is not stored in the cache memory, the memory control unit reads the pixel data indicated by the selected address as read data from an external memory provided outside the cache circuit. The write data determination unit selects cache hit data as write data when the pixel data indicated by the selected address is stored in the cache memory, and when the pixel data indicated by the selected address is not stored in the cache memory, The read data is selected as write data, the write data is sent to the cache memory, and a write data determination signal indicating that the write data can be used is generated. When the write data determination signal indicates that the write data is usable, the write area selection unit generates a write enable signal that enables writing to the area of the cache memory selected by the selection signal and sends the write enable signal to the cache memory .

  According to the cache circuit of the present invention, when a cache hit occurs, the data stored in the cache memory is referred to without accessing the external memory. As a result, the number of accesses to the external memory can be reduced, and the processing time can be shortened.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the embodiments are merely schematically shown to the extent that the present invention can be understood. In the following, a preferred configuration example of the present invention will be described, but it is merely a preferred example. Therefore, the present invention is not limited to the following embodiments, and many changes or modifications that can achieve the effects of the present invention can be made without departing from the scope of the configuration of the present invention.

(First embodiment)
The cache circuit of the first embodiment will be described with reference to FIGS. FIG. 3 is a schematic diagram for explaining the cache circuit of the first embodiment.

  The cache circuit 100 can be used in the conventional image data processing circuit described with reference to FIG. 1, and will be described with reference to FIG. In the following description, an example in which an address for four pixels (input addresses 1 to 4) of a source image is input to the cache circuit 100 and data for four pixels (output data 1 to 4) is output from the cache circuit 100 will be described. As will be described, the number of input addresses and output data can be set according to the image processing method.

  The cache circuit 100 includes a cache memory 300, a read control unit 120, an address selection unit 130, a cache hit determination unit 140, a cache hit data selection unit 150, a memory control unit 160, a write data determination unit 170, a write area selection unit 180, and an output. A data selection unit 190 is provided.

  Input addresses 1 to 4 input to the cache circuit 100 are sent to the cache memory 300 and the address selector 130.

  The cache memory 300 includes input addresses 1 to 4 input to the cache circuit 100, selection signals 1 to 4 generated by the read control unit 120, write enable signals 1 to 4 generated by the write area selection unit 180, and The write data selected by the write data determination unit 170 is input. Further, from the cache memory 300, the valid bits 1 to 4 and the upper addresses 1 to 4 are sent to the cache hit determination unit 140, and the lower addresses 1 to 4 are sent to the output data selection unit 190. 4 is sent to the cache hit data selection unit 150 and the output data selection unit 190.

  The cache memory will be described with reference to FIG. FIG. 4 is a schematic diagram of the cache memory.

  The cache memory 300 has a plurality of areas. The number of areas that the cache memory 300 has is at least the same as the number of input addresses. Here, the area that the cache memory 300 has is four. Each area of the cache memory 300 is provided with a valid bit column 330, a high-order address column 332, a low-order address column 334, and a cache data column 336, each storing a valid bit, a high-order address, a low-order address, and cache data. The

  In the following description, valid bits, upper addresses, lower addresses and cache data stored in the first to fourth areas 311 to 314 are distinguished from each other, and valid bits 1 to 4, addresses 1 to 4 and cache data 1 to 4 are distinguished. 4 may also be expressed.

  Here, the valid bit indicates whether or not the area in which the valid bit is stored is valid, that is, whether or not cache data is stored in the cache data column 336 of the area. Here, when the area is valid, the valid bit is “1”, and when the area is invalid, the valid bit is “0”.

  The upper address and the lower address indicate pixel addresses of the source image. Note that cache data can be stored in one area of the cache memory 300 with a plurality of consecutive pixels as one unit (block). In this case, the upper address indicates the position (address) of each block, and the lower address indicates the position of the pixel in each block.

  Among the input addresses 1 to 4, the upper address indicating the block position is sent to the upper address column 332 of the cache memory 300. Further, the lower address indicating the position in the block is sent to the lower address column 334 of the cache memory 300.

  The selection signals 1 to 4 are input to the write enable terminals (we) of the upper address column 332 and the lower address column 334 provided in each area of the cache memory 300, respectively. When the selection signals 1 to 4 are “1”, the upper address and the lower address of the input addresses 1 to 4 are stored in the upper address column 332 and the lower address column 334 of the cache memory 300, respectively.

  The write data is sent to the cache data column 336 of each area 311 to 314 of the cache memory 300. Further, the write enable signal is input to the write enable terminal (we) of the cache data column 336 of the cache memory 300. When the write enable signals 1 to 4 are “1”, the write data is stored in the cache data column 336 of the cache memory 300.

  The write enable signals 1 to 4 are sent to the effective bit column 330 of each area 311 to 314, respectively. When the valid bits 1 to 4 are “0” and the write enable signals 1 to 4 are “1”, the valid bits 1 to 4 are “1”. In the initial state, all the valid bits are “0”. However, once the valid bit becomes “1”, “1” is maintained until the bit is initialized again.

  The read control unit 120 generates selection signals 1 to 4 for selecting one of the first to fourth areas 311 to 314 of the cache memory 300. Here, only one of the selection signals 1 to 4 is “1”, and the others are “0”. The first to fourth regions 311 to 314 are sequentially selected by the selection signals 1 to 4. The selection signals 1 to 4 are sent to the cache memory 300, the address selection unit 130, and the write area selection unit 180.

  The address selection unit 130 uses the selection signals 1 to 4 to select one address as the selection address from the input addresses 1 to 4. For example, when the selection signal 1 is “1” and the selection signals 2 to 4 are “0”, the input address 1 is selected as the selection address.

  A configuration example of the address selection unit will be described with reference to FIG. FIG. 5 is a schematic configuration diagram of the address selection unit.

  The address selection unit 130 of this configuration example may be configured to include first to fourth AND operation units 132-1 to 13-4 and an OR operation unit 134. In this configuration, logical products (AND) 1 to 4 of the input addresses 1 to 4 and the selection signals 1 to 4 calculated by the first to fourth AND operation units 132-1 to 13-4 are respectively OR operation units. And the logical sum (OR) is calculated.

  Since only one of the selection signals 1 to 4 is “1”, any one of the ANDs 1 to 4 indicates an input address, and “0” otherwise. Accordingly, the logical sum of AND1 to AND4 becomes a selection address indicating any one of the input addresses 1 to 4. The selected address is sent to the cache hit determination unit 140 and the memory control unit 160.

  The cache hit determination unit 140 determines whether or not the pixel data indicated by the selected address is stored in the cache memory 300, and the cache hit determination signal indicating the determination result and the pixel data indicated by the selected address are stored. A cache hit signal indicating the area that is present is generated.

  A configuration example of the cache hit determination unit will be described with reference to FIG. FIG. 6 is a schematic configuration diagram of the cache hit determination unit.

  The cache hit determination unit 140 includes first to fourth comparison operation units 142-1 to 142-1, first to fourth AND operation units 144-1 to 144-1, and an OR operation unit 146. The first to fourth comparison operation units 142-1 to 14-4 compare the upper address of the selected address with the upper addresses 1 to 4 stored in the upper address column 332 of the cache memory 300, respectively. As a result of the comparison, if they match, the comparison results 1 to 4 that are the outputs of the first to fourth comparison operation units 142-1 to 14-4 are "1", and if they do not match, the comparison results 1 to 4 Becomes “0”.

  Comparison results 1 to 4 and valid bits 1 to 4 stored in the valid bit column 330 of the cache memory 300 are input to the first to fourth AND operation units 144-1 to 144-4, respectively. The first to fourth AND operation units 144-1 to 144-4 perform logical product (AND) operations on the valid bits 1 to 4 and the comparison results 1 to 4, respectively, and set the results as cache hit signals 1 to 4. .

  The cache hit signals 1 to 4 are “1” when the data is valid and the upper address of the selected address matches the upper address stored in the upper address column 332 of the cache memory 300. . For example, when the valid bit 3 is “1” and the comparison result 3 is “1”, the cache hit signal 3 is “1”. That is, the cache hit signals 1 to 4 indicate an area of the cache memory 300 in which an upper address equal to the upper address of the selected address is stored. The cache hit signals 1 to 4 are sent to the cache hit data selection unit 150.

  The cache hit signals 1 to 4 are also sent to the OR operation unit 146. The OR operation unit 146 performs a logical sum (OR) operation on the cache hit signals 1 to 4. The cache hit determination signal, which is the result of the logical sum operation, is “1” when data at an address equal to the selected address is stored in the cache memory 300, and “0” otherwise. The cache hit determination signal is sent to the memory control unit 160 and the write data determination unit 170.

  When the pixel data indicated by the selected address is stored in the cache memory 300, the cache hit data selection unit 150 selects the cache data in the area indicated by the cache hit signals 1 to 4 as the cache hit data.

  A configuration example of the cache hit data selection unit will be described with reference to FIG. FIG. 7 is a schematic configuration diagram of the cache hit data selection unit.

  The cache hit data selection unit 150 of this configuration example includes first to fourth AND operation units 152-1 to 152-1 to OR operation unit 154. In this configuration, the logical products (AND) 1 to 4 of the cache data 1 to 4 and the cache hit signals 1 to 4 calculated by the first to fourth AND operation units 152-1 to 15-4 are respectively calculated. The OR operation unit 154 calculates a logical sum (OR) for each of a plurality of bits of data output from the AND operation units 152-1 to 152-1-4.

  Since only one of the cache hit signals 1 to 4 is “1”, one of the AND 1 to 4 indicates cache data, and “0” otherwise. Accordingly, the logical sum of AND1 to AND4 becomes cache hit data indicating any one of the cache data 1 to 4. For example, when the cache hit signal 3 is “1”, the cache data 3 is selected as the cache hit data. The cache hit data is sent to the write data determination unit 170.

  The memory control unit 160 has a function of reading data stored in the external memory 20 with respect to the external memory 20 provided outside the cache circuit 100.

  The memory control unit 160 receives the selection address selected by the address selection unit 130 and the cache hit determination signal generated by the cache hit determination unit 140 by being inverted. When the cache hit determination signal is “0”, that is, when the data corresponding to the selected address is not stored in the cache memory 300, the memory control unit 160 stores the pixel indicated by the selected address from the external memory 20. Read data. On the other hand, when the cache hit determination signal is “1”, reading from the external memory 20 is not performed.

  The memory control unit 160 sends the data read from the external memory 20 to the write data determination unit 170 as read data. In addition, a read data enable signal indicating that the read data is usable is also sent to the write data determination unit 170. Here, the read data enable signal is set to “1” when the read data is usable, and the read data enable signal is set to “0” when the read data is not usable.

  When the pixel data indicated by the selected address is stored in the cache memory 300, the write data determination unit 170 selects the cache hit data as write data, and the pixel data indicated by the selected address is stored in the cache memory 300. If not, read data is selected as write data. The write data determination unit 170 sends the write data to the cache memory 300, generates a write data determination signal indicating that the write data can be used, and sends the write data determination signal to the write area selection unit 180.

  A configuration example of the write data determination unit will be described with reference to FIG. FIG. 8 is a schematic configuration diagram of the write data determination unit.

  The write data determination unit 170 includes a selection calculation unit 172 and an OR calculation unit 174. The selection calculation unit 172 receives cache hit data and read data. The selection calculation unit 172 receives a cache hit determination signal as a control signal. The selection calculator 172 selects and outputs either cache hit data or read data according to the value of the cache hit determination signal.

  In this configuration, when the cache hit determination signal is “1”, that is, when the pixel data indicated by the selected address is stored in the cache memory, the selection calculation unit 172 selects the cache hit data as write data. . On the other hand, when the cache hit determination signal is “0”, that is, when the pixel data indicated by the selected address is not stored in the cache memory, the selection calculation unit 172 selects the read data as the write data.

  The OR operation unit 174 receives a cache hit determination signal and a read data enable signal. The OR operation unit 174 sends the logical product (OR) of the cache hit determination signal and the read data enable signal to the write area selection unit 180 as a write data determination signal. The write data determination signal indicates “1” when the write data is usable, that is, when there is data corresponding to the selected address in the cache memory or when the read data has been read, otherwise In this case, it is “0”.

  When the write data is usable, the write area selection unit 180 generates a write enable signal that enables writing in the area of the cache memory 300 selected by the selection signal, and sends the write enable signal to the cache memory 300. Each time a write enable signal is generated, a write completion signal is sent to the read control unit 120.

  A configuration example of the write area selection unit will be described with reference to FIG. FIG. 9 is a schematic configuration diagram of the write area selection unit.

  The write area selection unit 180 includes first to fourth AND calculation units 182-1 to 182-1 to OR calculation unit 184. Selection signals 1 to 4 and a write data determination signal are input to the first to fourth AND operation units 182-1 to 182-1, respectively. The first to fourth AND operation units 182-1 to 182-1 perform logical product (AND) operations of the selection signals 1 to 4 and the write data determination signal, respectively.

  Write enable signals 1 to 4 that are the result of the logical product operation indicate areas in which write data can be written. For example, when the selection signal 1 is “1” and the write data determination signal is “1”, the write enable signal 1 is “1”. In this case, the first area 311 of the cache memory 300 becomes writable. The write enable signals 1 to 4 are sent to the cache memory 300.

  The write enable signals 1 to 4 are sent to the OR operation unit 184. The OR operation unit 184 generates a logical sum (OR) of the write enable signals 1 to 4 as a write completion signal. That is, the write completion signal becomes “1” every time the write enable signal is generated, and becomes “0” otherwise. This write completion signal is sent to the read control unit 120.

  The read control unit 120 generates a selection signal in which the region to be selected is changed every time the write completion signal becomes “1”. For example, if the selection signal 1 is “1” and the selection signals 2 to 4 are “0”, the selection signal 1 becomes “0” and the selection signal 2 becomes “0” when the write completion signal becomes “1”. 1 ". Thereafter, when the write enable signal 2 becomes “1”, the selection signal 2 becomes “0” and the selection signal 3 becomes “1”. Finally, when the write enable signal 4 becomes “1” and all data is stored, the output data preparation completion flag is set to “1”. The output data preparation completion flag is stored in any suitable storage means in the cache circuit 100 such as a RAM so that it can be read and rewritten.

  When the output data preparation completion flag becomes “1”, the output data selection unit 190 outputs the cache data stored in the cache memory 300 as output data and sends it to the image data processing means 30.

  A configuration example of the output data selection unit will be described with reference to FIG. FIG. 10 is a schematic configuration diagram of the output data selection unit.

  The output data selection unit 190 includes first to fourth selection calculation units 192-1 to 194-2. The cache data 1 to 4 are sent to the first to fourth selection arithmetic units 192-1 to 192-1, respectively. In addition, lower addresses 1 to 4 are input to these first to fourth selection calculation units 192-1 to 192-1 as control signals. The first to fourth selection calculators 192-1 to 19-4 select and output the data at the positions indicated by the lower addresses 1 to 4 as the output data from the cache data 1 to 4, respectively. After the output of the output data 1 to 4 is completed, the output data preparation completion flag becomes “0”. At this time, an address request is sent to the address calculation means 10 in the preceding stage.

  Each component of the cache circuit 100 described above is realized as each functional unit by, for example, a central processing unit (CPU: Central Processing Unit) executing a predetermined program.

(Operation of the first embodiment)
The operation of the cache circuit described above will be described with reference to FIG. FIG. 11 is a schematic diagram for explaining the operation of the cache circuit of the first embodiment, that is, the cache memory control method. 11A to 11H show information stored in each column of the cache memory.

  Here, it is assumed that data for two pixels is written in one area of the cache memory. An example of the relationship between the source image and the destination image described with reference to FIG. 2 will be described.

  In the initial state, all the contents of the cache memory 300 are “0” (FIG. 11A).

  As the input addresses 1 to 4, the addresses of the pixels 1-1, 1-2, 2-1, and 2-2 are input.

  When the selection signal 1 is “1”, the first area is write enabled, the upper address 1 is the pixel 1-1 address (sometimes referred to as the source address 1-1), and the lower address is the first address. An address (0) indicating a pixel is written. The address selection unit 120 selects the source address 1-1 as the selection address.

  Here, since the valid bits 1 to 4 are all 0, the cache hit signals 1 to 4 are all “0”, and the cache hit determination signal is also “0”. As a result, the memory control unit 160 reads the data (d1-1 and d1-2) of the source addresses 1-1 and 1-2 as read data and writes it in the first area. At this time, the effective bit 1 becomes “1” (FIG. 11B).

  Next, when the selection signal 2 becomes “1”, the second area 312 of the cache memory 300 is write-enabled, and the upper address 2 is the source address 2-1 and the lower address 2 is the first pixel. The address (0) indicating is written. The address selection unit 120 selects the source address 2-1 as the selection address.

  Here, valid bit 1 is 1, and valid bits 2 to 4 are 0. Since the upper address of the selected address is different from the upper address 1 read from the cache memory 300, the cache hit signals 1 to 4 are all “0” and the cache hit determination signal is also “0”. As a result, the memory control unit 160 reads the data (d2-1 and d2-2) of the source addresses 2-1 and 2-2 as read data and writes it in the second area 312. At this time, the effective bit 2 becomes “1” (FIG. 11C).

  Next, when the selection signal 3 becomes “1”, the third area 313 of the cache memory 300 is write-enabled, indicating that the upper address 3 is the source address 1-1 and the lower address is the second pixel. The indicated address (1) is written. The address selection unit 120 selects the source address 1-1 as the selection address.

  Here, the valid bit 1 and the valid bit 2 are 1, and the valid bit 3 and the valid bit 4 are 0. Since both the selected address and the higher address 1 become the source address 1-1 and coincide with each other, the cache hit signal 1 becomes “1” and the cache hit determination signal also becomes “1”. As a result, the cache hit data selection unit 150 selects the data 1 (d1-1 and d1-2) as the cache hit data and sends it to the write data determination unit 170. The write data determination unit 170 sends the cache hit data to the cache memory 300, and the cache hit data is written in the third area (FIG. 11D).

  Next, when the selection signal 4 becomes “1”, the fourth area 314 of the cache memory 300 is write-enabled, indicating that the upper address 3 is the source address 2-1 and the lower address is the second pixel. The indicated address (1) is written. In the address selection unit, the source address 2-1 is selected as the selection address.

  At this time, the valid bits 1 to 3 are 1 and the valid bit 4 is 0. Since both the selected address and the upper address 2 become the source address 2-1 and match, the cache hit signal 2 becomes “1” and the cache hit determination signal also becomes “1”. As a result, the cache hit data selection unit 150 selects the data 2 (d2-1 and d2-2) as the cache hit data and sends it to the write data determination unit 170. The write data determination unit 170 sends the cache hit data to the cache memory 300, and the cache hit data is written in the fourth area (FIG. 11E).

  After the data is written up to the fourth area, the data is output. Here, since the lower address 1 is 0, the cache data d1-1 is selected as the output data 1, and since the lower address 2 is 0, the cache data d2-1 is selected as the output data 2. Since the address 2 is 1, the cache data d1-2 is selected as the output data 3, and since the lower address 4 is 1, the cache data d2-2 is selected as the output data 4. When these output data 1 to 4 are output, the next address request is sent to the address calculation means.

  Upon receiving the address request, the address calculation means 10 sends the addresses of the pixels 1-2, 2-2, 1-3, and 2-3 as the input addresses 1 to 4 to the destination address b.

  In this case, since the cache hit occurs at the input address 1 (pixel 1-2) and the input address 2 (pixel 2-2), the cache data read from the cache memory is stored as write data (see FIG. 11 (F)).

  On the other hand, since there is no cache hit at the input address 3 (pixel 1-3) and the input address 4 (pixel 2-3), the read data read from the external memory is stored as write data (FIG. 11). (G)).

  After the data is written up to the fourth area, the data is output. Here, since lower address 1 is 1, d1-2 of cache data 1 is selected as output data 1, and since lower address 2 is 1, d2-2 of cache data 2 is selected as output data 2. Since the lower address 3 is 0, the cache data d1-3 is selected as the output data 3, and since the lower address 4 is 0, the cache data d2-3 is selected as the output data 4. When these output data 1 to 4 are output, the next address request is sent to the address calculation means.

  Upon receiving the address request, the address calculation means 10 sends the addresses of the pixels 2-3, 3-3, 2-4, and 3-4 as the input addresses 1 to 4 to the destination address c.

  In this case, at the input address 1 (pixel 2-3) and the input address 3 (pixel 2-4), a cache hit occurs and the input address 2 (pixel 3-3) and the input address 4 (pixel 3-4) Since no cache hit occurs, read data read from the external memory is stored as write data (FIG. 11 (H)).

  After the data is written up to the fourth area, the data is output. Here, since lower address 1 is 0, d2-3 of cache data 1 is selected as output data 1, and since lower address 2 is 0, d3-3 of cache data 2 is selected as output data 2. Since the lower address 3 is 1, d2-4 of the cache data 3 is selected as the output data 3, and since the lower address 4 is 0, d3-4 of the cache data 4 is selected as the output data 4. The When these output data 1 to 4 are output, the next address request is sent to the address calculation means.

  As described above, according to the configuration of the first embodiment, when a cache hit occurs, the data stored in the cache memory is referred to without accessing the external memory. As a result, the number of accesses to the external memory can be reduced, and the processing time can be shortened. Further, the present invention takes into consideration the characteristics of the address that needs to be accessed for the data indicated by the destination address. For this reason, the data stored in the cache memory can be used more efficiently than in the case where data is fetched into the cache memory in block units as in Patent Document 1, so that the speed is increased and the capacity of the cache memory is increased. There is also an effect that can be suppressed.

(Second Embodiment)
A cache circuit according to the second embodiment will be described with reference to FIG. FIG. 12 is a schematic diagram for explaining the cache circuit of the second embodiment.

  The cache circuit 101 includes a cache memory 301, a read control unit 120, an address selection unit 130, a cache hit determination unit 140, a cache hit data selection unit 150, a memory control unit 160, a write data determination unit 171, a write area selection unit 181, and an output. A data selection unit 190, a completion bit determination unit 200, a lead number selection unit 210, a lead number determination unit 220, and a read data selection unit 230 are configured.

  Input addresses 1 to 4 input to the cache circuit 101 are sent to the cache memory 301 and the address selector 130.

  The cache memory 301 includes input addresses 1 to 4 input to the cache circuit 101, selection signals 1 to 4 generated by the read control unit 120, write enable signals 1 to 4 generated by the write area selection unit 181, write The write data selected by the data determination unit 171 and the determined read number generated by the read number determination unit 220 are input. Further, the valid bits 1 to 4 and the upper addresses 1 to 4 are sent from the cache memory 301 to the cache hit determination unit 140, and the lower addresses 1 to 4 are sent to the output data selection unit 190. Further, the cache data 1 to 4 are sent to the cache hit data selection unit 150 and the output data selection unit 190. The completion bits 1 to 4 are sent to the completion bit determination unit 200 and the read number selection unit 210. The lead numbers 1 to 4 are sent to the lead number selection unit 210 and the read data selection unit 230.

  The cache memory will be described with reference to FIG. FIG. 13 is a schematic diagram of a cache memory.

  The cache memory 301 has a plurality of areas. The number of areas that the cache memory 301 has is at least the same as the number of input addresses. Here, the area that the cache memory 301 has is four. Each area of the cache memory 301 is provided with a valid bit field 330, a high-order address field 332, a low-order address field 334, a cache data field 336, a completion bit field 338, and a read number field 340. Address, lower address, cache data, completion bit and read number are stored.

  In the following description, the valid bits, upper addresses, lower addresses, cache data, completion bits, and read numbers stored in the first to fourth areas 321 to 324 are distinguished from each other. -4, lower addresses 1 to 4, cache data 1 to 4, completion bits 1 to 4, and read numbers 1 to 4.

  Here, the valid bit indicates that the area in which the valid bit is stored is valid. When the area is valid, the valid bit is “1”. On the other hand, when the area is invalid, the valid bit is “0”.

  The upper address, the lower address, and the cache data are the same as those in the first embodiment, and a description thereof will be omitted. The completion bit and the read number will be described later.

  Among the input addresses 1 to 4, the upper address is sent to the upper address column 332 of the cache memory 301, and the lower address is sent to the lower address column 334 of the cache memory 301.

  The selection signals 1 to 4 are input to the write enable terminals (we) of the upper address column 332 and the lower address column 334 of the cache memory 301. When the selection signals 1 to 4 are “1”, the upper address and lower address of the input addresses 1 to 4 are written in the upper address column 332 and the lower address column 334 of the cache memory 301, respectively.

  The write data is sent to the cache data column 336 in each of the areas 321 to 324 of the cache memory 301. The write enable signal is input to the write enable terminal (we) of the cache data column 336 of the cache memory 301. When the write enable signals 1 to 4 are “1”, the write data is written in the cache data column 336 of the cache memory 301.

  The write enable signals 1 to 4 are sent to the completion bit column 338, respectively. When the valid bits 1 to 4 are “0” and the write enable signals 1 to 4 are “1”, the valid bits 1 to 4 are “1”. In the initial state, the completion bit column 338 is all “0”, but once the completion bit becomes “1”, that bit is maintained at “1” until initialization is performed again.

Since the configurations of the read control unit 120, the address selection unit 130, the cache hit data selection unit 150, and the memory control unit 160 are the same as those in the first embodiment, description thereof may be omitted.
Note that the read control unit 120 generates a selection signal in which the region to be selected is changed after a certain time Δtsl has elapsed. For example, if the selection signal 1 is “1” and the selection signals 2 to 4 are “0”, the selection signal 1 becomes “0” and the selection signal 2 becomes “1” when the time Δtsl elapses. .

  The cache hit determination unit 140 can be configured similarly to the first embodiment described with reference to FIG. In the second embodiment, the cache hit signal generated by the cache hit determination unit 140 is sent not only to the cache hit data selection unit 150 but also to the completion bit determination unit 200 and the read number selection unit 210.

  When the pixel data indicated by the selected address is stored in the cache memory 301, the cache hit data selection unit 150 receives the cache data stored in each of the areas 321 to 324 of the cache memory 301, and receives the cache hit signals 1 to The data in the area indicated by 4 is selected as cache hit data.

  A configuration example of the completion bit determination unit will be described with reference to FIG. FIG. 14 is a schematic configuration diagram of the completion bit determination unit.

  The completion bit determination unit 200 of this configuration example includes first to fourth AND operation units 202-1 to 20-4 and an OR operation unit 204. In this configuration, logical products (AND) 1 to 4 of the completion bits 1 to 4 and the cache hit signals 1 to 4 calculated by the first to fourth AND operation units 202-1 to 20-4 are respectively ORed. The unit 204 performs a logical sum (OR) operation.

  Since only one of the cache hit signals 1 to 4 is “1”, one of the AND 1 to 4 indicates cache data, and “0” otherwise. Therefore, the completion bit determination signal given by the logical sum of AND1 to AND4 becomes the completion bit of the area indicated by the cache hit signal. The completion bit determination signal is sent to the write data determination unit 171 and the write area selection unit 181.

  When the pixel data indicated by the selected address is stored in the cache memory 301, the write data determination unit 171 selects the cache hit data as write data, and the pixel data indicated by the selected address is stored in the cache memory 301. If not, read data is selected as write data. The write data determination unit 171 sends the write data to the cache memory 301.

  The write data determination unit 171 includes a selection calculation unit 173. The selection calculation unit 173 receives cache hit data and read data. The selection calculation unit 173 receives a completion bit determination signal as a control signal. The selection calculator 173 selects and outputs either cache hit data or read data according to the value of the completion bit determination signal.

  In this configuration, when the completion bit determination signal is “1”, that is, when data corresponding to the selected address is stored in the cache memory, the selection calculation unit 173 selects the cache hit data as write data. On the other hand, when the completion bit determination signal is “0”, that is, when there is no data corresponding to the selected address in the cache memory, the selection calculation unit 173 selects read data as write data.

  When the storage has not been completed and the cache hit has occurred, the read number selection unit 210 selects the read number of the area as the selected read number.

  A configuration example of the lead number selection unit will be described with reference to FIG. FIG. 15 is a schematic configuration diagram of the lead number selection unit.

  The lead number selection unit 210 includes first to fourth first-stage AND operation units 212-1 to 212-4, first to fourth second-stage AND operation units 214-1 to 214-4, and an OR operation unit 216. It is.

  The first to fourth first-stage AND operation units 212-1 to 41-4 perform a logical product (AND) operation of the cache hit signals 1 to 4 and the inverted signals 1 to 4 obtained by logically inverting the completion bits 1 to 4, respectively. Do. The first to fourth second-stage AND operation units 214-1 to 214-4 perform the logical product operation in the first to fourth first-stage AND operation units 212-1 to 212-4 and the logic of the lead numbers 1 to 4. Perform product operation. The OR operation unit 216 performs a logical sum operation on the result of the logical product operation of the first to fourth second-stage AND operation units 214-1 to 214-4.

  The first to fourth first-stage AND operation units 212-1 to 212-4 are set to 1 when the cache hit signal is “1” and the completion bit is “0”, that is, the storage is not completed. The first to fourth second-stage AND operation units 214-1 to 214-4 and the OR operation unit 216 select the lead number of the area where ANDs 1 to 4 are “1”, and output the selected lead number.

  This selected lead number is sent to the lead number determination unit 220.

  The lead number determination unit 220 includes a request counter 222 and a selection calculation unit 224. A cache hit determination signal is input to the request counter 222 after being logically inverted. Therefore, the request counter 222 counts the number of times that a cache hit has not occurred. The request count value counted by the request counter 222 and the lead selection number selected by the lead number selection unit 210 are sent to the selection calculation unit 224. The selection calculation unit 224 receives a cache hit determination signal as a control signal. When the cache hit determination signal is “1”, that is, when a cache hit occurs, the selected read number is output as the determined read number. When the cache hit determination signal is “0”, that is, when no cache hit occurs The request count value is output as the determined lead number.

  The determined read number output from the read number determining unit 220 is sent to the cache memory 301.

  A configuration example of the read data selection unit will be described with reference to FIG. FIG. 16 is a schematic configuration diagram of the read data selection unit.

  The read data selection unit 230 counts the number of times the read data is read from the memory control unit 160 as a read counter value, and if the read counter value and the read number match, the read number that matches the read counter value A read data selection signal is sent to the area where is stored.

  The read data selection unit 230 includes a read data counter 232, first to fourth comparison operation units 234-1 to 234-1, and first to fourth AND operation units 236-1 to 236-1.

  A read data enable signal is input from the memory control unit 160 to the read data counter 232. The read data counter 232 counts the number of times read data is read from the memory control unit 160 as a read data count value. The read data count value is sent to the first to fourth comparison operation units 234-1 to 234-1. The read data count values and the lead numbers 1 to 4 are input to the first to fourth comparison operation units 234-1 to 234-4, and these are compared. The first to fourth comparison operation units 234-1 to 234-4 output “1” when the read numbers 1 to 4 are equal to the read data count value, and output “0” when they are not equal. The first to fourth AND operation units 236-1 to 236-4 perform a logical product operation of the comparison operation result in the first to fourth comparison operation units 234-1 to 234 and the read data enable signal.

  In the first to fourth AND operation units 236-1 to 236-4, read data selection signals 1 to 4 are read data usable for an area where the read number is equal to the read data count value. Indicates whether or not. For example, when the read data selection signal 2 is “1”, it indicates that the read number of the area 2 is equal to the read data count value and the read data stored in the area 2 can be used.

  The read selection signals 1 to 4 are sent to the write area selection unit 181.

  A configuration example of the write area selection unit will be described with reference to FIG. FIG. 17 is a schematic configuration diagram of the write area selection unit.

  The write area selection unit 181 includes first to fourth AND operation units 183-1 to 183-4 and first to fourth OR operation units 186-1 to 186-1. The selection signals 1 to 4 and the completion bit determination signal are input to the first to fourth AND operation units 183-1 to 183-4. AND1 to AND4, which are outputs of the first to fourth AND operation units 183-1 to 183-4, are sent to the first to fourth OR operation units 186-1 to 186-1. The first to fourth OR operation units 186-1 to 186-4 perform a logical sum operation on the AND1 to 4 and the read selection signals 1 to 4, and the result is stored in the cache memory 301 as the write enable signals 1 to 4. send. That is, the write area selection unit 181 caches the area designated by the selection signals 1 to 4 when the completion bit is “1” or when read data having a count value equal to the read number is read. Write to the memory 301.

(Operation of Second Embodiment)
The operation of the cache circuit described above will be described with reference to FIG. FIG. 18 is a schematic diagram for explaining the operation of the cache circuit of the second embodiment, that is, the cache memory control method. FIGS. 18A to 18G show information stored in each column of the cache memory. Here, it is assumed that data for two pixels is written in one area of the cache memory. An example of the relationship between the source image and the destination image described with reference to FIG. 2 will be described.

  In the initial state, all the contents of the cache memory 301 are set to “0” (FIG. 18A).

  Source addresses 1-1, 1-2, 2-1, and 2-2 are input as input addresses 1-4.

  The address selection unit 130 selects the source address 1-1 as the selection address. Since the cache hit determination unit 140 determines a cache hit before the storage in the cache memory 301 is completed, the cache hit signals 1 to 4 are all “0”, and the cache hit determination signal is also “0”. "

  When the selection signal 1 becomes “1”, the first area is write-enabled, and the source address 1-1 is written in the upper address 1 and the address (0) indicating the first pixel is written in the lower address. Also, the effective bit 1 becomes “1”.

  At this stage, the memory control unit 160 starts reading from the external memory.

  Further, the request counter 222 performs counting and writes “1” as the counting result in the read number column (FIG. 18B).

  During this reading, the selection signal 2 becomes “1”.

  In the address selection unit 130, the source address 2-1 is selected as the selection address. Since the cache hit determination unit 140 determines a cache hit before the storage in the cache memory is completed, the cache hit signals 1 to 4 are all “0”, and the cache hit determination signal is also “0”. It becomes.

  When the selection signal 2 becomes “1”, the second area is write-enabled, and the source address 2-1 is written in the upper address 2 and the address (0) indicating the first pixel is written in the lower address. Further, the effective bit 2 becomes “1”.

  At this stage, the memory control unit 160 starts reading from the external memory.

  Further, the request counter 222 performs counting, and “2” as the counting result is written in the read number column (FIG. 18C).

  Next, the selection signal 3 becomes “1”. In this case, the cache hit signal 1 is “1” and the cache hit determination signal is “1”. When the writing is not performed in the first area, the completion number 1 is “0”, so that the lead number 1 is selected and this value is written into the lead number 3. That is, the lead number 3 is 1 (FIG. 18D).

  Next, the selection signal 4 becomes “1”. In this case, the cache hit signal 2 is “1”, and the cache hit determination signal is “1”. When data is not written in the second area, since the completion bit 2 is “0”, the lead number 2 is selected and this value is written in the lead number 4. That is, the lead number 4 is 2 (FIG. 18E).

  Thereafter, when the reading of the first data is completed, the read data counter is incremented by 1 and becomes “1”. Since the read data selection unit 230 constantly compares the read numbers 1 to 4 with the read data count value, when the read data count value is “1”, the comparison results 1 and 3 are “1”. When the data reading is completed, the read data enable signal becomes “1”, so that the read data selection signals 1 and 3 become “1” and are sent to the write area selection unit 181.

  The write area selection unit 181 sets the write enable signals 1 and 3 to 1, and writes read data to the first area and the third area (FIG. 18F).

  Next, when the reading of the second data is completed, the read data counter is incremented by 1, and the read data count value becomes “2”. Since the read data selection unit 230 constantly compares the read numbers 1 to 4 with the read data count value, when the read data count value is “2”, the comparison results 2 and 4 are “1”. When the data reading is completed, the read data enable signal becomes “1”, so that the read data selection signals 2 and 4 become “1” and are sent to the write area selection unit 181.

  In the write area selection unit 181, the write enable signals 2 and 4 are set to 1, and the read data is written in the second area and the fourth area (FIG. 18G).

  After the data is written up to the fourth area, the data is output. This operation is the same as in the first embodiment.

  FIG. 19 is a schematic diagram for explaining a difference in operation between the first embodiment and the second embodiment. FIGS. 19A to 19D show selection signals 1 to 4 of the first embodiment. FIG. 19E shows a read process from the external memory 20. FIGS. 19F to 19I show selection signals 1 to 4 of the second embodiment. FIG. 19J shows a process for reading from the external memory 20.

  Here, the data d1-1 and d1-2 are read from the external memory 20 for the input address 1, the data d2-1 and d2-2 are read from the external memory 20 for the input address 2, and the input address 3 For 4 and 4, an example of reading from the cache memory will be described.

  According to the configuration of the first embodiment, when the selection signal 1 becomes “1” at time t0, the data d1-1 and d1-2 are read from the external memory after the time Δta required until the reading process of the external memory starts. Perform reading process. When the reading process from the external memory is completed, the selection signal 1 becomes “0” and the selection signal 2 becomes “1”. Here, the time required for the reading process from the external memory is represented by Δtb.

  Next, when the selection signal 2 becomes “1”, data d2-1 and d2-2 are read from the external memory.

  When the reading process of the data d2-1 and d2-2 is completed, the selection signal 2 becomes “0” and the selection signal 3 becomes “1”. When the selection signal 3 is “1”, the reading process from the external memory is not performed. Therefore, after the time Δtsl has elapsed, the selection signal 3 becomes “0” and the selection signal 4 becomes “1”.

  Even when the selection signal 4 becomes “1”, the reading process from the external memory is not performed, and therefore the selection signal 4 becomes “0” at time t1 after the time Δtsl has elapsed.

  At time t1, the cache processing for the four addresses is completed, and the process proceeds to output processing.

  On the other hand, according to the configuration of the second embodiment, even when the data d1-1 and d1-2 are being read by the selection signal 1, the selection signal 1 is obtained when the time Δtsl has elapsed. Becomes “0” and the selection signal 2 becomes “1”. As described above, in the configuration of the second embodiment, every time the time Δtsl elapses, the read control unit generates a selection signal in which the region to be selected is changed.

  Regarding the reading process from the external memory, when the reading process of the data d1-1 and d1-2 is completed, the reading process of the next data d2-1 and d2-2 is performed after a predetermined time Δtc has elapsed. The predetermined time Δtc is an interval when the reading process from the external memory is continued.

  Therefore, when processing is started at time t0, in the first embodiment, the cache processing for the four addresses ends at time t1 and proceeds to output processing, whereas in the second embodiment, at time t2, After the cache processing for the four addresses is completed, the output processing can be started.

  As described above, according to the configuration of the second embodiment, when a cache hit occurs as in the first embodiment, the data stored in the cache memory is referred to without accessing the external memory. As a result, the number of accesses to the external memory can be reduced, and the processing time can be shortened.

  Further, before the reading of data from the external memory is completed, the cache hit determination of the next data is performed. Therefore, data can be continuously read from the external memory, the use efficiency of the external memory can be increased, and the processing speed for transferring image data can be further improved.

(Third embodiment)
A cache circuit according to the third embodiment will be described with reference to FIG. FIG. 20 is a schematic diagram for explaining the cache circuit of the third embodiment.

  The cache circuit 102 according to the third embodiment is different from the cache circuit according to the second embodiment in that the cache memory 302 has two surfaces, an A surface and a B surface. Is configured similarly to the cache circuit of the second embodiment. Therefore, the overlapping description may be omitted.

  The cache memory 302 according to the third embodiment includes two surfaces, an A surface and a B surface. The A side and the B side have the same configuration as the cache memory 301 described with reference to FIG. That is, the A side and the B side of the cache memory 302 have a plurality of areas. The number of areas that each of the A side and B side of the cache memory 302 has is at least the same as the number of input addresses, and is four here. Each area of the A side and the B side of the cache memory 302 is provided with an effective bit column 330, an upper address column 332, a lower address column 334, a cache data column 336, a completion bit column 338, and a read number column 340. Each stores a valid bit, an upper address, a lower address, cache data, a completion bit, and a read number.

  The cache memory 302 has an input surface switching unit. The selection signal, the input address, and the write enable signal sent to the cache memory 302 are respectively selected as the destination A side or B side by the input side switching unit. Also for the output of the lead number, the A side or B side is selected as the sending source in the input surface switching unit. The input surface switching unit switches the A surface or the B surface by an input surface switching signal input as a control signal.

  When the input plane switching signal indicates the A plane, the selection signals 1 to 4, the input addresses 1 to 4, and the write enable signals 1 to 4 are sent to the A plane of the cache memory 302. In addition, the lead number stored in the A side is sent to the lead number selection unit 211 and the read data selection unit 230.

  On the other hand, when the input surface switching signal indicates the B surface, the selection signals 1 to 4, the input addresses 1 to 4, and the write enable signals 1 to 4 are sent to the B surface of the cache memory 302. Further, the lead number stored in the B side is sent to the lead number selection unit 211 and the read data selection unit 230.

  The write data and the read number are sent to each area of the A side and B side.

  The valid bit, upper address, cache data, and completion bit sent from the cache memory 302 to the cache hit determination unit 141, cache hit data selection unit 151, completion bit determination unit 201, and read number selection unit 211 are It is stored on both the A and B sides of the cache memory without depending on the switching signal.

  The cache hit determination unit 141, the completion bit determination unit 201, and the read number selection unit 211 are configured in the same manner as in the second embodiment except that the four systems of signals are eight systems.

  The lead number selection unit 211 includes a cache hit signal input surface switching unit and a completion bit input surface switching unit. An input surface switching signal is input as a control signal to the cache hit signal input surface switching unit and the completion bit input surface switching unit.

  The cache hit signal output plane switching section and the completion bit output plane switching section select and output a signal for data stored in the A plane of the cache memory when the input plane switching signal indicates the A plane. When the surface switching signal indicates the B surface, a signal for data stored in the B surface of the cache memory is selected and output. The subsequent processing is the same as in the second embodiment.

  The output data selection unit 190 has an output surface switching unit. An output surface switching signal is input to the output surface switching unit as a control signal.

  Here, the input surface switching signal and the output surface switching signal are complementary signals, and when one indicates the A surface, the other indicates the B surface. The output surface switching unit selects and outputs the data stored in the A surface of the cache memory when the output surface switching signal indicates the A surface, and the cache memory when the output surface switching signal indicates the B surface. The data stored in the B side is selected and output.

  The cache memory is switched according to the value of the output data preparation completion flag. With reference to FIG. 22, the switching of the cache memory plane will be described. FIG. 22A shows cache processing, and FIG. 22B shows output processing.

  The cache memory plane is switched when the cache processing on one side is completed and the output of data from the other side is completed.

  Here, the processing time of output from each surface is constant. The processing time when there are many processes for reading data from the external memory 20 is longer than the processing time for output, and the processing time when there are many processes for reading data from the cache memory is shorter than the processing time for output.

  In the initial state, since the data is not stored in the cache memory on the A side, the cache processing time on the A side becomes long. During this time, output from the B surface is not performed.

  When the A side cache processing is completed, the input surface is switched from the A surface to the B surface, and the output surface becomes the A surface. Thereafter, cache processing is performed on the B side, and at the same time, data is output from the A side.

  In this state, since the data is not stored in the cache memory on the B side, the cache processing time on the B side becomes long. Therefore, the time for performing the cache processing on the B side becomes longer than the processing time required for outputting the data from the A side. When the cache processing on the B surface is completed after the output processing of data from the A surface is completed, the input surface is switched from the B surface to the A surface, and the output surface is switched from the A surface to the B surface.

  In this state, since the data is stored in the cache memory on the A side, the cache processing time on the A side is shorter than the output processing time. Therefore, the time for performing the cache process on the A side is shorter than the time required for the data output process from the B side. When the data output processing on the B surface is completed after the cache processing on the A surface is completed, the input surface is switched from the A surface to the B surface, and the output surface is switched from the B surface to the A surface.

  As described above, according to this configuration, output processing is performed on the other surface while cache processing is performed on one surface of the A surface and the B surface, so compared to the configuration of the second embodiment. In addition, the processing can be performed efficiently.

  Further, in each of the above-described embodiments, an example of using four-point interpolation using data of four pixels of the source image to generate data of one pixel of the destination image has been described. However, the embodiment is limited to four-point interpolation. It is not something. The same effect can be obtained for various interpolation methods such as 6-point interpolation and 8-point interpolation only by changing the number of areas in the cache memory.

It is the schematic of an image data processing circuit. It is a schematic diagram of the relationship between a source image and a destination image. It is the schematic of the cache circuit of 1st Embodiment. It is the schematic of the cache memory of 1st Embodiment. It is a schematic block diagram of an address selection part. It is a schematic block diagram of a cache hit determination part. It is a schematic block diagram of a cache hit data selection part. It is a schematic block diagram of a write data determination part. It is a schematic block diagram of a write area | region selection part. It is a schematic block diagram of an output data selection part. It is a figure for demonstrating the cache memory control method of 1st Embodiment. It is the schematic of the cache circuit of 2nd Embodiment. It is the schematic of the cache memory of 2nd Embodiment. It is a schematic block diagram of a completion bit determination part. It is a schematic block diagram of a lead number selection part. It is a schematic block diagram of a read data selection part. It is a schematic block diagram of a write area | region selection part. It is a figure for demonstrating the cache memory control method of 2nd Embodiment. It is a timing diagram of 1st Embodiment and 2nd Embodiment. It is the schematic for demonstrating the cache circuit of 3rd Embodiment. It is the schematic of the cache memory of 3rd Embodiment. It is a figure for demonstrating the cache memory control method of 3rd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Address calculation means 20 External memory 30 Image data processing means 100, 101, 102 Cache circuit
120 Read control unit 130 Address selection unit 132, 144, 152, 182, 183, 202, 212, 214, 236 AND operation unit 134, 146, 154, 174, 184, 186, 204, 216 OR operation unit 140 Cache hit determination Unit 142, 234 Comparison operation unit 150 Cache hit data selection unit 160 Memory control unit 170, 171 Write data determination unit 172, 173, 192, 224 Selection operation unit 180, 181 Write area selection unit 190 Output data selection unit 200 Completion bit determination Unit 210 Read number selection unit 220 Read number determination unit 222 Request counter 230 Read data selection unit 232 Read data counter 300, 301, 302 Cache memory 311, 312, 313, 314, 321, 3 2,323,324 region 330 valid bit column 332 upper address field 334 lower address field 336 caches the data column 338 is complete bit field 340 leads number field

Claims (7)

A cache circuit having a cache memory storing an address and pixel data indicated by the address in each of the plurality of areas, and reading out and outputting the pixel data indicated by each of the plurality of input addresses input from the cache memory Because
A read control unit for generating a selection signal for selecting one area of the cache memory;
An address selection unit that selects one of the plurality of input addresses as a selection address;
It is determined whether or not the pixel data indicated by the selection address is stored in the cache memory, and a cache hit determination signal indicating the determination result and an area where the pixel data indicated by the selection address is stored A cache hit determination unit for generating a cache hit signal indicating;
A cache hit data selection unit that selects data in an area indicated by the cache hit signal as cache hit data when pixel data indicated by the selection address is stored in the cache memory;
A memory control unit that reads out pixel data indicated by the selected address as read data from an external memory provided outside the cache circuit when data of the pixel indicated by the selected address is not stored in the cache memory;
When the pixel data indicated by the selected address is stored in the cache memory, the cache hit data is selected as write data, while when the pixel data indicated by the selected address is not stored in the cache memory, A write data determination unit that selects read data as write data, sends the write data to the cache memory, and generates a write data determination signal indicating that the write data is usable;
When the write data determination signal indicates that the write data can be used, a write enable signal that enables writing to the cache memory area selected by the selection signal is generated and sent to the cache memory A cache circuit comprising: an area selection unit. In each of the plurality of areas, a valid bit indicating whether or not the area is valid, an address, pixel data indicated by the address, a completion bit indicating whether or not the data is stored, and a read number are stored. A cache circuit having a cache memory and reading out and outputting pixel data indicated by each of a plurality of input addresses from the cache memory;
A read control unit for generating a selection signal for selecting one area of the cache memory;
An address selection unit that selects one of the plurality of input addresses as a selection address;
It is determined whether or not an address equal to the selected address is stored in a valid area of the cache memory, and a cache hit determination signal indicating a determination result and, if stored, stored. A cache hit determination unit that generates a cache hit signal indicating an area;
A cache hit data selection unit that selects data in an area indicated by the cache hit signal as cache hit data when an address equal to the selected address is stored in an effective area of the cache memory;
Memory control for reading pixel data indicated by the selected address as read data from an external memory provided outside the cache circuit when an address equal to the selected address is not stored in a valid area of the cache memory And
When an address equal to the selected address is stored in a valid area of the cache memory and data storage in the area is incomplete, a read that selects the read number of the area as the selected read number A number selector,
An address equal to the selected address is stored in a valid area of the cache memory, and when the storage of data in the area is completed, a completion bit determination unit that outputs a completion bit determination signal;
The number of read data requests to the memory control unit is counted as a request counter value. If there is a cache hit, the selected read number is selected as the determined read number. If there is no cache hit, the request counter value is determined. A lead number determining unit that selects the lead number and sends the determined lead number to the cache memory;
The number of read data read from the memory control unit is counted as a read counter value. If the read counter value matches the read number, the read counter value that matches the read counter value is stored in the area. A read data selection section for sending a read data selection signal;
When the storage of the pixel data indicated by the selected address in the cache memory is completed, the cache hit data is selected as the write data, and the storage of the pixel data indicated by the selected address in the cache memory is not completed. In this case, a write data determination unit that selects the read data as write data and sends the write data to the cache memory;
A write area selection unit that generates a write enable signal that enables writing to the area of the cache memory selected by the selection signal and sends the write enable signal to the cache memory when the write data is usable; Cache circuit. Furthermore, an output data selection unit is provided,
The area of the cache memory stores a plurality of pixel data and a pixel selection address for selecting data stored in each area.
The cache circuit according to claim 1, wherein the output data selection unit selects and outputs pixel data indicated by the selection address from a plurality of data stored in the cache memory. In each of the plurality of areas, a valid bit indicating whether or not the area is valid, an address, pixel data indicated by the address, a completion bit indicating whether or not the data is stored, and a read number are stored. A cache memory having two planes and an input plane switching unit that switches between the two planes in response to an input plane switching signal, and reading out pixel data indicated by each of a plurality of input addresses from the cache memory; A cache circuit for output,
A read control unit for generating a selection signal for selecting one area of the cache memory;
An address selection unit that selects one of the plurality of input addresses as a selection address;
It is determined whether or not an address equal to the selected address is stored in a valid area of the cache memory, and a cache hit determination signal indicating a determination result and, if stored, stored. A cache hit determination unit that generates a cache hit signal indicating an area;
A cache hit data selection unit that selects data in an area indicated by the cache hit signal as cache hit data when an address equal to the selected address is stored in an effective area of the cache memory;
Memory control for reading pixel data indicated by the selected address as read data from an external memory provided outside the cache circuit when an address equal to the selected address is not stored in a valid area of the cache memory And
When an address equal to the selected address is stored in a valid area of the cache memory and data storage in the area is incomplete, a read that selects the read number of the area as the selected read number A number selector,
An address equal to the selected address is stored in a valid area of the cache memory, and when the storage of data in the area is completed, a completion bit determination unit that outputs a completion bit determination signal;
The number of read data requests to the memory control unit is counted as a request counter value. If there is a cache hit, the selected read number is selected as the determined read number. If there is no cache hit, the request counter value is determined. A lead number determining unit that selects and selects the lead number and sends the determined lead number to the cache memory;
The number of read data read from the memory control unit is counted as a read counter value. If the read counter value matches the read number, the read counter value that matches the read counter value is stored in the area. A read data selection section for sending a read data selection signal;
When the storage of the pixel data indicated by the selected address in the cache memory is completed, the cache hit data is selected as the write data, and the storage of the pixel data indicated by the selected address in the cache memory is not completed. In this case, a write data determination unit that selects the read data as write data and sends the write data to the cache memory;
A write area selection unit that generates a write enable signal that enables writing to the area of the cache memory selected by the selection signal when the write data is usable, and sends the write enable signal to the cache memory;
An output data selection unit that selects one of the two surfaces of the cache memory by an output surface switching signal complementary to the input surface switching signal and outputs data stored in the selected surface; A characteristic cache circuit. The area of the cache memory stores a plurality of pixel data and a pixel selection address for selecting data stored in each area.
5. The cache circuit according to claim 4, wherein the output data selection unit selects and outputs data indicated by the pixel selection address from a plurality of data stored in the cache memory. A cache circuit having a cache memory in which an address and pixel data indicated by each address are stored in each of a plurality of areas, and the pixel data indicated by each of a plurality of input addresses is read from the cache memory and output. Hits the,
Generating a selection signal for selecting one area of the cache memory;
Selecting one selected address from the plurality of input addresses;
Determining whether the pixel data indicated by the selected address is stored in a cache memory;
A process of receiving data stored in a plurality of areas of the cache memory when the pixel data indicated by the selection address is stored in a cache memory, and writing to the area selected by the selection signal;
When the pixel data indicated by the selection address is not stored in the cache memory, the data indicated by the selection address is read as read data from an external memory provided outside the cache circuit, and the selection signal selects the data. A cache memory control method comprising: writing to the area. In each of the plurality of areas, the pixel data indicated by each of the plurality of input addresses input in the cache circuit having the cache memory in which the valid bit, the address, the pixel data indicated by the address, the completion bit, and the read number are stored. Is read from the cache memory and output,
Generating a selection signal for selecting one area of the cache memory;
Selecting one selected address from the plurality of input addresses;
Determining whether an address equal to the selected address is stored,
If an address equal to the selected address is not stored,
Adding 1 to the request counter value;
Reading the data indicated by the selected address as read data from an external memory provided outside the cache circuit;
Adding 1 to the read counter value;
The process of writing the read data and the read counter value in the area selected by the selection signal,
When an address equal to the selected address is stored, it is further determined whether or not the completion bit indicates that the storage has been completed,
When the storage is completed, data in which an address equal to the selection address of the cache memory is stored is received, and written to an area selected by the selection signal;
When the storage is incomplete, the read number of the area where the address equal to the selected address of the cache memory is stored is written to the area selected by the selection signal, and the read counter value matches the read number. A cache memory control method, wherein read data is stored when the cache data is read.

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