JP2010028226A - Solid-state imaging element, and imaging apparatus using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging element and the like which provides a highly precise detection signal for exposure control. <P>SOLUTION: The charge storage layer 43 of a photodiode PD stores charges generated according to incident light, a floating diffusion FD receives the charge and converts the charge to a voltage, and a first amplification transistor AMPA outputs signals corresponding to the potential of the floating diffusion. A transfer transistor TX transfers the charge from the charge storage layer 43 to the photodiode PD, a floating gate 46 is turned to the potential corresponding to the charge stored in the charge storage layer 43, and a second amplification transistor outputs signals corresponding to the potential of the floating gate 46. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device and an imaging apparatus using the same.

In the following Patent Document 1, a solid-state imaging device capable of obtaining an exposure control detection signal is proposed. In this solid-state imaging device, a semiconductor region that generates a charge according to incident light is provided separately from a photoelectric conversion unit that obtains an image charge. According to this solid-state imaging device, the amount of light directly incident on the solid-state imaging device can be monitored, so that the amount of incident light can be monitored with high accuracy. Therefore, if this solid-state imaging device is used, automatic exposure control can be realized with high accuracy.
JP-A-11-204769

  An imaging apparatus using a solid-state imaging device is required to realize automatic exposure control with higher accuracy.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a solid-state imaging device capable of obtaining a detection signal for exposure control with higher accuracy, and an imaging apparatus using the same. .

  The following aspects are presented as means for solving the problems. A solid-state imaging device according to a first aspect includes a charge storage unit that stores a charge generated according to incident light, a charge-voltage conversion unit that receives the charge and converts the charge into a voltage, and the charge-voltage conversion unit A first amplifying unit that outputs a signal according to the potential, a transfer unit that transfers charge from the charge storage unit to the charge-voltage conversion unit, and a potential according to the charge stored in the charge storage unit, And a second amplifying section that outputs a signal corresponding to the potential of the floating gate.

  The solid-state imaging device according to a second aspect is the solid-state imaging device according to the first aspect, wherein at least a part of the floating gate is opposed to the charge storage portion via an insulating film.

  In the first or second aspect, the solid-state imaging device according to the third aspect includes a first signal line that receives an output of the first amplification unit, and the first amplification unit for the first signal line. A first selection switch for turning on / off the output of the output, a second signal line provided separately from the first signal line and receiving the output of the second amplification unit, and the second signal line with respect to the second signal line And a second selection switch for turning on / off the supply of the output of the second amplification unit.

  A solid-state imaging device according to a fourth aspect is the solid-state imaging device according to the first or second aspect, wherein a signal line that receives both the output of the first amplifying unit and the output of the second amplifying unit; And a second selection switch for turning on / off the supply of the output of the second amplification unit to the signal line.

  A solid-state imaging device according to a fifth aspect is the solid-state imaging device according to any one of the first to fourth aspects, wherein the second amplifying unit is in a part of the exposure period in which charges are stored in the charge storage unit. The output is to be read.

  In the solid-state imaging device according to the sixth aspect, in any one of the first to fifth aspects, the inversion layer forming potential for forming the inversion layer on the floating gate side in the charge storage unit is controlled by a control signal. In response to the above, a potential supply section for supplying the floating gate is provided.

  The solid-state imaging device according to a seventh aspect is the solid-state imaging device according to the sixth aspect, wherein the potential supply unit excludes an output readout period of the second amplification unit from an exposure period in which charges are accumulated in the charge accumulation unit. The potential for forming the inversion layer is supplied to the floating gate in at least a part of the period.

  The solid-state imaging device according to an eighth aspect is the solid-state imaging device according to any one of the first to seventh aspects, wherein the incident light is incident on the charge accumulation unit from the floating gate side, and the floating gate is the incident light. It has the translucency with respect to.

  In the solid-state imaging device according to a ninth aspect, in any one of the first to seventh aspects, the incident light is incident on the charge accumulation unit from the side opposite to the floating gate.

  A solid-state imaging device according to a tenth aspect according to any one of the first to ninth aspects, includes a plurality of pixels, and each of the pixels includes the charge accumulation unit, the first amplification unit, the transfer unit, The floating gate and the second amplifying unit are included.

  An imaging apparatus according to an eleventh aspect includes the solid-state imaging element according to any one of the first to tenth aspects, and an exposure control unit that performs automatic exposure control based on an output of the second amplification unit. Is.

  ADVANTAGE OF THE INVENTION According to this invention, the solid-state image sensor which can obtain the detection signal for exposure control with higher precision, and an imaging device using the same can be provided.

  Hereinafter, a solid-state imaging device and an imaging device using the same according to the present invention will be described with reference to the drawings.

  [First Embodiment]

  FIG. 1 is a schematic block diagram showing an electronic camera 1 as an imaging device according to the first embodiment of the present invention. The electronic camera 1 is equipped with a photographing lens 2 as an optical system for forming a subject image. The photographing lens 2 is driven by a lens control unit 2a for focus and diaphragm. In the image space of the photographic lens 2, an imaging surface of the solid-state imaging device 3 that photoelectrically converts the subject image formed by the photographic lens 2 via the mechanical shutter 15 is disposed. The mechanical shutter 15 is driven by a command from the imaging control unit 4.

  The solid-state imaging device 3 is driven by a command from the imaging control unit 4 and outputs a signal. Signals output from the solid-state imaging device 3 are an image signal and an exposure control detection signal. Each signal is processed through the signal processing unit 5 and the A / D converter 6 and then temporarily stored in the memory 7. The memory 7 is connected to the bus 8. The bus 8 includes a lens control unit 2a, an imaging control unit 4, a microprocessor 9, a focus calculation unit 10, an exposure calculation unit 14, a recording unit 11, an image compression unit 12, an image processing unit 13, a strobe emission control unit 16, and the like. Connected. The strobe light emission control unit 16 controls the light emission of the built-in or external strobe 17. The microprocessor 9 is connected to an operation unit 9a such as a release button. A recording medium 11a is detachably attached to the recording unit 11 described above. In the present embodiment, a focus detection sensor (not shown) is provided in addition to the solid-state image sensor 3, but as is known, the solid-state image sensor 3 can also obtain a focus detection signal. It may be configured. The operation of the electronic camera 1 will be described later.

  FIG. 2 is a circuit diagram showing a schematic configuration of the solid-state imaging device 3 in FIG. In the present embodiment, the solid-state image sensor 3 is formed as a CMOS solid-state image sensor. The solid-state imaging device 3 includes a plurality of pixels 20 arranged two-dimensionally and a peripheral circuit for outputting a signal from the pixels 20. In FIG. 2, only 3 × 3 pixels 20 are shown, but the number of pixels is not limited to this. These pixels 20 output an image signal and an exposure control detection signal in accordance with a control signal from a peripheral circuit.

  The peripheral circuit includes a vertical scanning circuit 21, a horizontal scanning circuit 22, control signal lines 23 to 27 connected thereto, and an image signal from the pixel 20 for each column of the pixels 20. The first vertical signal line 31A for receiving the pixel, the second vertical signal line 31B provided for each column of the pixels 20 and receiving the detection signal for exposure control from the pixel 20 for each column, and the first and second First and second constant current sources 32A and 32B connected to the vertical signal lines 31A and 31B, respectively.

  The peripheral circuit also transmits a first horizontal signal line 32S for transmitting an optical signal including optical information photoelectrically converted by the pixel 20, and a so-called dark signal as a differential signal including a noise component to be subtracted from the optical signal. A second horizontal signal line 32N for transmission and a differential output amplifier 33 are provided. Further, the peripheral circuit includes a column amplifier 34 connected to each first vertical signal line 31A, an optical signal storage capacitor CS provided corresponding to each column amplifier 34, and stores the optical signal, and the dark signal. A dark signal storage capacitor CN, an optical signal vertical transfer transistor TS, a dark signal vertical transfer transistor TN, an optical signal horizontal transfer transistor HS, and a dark signal horizontal transfer transistor HN. Actually, each transistor for resetting the horizontal signal lines 32S and 32N at a predetermined timing is provided, but the illustration of these transistors is omitted. In the present embodiment, the above-described elements 31A, 32A, 32S, 32N, 33, 34, CS, CN, TS, TN, HS, and HN constitute an image signal output unit.

  Further, the peripheral circuit includes a third horizontal signal line 35 for transmitting an exposure control detection signal and an output amplifier 36. The peripheral circuit has a horizontal transfer transistor HB provided corresponding to the vertical signal line 31B of each column. In the present embodiment, the above-described elements 31B, 32B, 35, 36, and HB constitute an output unit for an exposure control detection signal.

  The vertical scanning circuit 21 and the horizontal scanning circuit 22 output a control signal based on a command from the imaging control unit 4 of the electronic camera 1. Each pixel 20 is driven by receiving control signals φSELB, φTX, φRES, and φSELA, which will be described later, output from the vertical scanning circuit 21 from the control signal lines 23 to 26, and outputs an image signal to the vertical signal line 31A. An exposure control detection signal is output to the vertical signal line 31B. In FIG. 2 and FIG. 3 described later, n indicates a pixel row.

  FIG. 3 is a circuit diagram showing the pixel 20 of the solid-state imaging device 3 shown in FIG. However, some elements 41 to 47, PD, TX, and FD in FIG. 3 are shown as schematic cross-sectional views.

  In the present embodiment, each pixel 20 receives a photodiode PD as a photoelectric conversion unit that generates and accumulates electric charge according to incident light, as in a general CMOS solid-state imaging device, and receives the electric charge. A floating diffusion FD as a charge-voltage conversion unit that converts charges into voltage, a first amplification transistor AMPA as a first amplification unit that outputs a signal corresponding to the potential of the floating diffusion FD, and a floating diffusion from the photodiode PD A transfer transistor TX as a charge transfer unit for transferring charges to the FD, a reset transistor RES as a reset unit for resetting the potential of the floating diffusion FD, and an output of the first amplification transistor AMPA for the first vertical signal line 31A Turn on the supply First and a first selection transistor SELA as a selection switch for, are connected as shown in FIG. In the present embodiment, the transistors AMPA, TX, RES, and SELA of the pixel 20 are all nMOS transistors. In FIG. 3, Vdd is a power supply voltage.

  The gate electrode 45 of the transfer transistor TX is connected to the control signal line 24 for each row. The control signal line 24 supplies a control signal φTX for controlling the transfer transistor TX from the vertical scanning circuit 21 to the gate electrode 45 of the transfer transistor TX. The gate of the reset transistor RES is connected to the control signal line 25 for each row. The control signal line 25 supplies a control signal φRES for controlling the reset transistor RES from the vertical scanning circuit 21 to the gate of the reset transistor RES. The gate of the first selection transistor SELA is connected to the control signal line 26 for each row. The control signal line 26 supplies a control signal φSELA for controlling the first selection transistor SELA from the vertical scanning circuit 21 to the gate of the first selection transistor SELA.

  In the present embodiment, a P-type well 42 is provided on an N-type silicon substrate 41 as shown in FIG. In the P-type well 42, each element in the pixel portion such as the photodiode PD is arranged. FIG. 3 also schematically shows the state of incident light on the photodiode PD. In the present embodiment, incident light is incident on the charge storage layer 43 of the photodiode PD from above in FIG. 3 (from the side of a floating gate 46 described later). In practice, a color filter, a microlens, and the like are disposed above the photodiode PD (above the floating gate 46), but are omitted here.

  The photodiode PD generates an electric charge according to the amount of incident light (subject light). In the present embodiment, the photodiode PD has an N-type charge storage layer 43 provided in the P-type well 42 as a charge storage unit that stores charges generated according to incident light.

  The transfer transistor TX is turned on during a high level period of the transfer pulse (control signal) φTX, and transfers the charge accumulated in the charge accumulation layer 43 of the photodiode PD to the floating diffusion FD. The floating diffusion FD has an N-type impurity diffusion region 44 formed in the P-type well 42. The transfer transistor TX is a MOS transistor having the charge storage layer 43 of the photodiode PD as a source and the diffusion region 44 constituting a part of the floating diffusion FD as a drain. The transfer transistor TX is driven by a control signal φTX applied to the gate electrode 45. The gate electrode 45 is made of, for example, polysilicon. The reset transistor RES is turned on during a high level period of the reset pulse (control signal) φRES, and resets the charge accumulated in the floating diffusion FD.

  The charges transferred from the photodiode PD to the floating diffusion FD via the transfer transistor TX are converted into a voltage by the floating diffusion FD, and this voltage is applied to the gate of the first amplification transistor AMPA. The first amplification transistor AMPA has its drain connected to the power supply voltage Vdd, its gate connected to the floating diffusion FD, its source connected to the drain of the first selection transistor SELA, and the constant current source 32A as a load. A force follower circuit is configured. The first amplification transistor AMPA outputs a voltage to the first vertical signal line 31A via the first selection transistor SELA according to the voltage value of the floating diffusion FD. In this way, the first amplification transistor AMPA outputs an electrical signal (image signal) corresponding to the amount of charge generated and accumulated by the photodiode PD.

  The first selection transistor SELA is turned on during the high level period of the selection pulse (control signal) φSELA, and connects the source of the first amplification transistor AMPA to the first vertical signal line 31A. That is, reading by the source follower is possible by the first amplification transistor AMPA and the first selection transistor SELA.

  The configuration of each pixel 20 described above is the same as that of a general CMOS solid-state image sensor. In the present embodiment, the configuration of each pixel 20 is different from a general CMOS solid-state imaging device in the points described below.

  In the present embodiment, as shown in FIG. 3, each pixel 20 has a floating gate 46 having a potential corresponding to the charge stored in the charge storage layer 43 of the photodiode PD, and a potential corresponding to the potential of the floating gate 46. A second amplifying unit AMPB as a second amplifying unit for outputting the received signal and a second selecting switch as a second selection switch for turning on / off the supply of the output of the second amplifying transistor AMPB to the second vertical signal line 31B. Select transistor SELB. In the present embodiment, these transistors AMPB and SELB are also nMOS transistors and are mounted on the substrate 41.

  In the present embodiment, as shown in FIG. 3, most of the region of the floating gate 46 is opposed to the charge storage layer 43 of the photodiode PD with the insulating film 47 interposed therebetween. As a result, the potential of the floating gate 46 becomes a potential corresponding to the charge accumulated in the charge accumulation layer 43 and is applied to the gate of the second amplification transistor AMPB. In the present embodiment, the floating gate 46 is made of a material that transmits light with respect to incident light. The floating gate 46 can be composed of, for example, an ITO film or a thin polysilicon film of about 50 nm.

  The gate of the second selection transistor SELB is connected to the control signal line 23 for each row. The control signal line 23 supplies a control signal φSELB for controlling the second selection transistor SELB from the vertical scanning circuit 21 to the gate of the second selection transistor SELB. The second selection transistor SELB is turned on during the high level period of the selection pulse (control signal) φSELB, and connects the source of the second amplification transistor AMPB to the second vertical signal line 31B. That is, reading by the source follower is possible by the second amplification transistor AMPB and the second selection transistor SELB.

  The second amplification transistor AMPB has its drain connected to the power supply voltage Vdd, its gate connected to the floating gate 46, its source connected to the drain of the second selection transistor SELB, and the constant current source 32B as a load. A force follower circuit is configured. The second amplifying transistor AMPB receives a read current from the second vertical signal line 31B via the second selection transistor SELB in accordance with the potential of the floating gate 46 (that is, the charge accumulated in the charge accumulation layer 43). Is output. In this way, the second amplification transistor AMPB outputs an electrical signal (exposure control detection signal) corresponding to the amount of charge generated and accumulated by the photodiode PD. By using the floating gate 46, the charge stored in the charge storage layer 43 is not destroyed and the charge amount is read out.

  The vertical scanning circuit 21 receives a driving pulse (not shown) from the imaging control unit 4 and outputs first and second selection pulses φSELA and φSELB, a reset pulse φRES, and a transfer pulse φTX for each row of the pixels 20. Output each. The vertical scanning circuit 21 receives a drive pulse (not shown) from the imaging control unit 4 and outputs an optical signal transfer pulse φTS and a dark signal transfer pulse φTN. The optical signal transfer pulse φTS is commonly supplied to the gates of the optical signal vertical transfer transistors TS of all the columns. The dark signal transfer pulse φTN is commonly supplied to the gates of the dark signal vertical transfer transistors TN of all the columns.

  The horizontal scanning circuit 22 receives a driving pulse (not shown) from the imaging control unit 4 and outputs a horizontal scanning signal φH for each column of the pixels 20. The horizontal scanning signal φH is supplied to the gates of the optical signal horizontal transfer transistor HS, the dark signal horizontal transfer transistor HN, and the horizontal transfer transistor HB via the control signal line 27 for each column.

  FIG. 4 is a timing chart showing an example of the operation of the solid-state imaging device 3 shown in FIG. FIG. 4 shows only signals related to the pixels 20 in the first and second rows. In the example shown in FIG. 4, an exposure control detection signal is acquired from the solid-state imaging device 3 during the exposure period (charge accumulation period) T1, and the length of the exposure period T1 is determined based on the exposure control detection signal. Exposure control is performed, and an image signal based on accumulated charges in the exposure period T1 is read from the solid-state imaging element 3 in the image signal readout period T2 after the exposure period T1.

  In this example, the mechanical shutter 15 is opened during the exposure period T1 under the control of the imaging control unit 4. Although not shown in the drawing, before the exposure period T1, the transfer pulse φTX of all rows is changed in a state where the reset pulse φRES of all rows is set to a high level and the reset transistors RES of all rows are turned on. The charge storage layers 43 of all the pixels 20 are reset in advance by once turning on the transfer transistors TX of all the rows once set to the high level.

  When the exposure period T1 starts, charges are accumulated in the charge accumulation layer 43 of the photodiode PD by incident light, and the potential of the floating gate 46 is a potential corresponding to the amount of charges accumulated in the charge accumulation layer 43. Become.

  When the exposure period T1 starts, first, in the period T11, the second selection pulse φSELB (1) in the first row changes to the high level, and the second selection transistor SELB in the first row is turned on. As a result, the pixels 20 in the first row are selected as pixels for obtaining the exposure control detection signals, and the exposure control detection signals (output signals of the second amplification transistors AMPB) of the pixels 20 in the first row are the second. It is output to the vertical signal line 31B. That is, the source of the second amplification transistor AMPB of the pixel 20 in the first row is connected to the second vertical signal line 31B, and the source follower operation of the second amplification transistor AMPB corresponds to the potential of the floating gate 46. The signal is output to the second vertical signal line 31B. This operation is performed simultaneously and in parallel on the pixels 20 in each column of the first row.

  In this period T11, the horizontal transfer transistor HB is sequentially turned on for each column by the horizontal scanning signal φH from the horizontal scanning circuit 22, and from the first row of pixels 20 output to the second vertical signal line 31B. The exposure control detection signal is sequentially read out to the horizontal signal line 35 for each column, amplified by the output amplifier 36, and output to the outside.

  In a period T12 after the period T11, the readout operation of the detection signal for exposure control similar to that in the period T11 is performed on the pixels 20 in the second row. That is, in the period T12, the second selection pulse φSELB (2) in the second row changes to a high level, the second selection transistor SELB in the second row is turned on, and the horizontal scanning signal φH from the horizontal scanning circuit 22 turns on. The horizontal transfer transistors HB are sequentially turned on for each column.

  After the period T12, the readout operation of the exposure control detection signal similar to the periods T11 and T12 is sequentially performed on the pixels 20 in the third and subsequent rows.

  In this manner, the first exposure control detection signal readout operation is performed for all the pixels 20. The exposure control detection signal read from the solid-state imaging device 3 is temporarily stored in the memory 7 via the signal processing unit 5 and the A / D converter 6 shown in FIG. When the reading operation of the first exposure control detection signal for all the pixels 20 is completed and stored in the memory 7, the exposure calculation unit 14 uses, for example, the exposure of all the pixels 20 as an index value indicating the exposure amount. An average value of the control detection signals is calculated, and it is determined whether or not the average value is within a predetermined appropriate exposure range. If within the proper exposure range, the imaging control unit 4 closes the mechanical shutter 15 and ends the exposure period T1. On the other hand, if it is not within the proper exposure range, the imaging control unit 4 keeps the mechanical shutter 15 open, and the second and subsequent exposure control detection signal readout operations are performed, and the exposure control detection signal readout is performed each time. Every time the operation is completed, the above-described average value calculation / determination is performed for the exposure control detection signal, and the average value calculated for the exposure control detection signal is within the appropriate exposure range. The reading operation of the next exposure control detection signal is repeated.

  In the example shown in FIG. 4, the second exposure control detection signal reading operation starting from the period T13 and the third exposure control detection signal reading operation starting from the period T14 are performed, and the third exposure control detection operation is performed. It shows a situation in which the exposure period T1 is ended when the average value calculated for the detection signal is within the appropriate exposure range.

  In the exposure period T1, the amount of charge stored in the charge storage layer 43 of the photodiode PD is only read out through the path of the floating gate 46 and the second amplification transistor AMPB. The electric charge is accumulated as it is without being destroyed. In this example, in the image signal readout period T2 after the exposure period T1, the amount of accumulated charges accumulated in the charge accumulation layer 43 during the exposure period T1 is expressed as the transfer transistor TX, the floating diffusion FD, and the first amplification transistor. Read by AMPA route.

  When the image signal readout period T2 starts, first, in the period T21, the pixels 20 in the first row are selected as pixels for acquiring the image signals, and the reset pulse φRES (1) in the first row changes to a low level. The reset transistor RES of the pixels 20 in the first row is turned off. In the period T21, the first selection pulse φSELA (1) in the first row changes to a high level, and the first selection transistor SELA in the pixels 20 in the first row is turned on. When the first selection transistor SELA of the pixel 20 in the first row is turned on, the source of the first amplification transistor AMPA of the pixel 20 in the first row is connected to the first vertical signal line 31A. The first amplification transistor AMPA of the pixel 20 in the first row operates as a source follower circuit by the constant current source 32A.

  In the period from the start of the period T21 to the start of the period T32, the gate voltage of the first amplification transistor AMPA of the pixels 20 in the first row is in a floating state, and the reset level of the pixels 20 in the first row is It appears on the first vertical signal line 31A. At this time, in the period T31 after the period T21 starts, the dark signal transfer pulse φTN changes to the high level, and the dark signal vertical transfer transistor TN is turned on. As a result, the dark signal of the pixels 20 in the first row is amplified by the column amplifier 34 and then stored in the dark signal storage capacitor CN. This operation is performed simultaneously and in parallel on the pixels 20 in each column of the first row.

  Next, in the period T32 in the period T21, the transfer pulse φTX (1) in the first row changes to a high level, and the transfer transistor TX of the pixels 20 in the first row is turned on. When the transfer transistor TX of the pixel 20 in the first row is turned on, the charge accumulated in the charge accumulation layer 43 of the photodiode PD of the pixel 20 in the first row is transferred to the corresponding floating diffusion FD. The Thus, the voltage of the floating diffusion FD becomes a voltage corresponding to the transferred charge amount, and this voltage is applied to the gate of the first amplification transistor AMPA. As a result, a level including the optical information of the pixels 20 in the first row appears on the first vertical signal line 31A. At this time, in the period T33 after the period T32, the optical signal transfer pulse φTS changes to the high level, and the optical signal vertical transfer transistor TS is turned on. As a result, the optical signal of the pixels 20 in the first row is amplified by the column amplifier 34 and then stored in the optical signal storage capacitor CS. This operation is performed simultaneously and in parallel on the pixels 20 in each column of the first row.

  In this way, in the period T21, the image signal of the pixels 20 in the first row is sampled, and the dark signal of the pixels 20 in the first row is accumulated in the dark signal storage capacitor CN for each column. The optical signal storage capacitor CS stores the optical signal of the pixels 20 in the first row.

  A period T22 after the period T21 is a horizontal scanning period of the image signal of the pixels 20 in the first row. In the period T22, the dark signal horizontal transfer transistor HN and the optical signal horizontal transfer transistor HS are sequentially turned on for each of the vertical signal lines 31A by horizontal scanning using the horizontal scanning signal φH from the horizontal scanning circuit 22, and the storage capacitor CN , CS are sequentially read out to the second horizontal signal line 32N and the first horizontal signal line 32S for each of the signals corresponding to the vertical signal lines 31A, and the differential signals are output. The amplifier 33 obtains a difference between these signals and outputs the difference. By taking the difference in this way, correlated double sampling is realized, and an optical information signal from which fixed pattern noise and the like are removed is obtained.

  Next, in the periods T23 and T24, operations similar to those performed in the periods T21 and T22 for the pixels 20 in the first row are performed for the pixels 20 in the second row, and similar operations are performed in the subsequent rows. repeat. In this manner, the image signal readout operation is performed for all the pixels 20.

  Here, an example of the operation of the electronic camera 1 according to the present embodiment will be described.

  When a half-press operation of the release button of the operation unit 9a is performed, the microprocessor 9 in the electronic camera 1 causes the focus calculation unit 10 to calculate the defocus amount based on a detection signal from a focus detection sensor (not shown). Next, the microprocessor 9 causes the lens control unit 2a to adjust the photographing lens 2 so that the in-focus state is obtained according to the previously calculated defocus amount. Further, the microprocessor 9 causes the lens control unit 2a to adjust the photographing lens 2 so that the aperture is instructed in advance by the operation unit 9a.

  The microprocessor 9 performs shooting by driving the imaging control unit 4 so as to realize the above-described operation shown in FIG. 4 in synchronization with the full pressing operation of the release button of the operation unit 9a. At this time, automatic exposure control in which the length of the exposure period T1 is determined so as to achieve proper exposure based on the detection signal for exposure control obtained from the solid-state imaging device 3 during the exposure period T1 (here, aperture priority automatic) (Exposure control) is realized, and an image signal based on the accumulated charges during the exposure period T1 is read from the solid-state imaging device 3. The image signal is stored in the memory 7 by the imaging control unit 4.

  Thereafter, the microprocessor 9 performs desired processing on the image signal in the memory 7 by the image processing unit 13 and the image compression unit 12 as necessary based on the command of the operation unit 9a, and the recording unit 11 The processed signal is output and recorded on the recording medium 11a.

  In the description of the operation example described above, the automatic exposure control has been described as determining the shutter time from the output of the solid-state imaging device 3 in a bright environment such as daytime. In the case of shooting with strobe light emission in a dark environment such as at night, for example, the following is performed. That is, the imaging control unit 4 opens the mechanical shutter 15 for a predetermined relatively long time (a period longer than the light emission period of the strobe 17). The strobe light emission control unit 16 causes the strobe 17 to start light emission in a state where the mechanical shutter 15 is opened. Then, an operation in which the exposure period T1 is set as the strobe light emission period in the above description may be performed. At this time, instead of determining the length of the open period of the mechanical shutter 15 based on the exposure control detection signal obtained from the solid-state imaging device 3, the imaging control unit 4 does not use the strobe light emission. The control unit 16 determines the length of the light emission period of the strobe 17. Thereby, automatic exposure control using the strobe 17 can be realized.

  Note that the output of the second amplification transistor AMPB corresponding to the potential of the floating gate 42 has a worse S / N than the output of the first amplification transistor AMPA corresponding to the voltage of the floating diffusion FD. For this reason, the output of the second amplification transistor AMPB is not preferable as an image signal. However, the output of the second amplification transistor AMPB has a sufficient S / N as an exposure control signal.

  According to the present embodiment, as described above, the exposure control detection signal corresponding to the amount of charge accumulated in the charge accumulation layer 43 of the photodiode PD for accumulating the charge for forming the image signal, It can be obtained from the solid-state imaging device 3 through the path of the floating gate 46 and the second amplification transistor AMPB. Therefore, according to the present embodiment, exposure control detection is performed from charges generated by incident light in a semiconductor region separate from the charge storage layer 43 of the photodiode PD for storing charges forming an image signal. The detection signal for exposure control can be obtained from the solid-state imaging device 3 with higher accuracy than in the case of obtaining a signal. Therefore, according to the present embodiment, automatic exposure control can be realized with higher accuracy.

  In the present embodiment, as described above, the image signal is obtained by the charges accumulated in the charge accumulation layer 43 during the exposure period T1 in which the exposure control detection signal is acquired. Accordingly, since the amount of charge that is actually stored as an image signal can be directly monitored as an exposure control detection signal, automatic exposure control can be realized with higher accuracy. In the present embodiment, the exposure period T1 is used both as a charge accumulation period for obtaining an exposure control detection signal and as a charge accumulation period for obtaining an image signal. Therefore, according to the present embodiment, real-time automatic exposure control is realized for the image signal, and automatic exposure control can be realized with higher accuracy.

  However, in the present invention, when the solid-state imaging device 3 is used, the charge accumulation period for obtaining the exposure control detection signal and the charge accumulation period for obtaining the image signal may be separated. In this case, for example, it can be performed as follows. First, a charge accumulation period for obtaining an exposure control detection signal is performed for a predetermined length, and starts from a period T11 or the like in FIG. 4 in the last period or after the charge accumulation period. A reading operation of the detection signal for exposure control is performed once. Next, after the charge storage layer 43 is once reset, a charge storage period for obtaining an image signal is performed, and then an image signal read period T2 shown in FIG. 4 is performed. At this time, for example, the length of the charge accumulation period for obtaining the image signal may be determined so as to achieve proper exposure based on the previously obtained exposure control detection signal. In this case, the series of operations described above may be performed in synchronization with the full pressing operation of the release button of the operation unit 9a. Alternatively, in synchronization with the half-press operation of the release button of the operation unit 9a, the charge accumulation period for obtaining the exposure control detection signal is performed for a predetermined length, and in the last period in the charge accumulation period, or the charge After the accumulation period, a single exposure control detection signal reading operation starting from the period T11 in FIG. 4 is performed, and exposure conditions (aperture and shutter time) are determined based on the exposure control detection signal. In synchronism with the full-pressing operation of the release button of the unit 9a, the charge storage layer 43 is once reset, and then a charge storage period for obtaining an image signal is performed according to the previously determined exposure conditions. The illustrated image signal readout period T2 may be performed. In this case, not only aperture-priority automatic exposure control but also shutter time-priority automatic exposure control can be realized.

  Further, when automatic exposure control using the strobe 17 is performed in the case where the charge accumulation period for obtaining the exposure control detection signal and the charge accumulation period for obtaining the image signal are separated, for example, the operation unit 9a In synchronization with the half-pressing operation of the release button, the strobe 17 is pre-flashed, and the pre-flash period is set as a charge accumulation period for obtaining a detection signal for exposure control. In the last period in the charge accumulation period or After the charge accumulation period, one exposure control detection signal readout operation starting from the period T11 in FIG. 4 is performed, and the exposure conditions (the aperture and light emission period of the strobe 17) are set based on the exposure control detection signal. The charge accumulation layer 43 is once reset in synchronization with the full pressing operation of the release button of the operation unit 9a, and then a charge accumulation period for obtaining an image signal is performed. May perform image signal read period T2 shown in FIG. 4 after.

  In the present invention, the method of automatic exposure control using the solid-state imaging device 3 is not limited to the above examples. For example, in the above-described example, the average value of the detection signals for exposure control of all the pixels 20 is used as the index value indicating the exposure amount. Instead, the exposure control of the pixels 20 in a predetermined partial area is used instead. The average value of the detection signals for detection, the average value of the detection signals for exposure control of the pixels 20 in some areas manually or automatically determined according to the shooting conditions of the subject or the like may be used. When only the detection signals for exposure control from the pixels 20 in a predetermined partial area are always used, the floating gate 46, the second amplification transistor AMPB, and the second selection transistor SELB are used from the pixels 20 in the other areas. May be removed. In the present invention, it is sufficient that at least one pixel 20 has the floating gate 46 and the like.

  The present invention can be applied not only to still image capturing but also to moving image capturing. For example, the exposure period T1 and the image signal readout period T2 shown in FIG. 4 are sequentially repeated, and the image obtained in each image signal readout period T2 is adjusted by adjusting the length of each exposure period T1 by the automatic exposure control described above. The signal may be displayed in a so-called live view on a display unit such as a liquid crystal panel (not shown). In this case, it is possible to obtain a live view display image in which automatic exposure control is performed with high accuracy following changes in the brightness of the subject.

  [Second Embodiment]

  FIG. 5 is a circuit diagram showing a schematic configuration of the solid-state imaging device 53 used in the electronic camera according to the second embodiment of the present invention, and corresponds to FIG. FIG. 6 is a circuit diagram showing the pixel 20 of the solid-state imaging device 53 shown in FIG. 5, and corresponds to FIG. FIG. 7 is a timing chart showing an example of the operation of the solid-state imaging device 53 shown in FIG. 5, and corresponds to FIG. 5 to 7, the same or corresponding elements as those in FIGS. 2 to 4 are denoted by the same reference numerals, and redundant description thereof is omitted.

  The electronic camera according to the present embodiment differs from the electronic camera 1 according to the first embodiment only in that a solid-state image sensor 53 is used instead of the solid-state image sensor 3. The difference between the solid-state imaging device 53 and the solid-state imaging device 3 is that the horizontal signal line 35, the output amplifier 36, the vertical signal line 31B, the horizontal transfer transistor HB and the constant current source 32B are removed, and the second amplification transistor of each pixel 20 is removed. The only difference is that the source of AMPB is connected to the vertical signal line 31A of the corresponding column. As a result, in the present embodiment, the elements 31A, 32A, 32S, 33, 34, CS, TS, and HS that constitute the image signal output unit are also used as the exposure control detection signal output unit. .

  The operation example shown in FIG. 7 of the solid-state image sensor 53 is different from the operation example shown in FIG. 4 of the solid-state image sensor 3 only in the operation during the exposure period T1.

  In the operation example shown in FIG. 7, when the exposure period T1 starts, first, in the period T41, the second selection pulse φSELB (1) in the first row changes to the high level, and the second selection transistor in the first row. SELB turns on. Thereby, the pixels 20 in the first row are selected as pixels for obtaining the exposure control detection signals, and the exposure control detection signals (output signals of the second amplification transistors AMPB) of the pixels 20 in the first row are used as the vertical signal lines. It is output to 31A. At the same time, in the period T41, the transfer pulse φTS changes to the high level, and the vertical transfer transistor TS is turned on. Thus, the exposure control detection signal for the pixels 20 in the first row is amplified by the column amplifier 34 and then stored in the storage capacitor CS. This operation is performed simultaneously and in parallel on the pixels 20 in each column of the first row. Note that the output signal of the second amplification transistor AMPB has a relatively low level. Therefore, when a variable gain amplifier is used as the column amplifier 34, when the exposure control detection signal is output to the vertical signal line 31A in order to increase the S / N ratio, the gain of the column amplifier 34 is set by a control signal (not shown). It is preferable to set a large value.

  In a period T42 after the period T41, the horizontal transfer transistor HS is sequentially turned on for each column by the horizontal scanning signal φH from the horizontal scanning circuit 22, and the exposure control detection signal stored in the storage capacitor CS is applied to the horizontal signal line 32S. Reading is performed, and an exposure control detection signal is output to the outside via the differential output amplifier 33. In this example, during the exposure period T1, the horizontal signal line 32N is reset and maintained at the reset potential, so that the exposure control detection signal stored in the storage capacitor CS is read out to the horizontal signal line 32S. The detection signal for exposure control is output from the differential output amplifier 33.

  Next, in the periods T43 and T44, operations similar to those performed in the periods T41 and T42 for the pixels 20 in the first row are performed for the pixels 20 in the second row, and the pixels 20 in the subsequent rows are also performed. The same operation is repeated. In this manner, the exposure control detection signal readout operation is performed for all the pixels 20.

  Also in this example, the exposure control detection signal read from the solid-state imaging device 3 is temporarily stored in the memory 7 via the signal processing unit 5 and the A / D converter 6 shown in FIG. When the reading operation of the first exposure control detection signal for all the pixels 20 is completed and stored in the memory 7, the exposure calculation unit 14 uses, for example, the exposure of all the pixels 20 as an index value indicating the exposure amount. An average value of the control detection signals is calculated, and it is determined whether or not the average value is within a predetermined appropriate exposure range. If within the proper exposure range, the imaging control unit 4 closes the mechanical shutter 15 and ends the exposure period T1. On the other hand, if it is not within the proper exposure range, the imaging control unit 4 keeps the mechanical shutter 15 open, and the second and subsequent exposure control detection signal readout operations are performed, and the exposure control detection signal readout is performed each time. Every time the operation is completed, the above-described average value calculation / determination is performed for the exposure control detection signal, and the average value calculated for the exposure control detection signal is within the appropriate exposure range. The reading operation of the next exposure control detection signal is repeated.

  In the example shown in FIG. 7, the second exposure control detection signal read operation starting from the period T45 and the third exposure control detection signal read operation starting from the period T46 are performed, and the third exposure control detection operation is performed. It shows a situation in which the exposure period T1 is ended when the average value calculated for the detection signal is within the appropriate exposure range.

  Also in this embodiment, the same advantages as those in the first embodiment can be obtained. Further, in this embodiment, the horizontal signal line 35, the output amplifier 36, the vertical signal line 31B, the horizontal transfer transistor HB, and the constant current source 32B are removed as compared with the first embodiment. Can be simplified and the cost can be reduced.

  [Third Embodiment]

  FIG. 8 is a circuit diagram showing a schematic configuration of the solid-state imaging device 63 used in the electronic camera according to the third embodiment of the present invention, and corresponds to FIG. FIG. 9 is a circuit diagram showing the pixel 20 of the solid-state imaging device 63 shown in FIG. 8, and corresponds to FIG. FIG. 10 is a timing chart showing an example of the operation of the solid-state imaging device 63 shown in FIG. 8, and corresponds to FIG. 8 to 10, elements that are the same as or correspond to those in FIGS. 5 to 7 are given the same reference numerals, and redundant descriptions thereof are omitted.

  The electronic camera according to the present embodiment differs from the electronic camera according to the second embodiment only in that a solid-state image sensor 63 is used instead of the solid-state image sensor 53. The solid-state image sensor 63 is different from the solid-state image sensor 53 only in the points described below.

  In the solid-state imaging device 63, a potential supply transistor 64 is added to each pixel 20 as a potential supply unit that supplies the inversion layer forming potential Vpin to the floating gate 46 in response to the control signal φP. The inversion layer forming potential Vpin is a potential for forming an inversion layer on the floating gate 46 side in the charge storage layer 43 of the photodiode PD. In the present embodiment, since the charge storage layer 43 is N-type, a negative voltage is used as the inversion layer forming potential Vpin. The inversion layer forming potential Vpin is supplied as, for example, a power supply voltage. In the present embodiment, an nMOS transistor is used as the potential supply transistor 64. The source of the potential supply transistor 64 is connected to the inversion layer forming potential Vpin. The drain of the potential supply transistor 64 is connected to the floating gate 46.

  The gate of the potential supply transistor 64 is connected to the control signal line 65 for each row. The control signal line 65 supplies a control signal φP for controlling the potential supply transistor 64 from the vertical scanning circuit 21 to the gate of the potential supply transistor 64. The potential supply transistor 64 is turned on during the high level period of the control signal φP, and applies the inversion layer forming potential Vpin to the floating gate 46. When a negative voltage inversion layer formation potential Vpin is applied to the floating gate 46, a hole 66 is induced on the charge storage layer 43 on the floating gate 46 side to form a P-type inversion layer, and the photodiode PD is embedded. It will function as a photodiode. As a result, dark current generated from the surface of the charge storage layer 43 can be reduced, and the SN ratio can be increased. Further, after the charge is accumulated in the charge accumulation layer 43, when the transfer pulse φTX is set to the high level and the charge is transferred to the floating diffusion FD, if the inversion layer forming potential Vpin is applied to the floating gate 46, It is also possible to obtain an effect that charge transfer is facilitated (charge can be completely transferred without any transfer residue).

  In the operation example shown in FIG. 10, for each row, an inverted signal of the selection pulse φSELB (n) in the nth row is used as the control signal φP (n) in the nth row. As a result, with respect to each charge storage layer 43, the inversion layer is added to the floating gate 46 in all periods except for the readout period of the detection signal for exposure control from the floating gate 46 provided corresponding to the charge storage layer 43. A forming potential Vpin is applied. Therefore, this embodiment is preferable because the effect of reducing the dark current and the effect of facilitating charge transfer can be most effectively obtained. However, it is not necessarily limited to this. For example, the period during which the inversion layer forming potential Vpin is applied to the floating gate 46 of the pixel 20 in the n-th row is the readout period (φSELB) of the output of the second amplification transistor AMPB of the pixel 20 in the n-th row in the exposure period T1. Only a part of the period other than the period (n) is a high level) may be used. Even in this case, the dark current can be reduced as compared with the second embodiment.

  Note that the present embodiment can provide the same advantages as those of the second embodiment. In the first embodiment, the potential supply transistor 64 may be added as in the present embodiment.

  [Fourth Embodiment]

  FIG. 11 is a circuit diagram showing a pixel 20 of a solid-state imaging device used in an electronic camera according to the fourth embodiment of the present invention, and corresponds to FIG. 11, elements that are the same as or correspond to those in FIGS. 2 to 4 are given the same reference numerals, and redundant descriptions thereof are omitted.

  For example, Japanese Patent Laid-Open No. 2002-231930 discloses a so-called back-illuminated solid-state imaging device (a solid-state imaging device that makes incident light incident from the side opposite to a normal solid-state imaging device).

  In the present embodiment, in accordance with such a solid-state imaging device, the solid-state imaging device 63 is modified to a back-illuminated type in the third embodiment. In the present embodiment, light is irradiated from the back surface of the substrate 41 as shown in FIG. Although not shown in the drawing, the thickness of the substrate 41 is reduced to, for example, about 10 μm in order to irradiate light from the back side.

  In the present embodiment, as shown in FIG. 11, since incident light is incident on the charge storage layer 43 from the side opposite to the floating gate 46, the floating gate 46 must be made of a light-transmitting material. There is an advantage that there are less process restrictions. Note that the present embodiment can provide the same advantages as those of the third embodiment.

  Also in the first and second embodiments, the solid-state imaging devices 3 and 53 may be modified to a back-illuminated type as in the present embodiment.

  As mentioned above, although each embodiment of this invention and its modification were demonstrated, this invention is not limited to these.

1 is a schematic block diagram showing an electronic camera according to a first embodiment of the present invention. It is a circuit diagram which shows schematic structure of the solid-state image sensor in FIG. It is a circuit diagram which shows the pixel of the solid-state image sensor shown in FIG. 3 is a timing chart showing an example of the operation of the solid-state imaging device shown in FIG. It is a circuit diagram which shows schematic structure of the solid-state image sensor used with the electronic camera by the 2nd Embodiment of this invention. It is a circuit diagram which shows the pixel of the solid-state image sensor shown in FIG. It is a timing chart which shows an example of operation | movement of the solid-state image sensor shown in FIG. It is a circuit diagram which shows schematic structure of the solid-state image sensor used with the electronic camera by the 3rd Embodiment of this invention. It is a circuit diagram which shows the pixel of the solid-state image sensor shown in FIG. It is a timing chart which shows an example of operation | movement of the solid-state image sensor shown in FIG. It is a circuit diagram which shows the solid-state image sensor pixel used with the electronic camera by the 4th Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Electronic camera 3,53,63 Solid-state image sensor 31A 1st vertical signal line 31B 2nd vertical signal line 43 Charge storage layer 46 Floating gate 47 Insulating film 64 Potential supply transistor PD Photodiode FD Floating diffusion AMPA 1st amplification Transistor AMPB Second amplification transistor TX Transfer transistor SELA First selection transistor SELB Second selection transistor Vpin Inversion layer formation potential

Claims (10)

A charge accumulating unit for accumulating charges generated in response to incident light;
A charge-voltage converter that receives the charge and converts the charge into a voltage;
A first amplifying unit that outputs a signal corresponding to the potential of the charge-voltage conversion unit;
A transfer unit that transfers charges from the charge storage unit to the charge-voltage conversion unit;
A floating gate having a potential corresponding to the charge stored in the charge storage unit;
A second amplifier that outputs a signal corresponding to the potential of the floating gate;
A solid-state imaging device comprising:   The solid-state imaging device according to claim 1, wherein at least a part of the floating gate is opposed to the charge storage unit via an insulating film. A first signal line for receiving an output of the first amplifying unit;
A first selection switch for turning on / off the supply of the output of the first amplification unit to the first signal line;
A second signal line provided separately from the first signal line and receiving the output of the second amplifying unit;
A second selection switch for turning on / off the supply of the output of the second amplification section to the second signal line;
The solid-state imaging device according to claim 1, further comprising: A signal line that receives both the output of the first amplifier and the output of the second amplifier;
A first selection switch for turning on and off the supply of the output of the first amplifier to the signal line;
A second selection switch for turning on and off the supply of the output of the second amplifier to the signal line;
The solid-state imaging device according to claim 1, further comprising:   5. The solid-state imaging device according to claim 1, wherein an output of the second amplifying unit is read out during a part of an exposure period in which charges are accumulated in the charge accumulating unit. .   2. A potential supply unit that supplies an inversion layer forming potential for forming an inversion layer on the floating gate side in the charge storage unit to the floating gate in response to a control signal. The solid-state imaging device according to any one of 1 to 5.   The potential supply unit is configured to form the inversion layer in at least a part of a period excluding a reading period of an output of the second amplifying unit in an exposure period in which charges are accumulated in the charge accumulating unit. The solid-state imaging device according to claim 6, wherein a potential is supplied to the floating gate.   8. The solid according to claim 1, wherein the incident light is incident on the charge storage portion from the floating gate side, and the floating gate has translucency with respect to the incident light. Image sensor.   The solid-state imaging device according to claim 1, wherein the incident light is incident on the charge accumulation unit from a side opposite to the floating gate. A solid-state imaging device according to any one of claims 1 to 9,
An exposure control unit that performs automatic exposure control based on an output of the second amplification unit;
An imaging apparatus comprising:

Images