JP2010027921A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of preventing degradation of a drive characteristic of a peripheral transistor. <P>SOLUTION: As shown in Fig.2, this semiconductor device includes: a semiconductor substrate; an element isolation film formed to surround an element formation region AA of the semiconductor substrate; and a transistor arranged in the element formation region. The transistor includes: first and second diffusion layers formed in the element formation region; a channel region formed between the first and second diffusion layers; a gate insulation film formed on a surface of the channel region; and a gate electrode 4 arranged on the gate insulation film. A gate length LG2 of the gate electrode in a boundary part C between the element formation region AA and the element isolation film is larger than a gate length G1 of the gate electrode at the center part of the element formation region. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device capable of suppressing deterioration of drive characteristics of peripheral transistors.

  In recent years, flash memories are used in various electronic devices as storage devices. In the flash memory, miniaturization of an element isolation region for electrically isolating a memory cell and a memory cell has been promoted in order to increase a storage capacity.

  The element isolation region has an STI (Shallow Trench Isolation) structure. For example, silicon oxide such as TEOS (Tetraoxysilane, Tetraethoxysilane) and BPSG (Boron Phosphorus Silicon Glass) has been formed by CVD (Chemical Vapor Deposition). Used to be embedded in the STI trench. However, if the STI trench becomes very narrow due to miniaturization, the filling material is not sufficiently buried in the STI trench, and a filling failure occurs.

  In order to prevent such embedding defects, for example, a polysilazane-based coated silicon oxide film has been embedded in the STI trench (for example, see Patent Document 1).

  However, in the coated silicon oxide film, organic substances such as carbon (C) contained in the solvent remain in the silicon oxide film, and the carbon (C) remaining by the heat treatment in the manufacturing process is separated from the element isolation insulating film. There is a possibility that diffusion will occur at the boundary region between the channel region of the high breakdown voltage peripheral transistor formed in the peripheral circuit region and a fixed charge trap will be formed in that region.

  When the channel width of the transistor is large, the influence of the fixed charge trap on the transistor characteristics is small. However, this effect increases as the channel width decreases, and there is a problem that the leakage current due to the fixed charge trap increases and the threshold value of the transistor decreases. Such a decrease in the threshold value of the transistor causes a malfunction of the transistor, leading to deterioration of the driving characteristics of the transistor.

JP 2006-339446 A

  The present invention has been made in view of the above, and an object of the present invention is to provide a semiconductor device capable of suppressing deterioration of drive characteristics of peripheral transistors.

  According to one aspect of the present invention, a semiconductor substrate, an element isolation insulating film formed so as to surround an element formation region of the semiconductor substrate, and a transistor disposed in the element formation region, the transistor includes: The first and second diffusion layers provided in the element formation region, the channel region provided between the first and second diffusion layers, and the gate insulation provided on the surface of the channel region And a gate electrode disposed on the gate insulating film, wherein a gate length of the gate electrode at a boundary portion between the element forming region and the element isolation insulating film is at a central portion of the element forming region. A semiconductor device is provided that is longer than the gate length of the gate electrode.

  According to one aspect of the present invention, a semiconductor substrate having first and second element formation regions, and an element isolation provided between the first element formation region and the second element formation region An insulating film; a first transistor disposed in the first element formation region; first and second diffusion layers provided in the first element formation region; A first channel region provided between the second diffusion layers; a first gate insulating film formed on the first channel region; and provided on the first gate insulating film. A first transistor having a first gate electrode; and a second transistor disposed in the second element formation region, wherein the third and second transistors are disposed in the second element formation region. 4 diffusion layers and between the third and fourth diffusion layers A second channel region, a second gate insulating film formed on the second channel region, and a second gate electrode provided on the second gate insulating film. The first and second element formation regions are arranged adjacent to each other in the gate width direction of the first and second gate electrodes, and the first and second gate electrodes Are coupled on the element isolation insulating film in the gate width direction, and a first gate of the first gate electrode at a first boundary between the first element formation region and the element isolation insulating film The length is longer than the second gate length of the first gate electrode at the center of the first element formation region, and at the second boundary between the second element formation region and the element isolation insulating film. A third of the second gate electrode; Over preparative length, the second is longer than the fourth gate length of the gate electrode in the second element forming region central, is wherein a is provided.

  According to another aspect of the present invention, a semiconductor substrate, an element isolation insulating film formed so as to surround an element formation region of the semiconductor substrate, and a transistor disposed in the element formation region, The transistor includes a pair of diffusion layers provided in the element formation region, a channel region formed between the pair of diffusion layers, a gate insulating film formed on the channel region, and the gate insulating film A gate electrode disposed above the gate electrode, the gate electrode extending on the element isolation insulating film, and a width of the element formation region under the gate electrode is equal to that of the element formation region provided with the diffusion layer. A semiconductor device characterized by being wider than the width is provided.

  According to one aspect of the present invention, a semiconductor substrate having first and second element formation regions, and an element isolation provided between the first element formation region and the second element formation region An insulating film; a first transistor disposed in the first element formation region; first and second diffusion layers provided in the first element formation region; A first channel region provided between the second diffusion layers; a first gate insulating film formed on the first channel region; and provided on the first gate insulating film. A first transistor having a first gate electrode; and a second transistor disposed in the second element formation region, wherein the third and second transistors are disposed in the second element formation region. 4 diffusion layers and between the third and fourth diffusion layers A second channel region, a second gate insulating film formed on the second channel region, and a second gate electrode provided on the second gate insulating film. The first and second element formation regions are arranged adjacent to each other in the gate width direction of the first and second gate electrodes, and the first gate electrode and the second gate electrode The semiconductor device is characterized in that the first and second gate electrodes are shifted in the gate length direction of each of the first and second gate electrodes and connected on the element isolation insulating film.

  According to the present invention, it is possible to suppress the deterioration of the driving characteristics of peripheral transistors in a semiconductor device.

  Embodiments of a semiconductor device according to the present invention will be described below in detail with reference to the accompanying drawings. In addition, this invention is not limited to the following description, In the range which does not deviate from the summary of this invention, it can change suitably. In the drawings shown below, the scale of each member may be different from the actual scale for easy understanding. The same applies between the drawings.

(First embodiment)
(Basic structure)
FIG. 1 is a diagram showing an example of the entire configuration of a flash (nonvolatile) memory that is a semiconductor device according to a first embodiment of the present invention.

  The flash memory includes a memory cell array 100 constituting a memory cell region, and peripheral circuits such as a word line / select gate line driver 101, a sense amplifier circuit 102, and a control circuit 103 which are arranged around the memory cell region and constitute a peripheral circuit region. Become. The memory cell array 100 is provided with a plurality of memory cells. In the peripheral circuit, a plurality of high-voltage or low-voltage MIS (Metal-Insulator-Semiconductor) transistors are provided.

  The basic structure of the n-channel high breakdown voltage MIS transistor HVTr provided in the peripheral circuit in this embodiment will be described with reference to FIGS. FIG. 2 is a plan view showing a planar structure of the high breakdown voltage MIS transistor. 3 is a cross-sectional view showing a cross-sectional structure taken along line AA in FIG. 2, and FIG. 4 is a cross-sectional view showing a cross-sectional structure taken along line BB in FIG.

  An n-channel high breakdown voltage MIS transistor HVTr that generates a voltage of about 20V to 30V is an element formation region (active region, formed in a peripheral circuit region of a first conductivity type (p-type) semiconductor (silicon) substrate. Active region) provided in AA. The element formation region AA is partitioned by being surrounded by the element isolation region STI.

  In the semiconductor substrate 1 in the element formation region AA, there are two impurity diffusions of the second conductivity type (n-type) which become the source and drain of the high breakdown voltage MIS transistor HVTr and have a conductivity type opposite to the first conductivity type. Layer 2 is provided.

  On the semiconductor substrate 1 between the two diffusion layers 2, the gate electrode 4 of the high breakdown voltage MIS transistor HVTr is provided via a gate insulating film 3 made of a silicon oxide film. In addition, a plurality of diffusion layer contacts 6 conducting to the diffusion layer 2 are provided in the element formation region AA.

  An element isolation insulating film 5 is embedded on the surface of the semiconductor substrate 1 in the element isolation region STI. The element isolation insulating film 5 is made of, for example, a polysilazane-based coated silicon oxide film. The element isolation insulating film 5 made of this coating type silicon oxide film contains an organic substance such as carbon (C).

  In the present embodiment, as shown in FIGS. 2 to 4, the gate length (channel length) LG2 of the gate electrode 4 at the boundary C between the element formation region AA and the element isolation region STI is the center of the element formation region AA. The gate electrode A is formed longer than the gate length LG1.

  When the element isolation insulating film 5 is composed of a coating type insulating film containing an organic substance, the organic substance fixes the element region along the element isolation insulating film 5 in the boundary region between the channel region under the gate electrode 4 and the element isolation insulating film 5. A charge trap is formed. FIG. 5 is a plan view showing a planar structure of a conventional high voltage MIS transistor. FIG. 6 is a characteristic diagram showing an example of a change in threshold value of the high voltage MIS transistor when the gate width is changed in the conventional high voltage MIS transistor. FIG. 7 is a characteristic diagram for explaining the correlation between the gate width and the threshold in a conventional high voltage MIS transistor. FIG. 8 is a characteristic diagram showing an example of a change in leakage current when the gate width is changed in the conventional high voltage MIS transistor. FIG. 9 is a characteristic diagram for explaining the correlation between the gate width and the leakage current in the conventional high voltage MIS transistor.

  Due to the influence of the fixed charge trap described above, in the conventional high voltage MIS transistor structure as shown in FIG. 5, as the gate (channel) width becomes smaller, the threshold voltage decreases as shown in FIGS. Further, as shown in FIGS. 8 and 9, the off-leakage current increases. Such a decrease in threshold and an increase in off-leakage current cause a malfunction of the high voltage MIS transistor, leading to deterioration of the drive characteristics of the high voltage MIS transistor.

  According to the high voltage MIS transistor HVTr according to the present embodiment, as shown in FIG. 2, the gate length of the gate electrode 4 is long at the boundary with the element isolation insulating film 5. 5 can alleviate the influence of the fixed charge trap caused by the organic matter contained in 5 and suppress the decrease in the threshold and the increase in the off-leakage current in the high voltage MIS transistor. Therefore, according to the high withstand voltage MIS transistor HVTr according to the present embodiment, it is possible to provide the high withstand voltage MIS transistor HVTr in which the deterioration of the drive characteristics due to the influence of the fixed charge trap is suppressed.

  Several embodiments based on the above basic structure will be described below.

(First embodiment)
FIG. 10 shows an array of the n-channel type high breakdown voltage MIS transistors shown in FIG. 5 which are peripheral transistors used in a flash (nonvolatile) memory, and the gate electrodes 4 are linearly connected in series in the gate width direction. It is a top view which shows the planar structure at the time of connecting to. In FIG. 10, the same members as those in FIG. Even in the case where the n-channel type high breakdown voltage MIS transistors shown in FIG. 2 are arranged in an array like this, fixed charge traps caused by organic substances in the respective high breakdown voltage MIS transistors HVTr as in the example of FIG. Can be mitigated, and the threshold voltage drop in the high voltage MIS transistor can be suppressed. Therefore, according to the present embodiment, it is possible to provide a high-quality semiconductor device in which deterioration of drive characteristics due to the influence of the fixed charge trap is suppressed.

  In the case of the structure shown in FIG. 10, inversion between fields occurs between the element formation regions AA where the gate electrode 4 is common. That is, because of the structure, a virtual transistor is formed between the element formation regions AA that share the gate electrode 4, and a leak current is generated between the element formation regions AA. The leakage current increases as the gate length of the gate electrode 4 between the element formation regions AA increases.

  Therefore, in order to suppress the occurrence of this leakage current, in a transistor dense region such as a row decoder, the gate of the gate electrode 4 in the region D between the element formation regions AA connected to the gate electrode 4 as shown in FIG. The length LG3 is made shorter than the gate length LG2. Therefore, as shown in FIG. 9, the gate electrode 4 in the region D is constricted. Thereby, the inversion between the fields between the element formation regions AA to which the gate electrode 4 is connected can be weakened, and the leakage current between the element formation regions AA with which the gate electrode 4 is shared can be reduced.

(Second embodiment)
FIG. 11 is a plan view showing a planar structure of an n-channel high voltage MIS transistor according to the second embodiment. In FIG. 11, the same members as those in FIG. In the high breakdown voltage MIS transistor according to the second embodiment, the gate length LG2 of the gate electrode 4 at the boundary with the element isolation region STI is longer than the gate length LG1 at the center of the element formation region AA. The end of the gate electrode 4 on either the source side or the drain side in the formation area AA is formed in a straight line.

  When the gate length of the gate electrode 4 is increased, the driving current of the transistor is somewhat reduced. However, with the above-described configuration, a fixed charge trap caused by an organic substance contained in the element isolation insulating film 5 is suppressed as in the example of FIG. 2 while suppressing a decrease in the drive current of the transistor due to an increase in the gate length. Can be mitigated, and the threshold voltage drop in the high voltage MIS transistor can be suppressed.

  In addition, the arrangement margin M between the gate electrode 4 and the diffusion layer contact 6 in the in-plane direction of the diffusion layer 2 is substantially the same on the source side and the drain side. The length of the element formation region AA can be shortened, and the area of the element formation region AA can be reduced.

(Third embodiment)
FIG. 12 shows an array of n-channel type high breakdown voltage MIS transistors according to the second embodiment shown in FIG. 11, which are peripheral transistors controlled in the same potential and used in a nonvolatile semiconductor memory, and have gate electrodes. It is a top view which shows the planar structure at the time of connecting 4 in series. In FIG. 12, the same members as those in FIG. Even when the n-channel type high breakdown voltage MIS transistors shown in FIG. 11 are arranged in an array like this, as in the case of the second embodiment, in each high breakdown voltage MIS transistor HVTr, the element isolation insulating film 5 can alleviate the influence of the fixed charge trap caused by the organic matter contained in 5 and suppress the decrease in the threshold value in the high voltage MIS transistor. Therefore, according to the present embodiment, it is possible to provide a high-quality semiconductor device in which deterioration of drive characteristics due to the influence of the fixed charge trap is suppressed.

  When the high breakdown voltage MIS transistors according to the second embodiment shown in FIG. 11 are arranged in an array, as shown in the upper stage of FIG. Only one side of the same side (source side or drain side) may be provided with a long gate length and channel length of the gate electrode 4. Further, as shown in the lower part of FIG. 12, in the adjacent high voltage MIS transistor, only the gate length and the channel length of the gate electrode 4 are different from each other (source side and drain side) through the gate electrode 4. May be provided longer.

  Further, by arranging n-channel type high breakdown voltage MIS transistors capable of reducing the area of the element formation region AA in an array, the area of the peripheral circuit region can be reduced.

(Second Embodiment)
(Basic structure)
FIG. 13 is a diagram for explaining a basic structure of an n-channel type high breakdown voltage MIS transistor HVTr according to the second embodiment of the present invention, and is a plan view showing a planar structure of the high breakdown voltage MIS transistor. is there. 14 is a cross-sectional view showing a cross-sectional structure taken along line GG in FIG. 13, and FIG. 15 is a cross-sectional view showing a cross-sectional structure taken along line H-H in FIG. The basic structure of the high voltage MIS transistor HVTr of this embodiment will be described with reference to FIGS. In FIG. 13, the same members as those in FIG.

  The high breakdown voltage MIS transistor HVTr shown in FIG. 13 to FIG. 15 is an element isolation region formed in the peripheral circuit region of the first conductivity type (p-type) semiconductor (silicon) substrate, as in the first embodiment. An element formation region (active region, second region) AA surrounded by the STI is provided.

  In the semiconductor substrate 1 in the element formation region AA, there are two diffusion layers of the second conductivity type (n-type) showing the opposite conductivity type to the source and drain of the high voltage MIS transistor HVTr. 2 is provided.

  On the semiconductor substrate 1 between the two diffusion layers 2, the gate electrode 4 of the high breakdown voltage MIS transistor HVTr is provided via a gate insulating film 3 made of a silicon oxide film. In addition, a plurality of diffusion layer contacts 6 conducting to the diffusion layer 2 are provided in the element formation region AA.

  An element isolation insulating film 5 is embedded in the element isolation region STI. The element isolation insulating film 5 is an insulating film made of, for example, a polysilazane-based coated silicon oxide film, and contains an organic substance such as carbon (C).

  In the high voltage MIS transistor HVTr according to the present embodiment, as shown in FIGS. 13 to 15, the element formation region AA corresponding to the lower portion of the gate electrode 4 is formed in the region not corresponding to the lower portion of the gate electrode 4. The shape has a region F projecting outward in the gate width direction from the outer edge of the region AA. Here, the region F protruding outward has a quadrangular shape. That is, the width WAA2 of the element formation area AA corresponding to the lower part of the gate electrode 4 is longer than the width WAA1 of the element formation area AA of the area not corresponding to the lower part of the gate electrode 4. Note that channel conduction is performed in a region of width WAA1 in the region of width WAA2 in the element formation region AA corresponding to the lower portion of the gate electrode 4.

  According to such a high breakdown voltage MIS transistor HVTr, the width WAA2 of the element formation region AA corresponding to the lower portion of the gate electrode 4 is longer than the width WAA1 of the element formation region AA of the region not corresponding to the lower portion of the gate electrode 4. Thus, in the region WAA1 of the region WAA2 in the element formation region AA corresponding to the lower part of the gate electrode 4, the region is not affected by the fixed charge trap caused by the organic substance contained in the element isolation insulating film 5. Channel conduction occurs in Thereby, it is possible to suppress a decrease in threshold due to the influence of the fixed charge trap in the high voltage MIS transistor HVTr. That is, by adopting such a shape, it is possible to reduce the influence of the fixed charge trap, suppress the occurrence of leak current due to the influence of the fixed charge trap, and suppress the decrease in the threshold value. Therefore, according to the high withstand voltage MIS transistor HVTr according to the present embodiment, it is possible to provide the high withstand voltage MIS transistor HVTr in which the deterioration of the drive characteristics due to the influence of the fixed charge trap is suppressed.

  Several embodiments based on the above basic structure will be described below.

(Fourth embodiment)
FIG. 16 shows an array of n-channel high voltage MIS transistors HVTr shown in FIG. 13, which are peripheral transistors controlled in the same potential and used for a nonvolatile semiconductor memory, and gate electrodes 4 are connected in series. It is a top view which shows the planar structure in a case. Even when the high breakdown voltage MIS transistors HVTr shown in FIG. 13 are arranged in an array as shown in FIG. 16, in each high breakdown voltage MIS transistor HVTr, as shown in FIG. The influence of the fixed charge trap caused by the contained organic substance can be alleviated, and the occurrence of a leak current due to the influence of the fixed charge trap can be suppressed, so that the threshold value can be prevented from lowering. Therefore, according to the present embodiment, it is possible to provide a high-quality semiconductor device in which deterioration of drive characteristics due to the influence of the fixed charge trap is suppressed.

(5th Example)
In the fourth embodiment, when the high breakdown voltage MIS transistors HVTr are arranged in an array as shown in FIG. 16, the field breakdown voltage (element isolation breakdown voltage) at the bottom of the STI between adjacent high breakdown voltage MIS transistors is maintained. In order to maintain the isolation characteristics, it is preferable that the shortest distance α between the regions F projecting outward from the adjacent element formation regions AA is separated to some extent. In the fifth embodiment, an embodiment for improving the area efficiency in the layout of the high breakdown voltage MIS transistor HVTr in this case will be described.

  FIG. 17 is a peripheral transistor that is controlled at the same potential and used in a nonvolatile semiconductor memory. The high breakdown voltage MIS transistor HVTr shown in FIG. 13 is arranged in an array and the gate electrode 4 is connected in series. It is a top view which shows a planar structure. In the present embodiment, the high-breakdown-voltage MIS transistor HVTr adjacent in the gate width direction is shifted in the gate length direction (X direction in FIG. 17) of the gate electrode 4. As a result, the shortest distance α between the above-mentioned regions F can be ensured by an appropriate distance without setting a long distance between the element formation regions AA of the high-voltage MIS transistors HVTr adjacent in the gate width direction. The element isolation characteristics can be maintained.

  Further, as shown in the lower part of FIG. 17, the gate electrode 4 may be divided. By dividing the gate electrode 4 in this way, the field breakdown voltage (element isolation breakdown voltage) at the bottom of the STI between the transistors is improved. Since the gate electrode 4 is divided, the metal wiring 12 provided on the gate electrode 4 and the gate electrode contact 13 are connected to the gate electrode 4.

  Further, in this embodiment, as described above, the element formation of the substrate contact is performed in the region generated by disposing the adjacent high voltage MIS transistor HVTr in the gate length direction of the gate electrode 4 (X direction in FIG. 17). Regions AA-C are provided and substrate contacts 11 are disposed. As a result, the substrate contact which has been conventionally arranged so as to surround the outer periphery of the high voltage MIS transistor HVTr can be arranged in the arrangement region of the high voltage MIS transistor HVTr, and the peripheral circuit area can be used efficiently. Is possible.

  Here, the effect of the efficient use of the peripheral circuit area by the arrangement of the present embodiment will be described. FIG. 18 is a plan view showing an arrangement example of the high voltage MIS transistor HVTr in the peripheral circuit region of the conventional example. FIG. 19 is a plan view showing an arrangement example of the high breakdown voltage MIS transistor HVTr in the peripheral circuit region of the present embodiment. In FIG. 18, only m conventional high voltage MIS transistors HVTr are arranged in the X direction and n in the Y direction. In FIG. 19, only m high breakdown voltage MIS transistors HVTr shown in FIG. 13 are arranged in the X direction and n in the Y direction.

  The X direction here is the gate length direction (X direction in FIGS. 18 and 19), and the Y direction is the gate width direction (Y direction in FIGS. 18 and 19). In FIGS. 18 and 19, a: the length in the Y direction of the region F where the element formation region AA protrudes outward, b: the element formation region AA-C of the substrate contact and the element formation region AA-C Distance, c: length in the X direction of the element formation region AA-C of the substrate contact. Then, in the conventional arrangement shown in FIG. 18 and the arrangement of this embodiment shown in FIG. 19, the dimensions and areas of the arrangement region of the high breakdown voltage MIS transistor HVTr are as follows.

(Dimensions in X direction)
Conventional example: total length L = 2c + ml + (m + 1) b
Example: Total length L ′ = L− (c + b) = c + m (b + l)
Therefore, the dimension of the arrangement region in the X direction can be reduced by (c + b).
(Dimensions in the Y direction)
Conventional example: total length W = (n−1) b + nw
Example: Total length W ′ = (n−1) (a + b) + nw + 2a
= (N + 1) a + {(n-1) b + nw}
= W + (n + 1) a
(area)
Conventional example: S = LW
Example: S ′ = L′ W ′ = {L− (b + c)} {W + (n + 1) a}
If the term (b + c) becomes more dominant than the term (n + 1) a, the total area is advantageous over the area S = LW of the conventional example.

  Here, if a = αb and c = γb,

  As a design rule, for example, γ => 1, α = 0.02 to 0.05, and n number is 32 to 64, in the above formula (1), the numerator is at least 2 and the denominator is 2. Since (b + c) >> (n + 1) a is assumed, the total area can be reduced in the embodiment.

(Sixth embodiment)
FIG. 20 is a plan view showing a planar structure of a high voltage MIS transistor according to the sixth embodiment. In the high breakdown voltage MIS transistor according to the sixth embodiment, as shown in FIG. 20, the element formation region AA corresponding to the lower portion of the gate electrode 4 is formed in the region not corresponding to the lower portion of the gate electrode 4 in the gate width direction. The shape has a region F projecting outward from the outer edge of the region AA. In this embodiment, the region F projecting outward is triangular.

  Even in such a configuration, similarly to the high breakdown voltage MIS transistor shown in FIG. 13, the threshold value due to the influence of the fixed charge trap caused by the organic matter contained in the element isolation insulating film 5 in the high breakdown voltage MIS transistor HVTr. Can be suppressed. That is, the element forming area AA corresponding to the lower part of the gate electrode 4 in the gate width direction has a shape protruding outward from the outer edge of the element forming area AA in the area not corresponding to the lower part of the gate electrode 4. It is possible to suppress the occurrence of leak current due to the influence of charge traps and suppress the decrease in threshold value.

(Seventh embodiment)
FIG. 21 is a plan view when the high voltage MIS transistors HVTr shown in FIG. 20, which are peripheral transistors controlled in the same potential and used in the nonvolatile semiconductor memory, are arranged in an array and the gate electrodes 4 are connected in series. It is a top view which shows a structure. In the case where the high breakdown voltage MIS transistors HVTr are arranged in an array, in order to maintain the field breakdown voltage (element isolation breakdown voltage) at the bottom of the STI between adjacent high breakdown voltage MIS transistors, The shortest distance α between the regions F projecting outward from the formation region AA is preferably separated to some extent.

  In the present embodiment, the high-breakdown-voltage MIS transistor HVTr adjacent in the gate width direction is shifted in the gate length direction (X direction in FIG. 21) of the gate electrode 4. As a result, the shortest distance α between the above-mentioned regions F can be ensured by an appropriate distance without setting a long distance between the element formation regions AA of the high-voltage MIS transistors HVTr adjacent in the gate width direction. The element isolation characteristics can be maintained.

  Further, as shown in the lower part of FIG. 21, the gate electrode 4 can be divided. By dividing the gate electrode 4 in this way, the field breakdown voltage (element isolation breakdown voltage) at the bottom of the STI between the transistors is improved. Since the gate electrode 4 is divided, the metal wiring 12 provided on the gate electrode 4 and the gate electrode contact 13 are connected to the gate electrode 4.

  Further, in this embodiment, as described above, the element formation of the substrate contact is performed in the region generated by disposing the adjacent high voltage MIS transistor HVTr in the gate length direction of the gate electrode 4 (X direction in FIG. 21). Regions AA-C are provided and substrate contacts 11 are disposed. As a result, the substrate contact which has been conventionally arranged so as to surround the outer periphery of the high voltage MIS transistor HVTr can be arranged in the arrangement region of the high voltage MIS transistor HVTr, and the peripheral circuit area can be used efficiently. Is possible.

It is a figure which shows an example of the whole structure of the semiconductor device according to one Embodiment of this invention. It is a top view which shows the planar structure of the high voltage | pressure-resistant MIS transistor according to one Embodiment of this invention. FIG. 3 is a cross-sectional view showing a cross-sectional structure along the line AA in FIG. 2. It is sectional drawing which shows the cross-sectional structure which follows the BB line of FIG. It is a top view which shows the planar structure of the conventional high voltage | pressure-resistant MIS transistor. FIG. 10 is a characteristic diagram showing an example of a change in threshold value of a high voltage MIS transistor when a gate width is changed in a conventional high voltage MIS transistor. It is a characteristic diagram for demonstrating correlation with the gate width and threshold value in the conventional high voltage | pressure-resistant MIS transistor. FIG. 12 is a characteristic diagram showing an example of a change in leakage current when the gate width is changed in a conventional high voltage MIS transistor. It is a characteristic view for explaining the correlation between the gate width and the leakage current in the conventional high voltage MIS transistor. It is a top view which shows the planar structure at the time of arranging the high voltage | pressure-resistant MIS transistor according to one Embodiment of this invention in an array form, and connecting the gate electrode in series. It is a top view which shows the planar structure of the high voltage | pressure-resistant MIS transistor according to one Embodiment of this invention. It is a top view which shows the planar structure at the time of arranging the high voltage | pressure-resistant MIS transistor according to one Embodiment of this invention in the array form, and connecting the gate electrode in series. It is a top view which shows the planar structure of the high voltage | pressure-resistant MIS transistor according to one Embodiment of this invention. It is sectional drawing which shows the cross-sectional structure which follows the GG line of FIG. It is sectional drawing which shows the cross-sectional structure which follows the HH line | wire of FIG. It is a top view which shows the planar structure at the time of arranging the high voltage | pressure-resistant MIS transistor according to one Embodiment of this invention in an array form, and connecting the gate electrode in series. It is a top view which shows the planar structure at the time of arranging the high voltage | pressure-resistant MIS transistor according to one Embodiment of this invention in an array form, and connecting the gate electrode in series. It is a top view which shows the example of arrangement | positioning of the high voltage | pressure-resistant MIS transistor in the peripheral circuit area | region of a prior art example. It is a top view which shows the example of arrangement | positioning of the high voltage | pressure-resistant MIS transistor in the peripheral circuit area | region according to one Embodiment of this invention. It is a top view which shows the planar structure of the high voltage | pressure-resistant MIS transistor according to one Embodiment of this invention. It is a top view which shows the planar structure at the time of arranging the high voltage | pressure-resistant MIS transistor according to one Embodiment of this invention in an array form, and connecting the gate electrode in series.

Explanation of symbols

  1 semiconductor substrate, 2 diffusion layer, 3 gate insulating film, 4 gate electrode, 5 element isolation insulating film, 6 diffusion layer contact, 11 substrate contact, 12 metal wiring, 13 gate electrode contact, 100 memory cell array, 101 word line / select Gate line driver, 102 sense amplifier circuit, 103 control circuit, AA element formation region, STI element isolation region.

Claims (5)

A semiconductor substrate;
An element isolation insulating film formed so as to surround an element formation region of the semiconductor substrate;
A transistor disposed in the element formation region;
With
The transistor is
First and second diffusion layers provided in the element formation region;
A channel region provided between the first and second diffusion layers;
A gate insulating film provided on the surface of the channel region;
A gate electrode disposed on the gate insulating film;
Have
The gate length of the gate electrode at the boundary between the element formation region and the element isolation insulating film is longer than the gate length of the gate electrode at the center of the element formation region;
A semiconductor device characterized by the above. A semiconductor substrate having first and second element formation regions;
An element isolation insulating film provided between the first element formation region and the second element formation region;
A first transistor disposed in the first element formation region, the first and second diffusion layers provided in the first element formation region; the first and second A first channel region provided between the diffusion layers, a first gate insulating film formed on the first channel region, and a first gate provided on the first gate insulating film A first transistor having an electrode;
A second transistor disposed in the second element formation region, the third and fourth diffusion layers provided in the second element formation region; and the third and fourth A second channel region provided between the diffusion layers; a second gate insulating film formed on the second channel region; and a second gate provided on the second gate insulating film A second transistor having an electrode;
With
The first and second element formation regions are disposed adjacent to each other in the gate width direction of the first and second gate electrodes, and the first and second gate electrodes are arranged in the gate width direction. It is connected on the element isolation insulating film,
The first gate length of the first gate electrode at the first boundary between the first element formation region and the element isolation insulating film is equal to the first gate at the center of the first element formation region. Longer than the second gate length of the electrode,
The third gate length of the second gate electrode at the second boundary between the second element formation region and the element isolation insulating film is equal to the second gate at the center of the second element formation region. Longer than the fourth gate length of the electrode;
A semiconductor device characterized by the above. The first gate length and the third gate length are equal, and the second gate length and the fourth gate length are equal;
The semiconductor device according to claim 2. A semiconductor substrate;
An element isolation insulating film formed so as to surround an element formation region of the semiconductor substrate;
A transistor disposed in the element formation region;
With
The transistor is
A pair of diffusion layers provided in the element formation region;
A channel region formed between the pair of diffusion layers;
A gate insulating film formed on the channel region;
A gate electrode disposed on the gate insulating film;
Have
The gate electrode extends on the element isolation insulating film, and the width of the element formation region under the gate electrode is wider than the width of the element formation region provided with the diffusion layer;
A semiconductor device characterized by the above. A semiconductor substrate having first and second element formation regions;
An element isolation insulating film provided between the first element formation region and the second element formation region;
A first transistor disposed in the first element formation region, the first and second diffusion layers provided in the first element formation region; the first and second A first channel region provided between the diffusion layers, a first gate insulating film formed on the first channel region, and a first gate provided on the first gate insulating film A first transistor having an electrode;
A second transistor disposed in the second element formation region, the third and fourth diffusion layers provided in the second element formation region; and the third and fourth A second channel region provided between the diffusion layers; a second gate insulating film formed on the second channel region; and a second gate provided on the second gate insulating film A second transistor having an electrode;
With
The first and second element formation regions are disposed adjacent to each other in the gate width direction of the first and second gate electrodes;
The first gate electrode and the second gate electrode are arranged shifted in the gate length direction of each of the first and second gate electrodes and connected on the element isolation insulating film;
A semiconductor device characterized by the above.

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