JP2010027648A - Semiconductor device, semiconductor manufacturing apparatus, and method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that reduces stress of an embedded insulating film while suppressing deteriorations in embedding property and film quality even when a recessed portion on a semiconductor substrate is in a reverse tapered shape or overhang shape, and to provide a method for manufacturing the same. <P>SOLUTION: A trench 5 is formed on the semiconductor substrate 1, and an embedding insulating film 6 which embeds a portion of the trench 5 is deposited on the semiconductor substrate 1 by using a thermal CVD (Chemical Vapor Deposition) method, and heat-treated at a higher temperature than when the embedded insulating film 6 is deposited. Then an embedded insulating film 7 which embeds a portion of the trench 5 is deposited on the embedded insulating film 6 by using the thermal CVD method, and heat-treated at a higher temperature than when the embedded insulating film 7 is deposited. Then, an embedded film which completely embeds the trench 5 is deposited on the embedded insulating film 7 by using the thermal CVD method, and heat-treated at a higher temperature than when the embedded insulating film is deposited. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device, a semiconductor manufacturing apparatus, and a semiconductor device manufacturing method, and is particularly suitable for application to a method of forming a buried insulating film of STI (Shallow Trench Isolation).

  With the demand for miniaturization of semiconductor elements, a sidewall transfer process has begun to be used in order to realize a line and space below the resolution limit of photolithography (Patent Document 1). This sidewall transfer process is a method in which a sidewall pattern is formed on the sidewall of the core material pattern formed on the workpiece film, and the workpiece film is etched using the sidewall pattern remaining after removing the core material pattern as an etching mask. is there.

  Here, the side wall pattern used in this side wall transfer process is such that the contact surface in contact with the core material pattern stands vertically while the non-contact surface in contact with the core material pattern extends from the top to the bottom. It becomes a gently rounded shape. For this reason, when etching a film to be processed using the sidewall pattern as an etching mask, ions are more likely to enter the region sandwiched on the non-contact surface side of the sidewall pattern than the region sandwiched on the contact surface side of the sidewall pattern. Since the region sandwiched on the non-contact surface side is more likely to be etched, when the STI is formed by the sidewall transfer process, the trench formed in the region sandwiched on the non-contact surface side of the sidewall pattern is more The depth and width are larger than the trench formed in the region sandwiched by the contact surface side of the sidewall pattern.

Here, as a method of filling the STI trench with a buried insulating film, there are methods such as a thermal CVD method using a TEOS (tetraethoxysilane) / O ₃ mixed gas, an HDP (high density plasma) CVD method, and a coating method. .

  However, if a buried insulating film is buried in trenches having variations in depth and width at a time by such a method, the stress of the buried insulating film increases. Therefore, in the active region sandwiched between the trenches, There is a problem that warpage occurs along the depth direction of the substrate, causing deformation of a base structure such as a flash memory and deterioration of electrical characteristics.

  In addition, in the thermal CVD method or HDP-CVD method, when the trench has a reverse taper shape or an overhang shape, or when the aspect ratio (ratio of the trench depth to the frontage width) exceeds 3, the trench is buried. There was a problem of difficulty.

  In addition, in the coating method, even when the trench has a reverse taper shape or an overhang shape, or when the aspect ratio exceeds 3, the trench can be embedded satisfactorily, but the film quality such as insulation resistance and wet processing resistance is improved. There was a problem that it was inferior to a film formed by a thermal CVD method or an HDP-CVD method.

JP 2008-27978 A

  Therefore, an object of the present invention is to reduce the stress of the buried insulating film while suppressing the burying property and the deterioration of the film quality even when the concave portion formed on the semiconductor substrate has a reverse taper shape or an overhang shape. It is to provide a semiconductor device, a semiconductor manufacturing apparatus, and a method for manufacturing a semiconductor device.

  In order to solve the above-described problem, according to one aspect of the present invention, a base layer formed on a semiconductor substrate, and a trench formed in the semiconductor substrate along a side surface of the base layer, A trench having a portion in which the distance between the pair of side walls of the trench facing each other is larger than the distance between the pair of side walls in the surface portion on the bottom side of the trench with respect to the surface portion of the semiconductor substrate; A first buried insulating film formed along the side surfaces of the trench and the pair of side walls of the trench, wherein the film thickness formed on each of the pair of side walls is larger than the thickness formed on the side surface of the base layer. Thick and formed such that the distance between the first buried insulating films in the surface portion is equal to or greater than the distance between the first buried insulating films in any part on the bottom side of the surface portion. A first buried insulating film, a semiconductor device, characterized in that it comprises a second buried insulating film formed between the first buried insulating film.

  According to one embodiment of the present invention, a film formation chamber for performing a film formation process by a thermal CVD method, a heat treatment chamber for performing a heat treatment at a temperature higher than the temperature of the film formation process, and a vacuum state are maintained. And a transfer chamber for transferring a semiconductor wafer to the film formation chamber and the heat treatment chamber.

  Further, according to one embodiment of the present invention, a film formation chamber that performs a film formation process on a semiconductor wafer by a thermal CVD method, and the semiconductor wafer is placed in the film formation chamber at a temperature higher than the temperature of the film formation process. And a radiation heating unit that performs radiation heating subsequent to the film formation process.

  According to another aspect of the present invention, a step of forming a recess in a semiconductor substrate, a step of forming a first buried insulating film along the inner surface of the recess by a thermal CVD method, and the first embedding A step of heat-treating the first buried insulating film at a temperature higher than that at the time of forming the insulating film; a step of forming a second buried insulating film on the first buried insulating film by a thermal CVD method; And a step of heat-treating the second buried insulating film at a temperature higher than that at the time of forming the second buried insulating film.

  As described above, according to the present invention, even when the recess formed on the semiconductor substrate has a reverse taper shape or an overhang shape, the stress of the embedded insulating film is suppressed while suppressing the deterioration of the embeddability and the film quality. Can be reduced.

  Hereinafter, a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.

(First embodiment)
1 to 7 are sectional views showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention.
In FIG. 1, after forming a tunnel insulating film 2 on a semiconductor substrate 1, a charge holding film 3 and a stopper film 4 are sequentially stacked on the tunnel insulating film 2 by a method such as CVD. The material of the semiconductor substrate 1 is not limited to Si, and may be selected from Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, ZnSe, GaInAsP, and the like. . As the tunnel insulating film 2, for example, a silicon oxide film can be used. As the charge holding film 3, for example, when a floating gate type cell is formed on the semiconductor substrate 1, polycrystalline silicon or the like can be used. When forming a charge trap type cell on the semiconductor substrate 1, a silicon nitride film may be used as the charge holding film 3. As the stopper film 4, for example, a silicon nitride film or a silicon oxide film can be used.

  Next, as shown in FIG. 2, for example, by using a sidewall transfer process, a trench 5 reaching the semiconductor substrate 1 through the stopper film 4, the charge holding film 3 and the tunnel insulating film 2 is formed, and the charge holding film 3 is formed. To separate. Note that the aspect ratio of the trench 5 is preferably set to 8 or more in order to ensure a sufficient breakdown voltage due to STI.

  Further, the variation in cross-sectional area between the trenches 5 may be 5% or more, or 10% or more. If the variation in the cross-sectional area between the trenches 5 is 5% or more, it becomes easy to be affected by the stress of the filling material, so that the warp of the active region sandwiched between the trenches 5 tends to appear. Further, when the cross-sectional area variation between the trenches 5 is 10% or more, the warpage of the active region sandwiched between the trenches 5 becomes large, and the embedding in the trench 5 becomes incomplete or is embedded in the wrench 5. The possibility of voids appearing in the buried material increases.

By using the sidewall transfer process described above, the trenches 5 can be formed at intervals of 1/2 the arrangement pitch obtained at the resolution limit of photolithography. On the other hand, when the trench 5 is formed by the sidewall transfer process, the depth and width of the trench 5 vary, and the deep trench 5 and the shallow trench 5 appear alternately. Further, when the trench 5 is formed in the semiconductor substrate 1 through the stopper film 4, the charge holding film 3 and the tunnel insulating film 2, the stopper film 4, the charge holding film 3 and the tunnel insulating film are different depending on the etching rate of these films. The film 2 has an overhang shape protruding on the semiconductor substrate 1 in an eave shape.
That is, the trench 5 has a pair of opposing side walls, and a pair of side walls from a distance a between the pair of side walls in the surface portion of the semiconductor substrate 1 on the bottom side of the trench 5 from the surface portion of the semiconductor substrate 1. There is a portion where the distance b is large.

Next, as shown in FIG. 3, a buried insulating film 6 is formed on the semiconductor substrate 1 and along the inner surface of the trench 5 by using a thermal CVD method. Note that a TEOS / O ₃ mixed gas is used as a raw material for forming the buried insulating film 6. Further, the temperature at the time of forming the buried insulating film 6 is set in the range of 375 ° C. to 480 ° C.

  The film thickness of the buried insulating film 6 is set to such an extent that no warpage occurs in the active region sandwiched between the trenches 5, for example, about 1/5 or less of the width of the trench 5. preferable. Specifically, for example, if the width of the trench 5 is 30 nm, the thickness of the buried insulating film 6 is preferably set to 5 nm or less.

  Here, after setting the temperature at the time of forming the buried insulating film 6 within a range of 375 ° C. to 480 ° C., by adjusting the flow rate and pressure of the source gas, the stopper film 4 exposed in the trench 5, The film formation rate on the surface of the semiconductor substrate 1 is made larger than the side surfaces of the underlying layers such as the charge holding film 3 and the tunnel insulating film 2. Thereby, the semiconductor in the trench 5 is larger than the thickness of the buried insulating film 6 formed on the sidewalls of the stopper film 4, the charge holding film 3 and the tunnel insulating film 2 in the trench 5, that is, on the surface portion of the semiconductor substrate 1. The thickness of the buried insulating film 6 formed on the exposed surface of the substrate 1 can be increased. As a result, it is possible to avoid an overhang shape in which the stopper film 4, the charge holding film 3, and the tunnel insulating film 2 project in an eaves shape, and the embedding property in the trench 5 after the formation of the buried insulating film 6 is improved. Can be made. In other words, the buried insulating film 6 is a distance between the buried insulating films 6 on the surface portion of the semiconductor substrate 1 at any position where the distance d between the buried insulating films 6 on the bottom side of the trench 5 from the surface portion of the semiconductor substrate 1. c or less. In FIG. 3, the distance between the buried insulating films 6 is formed to be equal from the surface portion of the semiconductor substrate 1 to a predetermined distance, and then gradually decreased.

  Then, after the buried insulating film 6 is formed, the buried insulating film 6 is heat-treated at a higher temperature than when the buried insulating film 6 is formed, so that the stress of the buried insulating film 6 is relieved. Note that the heat treatment condition of the buried insulating film 6 is set to, for example, 850 ° C. and 30 minutes. Here, by performing a heat treatment after the formation of the buried insulating film 6, the shrinkage stress of the buried insulating film 6 that has been about 150 MPa to 300 MPa after the film formation is reduced to a shrinkage stress of 50 MPa or less or a compression stress of 50 MPa or less. Can do.

  Further, by performing a heat treatment after the formation of the buried insulating film 6, the structure of the buried insulating film 6 is made uniform between the stopper film 4, the charge holding film 3, the tunnel insulating film 2, and the side walls of the semiconductor substrate 1 in the trench 5. Even when the film formation rate by the thermal CVD method has a base dependency, the film thicknesses of the buried insulating films 7 and 8 of FIGS. 4 and 5 stacked on the buried insulating film 6 are made uniform. be able to.

  Next, as shown in FIG. 4, a buried insulating film 7 is formed along the buried insulating film 6 in the trench 5 by using a thermal CVD method. Then, the embedded insulating film 7 is heat-treated at a temperature higher than that at the time of forming the embedded insulating film 7, thereby relaxing the stress of the embedded insulating film 7. The conditions for the film formation process and heat treatment of the buried insulating film 7 can be set to be the same as the conditions for the film formation process and heat treatment of the buried insulating film 6, respectively.

  Next, as shown in FIG. 5, a buried insulating film 8 that completely fills the trench 5 is formed on the buried insulating film 7 by using a thermal CVD method. Then, the embedded insulating film 8 is heat-treated at a temperature higher than that at the time of forming the embedded insulating film 8 to relieve the stress of the embedded insulating film 8. The conditions for the film formation process and heat treatment of the buried insulating film 8 can be set to be the same as the conditions for the film formation process and heat treatment of the buried insulating film 6, respectively.

  Next, as shown in FIG. 6, by using a CMP (Chemical Mechanical Polishing) method, the buried insulating films 6, 7 and 8 are thinned until the stopper film 4 is exposed. Then, after removing the stopper film 4, the buried insulating films 6, 7, 8 are wet-etched to the height of the tunnel insulating film 2 by using a chemical solution such as hydrofluoric acid, and the buried insulating film 6 is interposed between the floating gate electrodes 3 a. , 7 and 8 are dropped.

  Next, as shown in FIG. 7, an inter-gate insulating film 9 is formed on the semiconductor substrate 1 by using a method such as a CVD method so that the upper surface and side surfaces of the floating gate electrode 3a are covered. As a material of the intergate insulating film 9, for example, a silicon oxide film may be used, or a high dielectric constant insulating film such as an Hf-based oxide may be used.

  Next, a conductive film is formed on the inter-gate insulating film 9 by using a method such as CVD. Then, the control gate electrode 10 is formed on the inter-gate insulating film 9 by patterning the conductive film using a photolithography technique and a dry etching technique. As a material of the control gate electrode 10, for example, polycrystalline silicon may be used, or silicide may be used.

  Here, the trenches formed on the semiconductor substrate 1 are formed by forming the buried insulating films 6, 7, and 8 in the trench 5 while repeating one film formation process and one heat treatment as one cycle for a plurality of cycles. Even when 5 has a reverse taper shape or an overhang shape, it is possible to reduce the stress of the buried insulating films 6, 7, and 8 while suppressing deterioration of embeddability and film quality. For this reason, it becomes possible to prevent the active region sandwiched between the trenches 5 from warping while ensuring insulation resistance and wet processing resistance in STI. Deterioration of electrical characteristics can be suppressed.

In the above-described embodiment, the method of forming the buried insulating films 6 to 8 in the trench 5 by applying the thermal CVD method using the TEOS / O ₃ mixed gas has been described. However, EOS / O _It is not necessary to embed the entire trench 5 by a thermal CVD method using a _3- system mixed gas, and the trench 5 is buried by a plasma CVD method, an HDP-CVD method, a coating method, or the like at the second and subsequent film formation. You may do it.

  In the above-described embodiment, the method of repeating the film formation process and the single heat treatment three times as one cycle to form the buried insulating films 6 to 8 in the trench 5 has been described. It is not limited to the number of times, and may be repeated twice, or may be repeated four or more times.

  In the above-described embodiment, the method for setting the film formation conditions when forming the buried insulating films 6 to 8 in the trench 5 to the same value has been described. The film forming conditions may be changed so that the base dependency becomes smaller.

In the above-described embodiment, the method of using the thermal CVD method using the TEOS / O ₃ mixed gas in order to form the buried insulating films 6 to 8 in the trench 5 has been described. However, SiH ₂ Cl ₂ ( HTO (high temperature oxidation) using a dichlorosilane / N ₂ O-based mixed gas may be applied, or an HSi [N (CH ₃ ) ₂ ] ₃ (trisdimethylaminosilane) / O ₃ -based mixed gas may be used. The used ALD (Atomic Layer Deposition) may be applied.

In the above-described embodiment, the method of forming the buried insulating film in the STI trench has been described. However, the method may be applied to filling between word lines such as a flash memory and a DRAM.
(Second Embodiment)

FIG. 8 is a cross-sectional view showing a schematic configuration of a semiconductor manufacturing apparatus according to the second embodiment of the present invention.
In FIG. 8, the semiconductor manufacturing apparatus is provided with a film formation chamber 21, a transfer chamber 31, and a heat treatment chamber 41. The film formation chamber 21 and the heat treatment chamber 41 are connected to the transfer chamber 31 through shutter valves 45 and 46, respectively. Has been.

  Here, the film forming chamber 21 can perform a film forming process on the semiconductor wafer W by a thermal CVD method. Further, the heat treatment chamber 41 can perform the heat treatment of the semiconductor wafer W at a temperature higher than the temperature of the film forming process in the film forming chamber 21. The transfer chamber 31 can transfer the semiconductor wafer W to the film forming chamber 21 and the heat treatment chamber 41 while maintaining a vacuum state.

  Specifically, an exhaust pipe 22 that exhausts the inside of the film forming chamber 21 is connected to the film forming chamber 21. In the film forming chamber 21, a table 25 on which the semiconductor wafer W is placed is installed, and a gas introduction unit 23 for introducing the reaction gas G into the film forming chamber 21 through the gas ejection holes 24 is provided. It has been. A resistance heating unit 26 for resistance heating the semiconductor wafer W is provided under the table 25.

  The heat treatment chamber 41 is connected to an exhaust pipe 42 for exhausting the heat treatment chamber 41. In the heat treatment chamber 41, a table 43 on which the semiconductor wafer W is placed is installed, and a lamp 44 that radiates and heats the semiconductor wafer W is provided. For example, a halogen lamp or a flash lamp can be used as the lamp 44.

  The transfer chamber 31 is connected to an exhaust pipe 32 that exhausts the inside of the transfer chamber 31. The transfer chamber 31 is provided with a transfer robot 33 for transferring the semiconductor wafer W, and the transfer robot 33 is provided with a transfer arm 34 for holding the semiconductor wafer W.

Then, the transfer robot 33 transfers, for example, the semiconductor wafer W in which the trench 5 of FIG. 2 is formed into the transfer chamber 31 with the shutter valves 45 and 46 being closed. Then, the film formation chamber 21, the transfer chamber 31, and the heat treatment chamber 41 are evacuated to bring the film formation chamber 21, the transfer chamber 31, and the heat treatment chamber 41 into a predetermined vacuum state. When the film forming chamber 21, the transfer chamber 31, and the heat treatment chamber 41 reach a predetermined vacuum state, the shutter valve 45 is opened. Then, the transfer robot 33 carries the semiconductor wafer W formed with the trench 5 in FIG. 2 into the film forming chamber 21 and places it on the table 25. When the semiconductor wafer W is placed on the table 25, the shutter valve 45 is closed. Then, a reactive gas G such as a TEOS / O ₃ system mixed gas is introduced into the film forming chamber 21 through the gas introducing unit 23, and the semiconductor wafer W is heated at the film forming temperature by the resistance heating unit 26. The buried insulating film 6 shown in FIG.

  When the buried insulating film 6 is formed in the trench 5 of FIG. 2, the introduction of the reaction gas G is stopped, and the reaction gas G remaining in the film formation chamber 21 is exhausted. be opened. When the shutter valve 45 is opened, the transfer robot 33 unloads the semiconductor wafer W on which the embedded insulating film 6 is formed from the film formation chamber 21. When the semiconductor wafer W on which the buried insulating film 6 is formed is unloaded from the film forming chamber 21, the shutter valve 45 is closed and the gate valve 46 is opened. Then, the transfer robot 33 carries the semiconductor wafer W on which the buried insulating film 6 is formed into the heat treatment chamber 41 and places it on the table 43. When the semiconductor wafer W is placed on the table 43, the gate valve 46 is closed. Then, the stress of the buried insulating film 6 is relieved by heating the semiconductor wafer W with a lamp 44 at a heat treatment temperature higher than the film forming temperature for a predetermined time.

  When the semiconductor wafer W on which the buried insulating film 6 is formed is heat-treated, the gate valve 46 is opened. Then, the transfer robot 33 unloads the heat-treated semiconductor wafer W from the heat treatment chamber 41 when the gate valve 46 is opened. When the heat-treated semiconductor wafer W is unloaded from the heat treatment chamber 41, the gate valve 46 is closed and the shutter valve 45 is opened.

  Thereafter, the transfer robot 33 transfers the film formation chamber 21 → the heat treatment chamber 41 → the film formation chamber 21 → the heat treatment chamber 41 in this order, and repeatedly performs the film formation process and the heat treatment in the film formation chamber 21 and the heat treatment chamber 41, respectively. Thus, the buried insulating films 7 and 8 shown in FIGS. 4 and 5 are sequentially formed on the buried insulating film 6 shown in FIG.

  Accordingly, the buried insulating films 6, 7, and 8 can be formed in the trench 5 without exposing the semiconductor wafer W on which the trench 5 of FIG. 2 is formed to the atmosphere, and the buried insulating films 6, 7, and 8 can be formed. While preventing the contamination, it is possible to repeat the film forming process and the heat treatment, and it is possible to suppress a decrease in throughput.

(Third embodiment)
FIG. 9 is a sectional view showing a schematic configuration of a semiconductor manufacturing apparatus according to the third embodiment of the present invention.
In FIG. 9, a film forming chamber 51 is provided in the semiconductor manufacturing apparatus. Here, the film forming chamber 51 performs a film forming process on the semiconductor wafer W by a thermal CVD method, and radiates and heats the semiconductor wafer W at a temperature higher than the temperature of the film forming process. Can do.

  Specifically, an exhaust pipe 52 that exhausts the inside of the film forming chamber 51 is connected to the film forming chamber 51. In the film forming chamber 51, a table 55 on which the semiconductor wafer W is placed is installed, and a gas introduction unit that introduces the reactive gas G or the purge gas P into the film forming chamber 51 through the gas ejection holes 54. 53 is provided. A lamp 56 for radiantly heating the semiconductor wafer W is provided below the table 55. For example, a halogen lamp or a flash lamp can be used as the lamp 56.

Then, for example, when the semiconductor wafer W in which the trench 5 of FIG. 2 is formed is placed on the table 55, the inside of the film forming chamber 51 is evacuated to bring the inside of the film forming chamber 51 into a predetermined vacuum state. . When the film formation chamber 51 reaches a predetermined vacuum state, a reaction gas G such as a TEOS / O ₃ mixed gas is introduced into the film formation chamber 51 through the gas introduction unit 53, and a semiconductor wafer is produced by a lamp 56. The buried insulating film 6 shown in FIG. 3 is formed in the trench 5 shown in FIG. 2 while heating W at the film forming temperature. Then, when the buried insulating film 6 is formed in the trench 5 of FIG. 2, the introduction of the reaction gas G is stopped, and the reaction gas G remaining in the film formation chamber 51 is exhausted, and then the gas introduction unit 53. Then, a purge gas P such as N ₂ gas is introduced into the film forming chamber 51. Then, the semiconductor wafer W on which the embedded insulating film 6 is formed is heated by the lamp 56 at a heat treatment temperature higher than the film forming temperature for a predetermined time, thereby relaxing the stress of the embedded insulating film 6.

  When the heat treatment is completed on the semiconductor wafer W on which the buried insulating film 6 is formed, the purge gas P remaining in the film formation chamber 51 is exhausted, and then the reaction gas G is supplied to the film formation chamber via the gas introduction unit 53. 51. Thereafter, the film formation process and the heat treatment are repeatedly performed in the film formation chamber 51 to sequentially form the embedded insulating films 7 and 8 of FIGS. 4 and 5 on the embedded insulating film 6 of FIG.

  As a result, it is possible to repeatedly perform the film forming process and the heat treatment in the same film forming chamber 51, and it is not necessary to provide a film forming apparatus and a heat treatment apparatus separately, so that space can be saved. And a decrease in throughput can be suppressed.

Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. Sectional drawing which shows schematic structure of the semiconductor manufacturing apparatus which concerns on 2nd Embodiment of this invention. Sectional drawing which shows schematic structure of the semiconductor manufacturing apparatus which concerns on 3rd Embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 2 Tunnel insulating film, 3 Charge retention film, 3a Floating gate electrode, 4 Stopper film, 5 Trench, 6, 7, 8 Embedded insulating film, 9 Inter-gate insulating film, 10 Control gate electrode, 21, 51 Composition Membrane chamber, 22, 32, 42, 52 Exhaust pipe, 23, 53 Gas introduction part, 24, 54 Gas injection hole, 25, 43, 55 Table, 26 Resistance heating part, 31 Transfer chamber, 33 Transfer robot, 34 Transfer arm , 41 Heat treatment chamber, 44, 56 Lamp, 45, 46 Shutter bulb

Claims (5)

An underlayer formed on a semiconductor substrate;
A trench formed in the semiconductor substrate along a side surface of the base layer, wherein a distance between a pair of side walls of the trench facing each other is closer to the bottom side of the trench than a surface portion of the semiconductor substrate. A trench having a portion larger than the distance between the pair of side walls in the portion;
A first buried insulating film formed along the side surface of the base layer and the pair of side walls of the trench, and formed on each of the pair of side walls from a film thickness formed on the side surface of the base layer. Formed such that the distance between the first buried insulating films on the surface portion is greater than the distance between the first buried insulating films in any part on the bottom side of the surface portion. A first buried insulating film formed;
A semiconductor device comprising: a second buried insulating film formed between the first buried insulating films. A film forming chamber for performing a film forming process by a thermal CVD method;
A heat treatment chamber for performing heat treatment at a temperature higher than the temperature of the film formation process;
A semiconductor manufacturing apparatus comprising: a transfer chamber for transferring a semiconductor wafer to the film formation chamber and the heat treatment chamber while maintaining a vacuum state. A film forming chamber for performing a film forming process on a semiconductor wafer by a thermal CVD method;
A semiconductor manufacturing apparatus, comprising: a radiation heating unit configured to radiately heat the semiconductor wafer in the film formation chamber following the film formation process at a temperature higher than the temperature of the film formation process. Forming a recess in the semiconductor substrate;
Forming a first buried insulating film along the inner surface of the recess by a thermal CVD method;
Heat-treating the first buried insulating film at a temperature higher than that at the time of forming the first buried insulating film;
Forming a second buried insulating film on the first buried insulating film by a thermal CVD method;
And a step of heat-treating the second buried insulating film at a temperature higher than that at the time of forming the second buried insulating film. Forming a recess in the semiconductor substrate,
Forming a base layer on the semiconductor substrate;
Forming a trench in the semiconductor substrate through the underlayer,
The film formation condition of the first buried insulating film is set so that a film formation rate on the surface of the semiconductor substrate is larger than a surface of the base layer exposed in the trench. Item 5. A method for manufacturing a semiconductor device according to Item 4.

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