JP2010026117A - Display and method of driving the same, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a driving method, a driving device, and a display that prevent a potential difference V<SB>gs</SB>from being lower than V<SB>th</SB>when the V<SB>th</SB>is corrected. <P>SOLUTION: The voltage of a gate line WSL is V<SB>off</SB>, the voltage of a drain line DSL provided according to a unit U1 is V<SB>cc</SB>, and the voltage of a drain line DSL provided according to a unit U2 adjacent to the unit U1 is V<SB>ss</SB>. In this case, while the voltage of the drain line DSL provided according to the u nit U1 is raised from V<SB>ss</SB>to V<SB>cc</SB>, the voltage of the drain line DSL provided according to the unit U2 is lowered from V<SB>ss</SB>toV<SB>cc</SB>. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a display device including a display unit having a light emitting element and a pixel circuit for each pixel, and a driving unit for driving the pixel circuit, and a driving method thereof. Moreover, this invention relates to the electronic device provided with the said display apparatus.

  In recent years, in the field of display devices that perform image display, display devices that use current-driven optical elements, such as organic EL (electroluminescence) elements, whose light emission luminance changes according to the value of a flowing current are used as light emitting elements of pixels. Developed and commercialized.

  Unlike a liquid crystal element or the like, the organic EL element is a self-luminous element. Therefore, a display device (organic EL display device) using an organic EL element does not require a light source (backlight), and thus has higher image visibility and lower power consumption than a liquid crystal display device that requires a light source. And the response speed of the element is fast.

  In the organic EL display device, similarly to the liquid crystal display device, there are a simple (passive) matrix method and an active matrix method as driving methods. Although the former has a simple structure, there is a problem that it is difficult to realize a large-sized and high-definition display device. For this reason, active matrix systems are currently being actively developed. In this method, a current flowing through a light emitting element arranged for each pixel is controlled by an active element (generally a TFT (Thin Film Transistor)) provided in a drive circuit provided for each light emitting element.

By the way, in general, the current-voltage (IV) characteristics of the organic EL element deteriorate (deteriorate with time) as time elapses. In a pixel circuit that current-drives an organic EL element, when the IV characteristic of the organic EL element changes with time, the voltage division ratio between the organic EL element and the drive transistor connected in series to the organic EL element changes. The gate-source voltage V _{gs of the} transistor also changes. As a result, since the current value flowing through the drive transistor changes, the current value flowing through the organic EL element also changes, and the light emission luminance also changes according to the current value.

In addition, the threshold voltage _Vth and mobility μ of the driving transistor may change over time, and the threshold voltage _Vth and mobility μ may vary from pixel circuit to pixel circuit due to variations in manufacturing processes. When the threshold voltage V _th and the mobility μ of the driving transistor are different for each pixel circuit, the current value flowing through the driving transistor varies for each pixel circuit. Therefore, even if the same voltage is applied to the gate of the driving transistor, the organic EL The light emission luminance of the elements varies, and the uniformity of the screen is lost.

Therefore, even if the IV characteristic of the organic EL element changes with time, or the threshold voltage _Vth or mobility μ of the driving transistor changes with time, the light emission luminance of the organic EL element is not affected by those effects. In order to keep the voltage constant, a display device incorporating a compensation function for variations in the IV characteristics of the organic EL element and a correction function for variations in the threshold voltage _Vth and mobility μ of the drive transistor has been developed. (For example, refer to Patent Document 1).

  FIG. 13 illustrates a schematic configuration of the display device described in Patent Document 1. A display device 100 illustrated in FIG. 13 includes a display unit 110 in which a plurality of pixels 111 are arranged in a matrix, and a driving unit that drives each pixel 111 (a horizontal driving circuit 120, a writing scanning circuit 130, and a power scanning circuit 140). And.

Each pixel 111 includes a red pixel 111R, a green pixel 111G, and a blue pixel 111B. As shown in FIG. 14, each of the pixels 111R, 111G, and 111B includes an organic EL element 112 (organic EL elements 112R, 112G, and 112B) and a pixel circuit 113 connected thereto. The pixel circuit 113 includes a sampling transistor T _WS , a storage capacitor C _s , and a driving transistor T _Dr , and has a 2Tr1C circuit configuration. A gate line WSL drawn from the write scanning circuit 130 is formed to extend in the row direction, and is connected to the gate of the transistor _TWS . A drain line DSL drawn from the power supply scanning circuit 140 is also formed to extend in the row direction, and is connected to the drain of the transistor _TDr . The signal line DTL drawn from the horizontal drive circuit 120 is formed to extend in the column direction, and is connected to the drain of the transistor _TWS . The source of the transistor _{T WS} is the gate of the transistor _{T Dr} for driving, is connected to one end of the storage capacitor _{C s,} the transistors _{T Dr} source and the storage capacitor _{C s} of the other end and an organic EL element 112R for, 112G, 112B (hereinafter abbreviated as organic EL element 112R etc.) is connected to the anode. A cathode of the organic EL element 112R and the like is connected to the ground line GND.

FIG. 15 shows an example of various waveforms in the display device 100 shown in FIG. In FIG. 15, two types of voltages (V _on , V _off (<V _on )) are applied to the gate line WSL, and two types of voltages (V _cc , V _ini (<V _cc )) are applied to the drain line DSL. A state in which two kinds of voltages (V _sig , V _ofs (<V _sig )) are applied to the line DTL is shown. Further, FIG. 15 shows how the gate voltage V _g and the source voltage V _{s of} the transistor T _Dr change from moment to moment in response to voltage application to the gate line WSL, the drain line DSL, and the signal line DTL. ing.

(Vth correction preparation period)
First, preparation for Vth correction is performed. Specifically, the power supply scanning circuit 140 reduces the voltage of the drain line DSL from V _cc to V _ini (T ₁ ). Then, the source voltage V _s becomes V _ini and the organic EL element 112 and the like are quenched. Next, after the horizontal drive circuit 120 switches the voltage of the signal line DTL from V _sig to V _ofs , the write scanning circuit 130 reduces the voltage of the gate line WSL while the voltage of the drain line DSL is V _ini. Increase from V _off to V _on (T ₂ ). Then, the gate voltage _{V g} drops to _{V ofs.}

(First Vth correction period)
Next, _Vth is corrected. Specifically, while the voltage of the signal line DTL is V _ofs , the power supply scanning circuit 140 increases the voltage of the drain line DSL from V _ini to V _cc (T ₃ ). Then, a current I _ds flows between the drain and source of the transistor T _Dr , and the source voltage V _s increases. Thereafter, before the horizontal driving circuit 120 switches the voltage of the signal line DTL from V _ofs to V _sig , the write scanning circuit 130 decreases the voltage of the gate line WSL from V _on to V _off (T ₄ ). Then, the gate of the transistor _TDr becomes floating, and the correction of _Vth is temporarily stopped.

(First Vth correction pause period)
During the period when the Vth correction is paused, the voltage of the signal line DTL is sampled in another row (pixel) different from the row (pixel) on which the previous Vth correction has been performed. Note that when the Vth correction is insufficient, i.e., the gate of the transistor _{T Dr} - when the potential difference _{V gs} between the source is larger than the threshold voltage _{V th} of the transistor _{T Dr} is also in Vth correction stop period, previously In the row (pixel) in which the Vth correction is performed, the current I _ds flows between the drain and source of the transistor T _Dr , the source voltage V _s rises, and the gate voltage V _g also increases due to coupling through the storage capacitor C _s. To rise.

(Second Vth correction period)
After the Vth correction pause period ends, _Vth is corrected again. Specifically, when the voltage of the signal line DTL is V _ofs and Vth correction is possible, the write scanning circuit 130 raises the voltage of the gate line WSL from V _off to V _on (T ₅ ). The gate of the transistor T _Dr is connected to the signal line DTL. At this time, when the source voltage V _s is lower than V _ofs −V _th (when Vth correction is not yet completed), until the transistor T _Dr is cut off (until the potential difference V _gs becomes V _th ). A current I _ds flows between the drain and source of the transistor T _Dr. As a result, the holding capacitor _{C s} is charged to _{V th,} the potential difference _{V gs} becomes _{V th.} Thereafter, before the horizontal drive circuit 120 switches the voltage of the signal line DTL from V _ofs to V _sig , the write scanning circuit 130 lowers the voltage of the gate line WSL from V _on to V _off (T ₆ ). Then, since the gate of the transistor T _Dr is in a floating state, the potential difference V _gs can be maintained as V _th regardless of the magnitude of the voltage of the signal line DTL. In this way, by setting the potential difference V _gs to V _th , even if the threshold voltage V _th of the transistor T _Dr varies from pixel circuit 122 to pixel circuit 122, the emission luminance of the organic EL element 112 and the like varies. Can be eliminated.

(Second Vth correction suspension period)
Thereafter, the horizontal drive circuit 120 switches the voltage of the signal line DTL from V _ofs to V _sig during the Vth correction pause period.

(Writing / μ correction period)
After the Vth correction pause period ends, writing and μ correction are performed. Specifically, while the voltage of the signal line DTL is V _sig , the write scanning circuit 130 raises the voltage of the gate line WSL from V _off to V _on (T ₇ ), and the gate of the transistor T _Dr is signaled. Connect to line DTL. Then, the gate voltage of the transistor T _Dr becomes V _sig . At this time, the voltage of the anode of the organic EL element 112R or the like is still lower than the threshold voltage V _el of the organic EL element 112R or the like at this stage, and the organic EL element 112R or the like is cut off. Therefore, the current I _ds flows to the element capacitance (not shown) such as the organic EL element 112R, and the element capacitance is charged. Therefore, the source voltage V _s increases by ΔV, and the potential difference V _gs eventually becomes V _sig + V _th − ΔV. In this way, μ correction is performed simultaneously with writing. Here, since ΔV increases as the mobility μ of the transistor T _Dr increases, variation in the mobility μ for each pixel can be eliminated by reducing the potential difference V _gs by ΔV before light emission.

(Light emission)
Finally, the write scanning circuit 130 lowers the voltage of the gate line WSL from V _on to V _off (T ₈ ). Then, the gate of the transistor _{T Dr} is a floating, the drain of the transistor _{T Dr} - current _{I ds} flows between the source, the source voltage _{V s} rises. As a result, the organic EL element 112R and the like emit light with desired luminance.

  By the way, the horizontal drive circuit 120, the write scanning circuit 130, and the power supply scanning circuit 140 are all basically composed of shift registers (not shown), and each stage corresponds to each column or each row of the pixels 111. Are provided with a signal output unit (not shown). Therefore, as the number of columns and rows of the pixels 111 increases, the number of signal lines DTL, drain lines DSL, and gate lines WSL increases accordingly, and the number of output stages of the shift register also increases accordingly. The circuit scale has been increased.

  In view of this, measures have been conventionally taken to reduce the increase in the circuit scale around the display unit 110 by sharing the output stage of the shift register. For example, Patent Document 2 proposes a method in which a signal line DTL is shared by a plurality of pixels 111. In this way, the output stage of the shift register in the horizontal driving circuit 120 that drives the signal line DTL can be shared by a plurality of pixel columns, and accordingly, the circuit scale can be reduced, the circuit area can be reduced, and the circuit cost can be reduced. Reduction is possible.

JP 2008-083272 A JP 2006-251322 A

  Patent Document 2 describes that the output stage of the shift register in the horizontal drive circuit 120 is shared by a plurality of pixel columns. However, the output stage of the shift register is also used in the write scanning circuit 130 and the power supply scanning circuit 140. It is important to increase the cost performance of the display device. In particular, for the power supply scanning circuit 140, it is necessary to increase the size of the signal output unit in order to stabilize the current supply capability. Therefore, the output stage of the shift register in the power supply scanning circuit 140 is shared by a plurality of pixel rows. By reducing the number of signal output units, it is possible to effectively reduce the cost and size of the display device.

  FIG. 16 illustrates a schematic configuration of a display device 200 in which a signal output unit in the power supply scanning circuit 140 is shared by a plurality of pixel rows. In the display device 200 shown in FIG. 16, one drain line DSL (DSL1, DSL2,...) Is connected to each signal output unit in the power supply scanning circuit 140, and each drain line DSL (DSL1, DSL1, DSL1,. Pixels 111 belonging to a plurality of pixel rows (three rows in FIG. 16) are connected to DSL2,. On the other hand, one signal line DTL (DTL1, DTL2,...) Is connected to each signal output unit in the horizontal drive circuit 120, and each row of pixels is connected to each signal line (DTL1, DTL2,...). 111 are connected one by one. Further, one gate line WSL (WSL1, WSL2,...) Is connected to each signal output unit in the write scanning circuit 130, and each column is connected to each gate line WSL (WSL1, WSL2,...). Are connected one by one.

FIG. 17 illustrates an example of various waveforms in the display device 200 illustrated in FIG. In FIG. 17, two types of voltages (V _cc , V _ss (<V _cc )) are applied to the drain line DSL, and two types of voltages (V _on , V _off (<V _on )) are applied to the gate lines WSL1 to WSL6. The state of being applied is shown. As can be seen from FIG. 17, in the display device 200, a plurality of pixel rows (three rows in FIG. 17) are used as one unit, and are common to each pixel 111 from the drain line DSL (DSL1, DSL2,. V _cc and V _ss are applied at the timing.

FIG. 18 illustrates an example of a voltage waveform applied to one pixel 111 of the display device 200. Specifically, two types of voltages (V _cc , V _ss ) are applied to the drain line DSL, and three types of voltages (V _sig , V _ers (<V _ell ), V _ofs (<V _ers )) are applied to the signal line DTL. However, it is shown that two types of voltages (V _on , V _off ) are applied to the gate line WSL. Further, FIG. 18 shows how the gate voltage V _g and the source voltage V _{s of} the transistor T _Dr change from moment to moment in response to voltage application to the drain line DSL, the signal line DTL, and the gate line WSL. ing. Note that the above V _el is a threshold voltage of the organic EL element 112R and the like.

  Since the waveform shown in FIG. 18 is slightly different from the waveform shown in FIG. 15, the waveform shown in FIG. 18 will be described in detail below.

(Extinction period)
First, the organic EL element 112R and the like are quenched. Specifically, when the voltage of the drain line DSL is V _cc and the voltage of the signal line DTL is _Vers , the write scanning circuit 130 changes the voltage of the gate line WSL from V _off to V _on . (T ₁ ), the gate of the transistor T _Dr is connected to the signal line DTL. Then, begins to fall the gate voltage _{V g} of the transistor _{T Dr,} it begins to drop even the source voltage _{V s} of the transistor _{T Dr} by coupling through the storage capacitor _{C s.} After that, the gate voltage V _g becomes V _ers , the source voltage V _s becomes V _el + V _ca (V _ca is a cathode voltage of the organic EL element 112R and the like), and the write scanning circuit 130 is turned on when the organic EL element 112R and the like are extinguished. The voltage of the gate line WSL is lowered from V _on to V _off, and the gate of the transistor T _Dr is brought into a floating state (T ₂ ).

(Vth correction preparation period)
Next, preparation for Vth correction is performed. Specifically, when the voltage of the gate line WSL is V _off , the power supply scanning circuit 140 decreases the voltage of the drain line DSL from V _cc to V _ss (T ₃ ). Then, is the drain line DSL side of the transistor _{T Dr} is the source and the drain of the transistor _{T Dr} - current _{I ds} flows between the source, where the gate voltage _{V g} becomes _V ss _{+ V th,} current _{I ds} stops. At this time, the source voltage V _s is V _el + V _ca − (V _ers − (V _ss + V _th )), and the potential difference V _gs is smaller than V _th .

Subsequently, the power supply scanning circuit 140 increases the voltage of the drain line DSL from V _ss to V _cc (T ₄ ). Then, a current I _ds flows between the drain and source of the transistor T _Dr , and the gate voltage V _g and the source voltage V _s are caused by capacitive coupling between the parasitic capacitance between the gate and drain of the transistor T _Dr and the holding capacitor C _s . To rise. At this time, the potential difference V _gs is still smaller than V _th .

(First Vth correction period)
Next, _Vth is corrected. Specifically, when the voltage of the drain line DSL is V _cc and the voltage of the signal line DTL is V _ofs , the write scanning circuit 130 changes the voltage of the gate line WSL from V _off to V _on . Raise (T ₅ ). Then, a current I _ds flows between the drain and source of the transistor T _Dr , and the gate voltage V _g and the source voltage V _s are caused by capacitive coupling between the parasitic capacitance between the gate and drain of the transistor T _Dr and the holding capacitor C _s . To rise. Here, since the storage capacitor C _s is extremely smaller than the element capacitance of the organic EL element 112R and the like, and the increase amount of the source voltage V _s is sufficiently smaller than the increase amount of the gate voltage V _g , the potential difference V _gs becomes large. Then, when the potential difference V _gs becomes larger than V _th , the write scanning circuit 130 reduces the voltage of the gate line WSL from V _on to V _off (T ₆ ). Then, the gate of the transistor _TDr becomes floating, and the correction of _Vth is temporarily stopped.

(First Vth correction pause period)
During the period when the Vth correction is paused, the voltage of the signal line DTL is sampled in another row (pixel) different from the row (pixel) on which the previous Vth correction has been performed. At this time, since the source voltage V _s is lower than V _ofs −V _th in the row (pixel) in which the previous Vth correction has been performed, the row in which the previous Vth correction has been performed even during the Vth correction pause period ( In the pixel), a current I _ds flows between the drain and source of the transistor T _Dr , the source voltage V _s rises, and the gate voltage V _g also rises due to coupling via the storage capacitor C _s .

(Second Vth correction period)
After the Vth correction pause period ends, _Vth is corrected again. Specifically, when the voltage of the signal line DTL is V _ofs and Vth correction is possible, the write scanning circuit 130 raises the voltage of the gate line WSL from V _off to V _on (T ₅ ). The gate of the transistor T _Dr is connected to the signal line DTL. At this time, when the source voltage V _s is lower than V _ofs −V _th (when Vth correction is not yet completed), until the transistor T _Dr is cut off (until the potential difference V _gs becomes V _th ). A current I _ds flows between the drain and source of the transistor T _Dr. Thereafter, before the horizontal drive circuit 120 switches the voltage of the signal line DTL from V _ofs to V _sig , the write scanning circuit 130 lowers the voltage of the gate line WSL from V _on to V _off (T ₆ ). Then, since the gate of the transistor T _Dr becomes floating, the potential difference V _gs can be kept constant regardless of the voltage level of the signal line DTL.

Incidentally, in this Vth correction period, the holding capacitor _{C s} is charged to _{V th,} when the potential difference _{V gs} becomes _{V th} is terminated Vth correction, not reached the potential difference _{V gs} until the _{V th} In this case, Vth correction and Vth correction pause are repeatedly performed until the potential difference V _gs reaches V _th .

(Writing / μ correction period)
After the Vth correction pause period ends, writing and μ correction are performed. Specifically, while the voltage of the signal line DTL is V _sig , the write scanning circuit 130 raises the voltage of the gate line WSL from V _off to V _on (T ₇ ), and the gate of the transistor T _Dr is signaled. Connect to line DTL. Then, the gate voltage of the transistor T _Dr becomes V _sig . At this time, the voltage of the anode of the organic EL element 112R or the like is still lower than the threshold voltage V _el of the organic EL element 112R or the like at this stage, and the organic EL element 112R or the like is cut off. Therefore, the current _{I ds} flows to the element capacitance such as an organic EL element 112R, since the element capacitance is charged, the source voltage _{V s} is increased by [Delta] V, the potential difference _{V gs} becomes _V sig _{+ V th -ΔV} soon. In this way, μ correction is performed simultaneously with writing.

(Light emission)
Finally, the write scanning circuit 130 lowers the voltage of the gate line WSL from V _on to V _off (T ₈ ). Then, the gate of the transistor _{T Dr} is a floating, the drain of the transistor _{T Dr} - current _{I ds} flows between the source, the source voltage _{V s} rises. As a result, the organic EL element 112R and the like emit light with desired luminance.

Incidentally, as shown in FIG. 14, the ground line GND connected to the cathode of the organic EL element 112 </ b> R and the like is arranged extending around the pixels 111 </ b> R, 111 </ b> G, and 111 </ b> B. Therefore, the ground line GND intersects with the drain line DSL connected to the power supply scanning circuit 140, and a parasitic capacitance _Cα exists at the intersection of the ground line GND and the drain line DSL. As a result, changes or voltage of the drain line DSL from _{V cc} to _{V ini,} when or changed from _{V ini} to _{V cc,} thereby swinging the voltage of the ground line GND by coupling through the parasitic capacitance C _alpha.

Figure 19 is a state in which the swing voltage of the ground line GND by coupling through the parasitic capacitance C _alpha that schematically shows. From FIG. 19, when the voltage of the drain line DSL of the pixels 111R, 111G, and 111B included in one unit is changed from V _cc to V _ini or from V _ini to V _cc , the voltage of the ground line GND is also increased. It can be seen that the signal fluctuates according to the voltage change of the line DSL.

Thus, when the voltage of the ground line GND fluctuates according to the voltage change of the drain line DSL of the pixels 111R, 111G, and 111B included in one unit, the pixels 111R, 111G, and 111B included in the adjacent unit. Then, Vth correction is just performed (see FIG. 17). However, this time, along with the swing of the voltage of the ground line GND, the pixel is performed Vth correction 111R, 111G, at 111B, thus also swing the gate voltage _{V g} and the source voltage _{V s.} As a result, for example, as shown in FIG. 20, when the source voltage V _s is pushed up during Vth correction and exceeds V _ofs −V _th , the potential difference V _gs becomes smaller than V _th , There has been a problem that Vth correction cannot be performed correctly.

The present invention has been made in view of the above problems, its object is, when correcting the V _th, capable display device and a driving method of a potential difference V _gs is prevented from becoming smaller than V _th And providing electronic equipment.

  A display device according to the present invention includes a display unit in which a plurality of pixels each including a light emitting element and a pixel circuit are two-dimensionally arranged in a row direction and a column direction, and a drive unit that drives the pixel circuit based on a video signal; It is equipped with. The pixel circuit is provided with a first transistor, a second transistor, and a storage capacitor. The driving unit includes a first driving unit, a second driving unit, a third driving unit, a control unit, a first wiring, a second wiring, a third wiring, and a fourth voltage set to a reference voltage. Wiring is provided. One second wiring is provided for each unit with a plurality of pixel rows as one unit. The gate of the first transistor is connected to the first drive unit via the first wiring. The drain or source of the first transistor is connected to the third drive unit via the third wiring. Of the drain and source of the first transistor, the one not connected to the third drive unit is connected to the gate of the second transistor and one end of the storage capacitor. The drain or source of the second transistor included in each pixel in the unit is connected to the second drive unit via a common second wiring. Of the drain and source of the second transistor, the one not connected to the second drive unit is connected to the other end of the storage capacitor and the anode of the light emitting element. The cathode of the light emitting element is connected to the fourth wiring. Here, the first drive unit can output a first voltage lower than the on-voltage of the first transistor and a second voltage equal to or higher than the on-voltage of the first transistor to the first wiring. The second drive unit can output a third voltage lower than the sum of the threshold voltage of the light emitting element and the reference voltage and a fourth voltage equal to or higher than the sum of the threshold voltage of the light emitting element and the reference voltage to the second wiring. It has become. The third driving unit can output the fifth voltage and the sixth voltage having a magnitude corresponding to the video signal to the third wiring. In the control unit, the voltage of the first wiring is the first voltage, and the voltage of the second wiring provided corresponding to one unit is the third voltage with respect to the second driving unit. And when the voltage of the second wiring provided corresponding to another unit adjacent to one unit is the fourth voltage, the voltage of the second wiring provided corresponding to the one unit is A control signal for instructing to lower the voltage of the second wiring provided corresponding to another unit adjacent to one unit from the fourth voltage to the third voltage at the same time as raising from the third voltage to the fourth voltage. It is designed to output.

  An electronic apparatus according to the present invention includes the display device.

  According to the display device driving method of the present invention, in the second driving unit of the display device having the following configuration, the voltage of the first wiring is the first voltage, and the first driving voltage is provided corresponding to one unit. Corresponds to one unit when the voltage of two wires is the third voltage and the voltage of the second wire provided corresponding to another unit adjacent to one unit is the fourth voltage The voltage of the second wiring provided in this manner is raised from the third voltage to the fourth voltage, and at the same time, the voltage of the second wiring provided corresponding to another unit adjacent to one unit is changed from the fourth voltage to the fourth voltage. The step of lowering to 3 voltages is executed.

  A display device using the driving method drives a pixel circuit based on a display unit in which a plurality of pixels each including a light emitting element and a pixel circuit are two-dimensionally arranged in a row direction and a column direction, and a video signal. And a drive unit. The pixel circuit is provided with a first transistor, a second transistor, and a storage capacitor. The driving unit includes a first driving unit, a second driving unit, a third driving unit, a first wiring, a second wiring, a third wiring, and a fourth wiring set to a reference voltage. It has been. One second wiring is provided for each unit with a plurality of pixel rows as one unit. The gate of the first transistor is connected to the first drive unit via the first wiring. The drain or source of the first transistor is connected to the third drive unit via the third wiring. Of the drain and source of the first transistor, the one not connected to the third drive unit is connected to the gate of the second transistor and one end of the storage capacitor. The drain or source of the second transistor included in each pixel in the unit is connected to the second drive unit via a common second wiring. Of the drain and source of the second transistor, the one not connected to the second drive unit is connected to the other end of the storage capacitor and the anode of the light emitting element. The cathode of the light emitting element is connected to the fourth wiring. Here, the first drive unit can output a first voltage lower than the on-voltage of the first transistor and a second voltage equal to or higher than the on-voltage of the first transistor to the first wiring. The second drive unit can output a third voltage lower than the sum of the threshold voltage of the light emitting element and the reference voltage and a fourth voltage equal to or higher than the sum of the threshold voltage of the light emitting element and the reference voltage to the second wiring. It has become. The third driving unit can output the fifth voltage and the sixth voltage having a magnitude corresponding to the video signal to the third wiring.

  In the display device, the driving method thereof, and the electronic device of the present invention, the voltage of the first wiring is the first voltage, and the voltage of the second wiring provided corresponding to one unit is the third voltage. And when the voltage of the second wiring provided corresponding to the other unit adjacent to one unit is the fourth voltage, the voltage of the second wiring provided corresponding to the one unit is At the same time as the third voltage is raised to the fourth voltage, the voltage of the second wiring provided corresponding to the other unit adjacent to the one unit is lowered from the fourth voltage to the third voltage. In this way, by synchronizing the voltage change of the second wiring between the units adjacent to each other, the fluctuation of the voltage of the fourth wiring due to the coupling through the parasitic capacitance is cancelled.

According to the display device, the driving method thereof, and the electronic apparatus of the present invention, the voltage variation of the fourth wiring due to the coupling through the parasitic capacitance is achieved by synchronizing the voltage change of the second wiring of the units adjacent to each other. since so as to cancel, when correcting the V _th, it is possible to fourth potential difference V _gs due to the fluctuation of the voltage of the wiring is prevented from becoming smaller than V _th. As a result, _Vth can be reliably corrected.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows an example of the entire configuration of a display device 1 according to an embodiment of the present invention. The display device 1 includes, for example, a display unit 10 and a peripheral circuit unit 20 (driving unit) formed around the display unit 10 on a substrate (not shown) made of glass, silicon (Si) wafer, resin, or the like. ).

  The display unit 10 has a plurality of pixels 11 arranged two-dimensionally in the row direction and the column direction over the entire surface of the display unit 10, and displays an image based on the video signal 20a input from the outside by active matrix driving. Is. Each pixel 11 includes a red pixel 11R, a green pixel 11G, and a blue pixel 11B.

  FIG. 2 illustrates an example of the internal configuration of the pixels 11R, 11G, and 11B. In the pixels 11R, 11G, and 11B, as shown in FIG. 2, organic EL elements 12R, 12G, and 12B (light emitting elements) and a pixel circuit 13 are provided.

  The organic EL elements 12R, 12G, and 12B (hereinafter referred to as the organic EL element 12R and the like) have, for example, a configuration in which an anode (anode), an organic layer, and a cathode (cathode) are sequentially stacked, although not shown. Yes. The organic layer is, for example, sequentially from the anode side, a hole injection layer that increases hole injection efficiency, a hole transport layer that increases hole transport efficiency to the light emitting layer, and light emission by recombination of electrons and holes. Has a stacked structure in which a light-emitting layer that generates light and an electron-transporting layer that increases the efficiency of electron transport to the light-emitting layer are stacked.

The pixel circuit 13 includes a sampling transistor T _WS (first transistor), a storage capacitor C _s , and a driving transistor T _Dr (second transistor), and has a circuit configuration of 2Tr1C. The transistors T _WS and T _Dr are formed by, for example, n-channel MOS type thin film transistors (TFTs).

  The peripheral circuit unit 20 includes a timing control circuit 21 (control unit), a horizontal drive circuit 22 (third drive unit), a write scan circuit 23 (first drive unit), and a power supply scan circuit 24 (second drive unit). And have. The timing control circuit 21 includes a display signal generation circuit 21A and a display signal holding control circuit 21B. The peripheral circuit unit 20 includes a gate line WSL (first wiring), a drain line DSL (second wiring), a signal line DTL (third wiring), and a ground line GND (fourth wiring). It has been. The ground line GND is connected to the ground and set to the ground voltage (reference voltage).

  As shown in FIGS. 1 and 3, one drain line DSL is provided for each unit U with a plurality of pixel rows as one unit U. FIG. 3 illustrates the case where five units U are provided, but the number of units is not limited thereto. Further, in FIG. 3, suffixes that are increased by one are given to the five units U in the scanning direction of the power supply scanning circuit 24. Accordingly, the unit U1 corresponds to the initial unit in the scanning direction, and the unit U5 corresponds to the final unit in the scanning direction.

  The display signal generation circuit 21A generates a display signal 21a to be displayed on the display unit 10 for each screen (for each display of one field), for example, based on the video signal 20a input from the outside.

  The display signal holding control circuit 21B stores the display signal 21a output from the display signal generation circuit 21A for each screen (for each display of one field), for example, in a field memory composed of SRAM (Static Random Access Memory) or the like. And hold it. The display signal holding control circuit 21B also plays a role of controlling the horizontal driving circuit 22, the writing scanning circuit 23, and the power supply scanning circuit 24 that drive each pixel 11 to operate in conjunction with each other. Specifically, the display signal holding control circuit 21B has a control signal 21b for the write scanning circuit 23, a control signal 21c for the power supply scanning circuit 24, and a control signal 21d for the horizontal drive circuit 22. Are each output.

The horizontal drive circuit 22 includes, for example, a shift register (not shown), and includes a signal output unit (not shown) for each stage corresponding to each column of the pixels 11. The horizontal drive circuit 22 has three types of voltages (V _ers (sixth voltage), V _ofs (fifth voltage), V _sig (sixth) according to the control signal 21d output from the display signal holding control circuit 21B. Voltage)) can be output. Specifically, the horizontal drive circuit 22 _applies three types of voltages (V _ers , V _ofs) to the pixel 11 selected by the write scanning circuit 23 via the signal line DTL connected to each pixel 11 of the display unit 10. , V _sig ).

Here, V _ofs has a lower voltage value than V _ers . V _sig is a voltage value corresponding to the video signal 20a. The minimum voltage of V _sig is a voltage value lower than V _ofs, and the maximum voltage of V _sig is a voltage value higher than V _ofs .

The write scanning circuit 23 is configured by, for example, a shift register (not shown), and includes a signal output unit (not shown) for each stage corresponding to each row of the pixels 11. The writing scanning circuit 23 can output two types of voltages (V _on (second voltage) and V _off (first voltage)) in accordance with the control signal 21b output from the display signal holding control circuit 21B. ing. Specifically, the writing scanning circuit 23 supplies two types of voltages (V _on , V _off ) to the pixel 11 to be driven via the gate line WSL connected to each pixel 11 of the display unit 10, The sampling transistor _TWS is controlled.

Here, the voltage V _on has a value equal to or higher than the on-voltage of the transistor _TWS . V _on is a voltage value output from the write scanning circuit 23 during extinction or Vth correction described later. V _off has a value lower than the on-voltage of the transistor T _WS and a value lower than V _on . V _off is a voltage value output from the writing scanning circuit 23 during the “quenching period”, “Vth correction preparation period”, “Vth correction pause period”, and “light emission period” which will be described later.

  The power supply scanning circuit 24 is configured by, for example, a shift register (not shown), and corresponds to each unit (U1 to U5) for each number of stages equal to the number of rows included in each unit (U1 to U5). Are provided with a signal output unit (not shown). That is, in this embodiment, the output stage of the shift register in the power supply scanning circuit 24 is shared for each unit (U1 to U5), and the unit scan method is adopted. For this reason, the number of signal output units in the power supply scanning circuit 24 is smaller than in the case where a signal output unit is provided for each stage corresponding to each pixel column.

The power supply scanning circuit 24 can output two types of voltages (V _ss (third voltage) and V _cc (fourth voltage)) in accordance with the control signal 21c output from the display signal holding control circuit 21B. ing. Specifically, the power supply scanning circuit 24 supplies two types of voltages (V _ini and V _ss ) to the drive target pixel 11 via the drain line DSL connected to each pixel 11 of the display unit 10. Light emission and quenching of the organic EL element 12R and the like are controlled.

Here, V _ss is a voltage value lower than a voltage (V _el + V _ca ) obtained by adding the threshold voltage V _el of the organic EL element 12R or the like and the cathode voltage V _ca of the organic EL element 12R or the like. V _cc is a voltage value equal to or higher than the voltage (V _el + V _ca ).

Next, with reference to FIG. 1 and FIG. 2, the connection relationship of each component is demonstrated. The signal lines DTL (DTL1, DTL2,...) Formed so as to extend in the column direction are connected to individual signal output portions in the horizontal drive circuit 22 one by one, and the individual signal lines (DTL1, DTL1,. DTL2, the ...), the drain of the transistor _{T WS} is one by one connections in each row of pixels 11. Further, gate lines WSL (WSL1, WSL2,...) Extending in the row direction are connected to individual signal output portions in the write scanning circuit 23 one by one, and the individual gate lines WSL are connected. (WSL1, WSL2,...) Are connected to the gates of the transistors _TWS included in the pixels 11 of each column one by one. In addition, drain lines DSL (DSL1, DSL2,...) Formed so as to extend in the row direction are connected to individual signal output portions in the power supply scanning circuit 24 one by one. (DSL1, DSL2,...) Are connected to the drain of the transistor T _Dr included in each pixel 11 in the unit (U1 to U5). Further, each pixel 11R, 11G, at 11B, the source of the transistor _{T WS} is the gate of the transistor _{T Dr} for driving, is connected to one end of the storage capacitor _{C s,} the source and the holding capacitor _{C s} of the transistor _{T Dr} The other end is connected to an anode such as the organic EL element 12R. The cathode of the organic EL element 12R and the like is connected to the ground line GND.

Next, the operation (operation from quenching to light emission) of the display device 1 of the present embodiment will be described. In the present embodiment, or the I-V characteristic changes over time, such as an organic EL element 12R, also the threshold voltage V _th and the mobility μ of the transistor T _Dr is or change over time, without receiving their effects In order to keep the light emission luminance of the organic EL element 12R and the like constant, the compensation operation for the variation of the IV characteristics of the organic EL element 12R and the like, and the variation of the threshold voltage _Vth and mobility μ of the transistor T _Dr A correction operation is incorporated.

FIG. 4 shows an example of various waveforms in the display device 1. In FIG. 4, two types of voltages (V _cc , V _ss (<V _cc )) are applied to the drain line DSL, and two types of voltages (V _on , V _off (<V _on )) are applied to the gate lines WSL1 to WSL6. The state of being applied is shown. As can be seen from FIGS. 1 and 4, in the display device 1, V _cc and V _ss are applied from the drain line DSL (DSL1, DSL2,...) To each pixel 11 at a common timing for each unit (U1 to U5). Is done. Further, the voltage of the gate line WSL is V _off , the voltage of the drain line DSL provided corresponding to one unit (for example, U1) is V _cc , and one unit (for example, U1). The voltage of the drain line DSL provided corresponding to one unit (for example, U1) when the voltage of the drain line DSL provided corresponding to another unit (for example, U2) adjacent to is V _ss Is raised from V _ss to V _cc , the voltage of the drain line DSL provided corresponding to another unit (eg, U 2) adjacent to one unit (eg, U 1) is lowered from V _cc to V _ss. . As described above, in this embodiment, the voltage changes of the drain lines DSL of the units adjacent to each other (for example, U1 and U2) are synchronized.

FIG. 5 shows an example of a voltage waveform applied to one pixel 11 of the display device 1. Specifically, two types of voltages (V _cc , V _ss ) are applied to the drain line DSL, and three types of voltages (V _sig , V _ers (<V _ell ), V _ofs (<V _ers )) are applied to the signal line DTL. However, it is shown that two types of voltages (V _on , V _off ) are applied to the gate line WSL. Further, FIG. 5 shows that the gate voltage V _g and the source voltage V _{s of} the transistor T _Dr change from moment to moment in response to voltage application to the drain line DSL, the signal line DTL, and the gate line WSL. ing. Note that the above V _el is a threshold voltage of the organic EL element 12R and the like.

(Extinction period)
First, quenching of the organic EL element 12R and the like is performed. Specifically, when the voltage of the drain line DSL is V _cc and the voltage of the signal line DTL is _Vers , the write scanning circuit 23 changes the voltage of the gate line WSL from V _off to V _on . (T ₁ ), the gate of the transistor T _Dr is connected to the signal line DTL. Then, begins to fall the gate voltage _{V g} of the transistor _{T Dr,} it begins to drop even the source voltage _{V s} of the transistor _{T Dr} by coupling through the storage capacitor _{C s.} After that, the gate voltage V _g becomes V _ers , the source voltage V _s becomes V _el + V _ca (V _ca is a cathode voltage of the organic EL element 12R, etc.), and the write scanning circuit 23 is activated when the organic EL element 12R, etc. is extinguished. The voltage of the gate line WSL is lowered from V _on to V _off, and the gate of the transistor T _Dr is brought into a floating state (T ₂ ).

(Vth correction preparation period)
Next, preparation for Vth correction is performed. Specifically, when the voltage of the gate line WSL is V _off , the power supply scanning circuit 24 lowers the voltage of the drain line DSL from V _cc to V _ss (T ₃ ). Then, is the drain line DSL side of the transistor _{T Dr} is the source and the drain of the transistor _{T Dr} - current _{I ds} flows between the source, where the gate voltage _{V g} becomes _V ss _{+ V th,} current _{I ds} stops. At this time, the source voltage V _s is V _el + V _ca − (V _ers − (V _ss + V _th )), and the potential difference V _gs is smaller than V _th .

Subsequently, the power supply scanning circuit 24 increases the voltage of the drain line DSL from V _ss to V _cc (T ₄ ). Then, a current I _ds flows between the drain and source of the transistor T _Dr , and the gate voltage V _g and the source voltage V _s are caused by capacitive coupling between the parasitic capacitance between the gate and drain of the transistor T _Dr and the holding capacitor C _s . To rise. At this time, the potential difference V _gs is still smaller than V _th .

(First Vth correction period)
Next, _Vth is corrected. Specifically, when the voltage of the drain line DSL is V _cc and the voltage of the signal line DTL is V _ofs , the write scanning circuit 23 changes the voltage of the gate line WSL from V _off to V _on . Raise (T ₅ ). Then, a current I _ds flows between the drain and source of the transistor T _Dr , and the gate voltage V _g and the source voltage V _s are caused by capacitive coupling between the parasitic capacitance between the gate and drain of the transistor T _Dr and the holding capacitor C _s . To rise. Here, since the storage capacitor C _s is extremely smaller than the element capacitance of the organic EL element 12R and the like, and the increase amount of the source voltage V _s is sufficiently smaller than the increase amount of the gate voltage V _g , the potential difference V _gs becomes large. Then, when the potential difference V _gs becomes larger than V _th , the write scanning circuit 23 lowers the voltage of the gate line WSL from V _on to V _off (T ₆ ). Then, the gate of the transistor _TDr becomes floating, and the correction of _Vth is temporarily stopped.

(First Vth correction pause period)
During the period when the Vth correction is paused, for example, the voltage of the signal line DTL is sampled in another row (pixel) different from the row (pixel) on which the previous Vth correction has been performed. At this time, since the source voltage V _s is lower than V _ofs −V _th in the row (pixel) in which the previous Vth correction has been performed, the row in which the previous Vth correction has been performed even during the Vth correction pause period ( In the pixel), a current I _ds flows between the drain and source of the transistor T _Dr , the source voltage V _s rises, and the gate voltage V _g also rises due to coupling via the storage capacitor C _s .

(Second Vth correction period)
After the Vth correction pause period ends, _Vth is corrected again. Specifically, when the voltage of the signal line DTL is V _ofs and Vth correction is possible, the write scanning circuit 23 increases the voltage of the gate line WSL from V _off to V _on (T ₅ ). The gate of the transistor T _Dr is connected to the signal line DTL. At this time, when the source voltage V _s is lower than V _ofs −V _th (when Vth correction is not yet completed), until the transistor T _Dr is cut off (until the potential difference V _gs becomes V _th ). A current I _ds flows between the drain and source of the transistor T _Dr. Thereafter, before the horizontal drive circuit 22 switches the voltage of the signal line DTL from V _ofs to V _sig , the write scanning circuit 23 lowers the voltage of the gate line WSL from V _on to V _off (T ₆ ). Then, since the gate of the transistor T _Dr becomes floating, the potential difference V _gs can be kept constant regardless of the voltage level of the signal line DTL.

Incidentally, in this Vth correction period, the holding capacitor _{C s} is charged to _{V th,} when the potential difference _{V gs} becomes _{V th} is terminated Vth correction, not reached the potential difference _{V gs} until the _{V th} In this case, Vth correction and Vth correction pause are repeatedly performed until the potential difference V _gs reaches V _th .

(Writing / μ correction period)
After the Vth correction pause period ends, writing and μ correction are performed. Specifically, while the voltage of the signal line DTL is V _sig , the write scanning circuit 23 increases the voltage of the gate line WSL from V _off to V _on (T ₇ ), and the gate of the transistor T _Dr is signaled. Connect to line DTL. Then, the gate voltage of the transistor T _Dr becomes V _sig . At this time, the anode voltage of an organic EL element 12R is smaller than the threshold voltage _{V el} still such as organic EL devices 12R at this stage, the organic EL device 12R and the like is cut off. Therefore, the current _{I ds} flows to the element capacitance such as an organic EL element 12R, since the element capacitance is charged, the source voltage _{V s} is increased by [Delta] V, the potential difference _{V gs} becomes _V sig _{+ V th -ΔV} soon. In this way, μ correction is performed simultaneously with writing.

(Light emission)
Finally, the write scanning circuit 23 lowers the voltage of the gate line WSL from V _on to V _off (T ₈ ). Then, the gate of the transistor _{T Dr} is a floating, the drain of the transistor _{T Dr} - current _{I ds} flows between the source, the source voltage _{V s} rises. As a result, the organic EL element 12R and the like emit light with desired luminance.

  In the display device 1 of the present embodiment, as described above, the pixel circuit 13 is controlled to be turned on / off in each pixel 11, and a driving current is injected into the organic EL element 12 </ b> R of each pixel 11. Light emission occurs due to recombination with electrons. This light is multiple-reflected between the anode and the cathode, passes through the cathode, etc., and is extracted outside. As a result, an image is displayed on the display unit 10.

By the way, as shown in FIG. 2, the ground line GND connected to the cathode of the organic EL element 12R or the like is arranged extending vertically and horizontally around the pixels 11R, 11G, and 11B. Therefore, the ground line GND intersects with the drain line DSL connected to the power supply scanning circuit 24, and a parasitic capacitance _Cα exists at the intersection between the ground line GND and the drain line DSL. As a result, changes or voltage of the drain line DSL from _{V cc} to _{V ini,} when or changed from _{V ini} to _{V cc,} thereby swinging the voltage of the ground line GND by coupling through the parasitic capacitance C _alpha.

Figure 19 is a state in which the swing voltage of the ground line GND by coupling through the parasitic capacitance C _alpha that schematically shows. From FIG. 19, when the voltage of the drain line DSL of the pixels 11R, 11G, and 11B included in one unit is changed from V _cc to V _ini or from V _ini to V _cc , the voltage of the ground line GND is also increased. It can be seen that the signal fluctuates according to the voltage change of the line DSL.

Thus, when the voltage of the ground line GND fluctuates according to the voltage change of the drain line DSL of the pixels 11R, 11G, and 11B included in one unit, as shown in FIG. In the included pixels 11R, 11G, and 11B, Vth correction has just been performed. However, this time, along with the swing of the voltage of the ground line GND, the pixel 11R are performed Vth correction, 11G, at 11B, thereby also swing the gate voltage _{V g} and the source voltage _{V s.} As a result, for example, as shown in FIG. 20, when the source voltage V _s is pushed up during Vth correction and exceeds V _ofs −V _th , the potential difference V _gs becomes smaller than V _th , Vth correction cannot be performed correctly.

On the other hand, in the display device 1 of the present embodiment, as shown in FIGS. 4 and 6, the voltage of the gate line WSL is V _off and provided corresponding to one unit (for example, U1). the voltage of the drain line DSL has a V _ss, and one unit (e.g., U1) other unit adjacent to (e.g., U2) to the voltage of the drain line DSL provided correspondingly has a V _cc Sometimes, the voltage of the drain line DSL provided corresponding to one unit (for example, U1) is raised from V _ss to V _cc , and at the same time, another unit (for example, U2) adjacent to the one unit (for example, U1). drain line DSL voltage provided corresponding to is lowered to _{V ss} from _{V cc.} In this manner, by synchronizing the change in voltage of the drain line DSL for between the adjacent units (e.g. U1, U2) with each other, to cancel the fluctuation of the voltage of the ground line GND by coupling through the parasitic capacitance C _alpha Can do. Thereby, when correcting _Vth , it is possible to prevent the potential difference _Vgs from becoming smaller than _Vth due to the fluctuation of the voltage of the ground line GND. As a result, _Vth can be reliably corrected.

(Modules and application examples)
Hereinafter, application examples of the display device 1 described in the above embodiment will be described. The display device 1 according to the above embodiment is a television device, a digital camera, a notebook personal computer, a mobile terminal device such as a mobile phone, or a video camera, such as an externally input video signal or an internally generated video signal. The present invention can be applied to display devices for electronic devices in various fields that display images or videos.

(module)
The display device 1 according to the above-described embodiment is incorporated into various electronic devices such as application examples 1 to 5 described later, for example, as a module as illustrated in FIG. In this module, for example, an area 210 exposed from a member (not shown) that seals the display unit 10 is provided on one side of the substrate 2, and the timing control circuit 21, the horizontal drive circuit 22, The wiring lines of the write scanning circuit 23 and the power supply scanning circuit 24 are extended to form external connection terminals (not shown). The external connection terminal may be provided with a flexible printed circuit (FPC) 220 for signal input / output.

(Application example 1)
FIG. 8 illustrates an appearance of a television device to which the display device 1 of the above embodiment is applied. The television apparatus has, for example, a video display screen unit 300 including a front panel 310 and a filter glass 320, and the video display screen unit 300 is configured by the display device 1 according to the above embodiment. .

(Application example 2)
FIG. 9 shows the appearance of a digital camera to which the display device 1 of the above embodiment is applied. The digital camera includes, for example, a flash light emitting unit 410, a display unit 420, a menu switch 430, and a shutter button 440. The display unit 420 is configured by the display device 1 according to the above embodiment. Yes.

(Application example 3)
FIG. 10 shows the appearance of a notebook personal computer to which the display device 1 of the above embodiment is applied. The notebook personal computer has, for example, a main body 510, a keyboard 520 for inputting characters and the like, and a display unit 530 for displaying an image. The display unit 530 is a display device according to the above embodiment. 1.

(Application example 4)
FIG. 11 shows the appearance of a video camera to which the display device 1 of the above embodiment is applied. This video camera has, for example, a main body 610, a subject photographing lens 620 provided on the front side surface of the main body 610, a start / stop switch 630 at the time of photographing, and a display 640. Reference numeral 640 denotes the display device 1 according to the above embodiment.

(Application example 5)
FIG. 12 shows the appearance of a mobile phone to which the display device 1 of the above embodiment is applied. For example, the mobile phone is obtained by connecting an upper housing 710 and a lower housing 720 with a connecting portion (hinge portion) 730, and includes a display 740, a sub-display 750, a picture light 760, and a camera 770. Yes. The display 740 or the sub-display 750 is configured by the display device 1 according to the above embodiment.

  While the present invention has been described with the embodiment and application examples, the present invention is not limited to the above-described embodiment and the like, and various modifications can be made.

  For example, in the above-described embodiment, the case where the display device 1 is an active matrix type has been described. However, the configuration of the pixel circuit 13 for driving the active matrix is not limited to that described in the above-described embodiment, and is necessary. Depending on the case, a capacitor or a transistor may be added to the pixel circuit 13. In that case, a necessary drive circuit may be added in addition to the above-described horizontal drive circuit 22, write scan circuit 23, and power supply scan circuit 24 according to the change of the pixel circuit 13.

  In the above embodiment and the like, the signal holding control circuit 21B controls the driving of the horizontal driving circuit 22, the writing scanning circuit 23, and the power supply scanning circuit 24. However, other circuits control the driving of these circuits. May be. The control of the horizontal drive circuit 22, the write scanning circuit 23, and the power supply scanning circuit 24 may be performed by hardware (circuit) or software (program).

It is a block diagram showing an example of the display apparatus which concerns on one embodiment of this invention. It is a block diagram showing an example of the internal structure of the pixel of FIG. It is a conceptual diagram for demonstrating the unit scan of the display apparatus of FIG. It is a wave form diagram for demonstrating an example of operation | movement of the display apparatus of FIG. It is a wave form chart for explaining an example of operation in one pixel. It is a wave form diagram for demonstrating the fluctuation | variation of the electric potential of a ground line. It is a top view showing schematic structure of the module containing the display apparatus of each said embodiment. It is a perspective view showing the external appearance of the application example 1 of the display apparatus of the said embodiment. (A) is a perspective view showing the external appearance seen from the front side of the application example 2, (B) is a perspective view showing the external appearance seen from the back side. 12 is a perspective view illustrating an appearance of application example 3. FIG. 14 is a perspective view illustrating an appearance of application example 4. FIG. (A) is a front view of the application example 5 in an open state, (B) is a side view thereof, (C) is a front view in a closed state, (D) is a left side view, and (E) is a right side view, (F) is a top view and (G) is a bottom view. It is a block diagram showing an example of the conventional display apparatus. It is a block diagram showing an example of the internal structure of the pixel of FIG. FIG. 14 is a waveform diagram for explaining an example of the operation of the display device of FIG. 13. It is a block diagram showing the other example of the conventional display apparatus. FIG. 17 is a waveform diagram for explaining an example of the operation of the display device of FIG. 16. It is a wave form chart for explaining an example of operation in one pixel. It is a wave form diagram for demonstrating the fluctuation | variation of the electric potential of a ground line. It is a wave form diagram for demonstrating the influence of the fluctuation | variation of the electric potential of a ground line.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Display apparatus, 10 ... Display part, 11, 11R, 11G, 11B ... Pixel, 12R, 12G, 12B ... Organic EL element, 13 ... Pixel circuit, 20 ... Peripheral circuit part, 21 ... Timing control circuit, 21A ... Display signal generating circuit, 21B ... display signal retention control circuit, 22 ... horizontal drive circuit, 23 ... writing scanning circuit, 24 ... power scanning circuit, C s _... holding capacity, DSL (DSL1, DSL2, ...... ) ... drain line, DTL (DTL1, DTL2, ......) ... signal line, I _{ds ... current, T Dr, T WS ...} transistors, V g _... gate voltage, V _{gs ...} potential, V s _... source voltage, V _{th ...} threshold voltage, WSL ( WSL1, WSL2, ...) ... Gate lines.

Claims (3)

A display unit in which a plurality of pixels configured to include a light emitting element and a pixel circuit are two-dimensionally arranged in a row direction and a column direction;
A drive unit for driving the pixel circuit based on a video signal,
The pixel circuit includes a first transistor, a second transistor, and a storage capacitor.
The driving unit is set to a first driving unit, a second driving unit, a third driving unit, a control unit, a first wiring, a second wiring, a third wiring, and a reference voltage. Wiring and
The second wiring is provided for each unit with a plurality of pixel rows as one unit,
A gate of the first transistor is connected to the first driver through the first wiring;
A drain or a source of the first transistor is connected to the third driver through the third wiring;
Of the drain and source of the first transistor, the one not connected to the third driver is connected to the gate of the second transistor and one end of the storage capacitor,
A drain or a source of a second transistor included in each pixel in the unit is connected to the second driving unit via a common second wiring;
Of the drain and source of the second transistor, the one not connected to the second drive unit is connected to the other end of the storage capacitor and the anode of the light emitting element,
A cathode of the light emitting element is connected to the fourth wiring;
The first driving unit can output a first voltage lower than an on-voltage of the first transistor and a second voltage equal to or higher than an on-voltage of the first transistor to the first wiring.
The second driving unit generates a third voltage lower than a sum of a threshold voltage of the light emitting element and the reference voltage, and a fourth voltage equal to or higher than a sum of the threshold voltage of the light emitting element and the reference voltage. It is possible to output to 2 wires,
The third driving unit can output a fifth voltage and a sixth voltage having a magnitude corresponding to the video signal to the third wiring.
In the control unit, the voltage of the first wiring is the first voltage with respect to the second driving unit, and the voltage of the second wiring provided corresponding to one unit is the third voltage. When the voltage of the second wiring provided corresponding to the other unit adjacent to the one unit is the fourth voltage, the voltage is provided corresponding to the one unit. The voltage of the second wiring provided corresponding to the other unit adjacent to the one unit is simultaneously raised to the fourth voltage from the third voltage to the fourth voltage. A display device that outputs a control signal instructing to lower the voltage to the third voltage. A display unit in which a plurality of pixels configured to include a light emitting element and a pixel circuit are two-dimensionally arranged in a row direction and a column direction;
A drive unit for driving the pixel circuit based on a video signal,
The pixel circuit includes a first transistor, a second transistor, and a storage capacitor.
The driving unit includes a first driving unit, a second driving unit, a third driving unit, a first wiring, a second wiring, a third wiring, and a fourth wiring set to a reference voltage. And
The second wiring is provided for each unit with a plurality of pixel rows as one unit,
A gate of the first transistor is connected to the first driver through the first wiring;
A drain or a source of the first transistor is connected to the third driver through the third wiring;
Of the drain and source of the first transistor, the one not connected to the third driver is connected to the gate of the second transistor and one end of the storage capacitor,
A drain or a source of a second transistor included in each pixel in the unit is connected to the second driving unit via a common second wiring;
Of the drain and source of the second transistor, the one not connected to the second drive unit is connected to the other end of the storage capacitor and the anode of the light emitting element,
A cathode of the light emitting element is connected to the fourth wiring;
The first driving unit can output a first voltage lower than an on-voltage of the first transistor and a second voltage equal to or higher than an on-voltage of the first transistor to the first wiring.
The second driving unit generates a third voltage lower than a sum of a threshold voltage of the light emitting element and the reference voltage, and a fourth voltage equal to or higher than a sum of the threshold voltage of the light emitting element and the reference voltage. It is possible to output to 2 wires,
The third driving unit is capable of outputting a fifth voltage and a sixth voltage having a magnitude corresponding to the video signal to the third wiring. The voltage of the wiring is the first voltage, the voltage of the second wiring provided corresponding to one unit is the third voltage, and another unit adjacent to the one unit When the voltage of the second wiring provided corresponding to the second voltage is the fourth voltage, the voltage of the second wiring provided corresponding to the one unit is changed from the third voltage to the fourth voltage. A method for driving a display device, wherein the voltage of the second wiring provided corresponding to another unit adjacent to the one unit is lowered from the fourth voltage to the third voltage at the same time when the voltage is raised. A display device,
The display device
A display unit in which a plurality of pixels configured to include a light emitting element and a pixel circuit are two-dimensionally arranged in a row direction and a column direction;
A drive unit for driving the pixel circuit based on a video signal,
The pixel circuit includes a first transistor, a second transistor, and a storage capacitor.
The driving unit is set to a first driving unit, a second driving unit, a third driving unit, a control unit, a first wiring, a second wiring, a third wiring, and a reference voltage. Wiring and
The second wiring is provided for each unit with a plurality of pixel rows as one unit,
A gate of the first transistor is connected to the first driver through the first wiring;
A drain or a source of the first transistor is connected to the third driver through the third wiring;
Of the drain and source of the first transistor, the one not connected to the third driver is connected to the gate of the second transistor and one end of the storage capacitor,
A drain or a source of a second transistor included in each pixel in the unit is connected to the second driving unit via a common second wiring;
Of the drain and source of the second transistor, the one not connected to the second drive unit is connected to the other end of the storage capacitor and the anode of the light emitting element,
A cathode of the light emitting element is connected to the fourth wiring;
The first driving unit can output a first voltage lower than an on-voltage of the first transistor and a second voltage equal to or higher than an on-voltage of the first transistor to the first wiring.
The second driving unit generates a third voltage lower than a sum of a threshold voltage of the light emitting element and the reference voltage, and a fourth voltage equal to or higher than a sum of the threshold voltage of the light emitting element and the reference voltage. It is possible to output to 2 wires,
The third driving unit can output a fifth voltage and a sixth voltage having a magnitude corresponding to the video signal to the third wiring.
In the control unit, the voltage of the first wiring is the first voltage with respect to the second driving unit, and the voltage of the second wiring provided corresponding to one unit is the third voltage. When the voltage of the second wiring provided corresponding to the other unit adjacent to the one unit is the fourth voltage, the voltage is provided corresponding to the one unit. The voltage of the second wiring provided corresponding to the other unit adjacent to the one unit is simultaneously raised to the fourth voltage from the third voltage to the fourth voltage. An electronic device that outputs a control signal instructing to lower the voltage to the third voltage.

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