JP2010021565A - Semiconductor memory device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a stable low voltage operation in a full CMOS SRAM memory cell provided with a shared contact. <P>SOLUTION: The semiconductor memory device includes: a first wiring that is electrically connected to a third drain active region and a second gate electrode wiring via a first contact disposed to open the third drain active region and the second gate electrode wiring; a second wiring that is electrically connected to the fourth drain active region and the first electrode wiring via a second contact disposed to open the fourth drain active region and the first gate electrode wiring; and an active region that is disposed, at a portion apart from either one of the first to fourth active regions or a continuous portion, wherein the active region and the first gate or the second gate electrode wiring overlap. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a static semiconductor memory device (hereinafter referred to as SRAM).

  In recent years, for the purpose of extending the usage time of a battery in a portable device, it has become important to save energy and operate at a low voltage in a semiconductor device incorporated in the portable device. Along with this, the demand for SRAM that can operate at low voltage with low consumption is increasing. In general, an SRAM memory cell for low-voltage operation is composed of six transistors, and a so-called full CMOS memory cell is generally used. FIG. 12 shows an equivalent circuit diagram of an SRAM memory cell, where 1a and 1b are access transistors formed by n-type transistors, 2a and 2b are driver transistors formed by n-type transistors, and 3a and 3b are p-type transistors. Load transistors formed by transistors, 4a and 4b are bit lines, 5 is a word line, and 6a and 6b are storage nodes. In the memory cell, driver transistors 2a and 2b and load transistors 3a and 3b constitute a flip-flop circuit.

  Subsequently, two types of conventional examples are shown below. First, FIG. 13 shows a layout pattern diagram of SRAM memory cells used in the first conventional example. In FIG. 13, an outer frame surrounded by a broken line indicates one region of the memory cell, 11a to 11c are isolation insulating films, 12a to 12f are n-type active regions, 12g to 12j are p-type active regions, and 13a to 13c. These are polysilicon wirings or wirings having a laminated structure of polysilicon and silicide (hereinafter represented by polysilicon wirings) as gate electrode wirings. Reference numerals 14a to 14h denote first contacts for connecting the active region and the polysilicon wiring to the first-layer metal wiring, and 15a to 15c denote first-layer metal wiring. Reference numerals 16a to 16d denote second contacts for connecting the active layer and the second layer metal wiring, and reference numerals 17a to 17d denote second layer metal wirings.

  Next, each part of the equivalent circuit diagram of the SRAM memory cell of FIG. 12 will be described with reference to FIG. Regarding the access transistor, for the sake of convenience, the active region connected to the bit line is hereinafter referred to as a drain active region, and the active region connected to the driver transistor is hereinafter referred to as a source active region. Here, when the transistors of the memory cell correspond to the drain active region, the gate, and the source active region in this order, the access transistor 1a is 12a, 13a, 12b, the access transistor 1b is 12d, 13a, 12e, and the driver transistor 2a is 12b, 13b, 12c, driver transistor 2b corresponds to 12e, 13c, 12f, load transistor 3a corresponds to 12g, 13b, 12h, and load transistor 3b corresponds to 12i, 13c, 12j. Further, the bit line 4a corresponds to 17a, the bit line 4b corresponds to 17b, and the word line 5 corresponds to 13a. 15c corresponds to the Vcc wiring, and 17c and 17d correspond to the GND wiring. Further, 14a, 14c, and 14e are contact groups of the storage node 6a connected by the first-layer metal wiring 15a, and 14b, 14d, and 14f are contact groups of the storage node 6b that are connected by the first-layer metal wiring 15b. Correspond.

  Next, FIG. 14 shows a cross-sectional view taken along line II of FIG. In FIG. 14, 21 is a silicon substrate, 22p is a p-type well, 23a to 23d are n-active regions, 24a to 24d are silicon oxide films which are sidewalls of transistors, and 25a and 25b are interlayer insulating films.

  Next, FIG. 15 shows a layout pattern diagram of SRAM memory cells used in the second conventional example. The first contact is different from the first conventional example. In FIG. 13, 14a and 14c become one and become 14i, and 14d and 14f become one and become 14j. Reference numerals 14i and 14j are generally called shared contacts, which connect the polysilicon wiring, the active region, and the first-layer metal wiring by one contact. Since the number of contacts can be reduced by using this shared contact, the cell size can generally be reduced.

  In the memory cell of the second conventional example shown here, since the shared metal contact is used, the first metal wiring is simultaneously connected to the polysilicon wiring and the active region by one contact. Advanced technology is required for the overlay accuracy of plate making. Therefore, the memory cell of the first or second conventional example is selected in accordance with the device performance in each manufacturing factory.

  The full CMOS SRAM memory cell as described above has the following four problems. The first problem is related to the second conventional example. By using the shared contact, the cell size can be reduced as compared with the memory cell of the first conventional example, but the low voltage operation is difficult as compared with the first conventional example. The reason for this is the first time I understand this time. FIG. 15 shows the relationship between the memory cell pattern of the second conventional example and the cell current at the time of reading. The cell current flows from the bit line load to the bit line and through the low side storage node to GND. When storage node 6a in FIG. 12 is at a low level, current I1 shown in FIG. 15 flows, and when storage node 6b in FIG. 12 is at a low level, current I2 shown in FIG. 15 flows. Here, only the current I1 side passes through a relatively narrow width W1 sandwiched between the polysilicon wiring 13c and the isolation insulating film 11a in the middle of the current path. However, normally, there is almost no influence of W1, and the current values of I1 and I2 are almost equal. On the other hand, as shown in FIG. 16, when the mask of the polysilicon wiring is displaced in the drawing upward direction with respect to the isolation insulating film, the width of W2 corresponding to the previous W1 becomes very narrow. For this reason, the cell current value I1 is smaller than I2. This leads to an imbalance of memory cell characteristics and worsens the memory cell operation lower limit. Specifically, since the current on the I1 side is small, it is difficult to lower the storage node 6a to the low level. On the other hand, in the memory cell of the first conventional example of FIG. 13, the cell current is not reduced due to mask displacement, so that the minimum operating voltage is superior to that of the second conventional example.

  The second problem is common to the first and second conventional examples, but the memory cell size is large. In the past, TFT (Thin Film Transistor) load type and high resistance load type memory cells in which four transistors are formed on a substrate have been used because they are not suitable for low voltage operation but have a small memory cell size. On the other hand, although the full CMOS type is excellent in low voltage operation, six transistors are formed on the substrate, so that the memory cell size is increased.

  The third problem is common to the first and second conventional examples, but is an increase in contact resistance. As the memory cell size is reduced, the contact area also decreases, so the contact resistance increases. A parasitic resistance is added to the memory cell due to an increase in contact resistance, which adversely affects the operation of the memory cell. For example, when the contact resistance connected to the GND wiring of the second contact 16c or 16d in FIG. 13 increases, the memory cell data may be destroyed because the GND potential in the memory cell increases when a cell current flows in the read operation. Get up.

  The fourth problem, which is common to the first and second conventional examples, is a decrease in soft error resistance. At a low power supply voltage, even if the same memory cell capacity as in the prior art is formed, the power supply voltage is lowered, so that the amount of stored charge in the storage node is reduced and soft error resistance is expected to be weakened.

  An object of the present invention is to solve the above-described problems, and a first object is to enable a low voltage operation in a memory cell using a shared contact. A second object is to reduce the memory cell size. A third object is to lower the contact resistance. A fourth object is to increase soft error tolerance even at a low power supply voltage.

  According to a first aspect of the present invention, there is provided a semiconductor memory device including a first drain active region of a first conductivity type first transistor, a second drain active region of a first conductivity type second transistor, and a second conductivity type. The third drain active region of the third transistor of the type 3, the fourth drain active region of the fourth transistor of the second conductivity type, the first active region of the fifth transistor of the first conductivity type and the first 2 active regions, the third active region and the fourth active region of the sixth transistor of the first conductivity type, and the first transistor and the third transistor that are continuously wired A first gate electrode wiring; a common second gate electrode wiring continuously connected to the second transistor and the fourth transistor; the first drain active region; The drain active region of the A first wiring that electrically connects the second gate electrode wiring, and the second drain active region, the fourth drain active region, and the first gate electrode wiring. A second wiring, and the first drain active region and the second active region are electrically connected, and the second drain active region and the fourth active region are electrically connected. In the static type semiconductor memory device, the first wiring is arranged through one first contact arranged so as to open the third drain active region and the second gate electrode wiring. The third drain active region and the second gate electrode wiring are electrically connected to each other, and the second wiring opens the fourth drain active region and the first gate electrode wiring. Arranged to be It is electrically connected to the fourth drain active region and the first gate electrode wiring through one second contact, and is separated from any of the first to fourth drain active regions. An active region is provided in a continuous portion or a continuous portion, and the active region and the first gate or second gate electrode wiring overlap.

  The semiconductor memory device according to a second aspect of the present invention is the semiconductor memory device according to the first aspect of the present invention, wherein, in the first contact, an area where the first wiring and the third drain active region are in contact with the first wiring The area of the second contact is larger than the area of contact with the second gate electrode wiring, and the area of contact of the second wiring and the fourth drain active region in the second contact is greater than that of the second wiring and the first gate. It is wider than the area where the electrode wiring contacts.

  According to a third aspect of the present invention, there is provided a semiconductor memory device including a first drain active region of a first conductivity type first transistor, a second drain active region of a first conductivity type second transistor, and a second conductivity type. The third drain active region of the third transistor of the type 3, the fourth drain active region of the fourth transistor of the second conductivity type, the first active region of the fifth transistor of the first conductivity type and the first 2 active regions, the third active region and the fourth active region of the sixth transistor of the first conductivity type, and the first transistor and the third transistor that are continuously wired A first gate electrode wiring; a common second gate electrode wiring continuously connected to the second transistor and the fourth transistor; the first drain active region; The drain active region of the A first wiring that electrically connects the second gate electrode wiring, and the second drain active region, the fourth drain active region, and the first gate electrode wiring. And an active region in a portion separated from or continuous with any one of the first to fourth drain active regions, the active region and the first gate or the second gate electrode. The wiring for use overlaps.

  According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device, comprising: a first drain active region and a first source active region of a first conductivity type first transistor; The second drain active region and the second source active region, the third drain active region and the third source active region of the second conductivity type third transistor, and the second conductivity type of the fourth transistor. 4 drain active region and fourth source active region, the first active region and second active region of the first conductivity type fifth transistor, and the third conductivity type of the sixth transistor of the first conductivity type. Common wiring continuously connected to the active region and the fourth active region, the first and second bit lines, the first and second power supply wirings, and the first transistor and the third transistor. First gate electrode of A wiring, a common second gate electrode wiring continuously connected to the second transistor and the fourth transistor, and a wiring continuously to the fifth transistor and the sixth transistor; And the third drain active region and the fourth active region are electrically connected to each other, and the second drain active region and the fourth active region are electrically connected to each other. Regions are electrically connected, the first source active region is electrically connected to the first power supply line through a first contact, and the second source active region is connected to the first source through a second contact. The third source active region is electrically connected to the second power source wiring through a third contact, and the fourth source active region is connected to the second power source wiring through a fourth contact. Second power supply wiring Electrically connected, the first active region is electrically connected to the first bit line via a fifth contact, and the third active region is connected to the second bit line via a sixth contact. In the method of manufacturing an electrically connected static semiconductor memory device, the first, second, fifth, sixth drain and source active regions and the first active region are formed after the first to third gate electrode wirings are formed. A step of implanting low-concentration impurities into the first to fourth active regions, a step of forming an interlayer insulating film on the first to third gate electrode wirings, and the first to sixth contacts. A step of opening a contact in a self-aligned manner with respect to the first to third gate electrode wirings, and a step of implanting a high concentration of impurities into the first to sixth contacts as compared with the low concentration. It is what you have.

  Since the present invention is configured as described above, the following effects can be obtained. According to the first aspect of the invention, since the shared contact is provided in the active region that does not serve as a cell current path, the low voltage operation of the memory cell can be realized. Further, by providing a region where the active region and the polysilicon wiring overlap in addition to the transistor region, the memory cell capacity can be increased and the soft error resistance can be increased.

  According to the second invention, since the area of the shared contact on the active region side is widened, the contact resistance is lowered, the current from the load transistor is likely to flow to the n-type active region, and the potential of the n-type active region is made faster. Can be set to High level.

  According to the third invention, by providing the active region and the region where the polysilicon wiring overlaps separately from the transistor region, the memory cell capacity can be increased and the soft error resistance can be increased.

  According to the fourth aspect of the present invention, the source / drain implantation mask can be reduced by implanting the high-concentration impurities after the self-aligned contact opening.

1 is a pattern diagram of an SRAM memory cell according to a first embodiment of the present invention. 1 is a cross-sectional view of an SRAM memory cell according to a first embodiment of the present invention. It is a pattern diagram of the SRAM memory cell of Embodiment 2 of this invention. It is a pattern diagram of the SRAM memory cell of Embodiment 3 of this invention. It is sectional drawing of the SRAM memory cell of Embodiment 3 of this invention. It is a figure which shows the manufacturing method of the SRAM memory cell of Embodiment 3 of this invention. It is a pattern diagram of the SRAM memory cell of Embodiment 4 of this invention. It is sectional drawing of the contact of Embodiment 4 and 5 of this invention. It is sectional drawing of the SRAM memory cell of Embodiment 6 of this invention. It is a figure which shows the manufacturing method of the SRAM memory cell of Embodiment 6 of this invention. It is a pattern diagram of the SRAM memory cell of Embodiment 8 of this invention. It is an equivalent circuit diagram in the conventional SRAM. It is a pattern diagram of the SRAM memory cell of the first conventional example. It is sectional drawing of the SRAM memory cell of the 1st prior art example. It is a pattern diagram of the SRAM memory cell of the 2nd prior art example. It is a pattern diagram when the SRAM memory cell of the 2nd prior art example carries out mask shift.

Embodiment 1.
FIG. 1 is a pattern diagram of an SRAM memory cell showing Embodiment 1 of the present invention. In FIG. 1, an outer frame surrounded by a broken line indicates one region of the memory cell, 11a to 11c are isolation insulating films, 12a to 12f are n-type active regions, 12g to 12j are p-type active regions, and 13a to 13c. Is a polysilicon wiring serving as a gate electrode wiring. 14a, 14b, 14g, and 14h are first contacts that connect the active region and the first layer metal wiring, and 14k and 14j are common contact contacts that connect the active region, the polysilicon wiring, and the first layer metal wiring. The first contacts 15a to 15c that are called are metal wirings of the first layer. Reference numerals 16a to 16d denote second contacts for connecting the active layer and the second layer metal wiring, and reference numerals 17a to 17d denote second layer metal wirings.

  Subsequently, each part of the equivalent circuit diagram of the SRAM memory cell of FIG. 12 will be described with reference to FIG. The equivalent circuit of the memory cell of this embodiment is the same as that of the conventional example. When the transistors of the memory cell correspond to the drain active region, the gate, and the source active region in this order, the access transistor 1a has 12a, 13a, and 12b, the access transistor 1b has 12d, 13a, and 12e, and the driver transistor 2a has 12b, 13b, and 12c. The driver transistor 2b is 12e, 13c, 12f, the load transistor 3a is 12g, 13b, 12h, and the load transistor 3b is 12i, 13c, 12j. Further, the bit line 4a corresponds to 17a, the bit line 4b corresponds to 17b, and the word line 5 corresponds to 13a. 15c corresponds to the Vcc wiring, and 17c and 17d correspond to the GND wiring. Further, 14a and 14k correspond to the contact group of the storage node 6a connected by the first layer metal wiring 15a, and 14b and 14j correspond to the contact group of the storage node 6b connected by the first layer metal wiring 15b.

  Next, FIG. 2 shows a cross-sectional view taken along line II of FIG. In FIG. 2, 21 is a silicon substrate, 22p is a p-type well, 23a to 23d are n-active regions, 24a to 24d are side walls of a transistor formed of a silicon oxide film, and 25a and 25b are interlayer insulating films.

  The difference of the memory cell between the second conventional example and the first embodiment is the shared contact arrangement. In the second conventional example, as shown in FIG. 16, the shared contacts are 14i in the n-type active region and 14j in the p-type active region. On the other hand, in the present embodiment, shared contacts 14k and 14j are both in the p-type active region. For this reason, when considering the cell current at the time of reading shown in FIG. 16, since there is no shared contact in the cell current path in this embodiment, the current path width becomes narrow due to the mask displacement of the first polysilicon. The cell currents I1 and I2 can be made substantially equal. As a result, the characteristics of the memory cell are improved, and a low voltage operation is possible in the memory cell using the shared contact which is the first object of the invention.

Embodiment 2.
Next, FIG. 3 shows a pattern diagram of the SRAM memory cell according to the second embodiment of the present invention. The difference from the first embodiment is the ratio of the area occupied by the active region and the polysilicon wiring in the shared contacts 14k and 14j. In the first embodiment, the ratio is substantially the same, but in the present embodiment, the active region side is increased. This is related to the stabilization of the memory cell operation by raising the potential of the n-type active region 12b or 12e shown in FIG. That is, if the area on the active region side of the shared contact is increased, the contact resistance on the active region side is lowered, and the current from the load transistor 3a or 3b tends to flow to the n-type active region 12b or 12e in FIG. The potential of the n-type active region can be quickly made high. Thus, in this embodiment, in addition to the effects of the first embodiment, it is possible to secure the stability at the time of writing.

Embodiment 3.
FIG. 4 is a pattern diagram of an SRAM memory cell showing Embodiment 3 of the present invention. This embodiment is an improvement over the first conventional example. For this reason, there are two differences from the first embodiment. First, in the first embodiment, the contacts using the shared contacts 14k and 14j as the first contacts are changed to 14c, 14e, 14d, and 14f. As a result, the pattern of the first contact of the first conventional example and the present embodiment is the same. Second, the first contacts 14g and 14h and the second contacts 16a to 16d are self-aligned contacts to the polysilicon wiring. The self-alignment type here means that even if the contact approaches the polysilicon wiring on the plane, it does not come into contact with the vertical structure. This will be specifically described with reference to FIG. FIG. 5 is a sectional view taken along line II in FIG. The difference from the first embodiment is that the silicon oxide films 24a to 24d which are the sidewalls of the transistor in FIG. 2 are changed to silicon nitride films or silicon nitride oxide films (hereinafter represented by silicon nitride films) 24e to 24h. It is. As a result, even if the first contact and the second contact come close to the polysilicon wiring due to manufacturing variations, etc., the interlayer insulating films 25a and 25b are usually made of a silicon oxide film as the main material. By making the contact etching directed to the silicon oxide film and making the silicon nitride film difficult to etch, the side wall becomes an etching protective film in the contact etching, and the contact can be opened without contacting the polysilicon wiring. . Therefore, the first contact and the second contact can be brought close to the polysilicon wiring, and the reduction of the memory cell size, which is the second object of the invention, can be realized.

  Next, a manufacturing method from the first contact to the first-layer metal wiring of the SRAM memory cell according to the present embodiment will be described. Sectional views of J-J in FIG. 4 are shown in FIGS. In FIG. 6A, 22n is an n-type well. In this figure, after the interlayer insulating film 25a is formed, a resist 31 is formed by photolithography, and only the first contact connected to the n-type active region is etched in the first contact 14a, 14e and 14g in this figure. . Since this etching is performed under the condition that the sidewall of the transistor, in this figure, 24k is an etching protective film, the first contact 14g does not come into contact with the polysilicon wiring 13b due to manufacturing variations or the like when approaching on the plane. Next, as shown in FIG. 6B, a resist 32 is formed by photolithography, and only the first contact connected to the polysilicon wiring is etched in the first contact 14c in this drawing. This etching is performed under conditions where the silicon oxide film and the silicon nitride film are etched in order to form a contact in contact with the polysilicon wiring. Next, as shown in FIG. 6C, a first level metal wiring is formed.

  Thus, for the manufacturing method in which the self-aligned contact that is in contact with the active region and not in contact with the polysilicon wiring and the normal contact in contact with the polysilicon wiring are opened in separate processes and then connected in the contact with the same layer wiring, One layer of wiring can be used for each connection of the self-aligned contact and the normal contact, and the wiring can be used effectively. In the above example, the first contact is shown, but the same applies to the second contact. Furthermore, in the present embodiment, an improvement over the first conventional example has been shown, but the present invention is also applicable to the second conventional example using the shared contact and the first and second embodiments. The opening may be opened simultaneously with the contact connected to the polysilicon wiring. Further, in the present embodiment, the side walls are made of silicon nitride films, but the same is true if silicon nitride films are formed between the interlayer insulating film 25a and the polysilicon wirings 14a to 14c.

Embodiment 4.
FIG. 7 is a pattern diagram of an SRAM memory cell showing Embodiment 4 of the present invention. This embodiment is a further improvement over the third embodiment. The difference from the third embodiment is that the first contacts 14g and 14h overlap with the isolation insulating film 11a and the second contacts 16c and 16d overlap with the isolation insulating films 11a to 11c, respectively. FIG. 8A shows a cross-sectional view of KK in FIG. It can be seen from the cross-sectional view that the isolation insulating films 11a and 11b are scraped to reach the silicon surface below the isolation insulating film. For this reason, the junction leakage current increases. However, since the n-type active region 12c and the p-type well 22p have substantially the same potential, no problem occurs even if a junction leakage current flows. By providing an overlap between the contact and the isolation insulating film, the contact area is substantially enlarged, so that the contact resistance, which is the third object of the invention, can be reduced, and the memory cell operation is stabilized.

Embodiment 5.
This embodiment is a further improvement over the fourth embodiment. The difference from the fourth embodiment is that the second contacts 16a and 16b overlap the isolation insulating films 11a to 11c in plan view (not shown). However, unlike 16c, 16d, 14g, and 14h, 16a and 16b are contacts connected to the bit line. Therefore, when the contacts reach the silicon surface under the isolation insulating film, an increase in junction leakage current is caused by the bit line potential. This is undesirable. The cause of the increase in the junction leakage current is expected to be that the contact reaches the silicon surface under the isolation insulating film, so that crystal defects are included in the junction portion and the leakage current is likely to be generated. For this reason, in this embodiment, the isolation insulating film is not cut before reaching the silicon surface under the isolation insulating film. This will be described below using the drawings. FIG. 8B shows a cross-sectional view of the LL when the present embodiment is applied to the memory cell of FIG. In the present embodiment, the silicon nitride film 26 is formed under the interlayer insulating film 25a as shown in FIG. 8B, instead of the side walls of the silicon nitride film shown in the fourth embodiment. . As a result, the second contact 16a can be formed without removing the isolation insulating films 11a and 11b to the silicon surface by contact etching, and the second metal wiring 17a is in contact with the isolation insulating film at the bottom of the second contact 16a. it can. Therefore, there is no problem of an increase in junction leakage current, the contact area with the active region can be increased, and a memory cell with a low contact resistance, which is the third object of the invention, can be formed. Further, in this embodiment, the contact of the isolation insulating film can be suppressed even in 14g, 14h, 16c, and 16d, and a contact with low resistance can be realized. Furthermore, the present invention can also be applied to the first contacts 14a and 14b in FIG. 1 and the first contacts 14e and 14f in FIG. The contact group for connecting these storage nodes does not cause a problem in contact resistance as much as the contact connected to the GND line or bit line. Therefore, the contact size can be kept constant and the distance between the contact and the isolation insulating film can be reduced. Thus, the reduction of the memory cell size, which is the first object of the invention, is further advanced. Further, even if this embodiment is applied to the shared contacts of the first and second embodiments, the same effect can be obtained.

Embodiment 6.
9 is a cross-sectional view corresponding to II in FIG. 4 showing Embodiment 6 of the present invention. The difference from the cross-sectional view of FIG. 5 is in the active region. In FIG. 5, the active regions 23a to 23d substantially under the sidewalls are n− active regions, and the other active regions 12b, 12c, 12e, and 12f are n + active regions. On the other hand, in the present embodiment, the active regions 12k, 12m, 12n, and 12p almost below the first contacts 14a and 14b and the second contacts 16c and 16d are n + active regions, and the other active regions are n- active regions. ing. Next, the manufacturing method of the present embodiment will be described. FIG. 10A to FIG. 10C show the formation from the first contact to the formation of the second contact in the II part of FIG. In a normal case, n-source / drain injection is performed before forming the sidewall, and n + source / drain injection is performed after forming the sidewall and before forming the interlayer insulating film. In this embodiment, n− source / drain implantation is performed, but n + source / drain implantation is not performed. Thereafter, as shown in FIG. 10A, an interlayer insulating film 25a is formed, the first contact is opened, and n + implantation is performed in the contact opening. Reference numeral 33 denotes a resist. Next, as shown in FIG. 10B, first-layer metal wirings 15a and 15b and an interlayer insulating film 25b are formed. Then, as shown in FIG. 10C, the second contact is opened, and n + implantation is performed in the contact opening. Reference numeral 34 denotes a resist. According to the present embodiment, since an n + source / drain implantation mask is not required, an inexpensive device can be formed by reducing the number of masks. In addition, the contact resistance tends to decrease when the n + implantation is performed after the contact is formed rather than the normal n + source / drain implantation, which is in accordance with the second object of the invention, contact resistance reduction. Although the above example has been described for the n-type active region, it can also be applied to the p-type active region and has the same effect.

Embodiment 7.
Embodiment 7 of the present invention relates to a wiring connecting an n-type active region and a p-type active region. In the embodiments described so far, for example, 15a and 15b in FIG. 1 correspond to the wiring connecting the n-type active region and the p-type active region, and this is formed by the first layer metal wiring. However, metal wiring is one of the limitations of reducing the memory cell size because it is difficult to make fine photomechanical and etching techniques compared to polysilicon wiring. In the present embodiment, p-type polysilicon wiring is used instead of the first layer metal wiring. In FIG. 1, there is a concern that a PN junction is formed by the first contacts 14a and 14b connecting the p-type polysilicon wiring and the n-type active region. In this embodiment, however, a PN that gives an abnormality to the memory cell operation in particular. Junctions tend not to form. On the other hand, when n-type polysilicon is used, a PN junction is formed by the first contacts 14k and 14j, which hinders cell operation. From the above, by using p-type polysilicon wiring. There is no problem of PN junction, and the memory cell size reduction of the first object of the invention is further advanced. The p-type polysilicon wiring can also be applied to 15c corresponding to the Vcc wiring in FIG. Further, the p-type polysilicon wiring does not mean only a single layer, but may be a two-layer wiring of p-type polysilicon and silicide, for example.

Embodiment 8.
FIG. 11 is a pattern diagram of an SRAM memory cell showing an eighth embodiment of the invention. The difference from FIG. 1 is that an active region 12q covered with a polysilicon wiring 13b and an active region 12r covered with a polysilicon wiring 13c are provided in FIG. As a result, a capacitor is formed between the polysilicon wiring and the active region with the gate insulating film of the transistor interposed therebetween. By providing a capacitor as in the present embodiment, the accumulated charge increases, and the soft error resistance improvement, which is the fourth object of the invention, can be realized. Further, although the isolated active regions 12q and 12r are provided in FIG. 11, the active region may be continuous with the drain active region. For example, the same effect can be obtained as the active regions 12s and 12t indicated by broken lines in FIG. Is obtained. Further, it can be considered that it is provided continuously in the source active region. However, although the active region can be provided in the middle of the polysilicon wiring of FIG. 11 in the region continuing to the drain region, if the active region is continuous to the source region, the polysilicon wiring needs to be changed and the pattern is complicated. Therefore, the former is preferable. Note that this embodiment can be applied not only to the first embodiment but also to other embodiments.

  In the first to eighth embodiments, an example in which the access transistor is an n-type transistor has been described, but the same effect can be obtained even if the access transistor is a p-type transistor. In this case, for example, in FIG. 1, an n-type transistor is a p-type transistor, and a p-type transistor is an n-type transistor. In the first to eighth embodiments, an example in which the wiring connecting the n-type active region and the p-type active region and the Vcc wiring are the first layer metal wiring, and the GND wiring and the bit line are the second layer metal wiring are shown. However, any of the above-described wirings may be used as the first and second layer metal wirings.

  12a, 12d access transistor active region, 12b, 12e driver transistor drain active region, 12c, 12f driver transistor source active region, 12g, 12i load transistor drain active region, 12h, 12j load transistor source active region, 12k , 12n, 12m, 12p n + active region, 12q, 12r active region, 13a-13c polysilicon wiring, 14k, 14j shared contact, 14g, 14h, 16a-16d self-aligned contact, 15a, 15b first layer metal Wiring, 24e-24k, 26 Silicon nitride film.

Claims (4)

A first drain active region of a first transistor of a first conductivity type;
A second drain active region of a second transistor of the first conductivity type;
A third drain active region of a second transistor of the second conductivity type;
A fourth drain active region of a second transistor of the second conductivity type;
A first active region and a second active region of a fifth transistor of the first conductivity type;
A third active region and a fourth active region of a sixth transistor of the first conductivity type;
A common first gate electrode wiring that is continuously wired to the first transistor and the third transistor;
A common second gate electrode wiring that is continuously wired to the second transistor and the fourth transistor;
A first wiring that electrically connects the first drain active region, the third drain active region, and the second gate electrode wiring;
A second wiring that electrically connects the second drain active region, the fourth drain active region, and the first gate electrode wiring;
The first drain active region and the second active region are electrically connected;
In the static semiconductor memory device in which the second drain active region and the fourth active region are electrically connected.
The first wiring is connected to the third drain active region and the second gate active region through one first contact disposed so as to open the third drain active region and the second gate electrode wiring. Electrically connected to the second gate electrode wiring;
The second wiring is connected to the fourth drain active region and the first drain active region via one second contact arranged to open the fourth drain active region and the first gate electrode wiring. Electrically connected to the first gate electrode wiring;
A semiconductor memory device comprising an active region in a portion separated from or continuous with any of the first to fourth drain active regions, wherein the active region and the first gate or second gate electrode wiring overlap. In the first contact, an area where the first wiring and the third drain active region are in contact is wider than an area where the first wiring and the second gate electrode wiring are in contact, and
2. The semiconductor according to claim 1, wherein, in the second contact, an area where the second wiring and the fourth drain active region are in contact with each other is larger than an area where the second wiring and the first gate electrode wiring are in contact with each other. Storage device. A first drain active region of a first transistor of a first conductivity type;
A second drain active region of a second transistor of the first conductivity type;
A third drain active region of a second transistor of the second conductivity type;
A fourth drain active region of a second transistor of the second conductivity type;
A first active region and a second active region of a fifth transistor of the first conductivity type;
A third active region and a fourth active region of a sixth transistor of the first conductivity type;
A common first gate electrode wiring that is continuously wired to the first transistor and the third transistor;
A common second gate electrode wiring that is continuously wired to the second transistor and the fourth transistor;
A first wiring that electrically connects the first drain active region, the third drain active region, and the second gate electrode wiring;
A second wiring that electrically connects the second drain active region, the fourth drain active region, and the first gate electrode wiring;
A semiconductor memory device comprising an active region in a portion separated from or continuous with any of the first to fourth drain active regions, wherein the active region and the first gate or second gate electrode wiring overlap. A first drain active region and a first source active region of a first transistor of a first conductivity type;
A second drain active region and a second source active region of a second transistor of the first conductivity type;
A third drain active region and a third source active region of a second transistor of the second conductivity type;
A fourth drain active region and a fourth source active region of a second transistor of the second conductivity type;
A first active region and a second active region of a fifth transistor of the first conductivity type;
A third active region and a fourth active region of a sixth transistor of the first conductivity type;
First and second bit lines;
First and second power supply wirings;
A common first gate electrode wiring that is continuously wired to the first transistor and the third transistor;
A common second gate electrode wiring that is continuously wired to the second transistor and the fourth transistor;
A common third gate electrode wiring that is continuously wired to the fifth transistor and the sixth transistor;
The first drain active region and the second active region are electrically connected;
The second drain active region and the fourth active region are electrically connected;
The first source active region is electrically connected to the first power line by a first contact;
The second source active region is electrically connected to the first power line by a second contact;
The third source active region is electrically connected to the second power line by a third contact;
The fourth source active region is electrically connected to the second power line by a fourth contact;
The first active region is electrically connected to the first bit line by a fifth contact;
In the method of manufacturing a static semiconductor memory device, wherein the third active region is electrically connected to the second bit line through a sixth contact.
After the first to third gate electrode wirings are formed, low concentration impurity implantation is performed on the first, second, fifth, sixth drain and source active regions and the first to fourth active regions. Process,
Forming an interlayer insulating film on the first to third gate electrode wirings;
Opening the first to sixth contacts in a self-aligned manner with respect to the first to third gate electrode wirings;
A method of manufacturing a semiconductor memory device, comprising: implanting a high concentration of impurities into the first to sixth contacts as compared with the low concentration.

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