JP2010021365A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device for selectively controlling Vth to a plurality of types of MOSFETs having a desired different Vth (threshold voltage). <P>SOLUTION: The method of manufacturing the semiconductor device includes: a step of forming a first gate insulation film 45 including silicon dioxide and a second one 46 including a metal oxide in a region for forming the plurality of kinds MOSFETs Tr1-Trn on a semiconductor substrate 40; a step of forming a gate electrode 47 including polysilicon on the first and second insulation films 45, 46; and further a step of forming the gate electrode 47 before performing heat treatment so that temperature of at least one of MOSFETs Trn differs from that of other types of MOSFETs Tr1-Tr3 in the plurality of types of MOSFETs Tr1-Trn. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device including a plurality of types of MOSFETs.

  Currently, with the enhancement of functions of semiconductor devices, a plurality of types of transistors having different functions are integrated on one integrated circuit (IC) chip. In general integrated circuits, a very large number of metal-oxide-semiconductor field effect transistors (MOSFETs) are used, and these MOSFETs have different threshold voltages (Vth) depending on the desired function. Designed to. For example, a MOSFET (hereinafter referred to as a core transistor) in a core portion that mainly performs an arithmetic function operates with a low power supply voltage such as 1.0 to 1.5 V and is designed to have a low Vth. In addition, a transistor (hereinafter referred to as an I / O transistor) in a peripheral circuit section that performs functions such as external input / output (I / O) and power management is relatively low, for example, 1.8V-3.3V. It operates with a high power supply voltage and is designed to have a relatively high Vth. Furthermore, the transistors in the memory portion may have different Vths, or MOSFETs having different Vths may be used in each group of core transistors and I / O transistors.

  In order for these MOSFETs to perform their respective desired functions, it is extremely important to appropriately control their respective Vth. In general, obtaining a desired Vth is achieved by appropriately combining three major elements of the material and thickness of the gate insulating film, the work function of the gate electrode material, and the impurity concentration of the channel region. It has been broken.

  In recent years, as the miniaturization of MOSFETs and the lowering of Vth are promoted, it has been studied to use a high dielectric constant (high-k) dielectric for the gate insulating film in order to suppress an increase in leakage current associated therewith. In particular, the application of hafnium-based oxides such as hafnium oxide, hafnium silicate, or nitrogen-added hafnium silicate, and other ion crystalline metal oxides has attracted attention. However, it is known that when a gate insulating film of an ion crystalline metal oxide such as hafnium-based oxide and a general polysilicon gate electrode are combined, a phenomenon called Fermi level pinning occurs at the interface. . Fermi level pinning shifts Vth to the deep side (the side with the larger absolute value) in both the N-type MOSFET and the P-type MOSFET.

In such a MOSFET in which the gate insulating film includes a hafnium-based oxide and the gate electrode includes polysilicon, in order to adjust Vth having an influence due to Fermi level pinning, the channel among the above three elements is selected. It is conceivable to adjust the impurity concentration of the region. In order to adjust the Vth to a shallow side so as to cancel the shift due to Fermi level pinning, the dose of ion implantation into the channel region is reduced, and the impurity in the channel region (however, the conductivity type of the adjacent source / drain region) The impurity (converse conductivity type) concentration is lowered. Doing so has the effect of suppressing variations in the standby current I _off corresponding to the leakage current in the off state of the MOSFET and the Vth.

Further, in relation to Vth control of a MOSFET having a gate insulating film containing hafnium-based oxide, the influence of Fermi level pinning is suppressed or controlled by adjusting the content of some elements in the hafnium-based oxide. Has been proposed (see Patent Documents 1 and 2). Thereby, for example, the amount of Vth shift is reduced in a P-type MOSFET that is known to have a large Vth shift due to Fermi level pinning.
JP 2005-191482 A JP 2005-340329 A

  However, the conventional Vth control technique by adjusting the impurity concentration of the channel region or adjusting the element content in the hafnium-based oxide causes a problem in a semiconductor device having a plurality of types of MOSFETs having different desired Vths.

Specifically, reducing the impurity concentration of the channel region in the MOSFET Vth deep side by Fermi level pinning is shifted, as described above, the effect of suppressing variation or standby current I _off of Vth Play. However, for example, an I / O transistor has a high desired Vth and requires a gate oxide film (eg, SiO ₂ ) thickness that is about 2-4 times that of the core transistor. If hafnium-based oxide is deposited on such an oxide film, it is impossible to set the desired Vth even if the impurity concentration in the channel region is reduced by reducing the dose of ion implantation into the channel region. It may become. That is, the presence of the I / O transistor makes it impossible to bring out the effect of Fermi level pinning or to use a hafnium-based oxide for other transistors.

  Further, for each of a plurality of types of MOSFETs having different desired Vths, for example, adjusting parameters such as the presence / absence of a hafnium-based oxide, thickness, and / or element content can be performed multiple times. Deposition or ion implantation into it, which is inefficient and reduces the reliability of the gate insulating film.

  According to one aspect of the present embodiment, a method for manufacturing a semiconductor device is provided. In this method, a step of forming a first gate insulating film containing silicon dioxide and a second gate insulating film containing a metal oxide in a region where a plurality of types of MOSFETs are to be formed on a semiconductor substrate, and first and second gates Forming a gate electrode containing polysilicon over the insulating film. This method further includes a step of heat-treating the temperature of one or more types of MOSFETs among the plurality of types of MOSFETs after the formation of the gate electrode so as to be different from the temperature of other types of MOSFETs.

  According to the present invention, for a plurality of types of MOSFETs having different desired Vths, a common high-k gate insulating film is used to improve the performance of the MOSFETs while selectively controlling the Vth according to the type of the MOSFETs. It is possible to provide a method of manufacturing a semiconductor device that can be used.

  Hereinafter, embodiments will be described with reference to the accompanying drawings.

  First, the Vth control method by heat treatment used in the embodiment will be described with reference to FIGS.

FIG. 1 schematically shows a typical MOSFET 1 having a hafnium-based oxide in a gate insulating film and polysilicon in a gate electrode. The MOSFET 1 has a semiconductor substrate 2 made of silicon, a gate electrode structure 3, and source / drain regions 4. A channel region 5 sandwiched between source / drain regions 4 is defined in the semiconductor substrate 2 under the gate electrode structure 3. The gate electrode structure 3 includes a first gate insulating film 11 made of, for example, SiO _{2, a} second gate insulating film 12 made of an ion crystalline metal oxide such as a hafnium-based oxide, and a dope formed sequentially on the semiconductor substrate 2. It has a gate electrode 13 made of toppolysilicon and sidewalls 14 formed on these side surfaces. As will be appreciated by those skilled in the art, source / drain regions 4 are formed in a self-aligned manner using sidewall spacers 14. The illustrated source / drain region 4 is schematic, and for example, an LDD region well known to those skilled in the art may be formed prior to the formation of the sidewall spacer 14.

Here, as the second gate insulating film 12, Hf / (Hf + Si ) ratio = 6-11% of _Hf x Si _y O film thickness of 0.3-1.5nm by chemical vapor deposition (CVD) To deposit. The deposition conditions are not limited to the following, but a temperature of 600 ° C. and a pressure of 5 torr. The Vth of the MOSFET 1 is shifted to the deep side by Fermi level pinning in both the P-type MOSFET and the N-type MOSFET.

  Referring to FIG. 2, Vth is shown when the MOSFET shown in FIG. 1 is subjected to heat treatment at different temperatures. More specifically, FIG. 2A shows Vth when N-type MOSFETs for I / O transistors manufactured under the same conditions are subjected to heat treatment at 1000 ° C. and 1015 ° C. FIG. 2B shows Vth when a P-type MOSFET for an I / O transistor manufactured under the same conditions is subjected to the same heat treatment as in FIG. In each of FIGS. 2A and 2B, it can be seen that the heat treatment at 1015 ° C. shifts Vth to a shallower side than the heat treatment at 1000 ° C. The difference in the Vth shift amount due to this heat treatment due to the temperature difference of 15 ° C. between 1000 ° C. and 1015 ° C. was about 20-30 mV for the N-type MOSFET and about 40-60 mV for the P-type MOSFET.

Further, referring to FIG. 3, when a general 6T-structure CMOS SRAM is subjected to heat treatment at different temperatures, (a) an N-type drive transistor, (b) an N-type transfer transistor, and (c) a P-type. The Vth of the load transistor is shown. The horizontal axis of Fig.3 (a)-(c) represents sample number # 1- # 4. The samples # 1 to # 4 are different from each other in at least one of the Hf / (Hf + Si) ratio and the heat treatment temperature of the second gate insulating film, that is, the Hf _x Si _y O film. The conditions are as shown in Table 1. is there. It has been observed that the Vth shift amount due to the heat treatment increases in the range of 0.5 nm to 1.0 nm out of the range of 0.3 to 1.5 nm of the film thickness of the Hf _x Si _y O film. The film thickness of the Hf _x Si _y O film of these samples # 1 to # 4 was 0.5 nm and common.

From FIG. 3, in any of the (a) N-type drive transistor, (b) N-type transfer transistor, and (c) P-type load transistor constituting the SRAM, the heat treatment at 1015 ° C. is shallower than the heat treatment at 1000 ° C. It turns out that it is shifting to the side. FIG. 3 also shows that the Vth of the # 3 and # 4 samples is generally deeper than that of the # 1 and # 2 samples, and that the Hf / (Hf + Si) ratio of the Hf _x Si _y O film is high, which is affected by Fermi level pinning. Is shown to be large. Furthermore, it can be seen that the Vth difference between 1000 ° C. and 1015 ° C. depends on the Hf / (Hf + Si) ratio, and increases as this ratio increases. In FIG. 3, as shown in # 3 and # 4 of (b) and # 3 and # 4 of (c), a maximum of about 100 mV is caused by a temperature difference of 15 ° C. between 1000 ° C. and 1015 ° C. There is a difference in Vth.

  According to these experiments, in the MOSFET in which the gate insulating film contains hafnium-based oxide and the gate electrode is made of polysilicon, Vth shifted to the deep side by Fermi level pinning is shifted to the shallow side by heat treatment. It was found. It was also found that the Vth shift amount due to heat treatment can vary from several tens mV to about 100 mV due to a relatively small temperature difference such as about 15 ° C. This means that in such a MOSFET, Vth can be controlled by performing a temperature-controlled heat treatment after forming the gate electrode.

  These experimental results are only examples, and Vth is large at other temperature differences such as 5 ° C. and 30 ° C. depending on the design of the specific type and thickness of the hafnium-based oxide and the length and width of the gate. It has been observed that a difference in shift amount is obtained and that a higher temperature heat treatment results in a smaller Vth shift amount. The temperature causing such a large Vth shift amount and the temperature difference causing the large Vth shift amount can be easily determined by performing heat treatment and Vth measurement after forming the gate electrode.

  Next, a method for manufacturing a semiconductor device according to the embodiment will be described in detail.

  4 and 5 show the method of manufacturing the semiconductor device according to the first embodiment with cross-sectional views in main steps. This semiconductor device has n types of MOSFETs (Tr1, Tr2,..., Trn) such as a core transistor, an I / O transistor, and an SRAM. At least one of these n types of MOSFETs has a desired Vth different from other types of MOSFETs. Three or more types of MOSFETs may have three or more different desired Vths.

  First, as shown in FIG. 4A, an element isolation shallow trench isolation (STI) 41 is formed on a semiconductor substrate 40 made of silicon. Methods for forming STI 41 are well known to those skilled in the art. In addition, between adjacent STIs 41, depending on whether the MOSFET formed therein is an N-type MOSFET or a P-type MOSFET, a P well or an N well is formed by ion implantation and a subsequent diffusion step, respectively. It may be provided. Further, if necessary, channel implantation for adjusting the impurity concentration of the channel region to be defined later is performed in the region corresponding to each of the MOSFETs (Tr1, Tr2,..., Trn) to be formed. Also good.

Next, as shown in FIG. 4B, a silicon dioxide (SiO ₂ ) film 42 and a high-k dielectric film 43 containing a hafnium-based oxide are formed on the structure obtained in FIG. accumulate. Here, description will be made assuming that the high-k dielectric film 43 is a hafnium silicate (Hf _x Si _y O) film. These films 42 and 43 are to form first and second gate insulating films later, respectively. The SiO ₂ film 42 has a thickness of 1 to 7 nm, for example, and the thickness can be determined according to the type of MOSFET to be formed and Vth desired for the MOSFET. For example, the thickness of the SiO ₂ film 42 may be 1-1.5 nm in the core transistor and 4 nm or 7 nm in the I / O transistor. On the other hand, _Hf x Si _y O film 43 is simultaneously deposited on all types of MOSFET. Therefore, the thickness is substantially the same regardless of the type of MOSFET, and is typically within the range of 0.3 to 1.5 nm, preferably 0 from the magnitude of the Vth shift amount due to the heat treatment as described above. Within the range of 0.5 nm to 1.0 nm. The Hf / (Hf + Si) ratio of the Hf _x Si _y O film 43, that is, x / (x + y) is typically in the range of 1-50%, but considering the high dielectric constant and the Vth shift amount due to Fermi level pinning. Then, it is preferably in the range of 6% -30%. Further, it is more preferably in the range of 6-11% from the magnitude of the Vth shift amount due to the heat treatment.

Next, as shown in FIG. 4C, a polysilicon layer is deposited on the Hf _x Si _y O film 43, and the first gate insulating film is formed by using a pattern formation method by, for example, photolithography and subsequent etching. 45, a gate stack 48 composed of the second gate insulating film 46 and the gate electrode 47 is defined. The polysilicon layer forming the gate electrode 47 is deposited to a thickness of about 100 nm, for example. The polysilicon layer is also heavily doped with P-type or N-type impurities during deposition, after deposition and before or after patterning, and has a high enough conductivity to function as a gate electrode.

Subsequently, as shown in FIG. 5A, a sidewall 50 (hereinafter, the gate stack 48 and the sidewall 50 are collectively referred to as a gate electrode structure 51) is formed on the side surface of the gate stack 48, and the source / drain is formed. Ion implantation 52 for forming a region is performed. The sidewall 50 is made of silicon nitride (Si ₃ N ₄ ), silicon dioxide (SiO ₂ ), or both, and the formation method is well known to those skilled in the art. Due to the ion implantation 52, in the case of an N-type MOSFET, an N-type impurity such as phosphorus (P) or arsenic (As), for example, and in the case of a P-type MOSFET, a P-type impurity such as boron (B) is introduced into a semiconductor substrate. 40 is injected. The ion implantation 52 may also serve as the doping of the gate electrode 47 described above. As will be appreciated by those skilled in the art, a lightly doped LDD region may be formed prior to the formation of the sidewall 50.

Next, as shown in FIG. 5B, a protective film 53 is deposited on the structure obtained in FIG. The protective film 53 is made of, for example, SiO ₂ or Si ₃ N ₄ and preferably has a thickness of about 20 to 300 nm as will be described in detail later. As a result, the gate electrode structure 51 is covered with the protective film 53. In FIG. 5B, a protective film 53 having a thickness larger than the height of the gate electrode structure 51 is deposited. In this case, the protective film 53 can be planarized by, for example, a chemical mechanical polishing (CMP) method for the subsequent photolithography process. When the thickness of the protective film 53 is small, the shape of the protective film 53 more closely follows the shape of the gate electrode structure 51.

  Next, as shown in FIG. 5C, after part of the protective film 53 is removed to form a patterned protective film 54, heat treatment is performed. The patterning of the protective film 54 can be performed by photolithography and etching, as in the conventional contact hole formation or silicide block formation. This exposes the gate electrode structure 51 of a particular type of MOSFET. In this embodiment, the type of MOSFET (Trn) whose Vth should be shifted to the shallow side is exposed, and the other types of MOSFETs (Tr1-Tr3) are still covered with the protective film 54. The heat treatment used here is a heat treatment that can raise the temperature of the surface side of the semiconductor substrate in a short time, and is preferably flash lamp annealing or laser annealing. As a result, all of the n groups of MOSFETs (Tr1, Tr2,..., Trn) are heated to a temperature of about 950 ° C. or higher, and the impurities implanted by the ion implantation 52 of FIG. Is done. The illustrated source / drain region 55 indicates that the impurity is activated.

Each of the MOSFETs (Tr1, Tr2,..., Trn) of the present embodiment has an interface between Hf _x Si _y O (second gate insulating film 46) and polysilicon (gate electrode 47) in the gate stack 48. There is a Vth shift due to Fermi level pinning. Therefore, Vth of all MOSFETs is once shifted to the deep side. However, as described with reference to FIGS. 1 to 3, the Vth of such a MOSFET can be controlled by the heat treatment applied to the gate stack 48 or the gate electrode structure 51, particularly the temperature thereof.

  In this embodiment, the heat treatment by laser annealing or flash lamp annealing causes a temperature difference between the exposed MOSFET (Trn) and the unexposed MOSFET due to the presence of the patterned protective film 54. At this time, the structure and film quality of the protective film 54 and / or the laser or flash lamp of the laser or flash lamp are set so that the exposed MOSFET (Trn) has a temperature about 5-30 ° C. (for example, 15 ° C.) higher than the other MOSFETs. Parameters such as power, wavelength, irradiation time and / or irradiation angle are set.

  Still referring to FIG. 5C, the protective film 54 (and the figure) for generating a predetermined temperature difference between the exposed MOSFET (Trn in this example) and the unexposed MOSFET. The conditions of the protective film 53) of 5 (b) and the irradiation conditions of the laser or flash lamp will be described. An arrow 56 illustrated above the protective film 54 represents laser or flash lamp irradiation. This irradiation angle is preferably 0 °, that is, perpendicular to the semiconductor substrate 40 in order to avoid the influence of the pattern of the protective film 54.

As an example, for laser annealing, the laser wavelength is typically 300-1000 nm. Depending on the specific wavelength, the material, thickness, and / or reflection coefficient of the protective film 54 are designed so as to achieve the predetermined temperature difference. For example, when the protective film 54 is SiO ₂ and the wavelength of the laser is about 500 nm, the reflectance of the Si surface not covered with the protective film 54 is about 0.6. On the other hand, the reflection coefficient of the protective film 54 made of SiO ₂ can be controlled by its film thickness, for example, about 0.65 when the film thickness is 30 nm and 0.8-0.9 when the film thickness is 100 nm. It will be about. Therefore, by increasing the film thickness of the protective film 54 and making its reflection coefficient higher than the reflection coefficient of the Si surface, the temperature of the gate insulating film of the exposed MOSFET (Trn) can be changed to other MOSFETs (Tr1-Tr3). It can be made higher by a predetermined temperature. When the required temperature difference of about 5-30 ° C. is generated, the thickness of the protective film 54 can be about 20-50 nm. In order to sufficiently lower the temperature of the gate insulating film of the unexposed MOSFET (Tr1-Tr3), for example, lower than the activation temperature of the source / drain region, the thickness of the protective film 54 is about 100 nm. That is all. Actually, the thickness of the protective film is preferably 300 nm or less from the upper limit of the protective film deposition time and the desired temperature difference. Of course, an intermediate film thickness can also be used when considering both the activation of the source / drain regions and the reduction of the Vth shift of the unexposed MOSFETs (Tr1-Tr3).

  FIG. 6 shows a first modification of the first embodiment. FIG. 6 shows a process corresponding to FIG. 5C, and the same portions are denoted by the same reference numerals. In this modification, the protective film 64 is left so as to cover the MOSFETs (Trn) of the group that should shift Vth to the shallow side. In this case, the protective film 64 (and the protective film 53 in FIG. 5B) is designed to have a lower reflection coefficient than the exposed Si surface.

  In addition, as described above, it has been observed that a higher temperature heat treatment results in a smaller amount of Vth shift. This modification may be used in such a case, in which case the protective film 64 is designed to have a higher reflection coefficient than the exposed Si surface.

  FIG. 7 shows a second modification of the first embodiment. FIGS. 7A to 7C show steps subsequent to FIG. 4C except that the heat treatment for forming the source / drain regions is performed prior to the heat treatment for the Vth shift. This is the same as (a)-(c) in FIG.

  That is, in FIG. 7A, following the ion implantation 52 for forming the source / drain regions, a first heat treatment for activating the implanted impurities to form the source / drain regions 75 is performed. The temperature of the first heat treatment is set to a temperature that is sufficient to activate the impurities implanted by the ion implantation 52 and does not cause a significant Vth shift for any of the n groups of MOSFETs. The This temperature is preferably in the range of 950-1000 ° C. The first heat treatment can be performed using conventional source / drain activation annealing, and may be performed, for example, by rapid thermal annealing (RTA) using a halogen lamp.

Then, after depositing the protective film 73 in FIG. 7B, a part of the protective film 73 is removed in FIG. 7C to form a patterned protective film 74, and the second for Vth shift. Heat treatment is performed. An arrow 76 illustrated above the protective film 74 represents irradiation of a laser or flash lamp used in the second heat treatment. In the second heat treatment, since the source / drain regions 75 are already formed, it is not necessary to heat all of the n groups of MOSFETs to a temperature necessary for activating the source / drain regions. Therefore, the protective film 74 and the second heat treatment exclusively shift the Vth of the MOSFET (Trn) exposed by the protective film 74 and the MOSFET (Tr1-Tr3) covered by the protective film 74 by a desired amount. Can be designed for. For example, the protective film 74 is made of SiO ₂ having a thickness of 100-300 nm, which temperature by the second heat treatment of MOSFET (Tr1-Tr3) which is covered by the low temperatures that do not cause significant change in the Vth You may make it keep at.

  Then, the manufacturing method of the semiconductor device which concerns on 2nd Embodiment is demonstrated using FIG. FIG. 8 shows a method for manufacturing this semiconductor device with sectional views in main steps. This semiconductor device has n types of MOSFETs (Tr1, Tr2,..., Trn), similarly to the semiconductor device in the first embodiment.

  First, as shown in FIG. 8A, a shallow trench isolation (STI) 81 for element isolation is formed on a semiconductor substrate 80 made of silicon. This process is the same as the process of FIG. 4A of the first embodiment, except that the semiconductor substrate 80 includes a non-annealed region 80-1, an annealed region 80-2, and a buffer region 80-3 interposed therebetween. have. In the non-annealed region 80-1, a type of MOSFET that does not require heat treatment for Vth shift is disposed. On the other hand, in the anneal region 80-2, a MOSFET of a kind that needs to be heat-treated for Vth shift later is disposed. Further, the buffer region 80-3 is a region for reducing the influence on the non-annealed region 80-1 of the heat treatment to the annealed region 80-2 performed later. When a plurality of types of MOSFETs are arranged in the non-annealed region 80-1, these types of MOSFETs may be arranged together for each type, or may be arranged so as to be arbitrarily scattered. Further, when a plurality of types of MOSFETs are arranged in the annealing region 80-2, when the required Vth shift amount differs for each type, the types of MOSFETs are preferably arranged for each type. In any of the non-annealed region 80-1, the annealed region 80-2, and the buffer region 80-3, as described with reference to FIG. Alternatively, channel implantation may be performed.

Next, as shown in FIG. 8B, and similarly to the process of FIG. 4B, a silicon dioxide (SiO ₂ ) film 82 and a hafnium-based material are formed on the structure obtained in FIG. 8A. A high-k dielectric film 83 containing an oxide is deposited. Here, description will be made assuming that the high-k dielectric film 83 is a hafnium silicate (Hf _x Si _y O) film. The thickness of the SiO ₂ film 82, the thickness of the Hf _x Si _y O film 83, and the Hf / (Hf + Si) ratio, that is, x / (x + y) can be determined in the same manner as in the first embodiment.

Next, as shown in FIG. 8C, and similarly to the step of FIG. 4C, a polysilicon layer is deposited on the Hf _x Si _y O film 83, for example, by photolithography and subsequent etching. A gate stack 88 composed of the first gate insulating film 85, the second gate insulating film 86, and the gate electrode 87 is defined by using a pattern forming method.

  Subsequently, as shown in FIG. 9A, a side wall 90 (hereinafter, the gate stack 88 and the side wall 90 are collectively referred to as a gate electrode structure 91) is formed on the side surface of the gate stack 88. An ion implantation 92 for forming the region 95 and a heat treatment for activation thereof are performed. As described in connection with the first embodiment, sidewall 90 formation methods and ion implantation 92 are well known to those skilled in the art, and prior to sidewall 90 formation, lightly doped LDD. A region may be formed.

  Next, as shown in FIG. 9B, local heat treatment is performed on the annealing region 80-2. The heat treatment used here is a heat treatment capable of locally raising the temperature of the surface side of the semiconductor substrate in a short time, and is preferably laser annealing. In this example, heat treatment can be applied only to the MOSFET (Trn) in the annealing region 80-2 by the local laser irradiation 96. The heat treatment temperature of Trn is typically in the range of 950 to 1200 ° C., and the laser power, wavelength, irradiation time, irradiation angle, etc. are adjusted so that the Vn of Trn is shifted to the shallower side by a desired amount. Controlled by parameters. Accordingly, when a plurality of types of MOSFETs are collectively arranged for each type in the annealing region 80-2, these parameters are used to control different heat treatment temperatures for each type, and different Vth shift amounts are set. Can be realized.

  The size of the annealing region 80-2 (the size for each type when a plurality of types of MOSFETs are arranged for each type) can be set to 100 μm × 100 μm, for example. However, as will be appreciated by those skilled in the art, a larger number of smaller anneal regions 80-2 may be provided in view of the layout efficiency of the entire semiconductor chip. For laser annealing of the annealing region 100-2, a laser having a beam diameter adapted to the size of this region may be used. However, from the viewpoint of layout efficiency and uniform temperature control in the annealing region 100-2, it is preferable to scan the region using a laser having a smaller beam diameter.

  FIG. 10 shows a first modification of the second embodiment. FIG. 10 shows a process corresponding to FIG. 9B, and the same reference numerals are given to the same portions. This semiconductor device does not have a buffer region between the non-annealed region 80-1 and the annealed region 80-2. However, the MOSFET (Tr3) adjacent to the annealing region 80-2 is a type of MOSFET having a large design and / or process margin related to Vth. Therefore, even if the Vth of the adjacent MOSFET (Tr3) is shifted due to the influence of the laser annealing on the annealing region 80-2, the function of the semiconductor device can be prevented from being significantly affected. This modification can be particularly advantageous in a semiconductor device provided with a large number of annealing regions 80-2.

  FIG. 11 shows a second modification of the second embodiment. FIG. 11 shows a process corresponding to FIG. 9B, and the same reference numerals are given to the same portions. In this modification, a protective film 94 is formed and heat treatment is performed following the heat treatment for activating the source / drain regions 95 in FIG. 9A. The protective film 94 is the same film as the protective film 54 in the first embodiment, and after being deposited on the entire surface of the semiconductor substrate 80, it is removed from the annealed region 80-2 and remains in the non-annealed region 80-1. Patterning. As a result, the gate electrode structure 91 of the MOSFET (Tr1-Tr3) disposed in the non-annealed region 80-1 is covered with the protective film 94, and is disposed together in the annealed region 80-2 and has a shallow Vth side. The gate electrode structure 91 of the MOSFET (Trn) to be shifted to is exposed.

The heat treatment used here is a heat treatment that can raise the temperature of the surface side of the semiconductor substrate in a short time, and is preferably flash lamp annealing or laser annealing. The protective film 94 is made of, for example, SiO ₂ or Si ₃ N ₄ and preferably has a thickness of about 20 to 300 nm, like the protective film 54 in the first embodiment. For example, as described with reference to FIG. 5C, the temperature of the gate insulating film of the MOSFET (Tr1-Tr3) in the non-annealed region 80-1 is lower than the activation temperature of the source / drain region, for example. In order to make it sufficiently low, the thickness of the protective film 94 (SiO ₂ ) may be about 100-300 nm.

In another example, the film thickness of the protective film 94 (SiO ₂ ) is set so that the temperature of the exposed gate insulating film of the MOSFET (Trn) is about 5-30 ° C. higher than that of the other MOSFETs (Tr1-Tr3). May be about 20-50 nm. In this case, as recognized by those skilled in the art, the heat treatment for activating the source / drain region 95 in the preceding FIG. 9A may be omitted.

  Note that the semiconductor device shown in FIG. 11 does not have a buffer region between the non-annealed region 80-1 and the annealed region 80-2, like the semiconductor device of FIG. However, the MOSFET (Tr3) adjacent to the annealing region 80-2 may be any type of MOSFET due to the presence of the protective film 94. The protective film 94 can also be applied to the non-annealed region 80-1 of the semiconductor device having the buffer region 80-3.

  As is clear from the above description, the selective Vth control method by heat treatment used in various embodiments uses a common high-k dielectric film (second gate insulating film) while the desired Vth is For a plurality of different types of MOSFETs, Vth can be selectively controlled for each type. This selective Vth control method therefore does not require selective control of processes such as deposition and ion implantation on the high-k dielectric film. Therefore, the manufacturing method of the semiconductor device according to the embodiment can minimize the steps performed by exposing the high-k dielectric film, and reduce the reliability of the high-k dielectric film, and thus the gate insulating film. There is nothing.

  As mentioned above, although specific embodiment was explained in full detail, various deformation | transformation and a change are possible for these embodiment within the range described in the claim. For example, the embodiment relating to the semiconductor device having a hafnium-based oxide in the gate insulating film has been described in detail. However, a gate that causes both Vth shift due to Fermi level pinning and Vth shift due to heat treatment, such as other ion crystalline metal oxides. The present invention is equally applicable to any semiconductor device having an insulating film and having a plurality of types of MOSFETs having different desired Vth.

Regarding the above description, the following items are further disclosed.
(Appendix 1)
Forming a first gate insulating film containing silicon dioxide and a second gate insulating film containing metal oxide in a region where a plurality of types of MOSFETs are formed on a semiconductor substrate;
Forming a gate electrode containing polysilicon on the first and second gate insulating films;
After the formation of the gate electrode, a step of heat-treating the temperature of one or more MOSFETs out of the plurality of types of MOSFETs to be different from the temperature of other types of MOSFETs,
A method for manufacturing a semiconductor device.
(Appendix 2)
2. The method of manufacturing a semiconductor device according to appendix 1, wherein the metal oxide is selected from the group consisting of hafnium dioxide, hafnium silicate, and nitrogen-added hafnium silicate.
(Appendix 3)
The method for manufacturing a semiconductor device according to appendix 2, wherein the metal oxide is hafnium silicate and the Hf / (Hf + Si) ratio is in the range of 6-11%.
(Appendix 4)
A step of implanting impurities for forming source regions and drain regions of the plurality of types of MOSFETs in the semiconductor substrate;
The method of manufacturing a semiconductor device according to any one of appendices 1 to 3, wherein the heat treatment step includes a step of irradiating a flash lamp or a laser.
(Appendix 5)
The method of manufacturing a semiconductor device according to appendix 4, wherein the irradiating step activates the impurity.
(Appendix 6)
A heat treatment step for activating the impurities;
Further comprising
The method of manufacturing a semiconductor device according to appendix 4, wherein the irradiating step is performed after the heat treatment step.
(Appendix 7)
Prior to the irradiating step, the heat treatment step includes a step of exposing the gate electrode of the one or more types of MOSFETs and forming a protective film covering the gate electrodes of the other types of MOSFETs. A method of manufacturing a semiconductor device according to any one of appendices 4 to 6, characterized in that:
(Appendix 8)
In the irradiation step, a flash lamp is applied to all types of the plurality of types of MOSFETs so that a predetermined temperature difference is generated between the one or more types of MOSFETs and the other types of MOSFETs by the protective film. Alternatively, the semiconductor device manufacturing method according to appendix 7, wherein laser irradiation is performed.
(Appendix 9)
9. The method of manufacturing a semiconductor device according to appendix 8, wherein the predetermined temperature difference is controlled by the power, wavelength, irradiation time and / or irradiation angle of the flash lamp or laser.
(Appendix 10)
10. The method of manufacturing a semiconductor device according to appendix 8 or 9, wherein the predetermined temperature difference is controlled by a material, a thickness and / or a reflection coefficient of the protective film.
(Appendix 11)
The method of manufacturing a semiconductor device according to appendix 10, wherein the protective film is made of silicon dioxide, and the thickness of the protective film is 20 to 300 nm.
(Appendix 12)
The method of manufacturing a semiconductor device according to appendix 11, wherein the protective film is made of silicon dioxide, and the thickness of the protective film is 20-50 nm.
(Appendix 13)
11. The method of manufacturing a semiconductor device according to any one of appendices 8 to 10, wherein the predetermined temperature difference is 5 to 30 ° C.
(Appendix 14)
On the semiconductor substrate, the one or more types of MOSFETs are disposed in a first region, the other types of MOSFETs are disposed in a second region, and the heat treatment step includes the steps of: Irradiate only the area of the laser,
2. A method of manufacturing a semiconductor device according to appendix 1, wherein:

It is a schematic sectional drawing of MOSFET which has a high-k dielectric film. It is a figure which shows the heat processing temperature dependence of Vth of an I / O transistor. It is a figure which shows Vth of each transistor which comprises SRAM. It is a process flow figure showing a process group concerning a 1st embodiment. FIG. 5 is a process flow diagram showing a process group following FIG. 4 according to the first embodiment. It is sectional drawing which shows the modification of 1st Embodiment. It is a process flow figure showing other modifications of a 1st embodiment. It is a process flow figure showing a process group concerning a 2nd embodiment. It is a process flow figure showing a process group following Drawing 8 concerning a 2nd embodiment. It is sectional drawing which shows the modification of 2nd Embodiment. It is a process flow figure showing other modifications of a 2nd embodiment.

Explanation of symbols

1 MOSFET
2, 40, 80 Semiconductor substrate 3, 51, 91 Gate electrode structure 4, 55, 75, 95 Source / drain region 5 Channel region 11, 45, 85 First gate insulating film 12, 46, 86 Second gate insulating film 13 , 47, 87 Gate electrode 14, 50, 90 Side wall 42, 82 Silicon dioxide film 43, 83 high-k dielectric film 52, 92 Ion implantation 54, 64, 74, 94 Protective film 56, 76, 96 Flash lamp irradiation Or laser irradiation 80-1 non-annealed region 80-2 annealed region 80-3 buffer region

Claims (5)

Forming a first gate insulating film containing silicon dioxide and a second gate insulating film containing metal oxide in a region where a plurality of types of MOSFETs are formed on a semiconductor substrate;
Forming a gate electrode containing polysilicon on the first and second gate insulating films;
After the formation of the gate electrode, a step of heat-treating the temperature of one or more MOSFETs out of the plurality of types of MOSFETs to be different from the temperature of other types of MOSFETs,
A method for manufacturing a semiconductor device. A step of implanting impurities for forming source regions and drain regions of the plurality of types of MOSFETs in the semiconductor substrate;
2. The method of manufacturing a semiconductor device according to claim 1, wherein the heat treatment step includes a step of irradiating a flash lamp or a laser.   Prior to the irradiating step, the heat treatment step includes a step of exposing the gate electrode of the one or more types of MOSFETs and forming a protective film covering the gate electrodes of the other types of MOSFETs. The method of manufacturing a semiconductor device according to claim 2.   In the irradiation step, a flash lamp is applied to all types of the plurality of types of MOSFETs so that a predetermined temperature difference is generated between the one or more types of MOSFETs and the other types of MOSFETs by the protective film. The method for manufacturing a semiconductor device according to claim 3, wherein laser irradiation is performed. On the semiconductor substrate, the one or more types of MOSFETs are disposed in a first region, the other types of MOSFETs are disposed in a second region, and the heat treatment step includes the steps of: Irradiate only the area of the laser,
The method of manufacturing a semiconductor device according to claim 1.

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