JP2010020847A - Failure analysis device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently use a plurality of kinds of relief lines provided in a semiconductor device for line fail relieving. <P>SOLUTION: The failure analysis device includes a first determination part 51 for determining whether there is a failed cell in each line of a plurality of IOs which become relief targets of composite relief lines for each IO, a second determination part 53 for determining whether the combination of IOs which are relief targets of composite relief lines and the combination of IOs determined to have failed cells by the first determination part 51 match each other, a third determination part GB for determining whether the total number of failed cells in each line of the plurality of IOs exceeds a predetermined threshold, and a line establishment part 54a for establishing replacement of each line of the plurality of IO by a composite relief line when the second determination part 53 determines the matching and the third determination part GB determines that the number exceeds the threshold. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a failure analysis apparatus that performs line fail repair processing in a semiconductor memory.

  With the recent high integration and multi-functionalization of semiconductor memory, the manufacturing process has become fine and precise, and it is practically difficult to produce a memory product having no defects. For this reason, there is a method in which a repair line including a plurality of spare cells is prepared in advance as a circuit for repairing a defective cell that has been generated later, and when a defective cell is detected, the defective cell is replaced with a defective spare cell. We are carrying out.

  Specifically, by detecting a defective cell from the semiconductor memory under test (DUT) and replacing the detected defective cell in combination with a relief line in the row direction (X-axis direction) or column direction (Y-axis direction). Then, it is determined whether or not all defective cells can be repaired by the repair line (see, for example, Patent Document 1). This is called “line-fail relief processing”.

In the memory inspection method disclosed in Patent Document 1, a mask for excluding the line replaced by the first line fail repair process from the target of the next line fail repair process is set. The line fail remedy process is performed only on the defective cells on the remaining lines where no mask is set.
JP 2008-65897 A

  By the way, in the relief line built in the semiconductor memory in advance, the relief line capable of relieving the defect of the memory cell generated on any line belonging to one IO and the occurrence on any line belonging to a plurality of IOs. There is a relief line capable of simultaneously relieving defective memory cells. The former is called “single relief line” and the latter is called “compound relief line”. A single relief line is created for each IO, but a composite relief line is created by specifying a rescueable IO, so there are various types depending on the number of IO that can be rescued and the number of IOs that can be rescued.

  However, since the memory inspection method disclosed in Patent Document 1 does not perform a line fail repair process using a single repair line and a composite repair line, various types of repair lines built in advance can be efficiently performed. I can't say I'm using it. In order to perform line fail repair processing in consideration of the type of repair line using the memory inspection method disclosed in Patent Document 1, first, the above line fail repair processing is performed in units of repair line types. It is necessary to determine which relief line is to be replaced based on the result. The circuit configuration for this determination process becomes complicated and enormous, which increases the processing time and test cost of the line fail repair process.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a failure analysis apparatus that can efficiently use a plurality of types of relief lines provided in a semiconductor memory under test.

  The present invention is characterized in that an address in a memory space is assigned to each IO, and one IO includes a plurality of storage cells arranged in a matrix, and a storage cell generated on an arbitrary repair target line belonging to one IO. For analyzing a memory cell failure in a semiconductor memory having a single relief line capable of relieving the failure of the memory and a composite relief line capable of relieving the failure of the memory cell occurring on any repair target line belonging to a plurality of IOs A first determination unit, which is an analysis device, wherein the failure analysis device determines, for each IO, whether there is a defective storage cell in a repair target line belonging to a plurality of IOs to be repaired of the composite repair line. A first storage unit that stores data indicating a combination of IOs to be repaired in the composite repair line; a combination of IOs stored in the first storage unit; A second determination unit that determines whether or not a combination of IOs determined to have a defective memory cell in the determination unit and a plurality of IOs that are targets of determination in the first determination unit A third determination unit that determines whether or not the total number of defective memory cells in the repair target line belonging to the number exceeds a predetermined threshold; and the composite repair line stored in the first storage unit The second determination unit determines that the combination of IOs relieved by the above and the combination of IOs having defective memory cells determined by the first determination unit match, and the determination by the first determination unit When the third determination unit determines that the total number of defective memory cells in the repair target line belonging to the plurality of IOs that are the target exceeds the predetermined threshold value, the first determination unit Defect description judged in And summarized in that and a line determination unit for determining that replacing the relieved line belonging to a plurality of IO which the cell is present in the composite relief line.

  According to the failure analysis apparatus according to the features of the present invention, line fail remedy processing using a single remedy line and a composite remedy line can be performed without preparing a line fail remedy processing circuit having an enormous and complicated circuit configuration, Various types of relief lines built in advance can be used efficiently. Further, by keeping the circuit scale to a minimum, it is possible to suppress an increase in processing time and test cost of the line fail remedy processing.

  In the present invention, the failure analysis apparatus includes a second storage unit that stores data indicating a combination of IOs different from a combination of IOs to be repaired of the single repair line and the composite repair line, and the second storage unit. And a fifth determination unit for determining whether or not the combination of IOs stored in the storage unit matches the combination of IOs determined to have defective memory cells in the first determination unit. The line determination unit includes the fifth combination when the combination of IOs stored in the second storage unit and the combination of IOs determined by the first determination unit to have a defective storage cell match. When the total number of defective memory cells in the repair target line belonging to the plurality of IOs determined by the determination unit and determined by the first determination unit exceeds a predetermined threshold When the determination unit of 3 determines, replacing the repair target line belonging to a plurality of IOs including a part of IOs determined as having defective memory cells by the first determination unit with the composite repair line It may be confirmed.

  According to the present invention, it is possible to provide a failure analysis apparatus that can efficiently use a plurality of types of relief lines provided in a semiconductor memory under test.

Embodiments of the present invention will be described below with reference to the drawings. In the description of the drawings, the same portions are denoted by the same reference numerals and description thereof is omitted.
(Unit configuration of semiconductor memory)
Before describing the embodiment of the present invention, a unit configuration of a semiconductor memory for performing line fail relief processing will be described.

  As shown in FIG. 1, the unit for performing the line fail repair process in the configuration of the semiconductor memory to be tested includes a main area 7, an X spare area 8, and a Y spare area 9. In the main area 7, a plurality of storage cells responsible for the storage function of the semiconductor memory are arranged in a matrix. As shown in FIGS. 1 and 2, a plurality of relief lines XR extending along the X line direction XL are formed in the X spare area 8, and a plurality of relief lines XR extending along the Y line direction YL are formed in the Y spare area 9. The relief line YR is formed.

  A semiconductor memory test apparatus (not shown) accesses each memory cell in the main area 7 for writing and reading, tests whether these accesses are normally performed, and tests the memory cells successfully performed. On the other hand, a good (pass) determination is performed, and a defective (fail) determination is performed on a memory cell that is not normally performed. A memory cell determined to be defective is referred to as a “defective cell FB”. As shown in FIG. 2, the position of the defective cell FB is specified in the main area 7 by the address in the memory space.

  The repair line XR includes a plurality of defect-free spare cells arranged along the X-line direction XL, and can be replaced with an arbitrary repair target line XTL. The repair target line XTL is composed of a plurality of memory cells in the main area 7 arranged along the X line direction XL. By replacing the repair target line XTL with the repair line XR, a plurality of defective cells FB on the repair target line XTL are collectively replaced by a plurality of spare cells and repaired.

  Similarly, the repair line YR includes a plurality of defect-free spare cells arranged in the Y line direction YL, and can be replaced with an arbitrary repair target line YTL. The relief target line YTL is composed of a plurality of memory cells in the main region 7 arranged along the Y line direction YL. By replacing the repair target line YTL with the repair line YR, the plurality of defective cells FB on the repair target line YTL are collectively replaced by a plurality of spare cells and repaired.

  One defective cell FB in the main region 7 can be repaired by replacing the repair target line XTL including the defective cell FB with the repair line XR, and at the same time repairs the repair target line YTL including the defective cell FB. Rescue is possible by replacing the line YR. In the line fail repair process, it is determined whether the line to be replaced to repair the defective cell FB is the repair target line XTL including the defective cell FB or the repair target line YTL. Determining whether the line to be replaced to repair the defective cell FB is the X line or the Y line is called “line determination”, and the line determination is performed in the first line fail repair process as “primary”. Called “determined”.

  In the example shown in FIG. 2, the number of repair target lines XTL in the main area 7 is n + 1, the number of repair target lines YTL is m + 1, the number of repair lines XR in the X spare area 8 is 5, and the Y spare area. The number of relief lines YR in 9 is four.

  If all the defective cells FB shown in FIG. 2 are to be repaired using the repair lines YR, the number of the repair lines YR formed in the Y spare area 9 is four, so the repair lines YR are insufficient. When a plurality of defective cells FB exist on one repair target line XTL, YTL, the plurality of defective cells FB are repaired by replacing the repair target lines XTL, YTL with one repair line XR, YR. .

  For example, in the line fail repair process, a repair target line that can be repaired only by one of the repair lines is preferentially replaced. Since there are six defective cells FB on the repair target line YTL in FIG. 2, it is impossible to repair the six defective cells FB with the repair line XR. Therefore, it can be said that the repair target line YTL in FIG. 2 is a repair target line that can be repaired only by the repair line YR, and, for example, is primarily determined in the first line fail repair process.

  As described above, in order to efficiently repair the defective cell FB by using the limited number of repair lines XR and YR, the number of defective cells FB arranged on one X line or Y line is counted, and the defective cells are counted. It is necessary to appropriately select the relief lines XR and YR according to the count value of the FB.

  As shown in FIG. 3, the apparatus that performs the line fail repair process includes fail counters 11X and 11Y, line determination flags 12x and 12y, and line masks 13x and 13y.

  The fail counter 11X is provided for each repair target line XTL in the main area 7, and counts and stores the number of defective cells existing on the repair target line XTL. The same applies to the fail counter 11Y.

  The line confirmation flag 12x is provided for each repair target line XTL in the main area 7, and stores flag information indicating that the line has been confirmed. This flag information indicates that it is determined that the corresponding repair target line XTL is replaced with the repair line XR. The same applies to the line confirmation flag 12y.

  The line mask 13x is a mask for handling the memory cell MC on the repair target line XTL as having already undergone pass determination in the next line fail repair process when the corresponding repair target line XTL is confirmed. Store information. The same applies to the line mask 13y.

  Here, the semiconductor memory includes the main area 7 shown in FIGS. 1 and 2 as many as the number of bits constituting one word or one byte. For example, when one word is composed of 36 bits, the semiconductor memory has 36 unit structures shown in FIGS. Hereinafter, the main area 7 shown in FIGS. 1 and 2 is referred to as “IO”. An address in the memory space is assigned to each IO, and repair target lines XTL and YTL exist in each of IO0 to IO35.

Correspondingly, the apparatus for performing line fail relief processing prepares the fail counters 11X and 11Y, the line confirmation flags 12x and 12y, and the line masks 13x and 13y shown in FIG. 3 for each IO. .
(Line fail relief process)
Next, before describing the embodiment of the present invention, the line fail remedy processing related to the embodiment of the present invention will be described, and a plurality of types of remedy lines including a single remedy line and a composite remedy line will be described. The problem of the line fail remedy processing in the semiconductor memory provided will be pointed out.

  With reference to FIG. 4, the circuit configuration of the first line fail remedy processing circuit will be described. The first line fail repair processing circuit includes an X-line circuit 91X and a Y-line circuit 91Y having the same circuit configuration. The Y line circuit 91Y will be described as an example, and the illustration and description of the X line circuit 91X will be omitted. The Y line circuit 91Y includes the fail counter 11Y shown in FIG. 3, a Y threshold memory 19 for storing a predetermined Y threshold, and a comparator 18a for comparing the Y threshold and the count value of the fail counter 11Y. The fail counters 11Y are prepared corresponding to all the IOs (here, IO0 to IO35) included in the semiconductor memory, and the same number of comparators 18a are prepared so as to be connected to each fail counter 11Y on a one-to-one basis. Is done.

  If the number of defective cells existing on each repair target line YTL is equal to or greater than the Y threshold, the comparator 18a determines the repair target line YTL, stores flag information in the line determination flag 12y, and stores the line mask. The mask information is stored in 13y. The first line fail repair processing circuit performs the above-described comparison determination processing for each repair target line YTL for each IO. Therefore, the repair line used is a single repair line that can repair a defective memory cell that occurs on an arbitrary repair target line belonging to one IO.

  The circuit configuration of the second line fail remedy processing circuit will be described with reference to FIG. The second line fail remedy processing circuit includes an X line circuit 92X and a Y line circuit 92Y having the same circuit configuration. The Y line circuit 92Y will be described as an example, and the illustration and description of the X line circuit 92X will be omitted. The Y line circuit 92Y includes the fail counter 11Y shown in FIG. 3, the selector 20 for selecting an arbitrary IO, and the adder 21 for adding up the count values of the repair target lines YTL belonging to the IO selected by the selector 20. And a Y threshold memory 19 for storing a predetermined Y threshold, and a comparator 18b for comparing the Y threshold with the count value added by the adder 21. The selector 20, the adder 21, the Y threshold memory 19, and the comparator 18 b constitute the adder / comparator circuit 6. As many summing comparison circuits 6 as the number of IOs included in the semiconductor memory are prepared.

  If the total number of defective cells existing on the repair target line YTL belonging to the IO arbitrarily selected by the selector 20 is equal to or greater than the Y threshold value, the comparator 18b is concerned with the repair target line YTL belonging to the arbitrarily selected IO. All of the lines are fixed, flag information is stored in the line determination flag 12y, and mask information is stored in the line mask 13y. The second line fail repair processing circuit performs the above comparison determination processing for each repair target line YTL belonging to a plurality of arbitrarily selected IOs. Therefore, the relief line used is a composite relief line that can simultaneously relieve the defect of the memory cell that occurs on any relief target line belonging to a plurality of IOs.

  Referring to FIGS. 6A and 6B, line fail repair in a semiconductor memory having a composite repair line capable of simultaneously repairing defective memory cells occurring on any repair target line belonging to two IOs. A specific example of processing will be described. FIGS. 6A and 6B show fail analysis planes in which IO0 and IO1 included in the semiconductor memory are developed. As shown in FIG. 6A, the semiconductor memory includes four composite repair lines YR that can simultaneously repair defective cells FB generated on any repair target line YTL belonging to IO0 and IO1. The number of defective cells FB generated on the IO0 repair target line YTL, that is, the count value YFC0 of the fail counter 11Y corresponding to the IO0 repair target line YTL is 2. The number of defective cells FB generated on the repair target line YTL of IO1, that is, the count value YFC1 of the fail counter 11Y corresponding to the repair target line YTL of IO1 is also 2.

The selector 20 selects the repair target line YTL of IO0 and IO1, and the adder 21 calculates 2 + 2 = 4. The comparator 18b compares the Y threshold value with 4 in the second line fail remedy processing circuit of FIG. When the Y threshold value is 3, the total value of the count values is larger than the Y threshold value, so that the repair target lines YTL of IO0 and IO1 are recognized as the same line as shown in FIG. at the same time the primary determined by the combined relief line YR ₁ common to IO1. As a result of the primary determination, flag information and mask information are simultaneously generated for the repair target lines YTL of IO0 and IO1, and are excluded from the repair targets in the next line fail repair process. Since the repair target lines YTL belonging to different IOs can be determined simultaneously and the flag information and the mask information can be generated simultaneously, the processing time can be shortened.

  FIG. 7 shows another example of a fail analysis surface in which IO0 to IO2 included in the semiconductor memory are developed. At the same time, examples of single relief lines and composite relief lines corresponding to IO0 to IO2 are shown. In IO0 to IO2, a defective cell FB as shown in FIG. 7 is detected. For IO0, two defective cells FB are detected on the repair target line YTLA, one defective cell FB is detected on the repair target line YTLB, and four defective cells FB are detected on the repair target line YTLC. For IO1, one defective cell FB is detected on the repair target line YTLA, three defective cells FB are detected on the repair target line YTLB, and no defective cell FB is detected on the repair target line YTLC. For IO2, two defective cells FB are detected on the repair target line YTLA, no defective cells FB are detected on the repair target line YTLB, and two defective cells FB are detected on the repair target line YTLC.

  The semiconductor memory includes a composite repair line YRa that can simultaneously repair a defective cell FB generated on any repair target line YTL belonging to IO0 to IO2, and a defective cell generated on any repair target line YTL belonging to IO1 and IO2. Composite repair line YRb capable of repairing FB simultaneously, composite repair line YRc capable of simultaneously repairing defective cells FB generated on any repair target line YTL belonging to IO0 and IO1, and any repair target belonging to one IO And a single repair line YRd capable of repairing a defective cell FB generated on the line YTL. The single relief line YRd is provided for each IO of IO0 to IO2.

  With reference to FIG. 8 and FIG. 9, an example of the line fail repair process related to the composite repair line YRa in the example of the fail analysis plane of FIG. 7 will be described. The line fail repair process is executed for each repair target line YTL.

  As shown in FIG. 8, first, the selector 20 selects the repair target line YTLA of IO0 to IO2, and the adder 21 calculates 2 + 1 + 2 = 5. Since the total value (5) of the comparator 18b is larger than the Y threshold value (= 3), as shown in FIG. 9, the repair target line YTLA of IO0 to IO2 is represented by the composite repair line YRa common to IO0 to IO2. At the same time, primary determination is performed, and flag information YDF0 to YDF2 is recorded in each line determination flag 12y of IO0 to IO2.

  The selector 20 selects the repair target line YTLB of IO0 to IO2, and the adder 21 calculates 1 + 3 + 0 = 4. Since the total value (4) of the comparator 18b is larger than the Y threshold value (= 3), as shown in FIG. 9, the repair target line YTLB of IO0 to IO2 is defined by the composite repair line YRa common to IO0 to IO2. At the same time, primary determination is performed, and flag information YDF0 to YDF2 is recorded in each line determination flag 12y of IO0 to IO2.

  Then, the selector 20 selects the repair target line YTLC of IO0 to IO2, and the adder 21 calculates 4 + 0 + 2 = 6. Since the total value (6) of the comparator 18b is larger than the Y threshold value (= 3), as shown in FIG. 9, the repair target line YTLC of IO0 to IO2 is defined by the composite repair line YRa common to IO0 to IO2. At the same time, primary determination is performed, and flag information YDF0 to YDF2 is recorded in each line determination flag 12y of IO0 to IO2.

  In this way, in the line fail repair process for the composite repair line YRa, the count values of IO0 to IO2 are added together, so that the three repair target lines YTLA to YTLC are all composite repair lines common to IO0 to IO2. It will be replaced by YRa.

  When the line fail repair processing is performed using the second line fail repair processing circuit of FIG. 5, since the combination of IO is arbitrarily selected and fixed, flag information is stored in each line determination flag 12y of the selected IO. Is recorded. This means that the line is fixed by a composite repair line common to the selected IO. As shown in FIG. 7, when the semiconductor memory has a plurality of types of relief lines YRa to YRd, the second line fail relief processing circuit in FIG. 5 appropriately selects which type of relief line is determined. It is not possible.

  The advantage of relieving a defective cell with a composite relief line common to a plurality of IOs is that a plurality of IOs can be determined with a single composite relief line, so that efficient use is required. As shown in FIG. 9, among the repair target lines YTLA to YTLC replaced by the composite repair line YRa, there are IOs in which no defective cell has occurred. Even if the line can be determined by the single relief line YRd or the other composite relief lines YRb, YRc, the second line fail relief processing circuit of FIG. 5 is used only for a specific composite relief line common to the selected IO. The line is fixed.

  As shown in FIG. 10, if there is a repair target line in which no flag information is recorded in IO1 or IO2, the repair target line YTLB can be determined as a composite repair line YRc, and the repair target line YTLC is a single repair line YRd. The line can be fixed.

  In order to perform the line fail remedy processing shown in FIG. 10, it is necessary to prepare a third line fail remedy processing circuit as shown in FIG. 11, for example. The third line fail repair processing circuit includes a line fail repair processing circuit 6Ra for the composite repair line YRa, a line fail repair processing circuit 6Rb for the composite repair line YRb, and a line fail repair processing circuit 6Rc for the composite repair line YRc. And a line fail repair processing circuit 6Rd for the single repair line YRd, and a determination circuit 4 that receives the processing results from these processing circuits 6Ra to 6Rd and determines which repair line the line is to be finalized.

  Each of the line fail repair processing circuits 6Ra to 6Rc corresponds to a second line fail repair processing circuit, and includes selectors 20Ra to 20Rc, adders 21Ra to 21Rc, and comparators 18Ra to 18Rc. The line fail repair processing circuit 6Rd corresponds to the first line fail repair processing circuit. That is, the selector 20Rd selects one IO, and the counter value passes through the adder 21Rd as it is, and is compared with a predetermined Y threshold value in the comparator 18Rd.

  In this way, the third line fail repair processing circuit must perform threshold determination for each type of repair line, and the determination circuit 4 must determine from which determination line the repair line is determined, The circuit configuration for this determination process becomes complicated and enormous, which increases the processing time and test cost of the line fail repair process.

In the embodiment of the present invention, various types of relief lines YRa to YRd that have been prepared in advance by efficiently performing line fail relief processing using the single relief line YRd and the composite relief lines YRa to YRc are used efficiently. A possible failure analysis apparatus will be described.
(First embodiment)
With reference to FIG. 12, the configuration of the failure analysis apparatus according to the first embodiment of the present invention will be described. The failure analysis apparatus includes an X-line circuit 93X and a Y-line circuit 93Y having the same circuit configuration. The Y line circuit 93Y will be described as an example, and the illustration and description of the X line circuit 93X will be omitted.

  The Y-line circuit 93Y determines, for each IO, whether or not there is a defective memory cell (hereinafter referred to as “defective cell”) in a repair target line belonging to a plurality of IOs to be repaired by the composite repair line. A determination unit 51, a first storage unit 52 that stores data indicating a combination of IOs to be repaired in the composite repair line, a combination of IOs stored in the first storage unit 52, and a first determination unit A second determination unit 53 that determines whether or not the combination of IOs determined to have a defective cell in 51 matches, and a relief that belongs to a plurality of IOs that have been determined by the first determination unit 51 A third determination unit GB that determines whether or not the total number of defective cells in the target line exceeds a predetermined threshold value, a determination result of the second determination unit 53, and a determination of the third determination unit GB Based on the results, the first Comprising a line determination unit 54a to determine the replacing in the relieved line the composite relief line belonging to the IO to the determined defective cell exists in tough 51, and a fourth judging unit GA.

  The first determination unit 51 adds up the presence / absence of defective cells generated on the repair target line in IO units for all the IOs constituting the semiconductor memory based on the failure data of the defective cells generated in the semiconductor memory. A sum circuit 61 and a selector 62 for arbitrarily selecting outputs for a plurality of IOs from outputs from the OR circuit 61 are provided. The presence / absence of defective cells on the repair target line is counted in units of IO, and a plurality of IOs to be repaired in the composite repair line are selected for the count result. Thus, it is possible to determine for each IO whether or not there is a defective cell in the repair target line belonging to a plurality of IOs to be repaired in the composite repair line.

  For example, in the example of FIG. 7, when the first determination unit 51 determines the repair target line YTLB belonging to IO0 to IO2 to be repaired of the composite repair line YRa, there is a defective cell at IO0 and there is a defective cell at IO1. Yes, an output that there is no defective cell in IO2 is obtained. The output of the first determination unit 51 is expressed as “1: 1: 0” (= IO0: IO1: IO2). Therefore, when the repair target lines YTLA belonging to IO0 to IO2 in FIG. 7 are determined, since all of IO0 to IO2 have defective cells, an output of 1: 1: 1 is obtained.

  In the example of FIG. 7, the first storage unit 52 stores the first data indicating that the IO to be repaired for the composite repair line YRa is IO0 to IO2, and the IO to be repaired for the composite repair line YRb. Is stored as second data indicating that IO is IO1 and IO2, and third data indicating that IOs to be repaired in the composite repair line YRc are IO0 and IO1. Corresponding to the output of the first determination unit 51, the first data is represented as “1: 1: 1” (= IO0: IO1: IO2), and the second data is represented as “0: 1: 1”. The third data is expressed as “1: 1: 0”.

  The second determination unit 53 compares the output of the first determination unit 51 and the first data with the first comparator 63a, and compares the output of the first determination unit 51 with the second data. 2 comparators 63b, and a third comparator 63c that compares the output of the first determination unit 51 with the third data.

  For example, the second determination unit 53 compares the output (1: 1: 1) of the first determination unit 51 with each of the first to third data for the repair target line YTLA in FIG. The output (1: 1: 1) of the first determination unit 51 matches the first data (1: 1: 1) but does not match the second and third data.

  For the repair target line YTLB in FIG. 7, the second determination unit 53 compares the output (1: 1: 0) of the first determination unit 51 and each of the first to third data, Although the output (1: 1: 0) of the determination unit 51 matches the third data (1: 1: 0), an output that does not match the first and second data is obtained.

  For the repair target line YTLC in FIG. 7, the second determination unit 53 compares the output (1: 0: 1) of the first determination unit 51 with each of the first to third data. An output indicating that the output (1: 0: 1) of the determination unit 51 does not match any of the first to third data is obtained.

  In this way, the second determination unit 53 matches each combination of IOs stored in the first storage unit 52 with the combination of IOs determined by the first determination unit 51 to have a defective cell. Whether or not each can be determined.

  The specific configuration of the third determination unit GB corresponds to the configuration of the Y-line circuit 92Y shown in FIG. That is, the third determination unit GB adds up the count value of the fail counter 11Y shown in FIG. 3, the selector 20 for selecting an arbitrary IO, and the repair target line YTL belonging to the IO selected by the selector 20. A comparator 21, a Y threshold memory 19 for storing a predetermined Y threshold, and a comparator 18b for comparing the Y threshold with the count value added by the adder 21. The selector 20 arbitrarily selects the same IO as a plurality of IOs to be determined by the first determination unit 51. With this configuration, the third determination unit GB determines whether the total number of defective cells in the repair target line belonging to the plurality of IOs determined by the first determination unit 51 exceeds a predetermined Y threshold value. Can be determined.

  The specific configuration of the fourth determination unit GA corresponds to the configuration of the Y-line circuit 91Y shown in FIG. That is, the fourth determination unit GA includes the fail counter 11Y shown in FIG. 3, the selector 20 that selects an arbitrary IO, and the comparator 18a that compares the Y threshold value with the count value of the fail counter 11Y. The selector 20 arbitrarily selects the same IO as a plurality of IOs to be determined by the first determination unit 51. The comparator 18a is prepared corresponding to the number of selected IOs, and compares the Y threshold value with the count value of the fail counter 11Y for the repair target line belonging to each selected IO. With this configuration, the fourth determination unit GA determines whether or not the total number of defective cells in the repair target line belonging to the IO that has been determined by the first determination unit 51 exceeds a predetermined Y threshold value. It can be determined for each IO.

  The line determination unit 54a receives the output of each of the first to third comparators 63a to 63c, and at least one of the first to third comparators 63a to 63c is true (= 1). A logical sum circuit 64 that outputs true (= 1), and a logical product circuit that calculates a logical product of the true / false of determination by the third determination unit GB and the determination of true / false by the first determination unit 51 for each IO. 65, a selection unit 66 that selects either the output of the logical product circuit 65 or the output of the fourth determination unit GA according to the output of the logical sum circuit 64, and the authenticity of the determination of the second determination unit 53 And a logical product circuit unit 67 for calculating the logical product of the determination by the third determination unit GB.

  The logical sum circuit 64 outputs false (= 0) when any of the first to third comparators 63a to 63c outputs false (= 0). The output of the OR circuit 64 is input to the selection unit 66. The selection unit 66 includes selectors 71a to 71d for each arbitrarily selected IO. Each of the selectors 71a to 71d selects the output of the logical product circuit 65 when the logical sum circuit 64 outputs true (= 1), and the fourth when the logical sum circuit 64 outputs false (= 0). The output of the determination part GA is selected.

  A determination result as to whether or not there is a defective cell in the arbitrarily selected IO relief target line is input to the AND circuit 65 for each IO. At the same time, the AND circuit 65 receives a determination result as to whether or not the total number of defective cells existing on the repair target line YTL belonging to the IO arbitrarily selected by the selector 20 is equal to or greater than the Y threshold value. .

  When the third determination unit GB determines that the total number of defective cells existing on the repair target line YTL belonging to the IO arbitrarily selected by the selector 20 is equal to or greater than the Y threshold, the AND circuit 65 arbitrarily True (= 1) for IOs determined to have defective cells in the repair target line among the selected IOs, false for IOs determined to have no defective cells in the repair target line among arbitrarily selected IOs (= 0) is output. The output true / false signals are respectively input to the corresponding selectors 71a to 71d.

  On the other hand, when the third determination unit GB determines that the total number of defective cells existing on the repair target line YTL belonging to the IO arbitrarily selected by the selector 20 is less than the Y threshold, the AND circuit 65 Regardless of the determination result of the first determination unit 51, false (= 0) is output to the corresponding selectors 71a to 71d for all the IOs that are arbitrarily selected.

  The AND circuit unit 67 includes AND circuits 72a to 72c corresponding to the first to third comparators 63a to 63c, respectively. The outputs of the first to third comparators 63a to 63c are input to the AND circuits 72a to 72c, respectively. In addition, a determination result as to whether or not the total number of defective cells existing on the repair target line YTL belonging to the IO arbitrarily selected by the selector 20 is greater than or equal to the Y threshold is input to all the AND circuits 72a to 72c. Is done. The logical product circuits 72a to 72c calculate the logical product of the true / false of the determination of the second determination unit 53 and the true / false of the determination of the third determination unit GB, respectively.

  When any of the logical product circuits 72a to 72c outputs true, the repair lines YRa, YRb, and YRc corresponding to the logical product circuits 72a to 72c that output true are repair lines used when the line is determined. . That is, the AND circuit unit 67 can output a data signal indicating which relief line YRa, YRb, YRc is used to determine the line when determining the line.

  Further, when the selectors 71a to 71d select the output of the AND circuit 65 and the total number of defective cells existing on the repair target line YTL belonging to the IO arbitrarily selected by the selector 20 is equal to or greater than the Y threshold value. When the third determination unit GB determines, the repair target line belonging to the IO corresponding to the selectors 71a to 71d that outputs true (= 1) becomes the repair target line belonging to the IO whose line is determined. In other words, the selection unit 66 can output a data signal indicating which line to be repaired belongs to which IO when the line is determined.

  With the circuit configuration described above, the line determination unit 54a determines that the total number of defective cells existing on the repair target line YTL belonging to the IO arbitrarily selected by the selector 20 is greater than or equal to the Y threshold. And the second determination unit 53 determines that the IO combination stored in the first storage unit 52 matches the IO combination determined to have a defective cell in the first determination unit 51. In this case, it is possible to determine that the repair target line belonging to each of the IOs is replaced using the repair lines YRa to YRc whose repair targets are the combinations of the IOs.

  With reference to FIG. 13, an example of a failure analysis result performed by the failure analysis apparatus of FIG. 12 will be described. The configurations of the fail data, the single relief line, and the composite relief line in FIG. 13 are the same as those in FIG. Here, a case will be described in which IO arbitrarily selected by the selector 62 and the selector 20 in FIG. 12 includes IO0, IO1, and IO2.

  For the repair target line YTLA in FIG. 7, the output of the first determination unit 51 is 1: 1: 1, which matches the first data (1: 1: 1), so the first comparator 63a outputs true. Then, the second and third comparators 63b and 63c output false. Since the total number (5) of defective cells FB on the repair target line YTLA of IO0 to IO2 is larger than the Y threshold (3), the AND circuit 72a outputs true, and the AND circuits 72b and 72c set false. Output. Thus, it is determined that the repair target line YTLA is replaced with the repair line YRa corresponding to the AND circuit 72a. On the other hand, the logical sum circuit 64 that has received the true output of the first comparator 63 a outputs true, and the selectors 71 a to 71 d select the output of the logical product circuit 65. Since the total number (5) of defective cells FB is larger than the Y threshold (3), the AND circuit 65 outputs the output (1: 1: 1) of the first determination unit 51 as it is. As a result, the repair target lines YTLA of IO0, IO1, and IO2 are determined, and flag information and mask information are generated.

  For the repair target line YTLB in FIG. 7, the output of the first determination unit 51 is 1: 1: 0, which matches the third data (1: 1: 0), so the third comparator 63c outputs true. Then, the first and second comparators 63a and 63b output false. Since the total number (4) of defective cells FB on the repair target line YTLB of IO0 to IO2 is larger than the Y threshold (3), the AND circuit 72c outputs true, and the AND circuits 72a and 72b return false. Output. Thus, it is determined that the repair target line YTLB is replaced with the repair line YRc corresponding to the AND circuit 72c. On the other hand, the logical sum circuit 64 that has received the true output of the third comparator 63c outputs true, and the selectors 71a to 71d select the output of the logical product circuit 65. Since the total number (4) of defective cells FB is larger than the Y threshold (3), the AND circuit 65 outputs the output (1: 1: 0) of the first determination unit 51 as it is. As a result, each repair target line YTLB of IO0 and IO1 is determined, and flag information and mask information are generated.

  For the repair target line YTLC in FIG. 7, the output of the first determination unit 51 is 1: 0: 1 and does not match the first to third data, so the first to third comparators 63a to 63c are false. Output. Therefore, the total number (6) of defective cells FB on the repair target line YTLC of IO0 to IO2 is larger than the Y threshold (3), but all the AND circuits 72a to 72c constituting the AND circuit unit 67 are included. Outputs false. Thereby, it is determined that the repair target line YTLC is not replaced by any of the composite repair lines YRa to YRc. On the other hand, the OR circuit 64 that receives the false outputs of the first to third comparators 63a to 63c outputs false, and the selectors 71a to 71d select the output of the fourth determination unit GA. Since the number (4) of defective cells FB on the repair target line YTLC of IO0 is larger than the Y threshold (3), the fourth determination unit GA outputs true for the repair target line YTLC of IO0. Since the number (0) of defective cells FB on the repair target line YTLC of IO1 is equal to or less than the Y threshold (3), the fourth determination unit GA outputs false for the repair target line YTLC of IO1, Since the number (2) of defective cells FB on the repair target line YTLC is equal to or less than the Y threshold (3), the fourth determination unit GA outputs false for the repair target line YTLC of IO2.

  Thus, for the repair target line YTLA, a flag indicating that the line is determined by the composite repair line YRa is formed, and for the repair target line YTLB, a flag indicating that the line is determined by the composite repair line YRc is formed. . On the other hand, no flag is formed for the repair target line YTLC because the line is not fixed in any of the composite repair lines YRa to YRc.

  As described above, according to the first embodiment of the present invention, the following operational effects can be obtained.

  According to the failure analysis apparatus according to the first embodiment, in order to perform the line fail remedy processing shown in FIG. 10, a line fail remedy processing circuit having an enormous and complicated circuit configuration as shown in FIG. 11 is prepared. There is no need to do. Further, by keeping the circuit scale to a minimum, it is possible to suppress an increase in processing time and test cost of the line fail remedy processing.

In addition, according to the failure analysis apparatus according to the first embodiment, it is possible to perform line fail remedy processing using the single remedy line YRd and the composite remedy lines YRa to YRc. The relief lines YRa to YRd can be used efficiently.
(Second Embodiment)
As shown in FIG. 15, consider a case in which there are two defective cells FB in IO0 and IO2 and no defective cell FB in IO1 in the repair target line YTLD. The total number (4) of defective cells FB on the repair target line YTLD of IO0 to IO2 is larger than the Y threshold (3). However, since there is no defective cell in IO1, the line cannot be determined by the repair line YRa. Further, since each of the number (2) of defective cells FB in the repair target line YTLD of IO0 and IO2 is smaller than the Y threshold value (3), the defective cell FB on the repair target line YTLD is also determined in the single repair line YRa. I can't do that either. In the second embodiment of the present invention, a failure analysis apparatus capable of determining a repair target line YTLD with a repair line YRa even in such a case will be described.

  With reference to FIG. 14, the structure of the failure analysis apparatus concerning the 2nd Embodiment of this invention is demonstrated. The failure analysis apparatus includes an X-line circuit 94X and a Y-line circuit 94Y having the same circuit configuration. The Y line circuit 94Y will be described as an example, and the illustration and description of the X line circuit 94X will be omitted. Further, since the Y-line circuit 94Y has a configuration similar to the Y-line circuit 93Y in FIG. 12, only the portions of the configuration of the Y-line circuit 94Y that are different from the Y-line circuit 93Y in FIG. Parts having the same configuration are denoted by the same reference numerals and description thereof is omitted.

  The Y-line circuit 94Y includes a second storage unit 81 that stores data indicating a combination of IOs different from the combination of IOs to be repaired of the single repair line YRd and the composite repair lines YRa to YRc, and the second storage unit 81 And a fifth determination unit 82 for determining whether or not the combination of IOs stored in the storage unit 81 matches the combination of IOs determined by the first determination unit 51 to have a defective cell. . The Y-line circuit 94Y is similar to the Y-line circuit 93Y in FIG. 12 in that the first determination unit 51, the first storage unit 52, the second determination unit 53, the third determination unit GB, and the 4 determination units GA are provided.

  The Y line circuit 94Y includes a line determination unit 54b. Compared with the line determination unit 54 a in FIG. 12, the line determination unit 54 b is provided between the switch unit 83 to which the output signal of the fifth determination unit 82 is input, and between the second determination unit 53 and the AND circuit unit 67. And an OR circuit unit 84 connected in series. The OR circuit unit 84 includes a plurality of OR circuits connected between the comparators 63a to 63c and the AND circuits 72a to 72c.

  As an example of another IO combination different from the combination of IOs to be repaired in the composite repair lines YRa to YRc, the second storage unit 81 includes data indicating the combination of IO0 and IO2 in FIG. 15 (1: 0: 1) is memorized.

  When the IO determined by the first determination unit 51 to have a defective cell is IO0 and IO2 as shown in FIG. 15, the fifth determination unit 82 stores the data stored in the second storage unit 81 ( 1: 0: 1) and the determination result (1: 0: 1) of the first determination unit 51 match, so true is output.

  The output signal of the fifth determination unit 82 is input to the switch unit 83 and the OR circuit 64. When the logical sum circuit 64 receives a true output from the fifth determination unit 82, the logical sum circuit 64 outputs true regardless of the determination result of the second determination unit 53, and the selection unit 66 selects the output of the logical product circuit 65. To do. In addition, when the switch unit 83 receives a true output from the fifth determination unit 82, the switch unit 83 arbitrarily selects one of the logical sum circuits included in the logical sum circuit unit 84 and outputs true, Outputs false to other OR circuits. The one OR circuit receiving the true output outputs true regardless of the determination result of the second determination unit 53. Any one of the AND circuits 72a to 72c outputs true because the total number (4) of defective cells FB on the repair target line YTLD is larger than the Y threshold (3).

  Here, when a true output is received from the fifth determination unit 82, one logical sum circuit from which the switch unit 83 outputs true is arbitrarily selected. For example, when data (1: 0: 1) indicating the combination of IO0 and IO2 in FIG. 15 is stored in the second storage unit 81, the switch unit 83 rescues a plurality of IOs including at least IO0 and IO2. A logic circuit corresponding to the target relief line YRa is selected.

  With the circuit configuration described above, the line determination unit 54b matches the combination of IOs stored in the second storage unit 81 with the combination of IOs determined by the first determination unit 51 as having defective storage cells. Then, when the fifth determination unit 82 determines and the total number of defective cells in the repair target line belonging to the plurality of IOs determined by the first determination unit 51 exceeds the Y threshold, the third When the determination unit GB determines, it is determined that the repair target line belonging to a plurality of IOs partially including the IO determined to have a defective cell by the first determination unit 51 is replaced with the composite repair line. Can do.

  An example of a failure analysis result performed by the failure analysis apparatus of FIG. 14 will be described with reference to FIG. The configurations of the fail data, the single repair line, and the composite repair line in FIG. 16 are the same as those in FIG. Here, a case will be described in which IO arbitrarily selected by the selector 62 and the selector 20 in FIG. 14 includes IO0, IO1, and IO2.

  For the repair target line YTLD in FIG. 15, the output of the first determination unit 51 is 1: 0: 1 and does not match any of the first to third data stored in the first storage unit 52. Any of the first to third comparators 63a to 63c outputs false. On the other hand, since the output of the first determination unit 51 matches the data (1: 0: 1) stored in the second storage unit 81, the fifth determination unit 82 outputs true. The logical sum circuit 64 that has received the true output of the fifth determination unit 82 outputs true, and the selectors 71 a to 71 d select the output of the logical product circuit 65. Since the total number (4) of defective cells FB is larger than the Y threshold (3), the AND circuit 65 outputs the output (1: 0: 1) of the first determination unit 51 as it is. As a result, each repair target line YTLD of IO0 and IO2 is determined, and flag information YDF and mask information are generated.

  On the other hand, the switch unit 83 that has received the true output of the fifth determination unit 82 outputs true to the OR circuit corresponding to the relief line YRa, and outputs false to the OR circuit corresponding to the relief lines YRb and YRc. . Therefore, the logical product circuit 72a outputs true, and the logical product circuits 72b and 72c output false. Thereby, it is determined that the repair target line YTLD is replaced with the repair line YRa corresponding to the AND circuit 72a.

  Since the combination of IO stored in the second storage unit 81 and one logical sum circuit from which the switch unit 83 outputs true when a true output is received from the fifth determination unit 82 are set in advance. As shown in FIG. 15, the lines of the defective cells FB scattered can be determined collectively.

  As described above, the present invention has been described by two embodiments. However, it should not be understood that the description and the drawings, which form a part of this disclosure, limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art. That is, it should be understood that the present invention includes various embodiments and the like not described herein. Therefore, the present invention is limited only by the invention specifying matters according to the scope of claims reasonable from this disclosure.

It is a schematic diagram which shows the unit which performs a line fail relief process among the structures of a semiconductor memory. FIG. 2 is a schematic diagram for explaining specific configurations and functions of an X spare area 8 and a Y spare area 9 in FIG. 1. FIG. 6 is a schematic diagram for explaining fail counters 11X and 11Y, line determination flags 12x and 12y, and line masks 13x and 13y. It is a schematic diagram which shows the circuit structure of a 1st line fail relief processing circuit. It is a schematic diagram which shows the circuit structure of a 2nd line fail relief processing circuit. FIGS. 6A and 6B illustrate line fail repair processing in a semiconductor memory having a composite repair line that can simultaneously repair a defect of a memory cell that occurs on any repair target line belonging to two IOs. It is a schematic diagram for doing. It is the model which shows the example of the independent relief line corresponding to IO0-IO2 which developed IO0-IO2 with which a semiconductor memory is equipped, and IO0-IO2, and a composite relief line. FIG. 8 is a schematic diagram for explaining an example of line fail repair processing related to a composite repair line YRa in the fail analysis plane of FIG. 7. FIG. 9 is a schematic diagram showing a repair target line YTL whose line is determined by the line fail repair process of FIG. 8. FIG. 10 is a schematic diagram illustrating an example of a result of line confirmation using a plurality of types of relief lines with respect to the example of the line confirmation result of FIG. 9. It is a schematic diagram which shows the circuit structure of a 3rd line fail relief processing circuit. It is a schematic diagram which shows the structure of the failure analysis apparatus concerning the 1st Embodiment of this invention. It is a schematic diagram which shows an example of the defect analysis result performed by the defect analysis apparatus of FIG. It is a schematic diagram which shows the structure of the defect analysis apparatus concerning the 2nd Embodiment of this invention. FIG. 10 is a schematic diagram illustrating an example of a fail analysis plane in which IO0 to IO2 are developed and a single relief line YRd and a composite relief line YRe corresponding to IO0 to IO2 according to the second embodiment. It is a schematic diagram which shows an example of the defect analysis result performed by the defect analysis apparatus of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 4 ... Judgment circuit 6 ... Total comparison circuit 6Ra-6Rd ... Line fail relief processing circuit 7 ... Main area 8 ... X spare area 9 ... Y spare area 11X, 11Y ... Fail counter 12X, 12Y ... Line determination flag 13X, 13Y ... Line Masks 18a, 18b, 18Ra to 18Rd ... Comparator 19 ... Y threshold memory 20, 20Ra-20Rd ... Selector 21, 21Ra-21Rd ... Adder 51 ... First determination unit 52 ... First storage unit 53 ... Second Determination unit 54a, 54b ... line determination unit 61 ... logical sum circuit 62 ... selector 63a ... first comparator 63b ... second comparator 63c ... third comparator 64 ... logical sum circuit 65 ... logical product circuit 66 ... selection unit 67 ... AND circuit units 71a to 71d ... selectors 72a to 72c ... AND circuit 81 ... second Storage unit 82 ... Fifth determination unit 83 ... Switch unit 84 ... OR circuit unit 91X to 94X ... X line circuit 91Y to 94Y ... Y line circuit FB ... Defective cell GA ... Fourth determination unit GB ... Third MC: Memory cells YRa to YRc: Compound relief line YRd: Single relief line XTL, YTL, YTLA to YTLD ... Relief target line

Claims (2)

An address in the memory space is assigned to each IO, and one IO has a plurality of memory cells arranged in a matrix, and can repair a defect of a memory cell that occurs on any repair target line belonging to one IO. A failure analysis apparatus for analyzing a failure of a memory cell in a semiconductor memory having a single relief line and a composite relief line capable of relieving a failure of a memory cell occurring on any relief target line belonging to a plurality of IOs,
A first determination unit that determines, for each IO, whether or not there is a defective memory cell in a repair target line belonging to a plurality of IOs to be repaired of the composite repair line;
A first storage unit for storing data indicating a combination of IOs to be repaired in the composite repair line;
A second determination unit that determines whether or not the combination of IOs stored in the first storage unit matches the combination of IOs determined to have defective memory cells in the first determination unit When,
A third determination unit that determines whether or not the total number of defective memory cells in the repair target line belonging to the plurality of IOs to be determined in the first determination unit exceeds a predetermined threshold value When,
The second determination is made when the combination of IOs saved by the composite repair line stored in the first storage unit coincides with the combination of IOs having defective storage cells determined by the first determination unit. And when the total number of defective memory cells in the repair target line belonging to the plurality of IOs determined by the first determination unit exceeds a predetermined threshold, the third A line determination unit that determines that the repair target line belonging to a plurality of IOs having defective memory cells determined by the first determination unit is replaced with the composite repair line. A failure analysis apparatus comprising: A second storage unit for storing data indicating a combination of IOs different from the combination of IOs to be repaired of the single repair line and the composite repair line;
A fifth determination unit that determines whether or not the combination of IOs stored in the second storage unit and the combination of IOs determined by the first determination unit to have a defective memory cell match. And further comprising
The fifth determination unit determines that the combination of IOs stored in the second storage unit and the combination of IOs determined to have defective memory cells in the first determination unit match, and the When the third determination unit determines that the total number of defective memory cells in the repair target line belonging to the plurality of IOs determined by the first determination unit exceeds a predetermined threshold value The line determination unit determines to replace a repair target line belonging to a plurality of IOs including a part of IOs determined as having defective memory cells by the first determination unit with the composite repair line. The failure analysis apparatus according to claim 1.

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