JP2010020819A - Control method of nonvolatile storage device, and nonvolatile storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a control method of a nonvolatile storage device in which application voltage dependency in a re-writing state of a memory cell can be detected by reading data from a memory cell to be verified by adjusting internal drop voltage output from an internal drop voltage power supply circuit in verify operation, and a nonvolatile storage device. <P>SOLUTION: In the nonvolatile storage device in which the internal drop voltage power supply circuit is mounted, bias for re-writing is applied to a memory cell, after applying bias for re-writing, a drop voltage value of internal drop voltage output from the internal drop voltage power supply circuit is adjusted. In a state in which the drop voltage value of the internal drop voltage is adjusted, contents of the re-written memory cell are read and verified. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a non-volatile memory device control method that requires a verify read operation after a rewrite operation, and more particularly to a non-volatile memory device control method incorporating an internal step-down power supply circuit. And a non-volatile memory device.

  The nonvolatile memory disclosed in Patent Document 1 includes a power supply circuit. In the power supply circuit, when the external supply voltage rises, an internal step-down circuit composed of a constant voltage circuit or the like operates by detecting the first voltage level, and generates and supplies an internal operating voltage that is smaller in absolute value than the first voltage level.

  Some of these nonvolatile memories include a built-in controller and incorporate a rewrite bias application to the memory cell and a subsequent verify function.

  On the other hand, a memory controller such as a ROM writer is usually used for controlling data writing to the nonvolatile memory. The memory controller rewrites data such as programs and erases in the nonvolatile memory. Further, verification is performed to confirm that rewriting has been normally performed during or after rewriting.

Further, Patent Documents 2 to 4 are exemplified as other related documents.
JP 2005-141811 A JP 2005-38545 A JP-A-2005-227124 JP 2004-118908 A

  In the verification by the memory controller, various signals necessary for the verification operation are transmitted from the memory controller to the nonvolatile memory. In addition, a power supply voltage applied to the nonvolatile memory is also supplied. It is also possible to check the rewrite state by applying the voltage value of the supplied power supply voltage to the memory cell in which the data has been rewritten.

  However, the nonvolatile memory disclosed in Patent Document 1 includes an internal step-down power supply circuit, and the power supply voltage applied to the memory cell during verification is fixed. The power supply voltage is variable, and the power supply voltage dependency of the rewritten state of the memory cell cannot be inspected. As a result, a memory cell in an insufficiently rewritten state cannot be detected, which is a problem.

  The present invention provides a method for controlling a nonvolatile memory device and a nonvolatile memory device proposed in view of the above problems, and a step-down of an internal step-down voltage output from an internal step-down power supply circuit in a verify operation after data rewriting. The purpose is to read the data by adjusting the voltage value applied to the memory cell to be verified by adjusting the voltage value, and to detect the applied voltage dependence of the rewrite state of the target memory cell.

  A non-volatile memory device control method according to the present invention is a non-volatile memory device control method in which an internal step-down power supply circuit is mounted. A rewrite bias is applied to a memory cell, and a rewrite bias is applied. Thereafter, the step-down voltage value of the internal step-down voltage output from the internal step-down power supply circuit is adjusted. In the state where the step-down voltage value of the internal step-down voltage is adjusted, the contents of the rewritten memory cell are read and verified.

  The nonvolatile memory device according to the present invention is a nonvolatile memory device in which an internal step-down power supply circuit is mounted, and detects whether or not a rewrite bias is applied to the memory cell; An adjustment unit that adjusts the step-down voltage value of the internal step-down voltage output from the internal step-down power supply circuit in response to detection of release of the rewrite bias by the detection unit, and a step-down voltage of the internal step-down voltage by the adjustment unit And a verify determination unit that reads and verifies the contents of the rewritten memory cell in a state where the value is adjusted.

  In the nonvolatile memory device according to the present invention, the detection unit detects whether or not a rewrite bias is applied to the memory cell. When the detection unit detects that the rewrite bias is released, the adjustment unit adjusts the step-down voltage value of the internal step-down voltage output from the internal step-down power supply circuit. In a state where the step-down voltage value of the internal step-down voltage is adjusted, the verify determination unit reads and verifies the contents of the rewritten memory cell.

  With respect to the nonvolatile memory device on which the internal step-down power supply circuit is mounted, the step-down voltage value of the internal step-down voltage output from the internal step-down power supply circuit can be adjusted in the verify operation after data rewrite. As a result, data can be read by adjusting the bias voltage value applied to the memory cell to be verified, and the bias voltage dependency of the rewrite state of the target memory cell can be detected. The reliability of data rewritten in the target memory cell can be ensured. Further, it is possible to cope with a verify function by external control such as a memory controller.

  FIG. 1 is a diagram showing operation steps of a nonvolatile memory program (hereinafter referred to as PGM) / erase (hereinafter referred to as ER). Operation steps when the PGM / ER operation is performed by the ROM writer (memory controller) are shown in FIG. The operation starts when an ACC entry is issued by the ROM writer (memory controller), and the operation ends when an ACC exit is issued.

  Here, the ACC mode is an abbreviation for an acceleration mode. The ACC entry is an operation that is entered when a high voltage is supplied to a dedicated pad (ACC pad) provided in the nonvolatile memory, and the ACC exit is an operation that is exited when the supply of the high voltage is canceled. It is. The ACC mode is a mode used by the vendor. The high voltage supplied to the ACC pad in the ACC mode is used as an auxiliary power supply ACC in the PGM / ER operation. With this auxiliary power supply ACC, the number of PGM / ER memory cells in one access operation becomes larger than that in the normal operation. Further, high-speed PGM / ER operation is performed. In order to perform the PGM / ER operation, a boost power source ACC is required in the nonvolatile memory. Since the normal access operation is supplied by the built-in boost power supply circuit, the supply current has a limit. This is because the boosting power supply circuit built in the nonvolatile memory has a limited supply capability. Therefore, by supplying the auxiliary power supply ACC from the ACC pad, the current supply capability can be improved, and the efficiency of testing and the like at the vendor can be improved.

  Returning to FIG. In the operation step (A), the PGM / ER operation is controlled by a ROM writer (memory controller). That is, after the ACC entry, the PGM / ER voltage application is performed, and then the read operation is performed. In FIG. 1A, application of the PGM / ER voltage indicates that the PGM voltage / ER voltage is applied to the memory cell, and read operation indicates that data is read from the PGM / ER memory cell. Show. The read data is compared with an expected value by a ROM writer (memory controller), so that a so-called verify operation is performed. Thereafter, the operation is terminated by the ACC exit. The operation in the period between the ACC entry and the ACC exit is configured by PGM / ER voltage application and read operation (verify operation).

  Here, some non-volatile memories include an operation step of PGM / ER operation (B). In this nonvolatile memory, in the operation step (B), the PGM / ER voltage application and the verify operation are automatically performed by a built-in controller (not shown).

  In this embodiment, during a verify operation controlled by a ROM writer (memory controller) and a verify operation by a controller (not shown) built in the nonvolatile memory, the voltage supplied to the internal power supply VCC (INT) The voltage value is different from the internal step-down voltage. This voltage value is set by adjusting the step-down voltage value of the internal step-down voltage. The internal step-down voltage is a voltage output from an internal step-down power supply circuit built in the nonvolatile memory. FIG. 1 shows a configuration in which the voltage supplied to the internal power supply VCC (INT) and the voltage supplied to the external power supply VCC (EX) are the same voltage in the verify operation. Here, the case where the external power supply VCC (EX) is 3 V is illustrated. The internal power supply VCC (INT) is supplied with 3 V, which is the same voltage as the external power supply VCC (EX), during the verify operation, and this is replaced with the internal power supply VCC ( It is shown that 3V is supplied to (INT). Note that when the PGM / ER voltage is applied, the internal power supply VCC (INT) is supplied with 3.3 V, which is the same voltage as the external power supply VCC (EX).

  Here, as a method of supplying the internal power supply VCC (INT) during the verify operation, (1) a method of stopping the operation of the internal step-down power supply circuit and connecting the external power supply VCC (EX) and the internal power supply VCC (INT), (2) A method of varying the voltage value of the internal step-down voltage supplied to the internal power supply VCC (INT) by adjusting the step-down voltage value of the internal step-down power supply circuit, and two types of methods are conceivable. The former method is shown in FIGS. 2 to 7 as a first embodiment, and the latter method is shown in FIGS. 8 and 9 as a second embodiment and will be described below.

  FIG. 2 is a circuit block diagram of the first embodiment. In the first embodiment, the operation of the internal step-down power supply circuit is stopped and the external power supply VCC (EX) and the internal power supply VCC (INT) are connected. Thereby, the voltage supplied to the external power supply VCC (EX) is supplied to the internal power supply VCC (INT) as it is. In the verify operation, a voltage is supplied from a ROM writer (memory controller).

  First, the configuration of the circuit block of FIG. 2 will be described. The ACC pad 1 is connected to the input terminal of the high voltage detection circuit 3, and the output terminal of the high voltage detection circuit 3 is connected to one input terminal of the control circuit 13. The other input terminal of the control circuit 13 is connected to an output terminal of a verify register 73 provided in the peripheral circuit 7. The output terminal of the control circuit 13 is connected to the changeover switch 11, and the changeover of the changeover switch 11 is controlled by the output of the control circuit 13.

  One end of the changeover switch 11 is an internal power supply VCC (INT). Internal power supply VCC (INT) is connected to memory cell array 5 and peripheral circuit 7. The other end of the changeover switch 11 is connected to the external power supply VCC (EX) and the output terminal of the internal step-down power supply circuit 15. One of the external power supply VCC (EX) and the output terminal of the internal step-down power supply circuit 15 is connected to the internal power supply VCC (INT).

  The peripheral circuit 7 includes a PGM / ER control circuit 71, a verify determination circuit 72, and a verify register 73. The output terminal of the PGM / ER control circuit 71 is connected to the set terminal (S) of the verify register 73, and the verify determination circuit 72 is connected to the reset terminal (R) of the verify register 73.

  Next, circuit operation will be described. The ACC pad 1 is supplied with auxiliary power ACC in response to a command from a ROM writer (memory controller) (not shown). When the auxiliary power supply ACC is supplied to the ACC pad 1, the high voltage detection circuit 3 detects the voltage value of the auxiliary power supply ACC. As a result of detection, if the voltage value of the auxiliary power supply ACC is equal to or higher than a predetermined voltage, the high voltage detection circuit 3 detects that the auxiliary power supply ACC supplied to the ACC pad 1 is an auxiliary power supply for PGM / ER operation. Is done. As a result of this detection, the high voltage detection circuit 3 outputs an ACC mode signal ACCM, and the ACC mode signal ACCM is input to one input terminal of the control circuit 13. Thereby, the ACC mode is set.

  On the other hand, when a PGM / ER operation is issued in response to a command from a ROM writer (memory controller) (not shown), PGM / ER voltage application is started by the PGM / ER control circuit 71 (FIG. 1). When the application of the PGM / ER voltage is finished and the voltage application to the memory cell is finished, the PGM / ER control circuit 71 outputs a PGM / ER end signal PEE, and the PGM / ER end signal PEE is a set terminal of the verify register 73. (S) is input. As a result, the verify register 73 is set. The verify state signal VER is output toward the other input terminal of the control circuit 13.

  The control circuit 13 outputs a switching signal SW to the changeover switch 11 in response to the input of at least one of the ACC mode signal ACCM and the verification state signal VER. Thereby, the changeover switch 11 connects the internal power supply VCC (INT) to the external power supply VCC (EX).

  A verify operation performed after the end of the PGM / ER operation is detected by a verify determination circuit 72. When the verify operation is completed, the verify determination circuit 72 outputs a verify end signal VE, and the verify end signal VE is input to the reset terminal (R) of the verify register 73. As a result, the verify register 73 is reset. The verify state signal VER is output toward the other input terminal of the control circuit 13.

  The ROM writer (memory controller) performs a verify operation after applying the PGM / ER voltage, and the PGM / ER operation is completed. When the PGM / ER operation is completed, the supply of the auxiliary power ACC to the ACC pad 1 is stopped, and the ACC mode signal ACCM is reset. The reset ACC mode signal ACCM is output toward one input terminal of the control circuit 13.

The control circuit 13 outputs a switching signal SW to the changeover switch 11 in response to the resetting of both the ACC mode signal ACCM and the verification state signal VER. Thereby, the changeover switch 11 connects the internal power supply VCC (INT) to the internal step-down power supply circuit 15.
FIG. 7 is a diagram for explaining switching of the changeover switch 11. By switching the changeover switch 11, an external voltage is supplied instead of the internal step-down voltage. The changeover switch 11 is switched under the control of the control circuit 13. Control of the control circuit 13 is performed by setting the binary value indicating the state in which the ACC mode signal ACCM is input / not input to the control circuit 13 (the ACC mode signal ACCM is active / inactive) and the setting / setting of the verify register 73 by the verification state signal VER. Corresponding to four values configured based on two values indicating the reset state.
In FIG. 3, the four values are represented by (11) (10) (01) (00). FIG. 4 shows control of the control circuit 13 and switching of the changeover switch 11 by an external controller. The verify state signal VER is a signal controlled by an external controller, as will be described later with reference to FIG. FIG. 5 shows control of the control circuit 13 and switching of the changeover switch 11 by AND logic operation processing of both the ACC mode signal ACCM and the verify state signal VER. FIG. 6 shows control of the control circuit 13 and switching of the changeover switch 11 by OR logic processing of both the ACC mode signal ACCM and the verify state signal VER. Switching of the changeover switch 11 will be described with reference to the example of FIG.
(11) in FIG. 6 shows a state where the ACC mode signal ACCM is input to the control circuit 13 (the ACC mode signal ACCM is active) and the verify register 73 is set. In this case, the control circuit 13 is controlled by the verify state signal VER, and the changeover switch 11 does not connect the internal step-down power supply circuit 15 to VCC (INT). 6 shows a state in which the ACC mode signal ACCM is input to the control circuit 13 (the ACC mode signal ACCM is active), and the verify register 73 is in a reset state. In this case, the control circuit 13 is controlled by the ACC mode signal ACCM, and the changeover switch 11 does not connect the internal step-down power supply circuit 15 to VCC (INT). (01) of FIG. 6 shows a state in which the ACC mode signal ACCM is not input to the control circuit 13 (the ACC mode signal ACCM is inactive), and the verify register 73 is in the set state. In this case, the control circuit 13 is controlled by the verify state signal VER, and the changeover switch 11 does not connect the internal step-down power supply circuit 15 to VCC (INT). (00) in FIG. 6 shows a state in which the ACC mode signal ACCM is not input to the control circuit 13 (the ACC mode signal ACCM is inactive), and the verify register 73 is in a reset state. In this case, the control circuit 13 performs internal step-down control. The changeover switch 11 connects the internal step-down power supply circuit 15 to VCC (INT).
As a result, semiconductor memory manufacturers, vendors, and the like can realize this embodiment with a configuration that enables desired internal step-down control that meets the needs of the business market. The correspondence relationship between the control of the control circuit 13 and the changeover of the changeover switch 11 is not limited to the examples shown in FIGS. 3 to 6 and can be arbitrarily set.

  FIG. 7 is a diagram showing a voltage relationship of the voltage value of the internal power supply VCC (INT) with respect to the voltage value supplied to the external power supply VCC (EX). The voltage relationship (I) during normal operation and the voltage relationship (II) during verify operation are shown. The voltage relationship (I) during normal operation indicates that the changeover switch 11 uses the internal power supply VCC (INT) as the internal step-down power supply. The voltage relationship (II) during the verify operation is a voltage relationship when the changeover switch 11 connects the internal power supply VCC (INT) to the external power supply VCC (EX).

  In the voltage relationship (I), the internal power supply VCC (INT) is connected to the internal step-down power supply circuit 15. Therefore, even when the voltage value supplied to the external power supply VCC (EX) exceeds the internal step-down voltage (in this case, 2 V is exemplified), the internal power supply VCC (INT) is fixed to the internal step-down voltage (2 V). The Normal operating state. As a result, the internal step-down voltage (2 V) stepped down by the internal step-down power supply circuit 15 is supplied to the memory cell array 5 and the peripheral circuit 7.

  In the voltage relationship (II), the internal power supply VCC (INT) is connected to the external power supply VCC (EX). Therefore, even if the voltage value supplied to the external power supply VCC (EX) exceeds the internal step-down voltage (2 V) output from the internal step-down power supply circuit 15, the voltage value of the internal power supply VCC (INT) is The voltage value becomes (EX). Thus, the voltage supplied to the external power supply VCC (EX) is supplied to the memory cell array 5 and the peripheral circuit 7, and the voltage value of the internal power supply VCC (INT) is the same as the voltage value of the external power supply VCC (EX). Become.

  In the first embodiment, in the PGM / ER operation step (FIG. 1), in the verify operation performed after the PGM / ER voltage application, the voltage value supplied to the internal power supply VCC (INT) is the internal step-down power supply circuit 15. Instead of the internal step-down voltage output from, the voltage value supplied to the external power supply VCC (EX) is used. The voltage value supplied during the verify operation after application of the PGM / ER voltage is not fixed to the internal step-down voltage and can be made variable from the outside.

  Since the voltage at the time of the verify operation can be varied from the outside, the voltage applied to the memory cell at the time of the verify operation can be made variable so that a read condition in which the voltage application state is severe in the memory cell can be achieved. The data storage state of the memory cell rewritten by applying the PGM / ER voltage can be confirmed. That is, data is stored in the memory cell by the threshold voltage of the nonvolatile transistor. However, the threshold voltage is sufficient by making the applied voltage to the nonvolatile transistor variable by the verify operation to be a strict reading condition. Whether or not the voltage is insufficient. It is possible to confirm that the PGM / ER operation has been performed reliably by checking whether or not the storage state has a sufficient operation margin.

  In the first embodiment, since the voltage supplied to the internal power supply VCC (INT) during the verify operation is supplied from the outside, the voltage during the verify operation can be set by the ROM writer (memory controller). It is.

  Next, a second embodiment will be described. FIG. 8 is a circuit block diagram of the second embodiment. In the second embodiment, the voltage value of the internal step-down voltage supplied to the internal power supply VCC (INT) is made variable by adjusting the step-down voltage value of the internal step-down power supply circuit. The same configurations and contents as those of the first embodiment are denoted by the same reference numerals and description thereof is omitted.

  The second embodiment is different from the first embodiment in the following points. A control circuit 23 is provided instead of the control circuit 13. Similar to the control circuit 13, the control circuit 23 is supplied with a verification number signal VN indicating the number of verifications in addition to the ACC mode signal ACCM and the verification state signal VER. Further, an internal step-down power supply circuit 25 is provided instead of the internal step-down power supply circuit 15. A reference voltage circuit 27 is also provided, and the reference voltage circuit 27 outputs a reference voltage to the internal step-down power supply circuit 25. In response to this reference voltage, the internal step-down power supply circuit 25 sets the voltage value of the internal step-down voltage, thereby variably controlling the internal step-down voltage. Further, the selector switch 11 is not provided, and the output terminal of the internal step-down power supply circuit 25 is connected to the internal power supply VCC (INT).

  The output terminal of the control circuit 23 is connected to the reference voltage circuit 27, and the control circuit 23 variably controls the reference voltage output from the reference voltage circuit 27.

  Next, circuit operation will be described. Regarding the description of the circuit operation, the description of the same operation as that of the first embodiment is omitted.

  The control circuit 23 outputs a control signal CNT to the reference voltage circuit 27 in response to setting and input of at least one of the ACC mode signal ACCM and the verify state signal VER, and the reference voltage Is changed to a voltage higher than the normal voltage value. Since the reference voltage is input to the internal step-down power supply circuit 25 and the internal step-down voltage is set, the internal step-down voltage output from the internal step-down power supply circuit 25 is higher than that in the normal operation state.

  Further, the control circuit 23 makes the control signal CNT variable according to the verify number signal VN. For example, the control signal CNT is output so as to set the voltage value of the reference voltage high for each verify operation. As a result, a high voltage is sequentially applied to the memory cell every number of verifications.

  FIG. 9 is a diagram illustrating the relationship between the voltage value of the internal power supply VCC (INT) and the voltage value supplied to the external power supply VCC (EX). The voltage relationship (III) shown in FIG. 9 is a voltage relationship when the voltage value of the external power supply VCC (EX) is variable according to the reference voltage. For example, the voltage value of the internal power supply VCC (INT) can be set to about 80% of the voltage value of the external power supply VCC (EX). Thereby, the internal step-down voltage supplied to the internal power supply VCC (INT) can be made variable, for example, as a voltage value of about 80%, depending on the voltage value of the external power supply VCC (EX).

  In the second embodiment, as in the first embodiment, the voltage of the reference voltage output from the reference voltage circuit 27 in the verify operation performed after the application of the PGM / ER voltage in the PGM / ER operation step (FIG. 1). By making the value variable, the internal step-down voltage from the internal step-down power supply circuit 15 supplied to the internal power supply VCC (INT) can be made variable. The voltage value supplied during the verify operation after the application of the PGM / ER voltage can be made variable.

  The voltage applied to the memory cell during the verify operation can be made variable, and the voltage application state to the memory cell can be set as a severe read condition. The data storage state of the memory cell rewritten by applying the PGM / ER voltage can be confirmed. In other words, data is stored in the memory cell by the threshold voltage of the nonvolatile transistor. Therefore, it is possible to confirm whether the threshold voltage is a sufficient voltage or an insufficient voltage by making the applied voltage to the nonvolatile transistor variable by the verify operation and setting a strict reading condition. It is possible to confirm that the PGM / ER operation has been performed reliably by checking whether or not the storage state has a sufficient operation margin.

  FIG. 10 is a circuit block diagram showing a modification of the first and second embodiments. In this configuration, the contents of the verify register 73 are reset or referred to from the outside.

  A plurality of control pads 2 are provided, and a control signal CNTL is input to each of them. The input control signal CNTL is decoded by the command decoder 4. The command decoder 4 includes a register reset command recognition unit 41 and a status register reference command recognition unit 42. The output terminals of the register reset command recognition unit 41 and the status register reference command recognition unit 42 are connected to the peripheral circuit 7, and the outputs of the register reset command recognition unit 41 and the status register reference command recognition unit 42 are sent to the peripheral circuit 7. Have been entered.

The register reset command recognition unit 41 recognizes a command for resetting the verify register 73 based on the input control signal CNTL. When the register reset command recognition unit 41 recognizes that the command is a command for resetting the verify register 73, the verify register 73 is reset regardless of the state of the verify determination circuit 72.
Further, the status register reference command recognition unit 42 reads the contents of the verify register 73. When the status register reference command recognition unit 42 recognizes that the command is to read the contents of the verify register 73, the contents of the verify register 73 are read from the I / O pad 6 via the I / O interface 9.

  Thereby, the contents of the verify register 73 can be referred to from the ROM writer (memory controller), and the verify register 73 can be reset. By resetting the verify register 73, the voltage supply to the internal power supply VCC (INT) during the verify operation can be returned to the normal state.

  As described above in detail, according to the present embodiment, in the nonvolatile memory in which the internal step-down power supply circuits 15 and 25 are mounted, in the verify operation after the PGM / ER voltage application, the internal step-down power supply circuits 15 and 25. The internal step-down voltage output from the internal power supply VCC (INT) is disconnected and the internal power supply VCC (INT) is connected to the external power supply VCC (EX), or the voltage value of the internal step-down voltage can be adjusted. As a result, the voltage supplied to the external power supply VCC (EX) is supplied to the internal power supply VCC (INT), or the adjusted internal step-down voltage is supplied. Data can be read from the memory cell by changing the voltage value applied to the memory cell to be verified. It becomes possible to confirm the dependency of the read voltage on the PGM / ER state of the target memory cell. Strict voltage conditions can be applied at the time of reading in the verify operation, and the margin of the storage state of the rewritten data in the target memory cell can be confirmed. Reliability due to the PGM / ER operation can be ensured. In the case of the first embodiment in which the external power supply VCC (EX) is connected to the internal power supply VCC (INT), the applied voltage can be made variable even in a verify function by external control such as a ROM writer (memory controller). can do.

Needless to say, the present invention is not limited to the above-described embodiment, and various improvements and modifications can be made without departing from the spirit of the present invention.
For example, in the present embodiment, the configuration in which the control circuits 13 and 23 output the switching signal SW or the control signal CNT by detecting the set of the ACC mode signal ACCM and the set of the verify register 73 is exemplified. However, the present application is not limited to this, and the control can be performed by either the setting of the ACC mode signal ACCM or the setting of the verify register 73.

It is a figure which shows the operation | movement step of PGM / ER. It is a circuit block diagram of a 1st embodiment. FIG. 4 is a diagram representing switching of a changeover switch 11 by control of a control circuit 13 in four values. It is a figure which shows control of the control circuit 13, and change of the changeover switch 11 by an external controller. It is a figure which shows the control of the control circuit 13, and the switching of the changeover switch 11 by the AND logic operation process of both the ACC mode signal ACCM and the verification state signal VER. It is a figure which shows the control of the control circuit 13, and the switch of the changeover switch 11 by OR logic operation processing of both the ACC mode signal ACCM and the verification state signal VER. In 1st Embodiment, it is a figure which shows the relationship of the voltage supplied to internal power supply VCC (INT) with respect to the voltage supplied to external power supply VCC (EX). It is a circuit block diagram of a 2nd embodiment. In 2nd Embodiment, it is a figure which shows the relationship of the voltage supplied to internal power supply VCC (INT) with respect to the voltage supplied to external power supply VCC (EX). It is a figure which shows the modification of 1st and 2nd embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ACC pad 2 Control pad 3 High voltage detection circuit 4 Command decoder 5 Memory cell array 6 I / O pad 7 Peripheral circuit 9 I / O interface 11 Changeover switch 13 Control circuit 15 Internal step-down power supply circuit 23 Control circuit 27 Reference voltage circuit 41 Register Reset command recognition unit 42 Status register reference command recognition unit 71 PGM / ER control circuit 72 Verify determination circuit 73 Verify register ACC Auxiliary power supply VCC (EX) External power supply VCC (INT) Internal power supply ACCM ACC mode signal CNT Control signal CNTL Control signal PEE PGM / ER end signal SW switching signal VER verify status signal VN verify count signal

Claims (13)

A method for controlling a nonvolatile memory device in which an internal step-down power supply circuit is mounted,
Applying a rewrite bias to the memory cell;
Adjusting the step-down voltage value of the internal step-down voltage output from the internal step-down power supply circuit after the step of applying the rewriting bias;
And a step of reading and verifying the contents of the rewritten memory cell in a state where the step-down voltage value of the internal step-down voltage is adjusted. Adjusting the step-down voltage value of the internal step-down voltage,
The method of controlling a nonvolatile memory device according to claim 1, further comprising a step of stopping the internal step-down power supply circuit and supplying an external voltage instead of the internal step-down voltage. Adjusting the step-down voltage value of the internal step-down voltage,
2. The method of controlling a nonvolatile memory device according to claim 1, further comprising a step of variably setting the step-down voltage value set in the internal step-down power supply circuit. The step of variably setting the step-down voltage value includes
4. The method of controlling a nonvolatile memory device according to claim 3, wherein the step-down voltage value is changed according to the number of times of verification in the verifying step.   5. The method of controlling a nonvolatile memory device according to claim 3, wherein the step-down voltage value includes a voltage value at which the internal step-down voltage becomes a minimum value and a maximum value that can be applied to the memory cell.   6. The control of a nonvolatile memory device according to claim 1, further comprising a step of canceling the adjustment of the step-down voltage value in the internal step-down power supply circuit after the verifying step. Method. A non-volatile memory device on which an internal step-down power supply circuit is mounted,
A detection unit for detecting whether or not a rewrite bias is applied to the memory cell;
An adjustment unit that adjusts the step-down voltage value of the internal step-down voltage output from the internal step-down power supply circuit in response to detecting that the rewrite bias is released by the detection unit;
A non-volatile memory device comprising: a verify determination unit that reads and verifies the contents of the rewritten memory cell in a state where the step-down voltage value of the internal step-down voltage is adjusted by the adjustment unit. The adjustment unit is
The nonvolatile memory device according to claim 7, further comprising a switching unit that switches between an output line of the internal step-down power supply circuit and an external power supply line.   The nonvolatile memory device according to claim 7, wherein the adjustment unit is a reference voltage source that sets the internal step-down voltage of the internal step-down power supply circuit.   The nonvolatile memory device according to claim 9, wherein the reference voltage source changes a reference voltage value in accordance with the number of verifications in the verification determination unit.   11. The nonvolatile memory device according to claim 9, wherein the reference voltage source outputs a reference voltage value at which the internal step-down voltage becomes a minimum value and a maximum value that can be applied to the memory cell. An auxiliary power supply terminal for supplying the rewriting bias for the memory cell from the outside;
An auxiliary detection unit for detecting a bias applied to the auxiliary power supply terminal,
8. The adjustment unit releases adjustment of a step-down voltage value of the internal step-down voltage in response to detection of release of application of the rewriting bias to the auxiliary power supply terminal by the auxiliary detection unit. The non-volatile memory device according to any one of items 11 to 11.   12. The at least one of claims 7 to 11, wherein the adjustment unit cancels the adjustment of the step-down voltage value of the internal step-down voltage in response to the end of the verify operation in the verify determination unit. Non-volatile storage device.

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