JP2010020818A - Semiconductor device and method of controlling the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce variation in precision of a timer function of a semiconductor device having variable resistance. <P>SOLUTION: The semiconductor device includes: a first reference cell 44 in which the rate of change in a resistance value varying with time is a first rate of change; a second reference cell 46 in which the rate of change in the resistance value varying with time is a second rate of change different from the first rate of change; and a determination circuit 48 which determines whether a period from the reference time to the evaluation time exceeds a predetermined period on the basis of an amount related to the difference between a variation in the resistance value of the first reference cell 44 at the evaluation time from the reference time and a variation in the resistance value of the second reference cell 46 at the evaluation time from the reference time. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a variable resistor.

  Data storage elements used in semiconductor devices include volatile data storage elements such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory), flash memory and EEPROM (Electrically Erasable and Programmable Read Only Memory), etc. There are non-volatile data storage elements. Volatile data storage elements can write and read data at high speed, but have poor data retention. A nonvolatile data storage element is excellent in data retention, but has a slower writing / reading speed than a volatile data storage element.

  On the other hand, data storage elements that store data by the resistivity of variable resistors such as ReRAM (Resistance Random Access Memory) and PRAM (Phase change Random Access Memory) have been developed. A data storage element having a variable resistance stores data by changing the variable resistance to either a high resistance state or a low resistance state. Data retention of a data storage element having a variable resistance is an intermediate performance between a volatile data storage element and a non-volatile data storage element, and is on the order of hours or days. For example, Patent Document 1, Patent Document 2, and Patent Document 3 show semiconductor devices using a memory with a programmable resistance element.

JP 2006-202383 A JP 2006-202411 A JP 2005-158221 A

  The resistance value of the variable resistor varies with time. A timer function for determining that a predetermined time has elapsed can be realized using the variation amount of the resistance value. There is a problem that the accuracy of the timer function of the semiconductor device having a variable resistor varies.

  The present invention has been made in view of the above problems, and an object thereof is to reduce variation in accuracy of a timer function of a semiconductor device having a variable resistor.

  The present invention provides a first reference cell having a first rate of change in resistance value that changes with time, and a first rate of change in resistance value that changes with time. A second reference cell having a second rate of change different from the first reference cell, and a variation amount of the resistance value of the first reference cell from the reference time at the evaluation time and the second reference cell from the reference time at the evaluation time A determination circuit for determining whether or not a time from the reference time to the evaluation time exceeds a predetermined time based on an amount related to a difference between the resistance value variation amount of the first resistance value and the evaluation value. It is a semiconductor device. According to the present invention, not the amount of variation in the resistance value of one reference cell, but the relative amount related to the difference between the amount of variation in the resistance value of the first reference cell and the amount of variation in the resistance value of the second reference cell. Based on the correct amount, it can be determined that the predetermined time has elapsed. Therefore, it is possible to suppress the variation of the resistance value due to the influence of the difference in the manufacturing process of the reference cell having the variable resistance and the operating temperature environment. Therefore, there is an effect in reducing variation in accuracy of the timer function of the semiconductor device having a variable resistor.

  In the above configuration, the first reference cell and the second reference cell are a plurality of reference cells, and a first determination circuit having a plurality of the determination circuits and a plurality of determinations determined by the first determination circuit A second determination circuit that determines that the time from the reference time to the evaluation time exceeds the predetermined time when the number of determination results that exceed the predetermined time exceeds the predetermined time It can be set as the structure to comprise. According to this configuration, variation in accuracy between reference cells having a plurality of variable resistors can be suppressed. Therefore, there is an effect in reducing variation in accuracy of the timer function of the semiconductor device having a variable resistor.

  In the above configuration, the first reference cell and the second reference cell may be variable resistance memory cells.

  In the above configuration, the first reference cell and the second reference cell may be phase change type memory cells.

  In the configuration described above, a configuration is provided that includes a setting circuit that sets resistance values of the first reference cell and the second reference cell so that the first change rate and the second change rate are different from each other. can do.

  In the above configuration, the first control circuit, which is a control circuit that converts the fluctuation amount of the resistance value of the first reference cell into the fluctuation amount of the voltage value, and the fluctuation amount of the resistance value of the second reference cell are the voltage. A second control circuit that is a control circuit that converts the value into a fluctuation amount of the value, and a fluctuation amount of a divided value between the first reference cell and the first control circuit that are connected in series between the power supplies And the evaluation from the reference time based on the amount related to the difference between the second reference cell connected in series between the power supplies and the amount of variation in the divided voltage value of the second control circuit. A determination circuit for determining whether or not a time until a time exceeds a predetermined time, and the first reference cell, the first control circuit, the second reference cell, and the first between the power sources Two control circuits can be connected in parallel.

  The above configuration includes a control circuit that outputs a reference voltage, and the amount of change in the value of the reference voltage and the divided value of the first reference cell and the second reference cell connected in series between the power supplies And a determination circuit that determines whether or not the time from the reference time to the evaluation time exceeds a predetermined time based on an amount related to the difference between the reference time and the evaluation time.

  In the above configuration, when a voltage value supplied to the semiconductor device reaches a value at which the first reference cell and the second reference cell operate normally, an activation signal is sent to the determination circuit. An activation signal generating circuit for inputting may be provided. According to this configuration, the malfunction of the determination circuit can be prevented by deactivating the determination circuit until the voltage value supplied to the semiconductor device reaches a value at which the reference cell operates normally. . Therefore, there is an effect in improving the accuracy of the timer function of the semiconductor device having a variable resistor.

  In the above configuration, a configuration includes: a memory cell that stores data; and a control circuit that is connected to the determination circuit and performs an erasing operation of data stored in the memory cell based on a determination result of the determination circuit; can do. According to this configuration, it is possible to accurately determine that the predetermined time has elapsed by the determination circuit that reduces the variation in accuracy of the timer function, and the control circuit can perform the erasing operation of the data stored in the memory cell. Therefore, there is an effect in improving the security of the semiconductor device having a variable resistance.

  In the above configuration, a configuration includes: a memory cell that stores data; and a control circuit that is connected to the determination circuit and performs an invalid data write operation on the memory cell based on a determination result of the determination circuit. It can be. According to this configuration, it is possible to accurately determine that the predetermined time has elapsed by the determination circuit that reduces the variation in accuracy of the timer function, and the control circuit can perform an invalid data write operation to the memory cell. Therefore, there is an effect in improving the security of the semiconductor device having a variable resistance.

  In the above configuration, a configuration includes: a memory cell that stores data; and a control circuit that is connected to the determination circuit and prohibits a read operation of data stored in the memory cell based on a determination result of the determination circuit. It can be. According to this configuration, it is possible to accurately determine that the predetermined time has elapsed by the determination circuit that reduces the variation in accuracy of the timer function, and the control circuit performs an operation of prohibiting reading of data stored in the memory cell. it can. Therefore, there is an effect in improving the security of the semiconductor device having a variable resistance.

  The present invention provides a first reference cell having a first rate of change in resistance value that changes with time, and a first rate of change in resistance value that changes with time. And a second reference cell having a second rate of change different from that of the first reference cell, the variation amount of the resistance value of the first reference cell from the reference time at the evaluation time and the evaluation It is determined whether or not the time from the reference time to the evaluation time exceeds a predetermined time based on an amount related to a difference between the resistance value variation amount of the second reference cell from the reference time at the time A method of controlling a semiconductor device comprising steps. According to the present invention, not the amount of variation in the resistance value of one reference cell, but the relative amount related to the difference between the amount of variation in the resistance value of the first reference cell and the amount of variation in the resistance value of the second reference cell. Based on the correct amount, it can be determined that the predetermined time has elapsed. Therefore, it is possible to suppress the variation of the resistance value due to the influence of the difference in the manufacturing process of the reference cell having the variable resistance and the operating temperature environment. Therefore, there is an effect in reducing variation in accuracy of the timer function of the semiconductor device having a variable resistor.

  According to the present invention, it is possible to suppress variations in the resistance value due to the difference in the manufacturing process of the reference cell having a variable resistor and the operating temperature environment, so that the variation in the accuracy of the timer function of the semiconductor device having the variable resistor can be reduced. It is effective for reduction.

  For comparison with the embodiment of the present invention, an example of a configuration of a semiconductor device having a variable resistor and an operation of a timer function will be described with reference to FIGS. 1, 2, and 3. FIG.

  The structure of the semiconductor device will be described with reference to FIG. FIG. 1 is a block diagram showing a configuration of the semiconductor device 10. The memory cell array 11 has a data storage element. The reference cell unit 12 includes a reference cell 14 having a variable resistance. The determination circuit 16 includes a control circuit 18, a reference voltage generation circuit 20, and a comparator 22. A voltage Vcc 24 is applied to the control circuit 18 and the reference voltage generation circuit 20. The reference cell 14 and the control circuit 18 are connected in series. The resistance value of the reference cell 14 is converted into a voltage value by the control circuit 18. The voltage value of the reference cell 14 at the evaluation time t is V (t). The reference voltage generation circuit 20 generates a reference voltage Vref.

  The reference time is t0, the predetermined time is Ti, and the evaluation time when the predetermined time Ti has elapsed from the reference time t0 is ti. In the setting circuit 26, the voltage value V (t) of the reference cell 14 decreases with time, and after the evaluation time t has passed the predetermined time Ti from the reference time t0, the setting circuit 26 becomes smaller than the value of the reference voltage Vref. Thus, the resistance value of the reference cell 14 is set.

  The operation of the timer function of the semiconductor device is described with reference to FIGS. FIG. 2 is a graph showing changes in the voltage value V (t) with respect to the evaluation time t. The voltage values V (t0) and V (ti) indicate voltage values at the reference time t0 and the evaluation time ti, respectively. V (ti) matches the value of the reference voltage Vref.

  FIG. 3 is a flowchart showing the operation of the timer function of the determination circuit 16 at the evaluation time t. First, the voltage value V (t) at the evaluation time t is measured (step S30). The initial value of the evaluation time t is the reference time t0. In the comparator 22, the voltage value V (t) is compared with the reference voltage Vref (step S32). When the voltage value V (t) is smaller than the value of the reference voltage Vref (YES in step S32), it means that the predetermined time Ti has elapsed from the reference time t0, and therefore the comparator 22 outputs the determination signal 28 (step). S34). The case where the voltage value V (t) is smaller than the value of the reference voltage Vref corresponds to the case where the evaluation time t is larger than the evaluation time ti in FIG. When the voltage value V (t) is greater than or equal to the reference voltage Vref (NO in step S32), the processing from step S30 is repeated. The case where the voltage value V (t) is greater than or equal to the value of the reference voltage Vref corresponds to the case where the evaluation time t is t0 or more and ti or less in FIG. The above is the description of the timer function of the semiconductor device 10.

  However, the fluctuation amount of the resistance value of the variable resistor varies due to the influence of the variable resistor manufacturing process and the operating temperature environment. Therefore, there is a problem that the accuracy of the timer function of the semiconductor device using the reference cell having the variable resistance varies. For example, in one semiconductor device, the predetermined time is determined after a predetermined time is exceeded, but in the other semiconductor device, the predetermined time is determined as soon as the timer function is started.

  Hereinafter, with reference to FIGS. 4, 5, 6, and 7, an embodiment of the semiconductor device having a variable resistor and having reduced variation in accuracy of the timer function, which is an embodiment of the present invention, will be described.

  FIG. 4 is a block diagram showing a configuration of the semiconductor device 40. The memory cell array 41 has data storage elements. The reference cell unit 42 includes a first reference cell 44 and a second reference cell 46 having variable resistance. The determination circuit 48 includes a first control circuit 50, a second control circuit 52, and a comparator 54. A voltage Vcc 56 is applied to the first control circuit 50 and the second control circuit 52. The first reference cell 44 and the first control circuit 50 connected in series and the second reference cell 46 and the second control circuit 52 connected in series are connected in parallel. The resistance values of the first reference cell 44 and the second reference cell 46 are converted into voltage values by the first control circuit 50 and the second control circuit 52, respectively. The voltage value obtained by converting the resistance value of the first reference cell 44 at the evaluation time t by the first control circuit 50 is defined as V1 (t). The voltage value obtained by converting the resistance value of the second reference cell 46 at the evaluation time t by the second control circuit 52 is defined as V2 (t). The comparator 54 receives the voltage value V1 (t) and the voltage value V2 (t) as inputs, and based on a comparison result between an amount based on the difference between the voltage value V1 (t) and the voltage value V2 (t) and a predetermined value. The determination signal 60 is output.

  The activation signal generation circuit 64 outputs an activation signal enz to the comparator 54 when the input voltage Vcc 56 reaches a predetermined value. The predetermined value is, for example, a voltage value that ensures normal operation of the memory cell array 41 and the reference cell unit 42. The comparator 54 is activated when the activation signal enz is input, and can compare the voltage value V1 (t) and the voltage value V2 (t).

  The determination signal 60, which is the output of the comparator 54, is fed back to the second control circuit 52 through the signal line 62 in order to give the comparator 54 hysteresis. As a result, chattering of the determination signal 60 can be prevented when the comparator 54 detects a slight difference in the input signal or noise mixing.

The reference time is t0, the predetermined time is Ti, the evaluation time when the predetermined time Ti has elapsed from the reference time t0 is ti, and the predetermined value is ΔV. The setting circuit 58 sets the resistance values of the first reference cell 44 and the second reference cell 46 so that the change rate of the voltage value V1 (t) and the change rate of the voltage value V2 (t) are different from each other. In addition, the setting circuit 58 sets the absolute value of the fluctuation amount of the voltage value of the first reference cell 44 from the reference time t0 at the evaluation time ti and the voltage value of the second reference cell 46 from the reference time t0 at the evaluation time ti. The resistance values of the first reference cell 44 and the second reference cell 46 are set so that the absolute value of the difference from the absolute value of the fluctuation amount becomes a predetermined value ΔV. That is, the following formula (1) is established.
ΔV = || V1 (ti) −V1 (t0) |
− | V2 (ti) −V2 (t0) || (1)
Expression (1) can be transformed as the following expression (2).
ΔV = || V1 (ti) −V2 (ti) |
− | V1 (t0) −V2 (t0) || (2)
Equation (2) is the absolute value of the difference between the voltage value of the first reference cell 44 and the voltage value of the second reference cell 46 at the evaluation time ti, and the second term is the voltage of the first reference cell 44 at the reference time t0. This means that the absolute value of the difference between the value and the absolute value of the difference between the voltage value of the second reference cell 46 is a predetermined value ΔV.

  FIG. 5 is a graph showing changes in the voltage value V1 (t) and the voltage value V2 (t) with respect to the evaluation time t. The voltage values V1 (t0) and V1 (ti) indicate the voltage values of the first reference cell 44 at the standard time t0 and the evaluation time ti, respectively. The voltage values V2 (t0) and V2 (ti) indicate the voltage values of the second reference cell 46 at the standard time t0 and the evaluation time ti, respectively. The slopes of the graphs of the voltage values V1 (t) and V2 (t) indicate the rate of change of the voltage values V1 (t) and V2 (t), respectively, and the rate of change of the voltage value V1 (t) and the voltage value V2 (t ) Is different from each other.

  FIG. 6 is a flowchart showing the operation of the timer function of the determination circuit 48. First, the voltage values V1 (t0) and V2 (t0) at the reference time t0 are measured (step S70). The absolute value | V1 (t0) −V2 (t0) | of the difference between the voltage values V1 (t0) and V2 (t0) is stored in the variable α (step S72). The voltage values V1 (t) and V2 (t) at the evaluation time t are measured (step S74). The absolute value | V1 (t) −V2 (t) | of the difference between the voltage value V1 (t) and the voltage value V2 (t) is stored in the variable β (step S76). It is checked whether or not the absolute value | α−β | of the difference between the variable α and the variable β exceeds a predetermined value ΔV (step S78). If | α−β | exceeds the predetermined value ΔV (YES in step S78), it means that the predetermined time Ti has elapsed from the reference time t0, and therefore the comparator 54 outputs the determination signal 60 (step S78). If | α−β | is equal to or smaller than the predetermined value ΔV (NO in step S80), the processing from step S74 is repeated. As described above, a timer function for determining that the predetermined time Ti has elapsed from the reference time t0 can be realized.

FIG. 7 is a cross-sectional view showing the configuration of the reference cell 82 corresponding to the first reference cell 44 and the second reference cell 46 of FIG. The reference cell 82 includes a variable resistor 84 and electrodes 86 provided at both ends thereof. Variable resistor 84, the magnitude of the resistance value used for storing data, resistance is large (e.g. 10 ⁴ times or more) when a current flows consists change material. Such materials include transition metal oxides such as CuO. The electrode 86 stores data by storing electric charge as a capacitor, and is made of a highly conductive material such as copper. The periphery of the variable resistor 84 is covered with an insulating portion 88.

  In the first embodiment, the first reference cell 44 having a first rate of change in resistance value that changes with time, and the first change rate of the resistance value that changes with time. The second reference cell 46 having a second rate of change different from the rate, the amount of change in the resistance value of the first reference cell 44 from the reference time t0 at the evaluation time t, and the second from the reference time t0 at the evaluation time t. And a determination circuit 48 that determines whether or not the time from the reference time t0 to the evaluation time t exceeds a predetermined time Ti based on an amount related to a difference from the variation amount of the resistance value of the reference cell 46. An example of the configuration has been described. According to this configuration, the relative amount related to the difference between the variation amount of the resistance value of the first reference cell and the variation amount of the resistance value of the second reference cell, not the variation amount of the resistance value of one reference cell. Based on the correct amount, it can be determined that the predetermined time has elapsed. Therefore, it is possible to suppress fluctuation due to the influence of the difference in temperature environment in which the reference cell manufacturing process and the reference cell are operated. Therefore, it is effective in reducing variation in accuracy of the timer function of the semiconductor device.

  In the first embodiment, the first reference cell 44 and the second reference cell 46 may be either a resistance change type memory cell or a phase change type memory cell.

  In the first embodiment, the first reference cell 44 and the second reference cell 46 and the data storage element included in the memory cell array 41 may have the same configuration. The first reference cell 44 and the second reference cell 46 may be disposed in the memory cell array 41. Thus, the reference cell and the data storage element included in the memory cell array can be manufactured by the same manufacturing method, which is effective in reducing the cost.

  In the first embodiment, the setting circuit 58 sets the resistance values of the first reference cell 44 and the second reference cell 46 so that the change rate of V1 (t) and the change rate of V2 (t) are different from each other. The setting circuit 58 varies the time for applying the voltage to the first reference cell 44 and the second reference cell 46 so that the change rate of V1 (t) and the change rate of V2 (t) are different from each other. Alternatively, the magnitude of the applied current may be varied.

  In the first embodiment, when the voltage Vcc 56 supplied to the semiconductor device reaches a value at which the first reference cell 44 and the second reference cell 46 operate normally, the activation signal enz is input to the determination circuit 48. An example in which the activation signal generating circuit 64 is provided has been described. According to this configuration, it is possible to prevent the determination circuit from malfunctioning by inactivating the determination circuit until the voltage supplied to the semiconductor device reaches a value at which the reference cell normally operates. Therefore, there is an effect in improving the accuracy of the timer function of the semiconductor device having a variable resistor.

  Hereinafter, referring to FIG. 8, a semiconductor device having a timer function using a determination circuit that determines that a predetermined time has elapsed by using a plurality of determination results by a plurality of reference cells and a plurality of determination circuits. Examples will be described. FIG. 8 is a block diagram illustrating a configuration of a semiconductor device having a timer function using a determination circuit that determines that a predetermined time has elapsed using four determination results of five reference cells and four determination circuits. FIG. The memory cell array 90 has data storage elements. The reference cell unit 92 includes first to fifth reference cells 94 to 102 having variable resistors. The first determination circuit 104 includes a control circuit 106 and first to fourth comparators 108 to 114. A voltage Vcc 116 is applied to the control circuit 106. The control circuit 106 converts the resistance values of the first to fifth reference cells 94 to 102 into voltage values.

  The first to fourth comparators 108 to 114 are a first reference cell 94 and a second reference cell 96, a first reference cell 94 and a third reference cell 98, and a first reference cell 94 and a fourth reference cell 100, respectively. The voltage values of the first reference cell 94 and the fifth reference cell 102 are compared to determine whether or not a predetermined time is exceeded. The first to fourth comparators 108 to 114 output first to fourth determination signals to the second determination circuit 118, respectively, when it is determined that the predetermined time is exceeded. Since the determination processing performed by the first to fourth comparators 108 to 114 is the same as that of the first embodiment, description thereof is omitted.

  The second determination circuit 118 includes NAND circuits 122 to 128 and NOR circuits 130 to 134. When the number of determination signals input from the first determination circuit 104 exceeds a predetermined number, the second determination circuit 118 determines that the predetermined time is exceeded and outputs a final determination signal 120.

  Hereinafter, an example in which the predetermined number is 2 will be described. When the first determination circuit 104 outputs the first, second, and third determination signals to the second determination circuit 118, since the number of determination signals is 3, the number of determination signals exceeds a predetermined number. This condition is satisfied. At this time, the NAND circuit 122 and the NOR circuits 130 and 134 included in the second determination circuit 118 are sequentially turned on by the first, second, and third determination signals. Then, the second determination circuit 118 outputs a final determination signal 120.

  In the second embodiment, when the number of determination results exceeding a predetermined time among the first determination circuit 104 having a plurality of determination circuits and the plurality of determination results determined by the first determination circuit 104 exceeds a predetermined number. An example has been described in which the second determination circuit 118 determines that the time from the reference time to the evaluation time exceeds a predetermined time. According to this configuration, variation in accuracy between reference cells having a plurality of variable resistors can be suppressed. Therefore, there is an effect in reducing variation in accuracy of the timer function of the semiconductor device having a variable resistor.

  In the second embodiment, the first to fifth reference cells 94 to 102 may be either resistance change type memory cells or phase change type memory cells.

  In the second embodiment, the first to fifth reference cells 94 to 102 and the data storage element included in the memory cell array 90 may have the same configuration. The first to fifth reference cells 94 to 102 may be arranged in the memory cell array 90. Thus, the reference cell and the data storage element included in the memory cell array can be manufactured by the same manufacturing method, which is effective in reducing the cost.

  Hereinafter, specific examples of the reference cell and the determination circuit shown in the first embodiment will be described with reference to FIGS. 9, 10, 11, and 12. The description overlapping with the first embodiment is omitted.

  FIG. 9 is a circuit diagram showing a determination circuit to which the current mirror circuit is applied. The variable resistor 140 and the diode 142 correspond to the first reference cell 44 of FIG. The variable resistor 144 and the diode 146 correspond to the second reference cell 46 of FIG. The MOSFET 152 corresponds to the first control circuit 50 of FIG. The MOSFET 154 corresponds to the second control circuit 52 of FIG. A voltage is applied between the power supplies E1 and E2. Between the power supplies E1 and E2, the variable resistor 140, the diode 142, and the MOSFET 152 are connected in series to form a voltage dividing circuit. Between the power supplies E1 and E2, the variable resistor 144, the diode 146, and the MOSFET 154 are connected in series to form a voltage dividing circuit. Between the power supplies E1 and E2, the variable resistor 140, the diode 142, and the MOSFET 152, and the variable resistor 144, the diode 146, and the MOSFET 154 are connected in parallel. MOSFETs 150, 152, and 154 form a current mirror circuit. The MOSFETs 156 and 158 function as a switch for operating the current mirror circuit, and are turned on when the voltage E0 is applied. Due to the nature of the current mirror circuit, currents of the same magnitude flow through the variable resistor 140 and the diode 142, and the variable resistor 144 and the diode 146. Therefore, the comparator 160 can compare the voltage fluctuation amount applied to the variable resistor 140 and the diode 142 and the voltage fluctuation amount applied to the variable resistance 144 and the diode 146. The comparator 160 outputs a determination signal 162 based on the comparison result. Since the determination process in the comparator 160 is the same as that in the first embodiment, a description thereof will be omitted. The MOSFETs 164 and 166 and the signal line 168 are feedback circuits for providing the comparator 160 with hysteresis.

  In the third embodiment, the comparator 160 is configured to determine whether or not the time from the reference time to the evaluation time exceeds a predetermined time based on an amount related to the difference between the fluctuation amounts of the two partial pressure values. An example of the determination circuit has been described.

  FIG. 10 is a circuit diagram showing a determination circuit to which the current mirror circuit is applied. The variable resistor 170 and the diode 172 correspond to the first reference cell 44 in FIG. The variable resistor 174 and the diode 176 correspond to the second reference cell 46 in FIG. The MOSFET 178 and the resistor 186 correspond to the first control circuit 50 in FIG. The MOSFET 180 and the resistor 188 correspond to the second control circuit 52 of FIG. A voltage is applied between the power supplies E1 and E2. Between the power supplies E1 and E2, the variable resistor 170 and the diode 172, the MOSFET 178 and the resistor 186 are connected in series to constitute a voltage dividing circuit. Between the power supplies E1 and E2, the variable resistor 174 and the diode 176, the MOSFET 180 and the resistor 188 are connected in series to constitute a voltage dividing circuit. Between the power supplies E1 and E2, the variable resistor 170 and the diode 172, the MOSFET 178 and the resistor 186, and the variable resistor 174 and the diode 176, the MOSFET 180 and the resistor 188 are connected in parallel. MOSFETs 178 and 180 form a current mirror circuit. Due to the nature of the current mirror circuit, the same current flows through the variable resistor 170 and the diode 172, and the variable resistor 174 and the diode 176. Therefore, the comparator 182 can compare the amount of change in voltage applied to the variable resistor 170 and the diode 172 with the amount of change in voltage applied to the variable resistor 174 and the diode 176. Based on the comparison result, the comparator 182 outputs a determination signal 184. Since the determination process in the comparator 182 is the same as that in the first embodiment, a description thereof will be omitted. Since the input voltage of the comparator 182 depends on the current values flowing through the variable resistor 170 and the diode 172 and the variable resistor 174 and the diode 176, the resistance values of the resistors 186 and 188 can be automatically adjusted. For this reason, the compared result can be output at high speed. The MOSFETs 190 and 192 and the signal line 194 are feedback circuits for providing the comparator 182 with hysteresis.

  In the fourth embodiment, the comparator 182 is configured to determine whether or not the time from the reference time to the evaluation time exceeds a predetermined time based on an amount related to the difference between the fluctuation amounts of the two partial pressure values. An example of the determination circuit has been described.

  FIG. 11 is a circuit diagram showing a determination circuit in which two voltage dividing circuits in which a reference cell and a capacitor are connected in series between power sources are connected in parallel. The variable resistor 200 and the diode 202 correspond to the first reference cell 44 of FIG. The variable resistor 204 and the diode 206 correspond to the second reference cell 46 in FIG. The capacitor 208 corresponds to the first control circuit 50 in FIG. The capacitor 210 corresponds to the second control circuit 52 in FIG. A voltage is applied between the power supplies E1 and E2. Between the power supplies E1 and E2, the variable resistor 200, the diode 202, and the capacitor 208 are connected in series to form a voltage dividing circuit. Similarly, the variable resistor 204, the diode 206, and the capacitor 210 are connected in series between the power supplies E1 and E2 to form a voltage dividing circuit. Between the power supplies E1 and E2, the variable resistor 200 and the diode 202, and the variable resistor 204 and the diode 206 are connected in parallel. When the voltage E1 is increased, a current corresponding to the resistivity flows through the variable resistor 200 and the diode 202, and the variable resistor 204 and the diode 206. Due to this current, charges are accumulated in the capacitors 208 and 210, and the voltages of the capacitors 208 and 210 fluctuate in proportion to the amount of the charges. The comparator 212 can compare the amount of change in the voltage of the capacitor 208 with the amount of change in the voltage of the capacitor 210. The comparator 212 outputs a determination signal 214 based on the comparison result. Since the determination process in the comparator 212 is the same as that in the first embodiment, a description thereof will be omitted.

  In the fifth embodiment, the comparator 212 is configured to determine whether or not the time from the reference time to the evaluation time exceeds a predetermined time based on the amount related to the difference between the fluctuation amounts of the two partial pressure values. An example of the determination circuit has been described.

  In the determination circuit according to the fifth embodiment, a capacitor is used instead of a transistor in circuits corresponding to the first control circuit 50 and the second control circuit 52 in FIG. For this reason, there is little fluctuation and deterioration of the threshold due to a temperature change peculiar to the transistor, and a configuration resistant to disturbance can be obtained. The comparator 212 may have a feedback circuit for providing hysteresis therein.

  FIG. 12 is a circuit diagram showing a determination circuit using a voltage dividing circuit in which two reference cells are connected in series between power supplies. In the first to fifth embodiments, the first reference cell and the second reference cell are connected in parallel between the power supplies. However, in FIG. 12, the first reference cell and the second reference cell are connected between the power supplies. The example connected in series is shown. A voltage is applied between the power supplies E1 and E2. The variable resistor 220 and the diode 222 connected in series between the power supplies E1 and E2 correspond to the first reference cell. The variable resistor 224 and the diode 226 connected in series between the power supplies E1 and E2 correspond to the second reference cell. Between the power supplies E1 and E2, the variable resistor 220 and the diode 222, and the variable resistor 224 and the diode 226 are connected in series to form a voltage dividing circuit. Between the power supplies E1 and E2, the resistor 228 and the resistor 230 are connected in series to form a voltage dividing circuit. The resistance value of the variable resistor 220 and the resistance value of the variable resistor 224 are set to the same value. At this time, the voltage value of the connection point 232 between the variable resistor 220 and the diode 222 and the variable resistor 224 and the diode 226 is half of the voltage value applied between the power supplies E1 and E2. Since the resistance state of the variable resistor 220 and the diode 222 and the resistance state of the variable resistor 224 and the diode 226 change with time, the voltage value at the connection point 232 is a voltage applied between the power supplies E1 and E2. Fluctuates from half the value. On the other hand, the voltage value at the connection point 234 of the resistors 228 and 230 remains constant at half of the voltage value applied between the power sources E1 and E2, regardless of the passage of time. That is, the voltage dividing circuit including the resistor 228 and the resistor 230 outputs a reference voltage value that is a half of the voltage value applied between the power supplies E1 and E2. The comparator 236 can compare the amount of fluctuation of the voltage value at the connection point 232 with the amount of fluctuation of the reference voltage value. Since the currents flowing through the variable resistors 220 and 224 are always equal, the determination accuracy can be improved. Based on the comparison result, the comparator 236 outputs a determination signal 242. Since the determination process in the comparator 236 is the same as that in the first embodiment, a description thereof will be omitted. The resistor 238, the MOSFET 240, and the signal line 244 are a feedback circuit for providing the comparator 236 with hysteresis.

  In the sixth embodiment, an example of a control circuit that outputs a reference voltage including the resistor 228 and the resistor 230 has been described. In addition, an example of the determination circuit configured to include the comparator 236 for determination based on the amount related to the difference between the reference voltage value and the amount of change in the divided voltage value has been described.

  The circuits of the fourth to sixth embodiments can reduce the circuit area as compared with the circuit of the third embodiment.

  In the first to sixth embodiments, power may be supplied to the circuit corresponding to the reference cell only when the timer function is executed at least.

  Hereinafter, referring to FIG. 13 and FIG. 14, by using the timer function that reduces the variation in accuracy of the timer function, the erasing operation of data stored in the memory cell after a predetermined time has elapsed, and the memory cell An example of a semiconductor device that performs an operation of prohibiting reading of stored data will be described.

  FIG. 13 is a block diagram illustrating the configuration of the semiconductor device 250 according to the seventh embodiment.

  The timer circuit 252 corresponds to any one of the semiconductor devices having a timer function shown in the first to sixth embodiments, for example. Hereinafter, the timer circuit 252 is assumed to correspond to the semiconductor device 40 having the timer function shown in the first embodiment, and will be described using the reference numerals shown in FIG. The description overlapping with the first embodiment is omitted. When the timer circuit 252 determines that the predetermined time has elapsed, a determination signal 258 is input to the control circuit 260. The Vcc level determination circuit 254 corresponds to, for example, the activation signal generation circuit 64 of the first embodiment.

  The memory cell array 256 has a plurality of memory cells MC. In this description, the memory cell MC is a nonvolatile memory. In the memory cell array 256, a plurality of bit lines BL and word lines WL are provided in parallel. The bit line BL constitutes a bit line pair including a first bit line BLz and a second bit line BLx. The memory cell MC is provided in the intersection region of the bit line BL and the word line WL, and is connected to the word line WL and the bit line BL, respectively. As illustrated, the memory cell MC includes a first memory cell MCz connected to the first bit line BLz and a second memory cell MCx connected to the second bit line BLx. The first memory cells MCz and the second memory cells MCx are alternately provided every other word line WL.

  A row decoder 262 for selecting a row is connected to the word line WL, and a column decoder 264 for selecting a column is connected to the bit line BL, respectively, and a memory cell MC to be accessed is determined by a combination of a column and a row. Selected. An address signal 265 for selecting the memory cell MC is sent from the outside to the row decoder 262 and the column decoder 264 via the address buffer 266, respectively.

  The write circuit 268 supplies a high voltage for data writing applied to the memory cell MC at the time of data writing. The reset circuit 270 supplies a reference voltage Vref applied to the bit line BL at the time of data reading. The clamp circuit 272 supplies a clamp voltage Vclmp applied to the bit line BL at the time of data reading. The sense amplifier 274 reads and amplifies a signal from the memory cell MC. The sense amplifier driver 276 drives the sense amplifier 274 when reading data.

  The input / output circuit 278 exchanges data between the memory cell array 256 and the external input / output terminal 292. The selection register 280 stores information regarding the storage mode of the semiconductor device 250. The control circuit 260 selects the storage mode of the semiconductor device 250 based on the information regarding the storage mode stored in the selection register 280. The control circuit 260 controls the write circuit 268, the reset circuit 270, the clamp circuit 272, and the input / output circuit 278 in accordance with an external command signal 282. In addition, the control circuit 260 controls the column decoder 264, so that one bit to be applied with a voltage at the time of data writing or reading from the bit line pair including the first bit line BLz and the second bit line BLx. Select a line.

  A storage mode of the semiconductor device 250 according to the seventh embodiment will be described. The memory cell array 256 included in the semiconductor device 250 has three types of storage modes (NVM mode, RAM mode, and MID mode). The control circuit 260 selects one storage mode from the three types of storage modes. The non-volatile NVM mode has a long data retention time and is suitable for use in storing data for a long time when the semiconductor device 250 is powered off. The volatile RAM mode has a short access time and is suitable for high-speed data processing when the semiconductor device 250 is powered on. The MID mode, which is located between the NVM mode and the RAM mode, has a shorter access time than the NVM mode. The normal data retention time is about one day, but the data retention time can be extended by performing refresh. For this reason, for example, a system that refreshes data about once a day can be used substantially as a non-volatile memory, and is excellent as a memory because it has a shorter access time than the NVM mode.

  FIG. 14 is a flowchart of the erasing operation of data stored in the memory cell MC and the prohibiting operation of reading data stored in the memory cell MC performed by the control circuit 260 after a predetermined time has elapsed. The semiconductor device 250 is activated when the activation circuit 284 receives the MID mode signal. The activation circuit 284 sets the MID mode in the selection register. Based on the selection register 280, the control circuit 260 sets the storage mode of the memory cell array 256 to the MID mode. When the semiconductor device 250 is activated, the starter signal detection circuit 288 outputs a starter signal sttz. The starter signal sttz is input to the Vcc level determination circuit 254 (step S300). Vcc level determination circuit 254 outputs timer activation signal enz when the voltage value of voltage Vcc 290 reaches a predetermined value. The predetermined value is, for example, a voltage value that ensures normal operation of the first reference cell 44 and the second reference cell 46 included in the timer circuit 252. The timer circuit 252 is activated by the timer activation signal enz (step S302). The timer circuit 252 sets the resistance values of the first reference cell 44 and the second reference cell 46 so that the change rates of the resistance values of the first reference cell 44 and the second reference cell 46 are different from each other (step S304). The elapse determination of a predetermined time is started. The timer circuit 252 converts the resistance values of the first reference cell 44 and the second reference cell 46 into voltage values. The comparator 54 compares the voltage value of the first reference cell 44 with the voltage value of the second reference cell 46 (step S306). As a result of the comparison process in step S306, the timer circuit 252 confirms whether or not the amount related to the difference in the voltage value variation between the first reference cell 44 and the second reference cell 46 exceeds a predetermined value (step S308). ). The timer circuit 252 outputs the determination signal 258 when step S308 is YES (step S314). When step S308 is NO, the timer circuit 252 does not output the determination signal 258 (step S310), and permits reading of data stored in the memory cell MC of the memory cell array 256 (step S312). The processing from step S304 to step S312 is repeated until the timer circuit 252 outputs the determination signal 258.

  When the timer circuit 252 outputs the determination signal 258, the control circuit 260 checks whether or not the data stored in the memory cell MC is protected (step S316). If the data stored in the memory cell MC is not protected (NO in step S316), the control circuit 260 erases the data stored in the memory cell MC (step S318). Thereafter, the MID mode set in the memory cell array 256 is canceled (step S328), and the operation ends.

  When the data stored in the memory cell MC is protected (YES in step S316), the control circuit 260 invalidates the read operation of the data stored in the memory cell MC (step S320). The invalidation of the read operation means that the control circuit 260 can accept only a special command for canceling the invalidation of the read operation, for example, and cannot accept a normal command for performing the read operation. 260 becomes inactive.

  The control circuit 260 checks whether a special command for canceling the invalidation of the read operation is input (step S322). If the special command is input, the control circuit 260 cancels the invalidation of the read operation (step S324). The cancellation of invalidation of data reading is, for example, activating the control circuit 260.

  The control circuit 260 checks whether or not to cancel the MID mode (step S326), and when canceling the MID mode (YES in step S326), cancels the MID mode (step S328) and ends. When the MID mode is continued (NO in step S326), the process returns to step S304. The above is the operation of the semiconductor device 250 according to the seventh embodiment.

  In the seventh embodiment, the memory cell MC may be either a resistance change type memory cell or a phase change type memory cell. Resistance change memory cells and phase change memory cells do not have the concept of erasure. Therefore, when the memory cell MC is one of the resistance change type memory cell and the phase change type memory cell, instead of the operation of erasing the data stored in the memory cell array 256 having the memory cell MC in step S318, Invalid data may be written to the memory cells MC included in the memory cell array 256. For example, “0” or “1” may be written to all the memory cells MC included in the memory cell array 256.

  In the seventh embodiment, a memory cell MC that stores data and a control circuit 260 that is connected to the timer circuit 252 and performs an erasing operation of data stored in the memory cell MC based on the determination result of the timer circuit 252 are provided. An example of the configuration has been described. The memory cell MC that stores data and the control circuit 260 that is connected to the timer circuit 252 and performs an invalid data write operation to the memory cell MC based on the determination result of the timer circuit 252 are provided. An example was described. The memory cell MC that stores data, and the control circuit 260 that is connected to the timer circuit 252 and that prohibits the reading of data stored in the memory cell MC based on the determination result of the timer circuit 252. An example was described. According to these configurations, the timer circuit 252 that reduces the variation in accuracy of the timer function accurately determines that a predetermined time has elapsed, and the control circuit 260 performs an erasing operation of data stored in the memory cell MC. An invalid data write operation to the memory cell MC and a read prohibition operation of data stored in the memory cell MC can be performed. Therefore, there is an effect in improving the security of the semiconductor device having a variable resistance.

  In the seventh embodiment, the configuration of the reference cell included in the timer circuit 252 may be either a resistance change type memory cell or a phase change type memory cell.

  In the seventh embodiment, the configuration of the memory cell MC and the configuration of the reference cell included in the timer circuit 252 may be the same. Accordingly, the memory cell and the reference cell included in the timer circuit can be manufactured by the same manufacturing method, which is effective in reducing the cost.

  In the seventh embodiment, the control circuit 260 sets the storage mode of the memory cell array 256 to the MID mode in which the data holding time is about one day. However, the control circuit 260 may set to another storage mode.

  The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to such specific embodiments, and various modifications can be made within the scope of the gist of the present invention described in the claims.・ Change is possible

FIG. 1 is a diagram showing a configuration of a conventional semiconductor device. FIG. 2 is a graph showing a change in voltage value with respect to an evaluation time t of a reference cell of a conventional semiconductor device. FIG. 3 is a flowchart showing the operation of the timer function of the conventional semiconductor device. FIG. 4 is a diagram illustrating a configuration of the semiconductor device according to the first embodiment. FIG. 5 is a graph showing a change in voltage value with respect to the evaluation time t of the first reference cell and the second reference cell of the semiconductor device of Example 1. FIG. 6 is a flowchart showing the operation of the timer function of the semiconductor device of the first embodiment. FIG. 7 is a diagram illustrating a configuration of a reference cell according to the first embodiment. FIG. 8 is a diagram showing the configuration of the semiconductor device of the second embodiment. FIG. 9 is a diagram illustrating a circuit configuration of the third embodiment. FIG. 10 is a diagram illustrating a circuit configuration of the fourth embodiment. FIG. 11 is a diagram illustrating a circuit configuration of the fifth embodiment. FIG. 12 is a diagram illustrating a circuit configuration of the sixth embodiment. FIG. 13 is a diagram illustrating the configuration of the semiconductor device according to the seventh embodiment. FIG. 14 is a flowchart illustrating the operation of the semiconductor device according to the seventh embodiment.

Explanation of symbols

14 reference cell 16 determination circuit 18 control circuit 20 reference voltage generation circuit 22 comparator 24 power supply voltage 44 first reference cell 46 second reference cell 48 determination circuit 50 first control circuit 52 second control circuit 54 comparator 56 power supply voltage 58 Setting circuit 64 Activation signal generation circuit

Claims (12)

A first reference cell in which the rate of change of the resistance value that changes with time is the first rate of change;
A second reference cell having a second rate of change, which is different from the first rate of change, of the resistance value that changes with time;
Based on the amount related to the difference between the variation amount of the resistance value of the first reference cell from the reference time at the evaluation time and the variation amount of the resistance value of the second reference cell from the reference time at the evaluation time, A determination circuit for determining whether or not a time from the reference time to the evaluation time exceeds a predetermined time;
A semiconductor device comprising: The first reference cell and the second reference cell are a plurality of reference cells,
A first determination circuit having a plurality of the determination circuits;
Of the plurality of determination results determined by the first determination circuit, when the number of determination results exceeding the predetermined time exceeds a predetermined number, the time from the reference time to the evaluation time is set to the predetermined time. A second determination circuit for determining that it exceeds,
The semiconductor device according to claim 1, comprising:   The semiconductor device according to claim 1, wherein the first reference cell and the second reference cell are resistance change type memory cells.   3. The semiconductor device according to claim 1, wherein the first reference cell and the second reference cell are phase change type memory cells.   And a setting circuit configured to set resistance values of the first reference cell and the second reference cell so that the first change rate and the second change rate are different from each other. Item 5. The semiconductor device according to any one of Items 1 to 4. A first control circuit that is a control circuit that converts a fluctuation amount of the resistance value of the first reference cell into a fluctuation amount of a voltage value;
A second control circuit which is a control circuit for converting a fluctuation amount of the resistance value of the second reference cell into a fluctuation amount of a voltage value;
And a variation amount of a divided voltage value between the first reference cell and the first control circuit connected in series between power sources, and the second reference cell connected in series between the power sources A determination circuit configured to determine whether or not a time from the reference time to the evaluation time exceeds a predetermined time based on an amount related to a difference between the variation value of the partial pressure value with the second control circuit; Equipped,
The first reference cell and the first control circuit, and the second reference cell and the second control circuit are connected in parallel between the power supplies. 5. The semiconductor device according to claim 1. A control circuit that outputs a reference voltage, and the difference between the value of the reference voltage and the amount of variation in the divided voltage value between the first reference cell and the second reference cell connected in series between power sources 6. A determination circuit for determining whether or not a time from the reference time to the evaluation time exceeds a predetermined time based on an amount related to A semiconductor device according to 1.   Activation of inputting an activation signal to the determination circuit when a voltage value supplied to the semiconductor device reaches a value at which the first reference cell and the second reference cell operate normally 8. The semiconductor device according to claim 1, further comprising a signal generation circuit. A memory cell for storing data;
A control circuit connected to the determination circuit and performing an erasing operation of data stored in the memory cell based on a determination result of the determination circuit;
The semiconductor device according to claim 1, further comprising: A memory cell for storing data;
A control circuit connected to the determination circuit and performing an invalid data write operation on the memory cell based on a determination result of the determination circuit;
The semiconductor device according to claim 1, further comprising: A memory cell for storing data;
A control circuit that is connected to the determination circuit and prohibits a read operation of data stored in the memory cell based on a determination result of the determination circuit;
The semiconductor device according to claim 1, further comprising: A first reference cell having a first rate of change in resistance value that changes over time, and a first rate of change in resistance value that changes over time differ from the first rate of change. A control method of a semiconductor device comprising: a second reference cell having a rate of change of 2;
Based on the amount related to the difference between the variation amount of the resistance value of the first reference cell from the reference time at the evaluation time and the variation amount of the resistance value of the second reference cell from the reference time at the evaluation time, A method for controlling a semiconductor device, comprising: determining whether a time from the reference time to the evaluation time exceeds a predetermined time.

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