JP2010016706A - Voltage controlled oscillation circuit and voltage conversion circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a voltage conversion circuit and a voltage controlled oscillation circuit in which a control current can be allowed to flow even if a control voltage is lower than or equal to a gate threshold voltage with a simple circuit configuration without using any complicated constant current source. <P>SOLUTION: A voltage-to-voltage conversion circuit 101 includes an n-type MOS transistor N110 which receives a control voltage VIN at a gate terminal; an n-type MOS transistor N111 which receives a reference voltage VR at a gate terminal; a p-type MOS transistor P110 which connects a common drain terminal of the n-type MOS transistors N110 and N111 to a drain terminal and connects a source terminal to a high-potential power source VDD; and a resistor R100 connected between a common source terminal of the n-type MOS transistors N110 and N111 and a ground GND. The voltage-to-current conversion circuit 100 further includes a ring oscillator 201 to which an operating current corresponding to a generated control current flows and which is oscillated at a frequency corresponding to a current value; and a bias voltage generation circuit 301 that applies a reference voltage VR. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a voltage-controlled oscillation circuit that oscillates at a frequency corresponding to a control voltage, and a voltage conversion circuit that converts a control voltage into a control current, and in particular, a voltage mounted on a PLL (Phase Locked Loop) semiconductor integrated circuit. The present invention relates to a control type oscillation circuit and a voltage conversion circuit useful when applied to a semiconductor circuit.

  In a PLL semiconductor integrated circuit, a voltage control type in which an oscillation frequency is changed by changing a transmission delay time per inverter stage by changing an amount of current supplied to a ring oscillator in which an inverter is connected in an odd number of stages in a ring shape. An oscillator is used. Further, in order to change the amount of current supplied to the ring oscillator, a voltage-current conversion circuit that changes the current value according to the value of the control voltage is used.

  When the control voltage is low, the control current is not generated from the voltage-current conversion circuit and the frequency of the ring oscillator may become unstable. Therefore, as a method for stabilizing the frequency of the ring oscillator even when the control voltage is low, There is a voltage controlled oscillator described in Document 1. The voltage controlled oscillator described in Patent Document 1 steadily adds an offset current to the voltage-current conversion circuit.

  FIG. 7 is a circuit diagram of the voltage controlled oscillator described in Patent Document 1. In FIG.

  In FIG. 7, the voltage-controlled oscillator 1 includes a voltage-voltage conversion circuit 10, a ring oscillator 20, and an offset current generation circuit 50 that adds a constant current to the control current of the voltage-voltage conversion circuit 10. The

  The voltage-voltage conversion circuit 10 includes an n-type MOS transistor N11 and a p-type MOS transistor P11. The gate terminal of the n-type MOS transistor N11 is connected to the control input terminal 11, and the drain terminal of the n-type MOS transistor N11 is connected to the drain terminal of the p-type MOS transistor P11. The source terminal of the n-type MOS transistor N11 is connected to the ground GND. The gate terminal and the drain terminal of the p-type MOS transistor P11 are connected to the node 12 of the voltage-voltage conversion circuit 10, and the source terminal of the p-type MOS transistor P11 is connected to the power supply VDD.

  The ring oscillator 20 includes a first inverter 21 including an n-type MOS transistor N21 and a p-type MOS transistor P21, a second inverter 22 including an n-type MOS transistor N22 and a p-type MOS transistor P22, and an n-type MOS transistor N23. And a third inverter 23 composed of a p-type MOS transistor P23 are connected in an odd number of stages in a ring shape. The node 12 of the voltage-voltage conversion circuit 10 is connected to the gate terminals of the p-type MOS transistors P21, P22, P23, and the output VOUT of the third inverter 23 is the gate of the n-type MOS transistor N21 of the first inverter 21. Returned to the terminal.

  The offset current generation circuit 50 includes a current mirror circuit 53 including an n-type MOS transistor N51 and an n-type MOS transistor N52, and a constant current source 60 that supplies a constant current 65. The gate terminal and drain terminal of the n-type MOS transistor N51 are connected to the negative terminal of the constant current source 60 and the gate terminal of the n-type MOS transistor N52. The source terminal of the n-type MOS transistor N51 is connected to the ground GND. The positive terminal of the constant current source 60 is connected to the power supply VDD. The drain terminal of the n-type MOS transistor N52 is connected to the node 12 of the voltage-voltage conversion circuit 10.

  The n-type MOS transistor N52 of the offset current generation circuit 50 is connected in parallel with the n-type MOS transistor N11 of the voltage-voltage conversion circuit 10, and the n-type MOS transistor N11 converts the input control voltage into a control current.

  The constant current source 60 is a current source having no voltage dependency. The circuit configuration is complicated for the following reasons. Depending on the amount of current flowing through the current source, the potential of the high-potential side power supply VDD slightly varies. Therefore, a circuit for phase compensation by applying feedback and a starter circuit for starting the current source are required. A detailed circuit configuration will be described with reference to FIG.

  Whether the oscillation circuit is a latch type or a ring oscillator, the frequency changes depending on the current. Since the frequency varies when the current fluctuates, a highly accurate current source is required regardless of the type of the oscillation circuit.

  FIG. 8 is a circuit diagram showing a configuration of a constant current source 60 of the conventional voltage controlled oscillator 1.

  In FIG. 8, the constant current source 60 includes p-type MOS transistors P61 to P63, n-type MOS transistors N61 and N62, and a resistor R60. In FIG. 8, the starter circuit is omitted.

  The source of the p-type MOS transistor P61 is connected to the power supply VDD, the gate of the p-type MOS transistor P61 is connected to the gate of the p-type MOS transistor P62, and the drain of the p-type MOS transistor P61 is connected to the drain of the n-type MOS transistor N61. To do. The drain and gate of n-type MOS transistor N61 are connected to the gate of n-type MOS transistor N62. The source of the n-type MOS transistor N61 is connected to the ground GND.

  The source of the p-type MOS transistor P62 is connected to the power supply VDD, the gate and drain of the p-type MOS transistor P62 are connected to the drain of the n-type MOS transistor N62, and further connected to the gate of the p-type MOS transistor P63. The source of the n-type MOS transistor N62 is connected to the ground GND through the resistor R60. The source of the p-type MOS transistor P63 is connected to the power supply VDD. The drain of the p-type MOS transistor P63 is the output of the constant current source 60 that supplies the current I65, and is connected to the drain of the n-type MOS transistor N51 of the offset current generation circuit 50.

  The constant current source 60 is a band gap type current source that does not depend on temperature.

  In the above configuration, the p-type MOS transistor P61 and the p-type MOS transistor P62 constitute a first current mirror circuit, and the n-type MOS transistor N61 and the n-type MOS transistor N62 constitute a second current mirror circuit. The flowing current I is mirrored by the first and second current mirror circuits and becomes a constant current. A current that is equal to the gate-source voltage VGS of the p-type MOS transistors P61 and P62 and the gate-source voltage VGS of the n-type MOS transistors N61 and N62 plus the voltage drop of the resistor R60 is obtained. Will flow.

  This current is applied to the gate-source voltage VGS of the p-type MOS transistors P61 and P62, and further applied to the gate of the p-type MOS transistor P63. As a result, the same current that flows in the p-type MOS transistors P61 and P62 also flows to the p-type MOS transistor P63 side, which becomes a current I65. This current I65 is supplied as an output current IOUT65 that does not depend on the power supply voltage.

  According to the above configuration, the constant current source 60 can generate a constant current that does not depend on the power supply voltage as described in the conventional example. The constant current source 60 includes a p-type MOS transistor P63 having a gate terminal in common with the p-type MOS transistor P62, forms a current mirror, and supplies a constant current to the voltage-controlled oscillator. Further, although not shown, a starter circuit including a plurality of diodes and the like for use as a trigger is added thereto. As described above, the constant current source 60 has a considerably complicated configuration in order to make the current source independent of voltage.

  FIG. 9 is a diagram showing the oscillation frequency characteristic of the voltage controlled oscillator 1 of FIG. 7, and shows the oscillation frequency characteristic 21 with respect to the input control voltage.

  In FIG. 9, when a voltage equal to or higher than the gate threshold voltage of the n-type MOS transistor is not applied between the control input terminal 11 and the ground GND, the n-type MOS transistor N11 is cut off, and the voltage-current conversion operation is performed. The case of not performing is the characteristic 41. That is, in this cut-off state, the bias current corresponding to the control voltage VIN is not supplied to the p-type MOS transistor P11. However, since the bias current supplied from the constant current source 60 flows to the p-type MOS transistor P11 through the n-type MOS transistor N52 connected to the node 12, a bias voltage is generated at the node 12 by the constant current source 60. Therefore, as shown by the solid line 21 in FIG. 9, oscillation occurs at a constant frequency even below the gate threshold voltage.

When a voltage equal to or higher than the gate threshold voltage of the n-type MOS transistor is applied between the control input terminal 11 and the ground GND, the n-type MOS transistor N11 becomes conductive and the p-type MOS transistor P11 has a control voltage. A current obtained by adding a bias current corresponding to the voltage VIN and a bias current from the constant current source 60 flows. Therefore, as shown in FIG. 9, the characteristic 21 is obtained by adding the offset frequency due to the bias current generated in the constant current source 60 to the characteristic 41.
JP 2006-245860 A

  However, such a conventional voltage controlled oscillator has a problem that a constant current circuit having a complicated configuration is required.

  For example, in the voltage controlled oscillator 1 shown in FIG. 7, even if the control voltage VIN is equal to or lower than the threshold voltage of the n-type MOS transistor N11, the constant current source 60 is special in order to flow a control current independent of the power supply voltage VDD to the ring oscillator. Therefore, the entire circuit configuration of the voltage controlled oscillator is complicated.

  The present invention has been made in view of the above points, and is a voltage conversion circuit capable of flowing a control current even when the control voltage is equal to or lower than the gate threshold voltage with a simple circuit configuration without using a complicated constant current source. The purpose is to provide.

  Another object of the present invention is to provide a voltage-controlled oscillation circuit that can stably oscillate an oscillation circuit such as a ring oscillator by realizing this voltage conversion circuit.

  A voltage-controlled oscillator circuit according to the present invention is a voltage-controlled oscillator that oscillates at a frequency corresponding to a control voltage, a voltage converter circuit that converts the control voltage into a control current, and a reference voltage that is applied to the voltage converter circuit. A reference voltage generation circuit to be supplied; and an oscillation circuit that oscillates at a frequency according to a current value through which an operating current corresponding to the control current generated by the voltage conversion circuit is passed. A first MOS transistor that receives a voltage at a gate terminal; and a second MOS transistor that receives the reference voltage at a gate terminal. The first MOS transistor and the second MOS transistor include drain terminals and The source terminals are made common, and the control voltage is applied to the gate terminal of the first MOS transistor, and the second MOS transistor A differential circuit for applying the reference voltage to the gate terminal, a resistor is connected between the common source terminal of the first MOS transistor and the second MOS transistor and the first power supply; A configuration is adopted in which the sum of the drain current of one MOS transistor and the drain current of the second MOS transistor forms the control current.

  The voltage conversion circuit according to the present invention is a voltage conversion circuit for converting a control voltage into a control current, the first MOS transistor receiving the control voltage at the gate terminal, and the second MOS transistor receiving the reference voltage at the gate terminal. And the first MOS transistor and the second MOS transistor share drain terminals and source terminals in common, and apply the control voltage to the gate terminal of the first MOS transistor, A differential circuit for applying the reference voltage is formed at the gate terminal of the second MOS transistor, and a resistor is provided between the common source terminal of the first MOS transistor and the second MOS transistor and the first power supply. And the sum of the drain current of the first MOS transistor and the drain current of the second MOS transistor is A configuration to form a current.

  According to the present invention, the differential circuit composed of the first and second MOS transistors that receives the control voltage and the reference potential at the gate terminals, respectively, and the source side of the differential circuit to the first potential via the resistor R100. By connecting, it is possible to generate a control current independent of the value of the power supply voltage even when the control voltage VIN is equal to or lower than the gate threshold voltage without using a constant current circuit. Further, it is possible to realize a voltage controlled oscillation circuit that stably oscillates the ring oscillator from the control voltage VIN of 0V.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
FIG. 1 is a diagram showing a configuration of a voltage controlled oscillator circuit according to Embodiment 1 of the present invention. The present embodiment is an example applied to a voltage controlled oscillation circuit that includes a voltage conversion circuit and oscillates at a frequency corresponding to a control voltage.

  In FIG. 1, a voltage-controlled oscillation circuit 100 includes a voltage-voltage conversion circuit 101 that converts a control current IIN according to a control voltage VIN, and an operating current corresponding to the control current generated by the voltage-voltage conversion circuit 101. A ring oscillator 201 that oscillates at a frequency corresponding to a current value and a bias voltage generation circuit 301 that applies a reference voltage VR to the voltage-voltage conversion circuit 101 are configured.

  The voltage-voltage conversion circuit 101 is connected to a control input terminal 110 and receives an n-type MOS transistor N110 receiving a control voltage VIN at a gate terminal, an n-type MOS transistor N111 receiving a reference voltage VR at a gate terminal, and an n-type MOS transistor. A common drain terminal of N110 and MOS transistor N111 is connected to the drain terminal, a p-type MOS transistor P110 having a source terminal connected to the high-potential power supply VDD, and a common source terminal of n-type MOS transistor N110 and MOS transistor N111 and ground GND. And a resistor R100 connected to the.

  The gate terminal of the p-type MOS transistor P110 is connected to the ring oscillator 201 as the node 120 of the voltage-controlled oscillation circuit 100.

  The n-type MOS transistor N110 and the n-type MOS transistor N111 share the drain terminals and the source terminals, and apply the control voltage VIN from one control input terminal 110 to the gate terminal of the n-type MOS transistor N110. A differential circuit 115 is configured to apply a reference voltage VR from the other input terminal to the gate terminal of the n-type MOS transistor N111.

  A resistor R100 is connected to the common source terminal side of the n-type MOS transistor N110 and the MOS transistor N111, that is, the low potential side (source side) of the differential circuit 115. In general, a constant current source is installed on the low potential side of the differential circuit, and the differential circuit performs a differential amplification operation by passing a constant current through the constant current source. In the present embodiment, the configuration is different from that of the general differential circuit, and a resistor R100 is connected instead of the constant current source of the general differential circuit.

  A differential circuit 115 composed of an n-type MOS transistor N110 and an n-type MOS transistor N111 is connected to the ground GND through a resistor R100. By connecting the resistor R100, the n-type MOS transistor N110 or the n-type MOS transistor N111 can be turned on according to the control voltage VIN or the reference voltage VR to the gate terminal. Therefore, the current flowing through the resistor R100 changes according to the ON state of the n-type MOS transistor N110 and / or the n-type MOS transistor N111. In other words, the current flows through the resistor R100, so that the n-type MOS transistor N110 and / or the n-type MOS transistor N111 can be turned on at any time.

  Incidentally, when one transistor constituting the differential circuit 115 is OFF, the other transistor constitutes a source follower together with the resistor R100. For example, when the n-type MOS transistor N110 is OFF, the MOS transistor N111 forms a source follower by connecting the gate terminal to the reference voltage VR and the source terminal to the ground GND via the resistor R100. In this case, the MOS transistor N111 serves as a source follower through which a current flows by an amount determined by the source of VGS applied to the gate and the ground GND. Similarly, when the n-type MOS transistor N111 is OFF, the MOS transistor N110 forms a source follower by connecting the gate terminal to the reference voltage VIN and the source terminal to the ground GND via the resistor R100.

  From this relationship, the differential circuit 115 according to the present embodiment includes a pair of a source follower including the n-type MOS transistor N110 and the resistor R100 and a source follower including the n-type MOS transistor N111 and the resistor R100. It can be said that it is a combination.

  A control voltage VIN is applied to the gate terminal of the n-type MOS transistor N110. The resistor R100 is connected between the source terminals of the n-type MOS transistor N110 and the n-type MOS transistor N111 and the ground GND, and the drain terminals of the n-type MOS transistor N110 and the n-type MOS transistor N111 connected to each other. Thus, a control current IIN = IR + IM is generated.

  Specifically, the drain current IM flows through the drain terminal of the n-type MOS transistor N110. A drain current IR flows through the drain terminal of the n-type MOS transistor N111. A control current IIN obtained by adding the drain current IM and the drain current IR flows to the commonly connected drains of the n-type MOS transistor N110 and the n-type MOS transistor N111.

  This control current IIN is supplied as a mirror current to the ring oscillator 201 by a current mirror circuit 210 including a diode-connected p-type MOS transistor P110, a p-type MOS transistor P211, a p-type MOS transistor P212, and a p-type MOS transistor P213. Is done.

  The ring oscillator 201 includes a first inverter 211 composed of an n-type MOS transistor N211 and a p-type MOS transistor P211, a second inverter 212 composed of an n-type MOS transistor N212 and a p-type MOS transistor P212, and an n-type MOS transistor N213. And a third inverter 213 composed of a p-type MOS transistor P213 are connected in an odd number of stages in a ring shape. The node 120 of the voltage-voltage conversion circuit 101 is connected to the gate terminals of the p-type MOS transistors P211, P212, and P213, and the output VOUT of the third inverter 213 is the gate of the n-type MOS transistor N211 of the first inverter 211. Returned to the terminal.

  The p-type MOS transistor P110 of the voltage-voltage conversion circuit 101 and the p-type MOS transistors P211, P212, and P213 of the ring oscillator 201 constitute a current mirror circuit 210 having a gate terminal and a drain terminal connected in common.

  The bias voltage generation circuit 301 includes a resistor R301 connected between the high potential side power supply VDD and the ground GND, and an n-type MOS transistor N310. The n-type MOS transistor N310 connects the drain terminal and the gate terminal to form a forward diode, and a reference voltage VR is generated in the forward diode. The generated reference voltage VR is a gate-source voltage VGS generated in the forward diode-connected n-type MOS transistor N310. Since the VGS characteristic is substantially constant, the reference voltage VR hardly changes even when the voltage of the power supply VDD fluctuates and the flowing current IBASE changes. As described above, the bias voltage generation circuit 301 uses the gate-source voltage VGS generated in the n-type MOS transistor N310, so that the bias voltage generation circuit 301 has a simple configuration and is not affected by the voltage fluctuation of the power supply VDD. Can be generated.

  Hereinafter, the operation of the voltage controlled oscillation circuit 100 configured as described above will be described.

  As described above, the n-type MOS transistor N110 and the n-type MOS transistor N111 of the voltage-voltage conversion circuit 101 share the drain terminals and the source terminals, and control one of the gate terminals of the n-type MOS transistor N110. A differential circuit 115 is configured to apply the control voltage VIN from the input terminal 110 and apply the reference voltage VR from the other input terminal to the gate terminal of the n-type MOS transistor N111. A resistor R100 is connected to the common source terminal side of the n-type MOS transistor N110 and the MOS transistor N111, that is, the low potential side of the differential circuit 115.

  When the control voltage VIN is applied to the control input terminal 110, the drain current IM flows through the n-type MOS transistor N110 according to the magnitude of the control voltage VIN, and the control current IIN flows through the p-type MOS transistor P110 in response to the drain current IM. The p-type MOS transistor P110 of the voltage-voltage conversion circuit 101 and the p-type MOS transistors P211, P212, and P213 of the ring oscillator 201 have a current mirror configuration, and the same mirror current as the control current IIN is generated by the p-type MOS transistor P211, It flows to P212 and P213. The ring oscillator 201 oscillates at a frequency corresponding to the magnitude of the control current IIN by the mirror current, and outputs an oscillation output VOUT from the output terminal VO.

  On the other hand, the reference voltage VR generated in the bias voltage generation circuit 301 is the gate-source voltage VGS generated in the forward-diode-connected n-type MOS transistor N310. Even if it changes, the reference voltage VR hardly changes. Accordingly, a constant value is obtained for the reference voltage VR with respect to a change in the voltage of the power supply VDD.

  This reference voltage VR is applied to the gate terminal of the n-type MOS transistor N111 of the voltage-voltage conversion circuit 101. The reference voltage VR is used as the reference voltage VR of the differential circuit 115 including the n-type MOS transistor N110 and the n-type MOS transistor N111. The reference voltage VR is applied to the gate terminal of the n-type MOS transistor N111. ing. The n-type MOS transistor N111 receives a reference voltage VR having a constant potential at its gate and continues to be turned on until the control voltage VIN becomes equal to or higher than a predetermined voltage.

  When the control voltage VIN applied to the gate terminal of the n-type MOS transistor N110 is smaller than the reference voltage VR applied to the gate terminal of the n-type MOS transistor N111, the drain of the n-type MOS transistor N111 is near 0V. The current IR is almost zero. However, since the n-type MOS transistor N111 is ON, the drain current IR of the n-type MOS transistor N111 flows, and the control current IIN flows even below the threshold voltage of the n-type MOS transistor N110 due to the relationship of IIN = IR + IM. Even when the n-type MOS transistor N110 is equal to or lower than the threshold voltage, that is, when the n-type MOS transistor N110 is OFF, the control current IIN flows when the n-type MOS transistor N111 is ON, so that the ring oscillator 201 is stable. Then oscillates. This can be realized by the n-type MOS transistor N110 and the n-type MOS transistor N111 constituting the differential circuit 115, and the low potential side (source side) of the differential circuit 115 is connected to the ground GND via the resistor R100. This is because the connected configuration is adopted. In addition, a reference voltage VR that is generated based on the voltage VGS between the gate and the source of the n-type MOS transistor N310 and hardly dependent on the voltage fluctuation of the power supply VDD is applied to the gate terminal of the n-type MOS transistor N111. one of. The bias voltage generation circuit 301 that generates the reference voltage VR can be realized by an extremely simple configuration including the n-type MOS transistor N310 and the resistor R301. Not only is the configuration simple, but it is particularly excellent in that a constant current circuit having a complicated configuration as in the conventional example is not used.

  In addition, when the control voltage VIN increases and becomes equal to the reference voltage VR, the control current IIN of the current IR = IM in which the drain current IM of the n-type MOS transistor N110 and the drain current IR of the n-type MOS transistor N111 are balanced. Flows.

  Further, when the control voltage VIN increases beyond the reference voltage VR, the drain current IR of the n-type MOS transistor N111 becomes almost zero, and the n-type MOS transistor N111 is turned off. Then, the drain current IM of the n-type MOS transistor N110 flows dominantly.

  Thereafter, since the drain current IM of the n-type MOS transistor N110 becomes the control current IIN, the control current IIN increases according to the control voltage VIN from the relationship of IIN = IR + IM.

  Thus, this configuration has a specific effect that an offset current as in the conventional example can be automatically generated. According to this configuration, an effect of creating an offset current can be obtained. Further, in the conventional example, a complicated constant current circuit that is necessary in the offset current generation circuit is not required in the bias voltage generation circuit 301 of the present embodiment.

  Further, the bias voltage generation circuit 301 has an excellent effect in terms of cost that the reference voltage VR independent of the fluctuation of the power supply voltage VDD can be realized by one MOS transistor and a resistor.

  Next, the relationship between the control current IIN and the oscillation frequency of the ring oscillator 201 with respect to the control voltage VIN of the voltage controlled oscillation circuit 100 will be described with reference to a characteristic diagram.

  FIG. 2 is an oscillation frequency characteristic diagram showing the relationship between the control current IIN and the oscillation frequency of the ring oscillator 201 with respect to the control voltage VIN of the voltage controlled oscillation circuit 100.

  2A shows the relationship between the control voltage VIN applied to the gate of the n-type MOS transistor N110 and the control current IIN, and FIG. 2B shows the oscillation frequency of the ring oscillator 201 with respect to the control voltage VIN. Show.

  2A and 2B, the horizontal axis represents the control voltage VIN applied to the gate of the n-type MOS transistor N110. 2A, the drain current IM of the n-type MOS transistor N110, the drain current IR of the n-type MOS transistor N111, and the control current IIN (μA) which is the sum (IR + IM) are shown in FIG. The vertical axis of b) represents the oscillation frequency (Hz) of the ring oscillator 201 with respect to the control voltage VIN.

  As shown by the chain line in FIG. 2A, when the control voltage VIN is smaller than the reference voltage VR, the drain current IR of the n-type MOS transistor N111 is almost zero when the control voltage VIN is around 0V. Here, the n-type MOS transistor N111 forms a differential circuit 115 together with the n-type MOS transistor N110, and the source side of the differential circuit 115 is connected to the resistor R100, so that the n-type MOS transistor N111 is turned on. is doing. For this reason, the drain current IR flows, and the control current IIN flows even below the threshold voltage of the n-type MOS transistor N110 from the relationship of IIN = IR + IM. Note that the n-type MOS transistor N111 with the control voltage VIN near 0 V constitutes a source follower whose source terminal is connected to the ground GND via the resistor R100.

  As shown by the chain line in FIG. 2A, as the control voltage VIN increases, the drain current IM of the n-type MOS transistor N110 increases, and accordingly the drain current IR of the n-type MOS transistor N111. Will decrease. This is because the n-type MOS transistor N110 and the n-type MOS transistor N111 constitute the differential circuit 115, and the source side of the differential circuit 115 is connected to the resistor R100. The drain current IM of the n-type MOS transistor N110, the drain current IR of the n-type MOS transistor N111, and the control current IIN that is the sum (IR + IM) are substantially constant.

  As shown in FIG. 2A, when the control voltage VIN increases and becomes equal to the reference voltage VR, the drain current IM of the n-type MOS transistor N110 and the drain current IR of the n-type MOS transistor N111 are equal to IR. = IM (current in VR of FIG. 2A), and a control current IIN that is the sum (IR + IM) flows.

  Further, when the control voltage VIN increases beyond the reference voltage VR, the drain current IR of the n-type MOS transistor N111 becomes almost zero (see VS in FIG. 2A).

  Thereafter, the drain current IM of the n-type MOS transistor N110 becomes the control current IIN. Further, the drain current IR of the n-type MOS transistor N111 is almost zero. From the relationship of IIN = IR + IM, the control current IIN increases according to the control voltage VIN.

  As described above, as shown in FIG. 2A, according to this configuration, an offset current as in the conventional example is automatically generated, and therefore, the control current IIN flows from the control voltage VIN of 0V. Therefore, as shown in FIG. 2B, the ring oscillator 201 can stably oscillate from the control voltage VIN of 0V.

  As described above in detail, according to the present embodiment, the voltage-voltage conversion circuit 101 is connected to the control input terminal 110, receives the control voltage VIN at the gate terminal, the n-type MOS transistor N110, and the reference voltage VR. N-type MOS transistor N111 receiving the gate terminal, a p-type MOS transistor P110 connecting the common drain terminal of the n-type MOS transistor N110 and the MOS transistor N111 to the drain terminal, and connecting the source terminal to the high potential power supply VDD, n A resistor R100 connected between the common source terminal of the MOS transistor N110 and the MOS transistor N111 and the ground GND, and the drain current IM of the n-type first MOS transistor N110 and the drain current IR of the n-type MOS transistor N111. The sum is the control current IIN Since formation, without the use of complex constant current source 60 as shown in Figure 8 in the conventional example, the control voltage VIN with a simple circuit configuration can flow control current IIN even less gate threshold voltage. That is, the control current IIN independent of the value of the power supply voltage can be generated even when the control voltage VIN is equal to or lower than the gate threshold voltage without using a complicated and expensive constant current circuit.

  In the present embodiment, the voltage-voltage conversion circuit 101, the ring oscillator 201 that oscillates at a frequency corresponding to the current value through the operation current corresponding to the generated control current, and the bias that applies the reference voltage VR. By applying it to the voltage-current converter circuit 100 including the voltage generation circuit 301, the ring oscillator 201 can be stably oscillated even when the control voltage VIN is low. In particular, the ring oscillator 201 can stably oscillate from the control voltage VIN of 0 V with a circuit configuration that does not use a complicated constant current circuit.

  Further, the bias voltage generation circuit 301 generates a stable reference voltage VR that is not affected by voltage fluctuations of the power supply VDD while having a simple configuration by using the gate-source voltage VGS generated in the n-type MOS transistor N310. can do.

(Embodiment 2)
FIG. 3 is a diagram showing the configuration of the voltage controlled oscillator circuit according to the second embodiment of the present invention. The same components as those in FIG.

  In FIG. 3, the voltage-controlled oscillation circuit 400 includes a voltage-voltage conversion circuit 101 that converts a control current IIN according to the control voltage VIN, and an operating current corresponding to the control current generated by the voltage-voltage conversion circuit 101. A ring oscillator 201 that oscillates at a frequency corresponding to a current value and a bias voltage generation circuit 401 that applies a reference voltage VR to the voltage-voltage conversion circuit 101 is configured.

  A reference voltage VR is applied from the bias voltage generation circuit 401 to the gate of the n-type MOS transistor N111 of the voltage-voltage conversion circuit 101.

  The bias voltage generation circuit 401 includes a resistor R401 and a resistor R402 connected between the reference voltage source VREF and the ground GND.

  The reference voltage source VREF supplied to the bias voltage generation circuit 401 is a reference voltage that does not vary the power supply voltage. The reference voltage source VREF does not have this voltage fluctuation.

  Hereinafter, the operation of the voltage controlled oscillation circuit 400 configured as described above will be described. Since the basic operation is the same as that of the first embodiment, description thereof is omitted.

  In the bias voltage generation circuit 401, a resistor R401 and a resistor R402 are connected between a reference voltage source VREF and the ground GND, and a reference voltage VR divided by the resistor R401 and the resistor R402 is generated. For example, when a 0.7 V reference voltage VR corresponding to a forward diode voltage by the n-type MOS transistor N310 used in the first embodiment is created from a 1.2 V reference voltage source VREF, the resistor R401 and the resistor What is necessary is just to set the resistance ratio of R402 according to following Formula (1).

R401 / R402 = (1.2V−0.7V) /0.7V=0.714 (1)
When the reference voltage source VREF itself is 0.7 V, the reference voltage source VREF may be directly applied to the gate of the n-type MOS transistor N111 without being divided by the resistances of the resistor R401 and the resistor R402. .

  Further, the reference voltage VR is not limited to 0.7V, and may be a voltage equal to or higher than the threshold value of the n-type MOS transistor N111. The reference voltage VR can be determined by the amount of drain current IR of the n-type MOS transistor N111 that flows when the control voltage VIN is 0V. For example, when the resistance value of the resistor R100 is 2 kΩ and the threshold values VT of the n-type MOS transistor N110 and the n-type MOS transistor N111 are both 0.6 V, the drain current IR of the n-type MOS transistor N111 is 100 μA. The VR setting is as follows.

  That is, as for the reference voltage VR, when the control voltage VIN is 0V, the n-type MOS transistor N110 is OFF. Therefore, when the gate voltage of the n-type MOS transistor N111 is VG, the following equation (2) is established, and the equation (2) is established. The following equation (3) is obtained by deformation.

IR = (VG−VT) / R100 = (VR−VT) / R100 (2)
VR = IR / R100 + VT = 100 μA / 2 kΩ + 0.6 V = 0.65 V (3)
From the above equation (3), 0.65 V may be applied to the n-type MOS transistor N111.

  As described above, the reference voltage VR generated from the bias voltage generation circuit 401 is a voltage generated by dividing the resistance by the resistor R401 and the resistor R402 from the reference voltage source VREF where the voltage does not vary. For this reason, the reference voltage VR is constant regardless of the power supply VDD used in the voltage-voltage conversion circuit 101 and the ring oscillator 201.

  Further, the reference voltage VR generated by the bias voltage generation circuit 401 is input to the voltage-voltage conversion circuit 101 and applied to the gate of the n-type MOS transistor N111. The n-type MOS transistor N111 forms a differential circuit 115 together with the n-type MOS transistor N110, and is used as a reference voltage VR for the differential circuit 115. On the other hand, a control voltage VIN is applied to the gate of the n-type MOS transistor N110, and a resistor R100 is connected between the sources of the n-type MOS transistor N110 and the n-type MOS transistor N111 and the ground GND. Control current IIN = IR + IM is generated from the drains of n-type MOS transistor N110 and n-type MOS transistor N111 connected to each other.

  This control current IIN is supplied as a mirror current to the ring oscillator 201 by a current mirror circuit 210 including a diode-connected p-type MOS transistor P110 and the p-type MOS transistors P211, P212, and P213 of the ring oscillator 201. The ring oscillator 201 oscillates at a frequency corresponding to the magnitude of the control current IIN by the mirror current, and outputs an output VOUT from the output terminal VO.

  The relationship between the control current IIN and the oscillation frequency of the ring oscillator 201 with respect to the control voltage VIN of the voltage controlled oscillation circuit 400 is the same as that described in the first embodiment. For the same reason, the ring oscillator 201 of the voltage controlled oscillation circuit 400 can oscillate stably from the control voltage VIN of 0V.

  The reference voltage source VREF supplied to the bias voltage generation circuit 401 is a reference voltage that does not vary the power supply voltage. The power supply voltage of the power supply VDD may vary depending on the current flowing through the circuit. The reference voltage source VREF of the bias voltage generation circuit 401 of the second embodiment does not have this variation. Since the voltage is generated by resistance division by the resistor R401 and the resistor R402 from the reference voltage source VREF where the voltage does not vary, the power source used in the voltage-voltage conversion circuit 101 and the ring oscillator 201 Regardless of VDD, the reference voltage VR is constant.

  Therefore, the same effect as that of the first embodiment, that is, the voltage-voltage conversion circuit 101 has a control current that does not depend on the value of the power supply voltage even when the control voltage VIN is equal to or lower than the gate threshold voltage without using a constant current circuit. Can be generated. The voltage controlled oscillation circuit 400 including the voltage-voltage conversion circuit 101 can stably oscillate the ring oscillator 201 from the control voltage VIN of 0V.

(Embodiment 3)
FIG. 4 is a diagram showing the configuration of the voltage controlled oscillator circuit according to the third embodiment of the present invention. The same components as those in FIG.

  In FIG. 4, the voltage-controlled oscillation circuit 500 includes a voltage-voltage conversion circuit 101 that converts the control current IIN according to the control voltage VIN, and an operating current corresponding to the control current generated by the voltage-voltage conversion circuit 101. A ring oscillator 201 that oscillates at a frequency corresponding to a current value and a bias voltage generation circuit 501 that applies a reference voltage VR to the voltage-voltage conversion circuit 101 is configured.

  A reference voltage VR is applied from the bias voltage generation circuit 501 to the gate of the n-type MOS transistor N111 of the voltage-voltage conversion circuit 101.

  The bias voltage generation circuit 501 includes a reference voltage source 510 connected between the power supply VDD and the ground GND.

  Hereinafter, the operation of the voltage controlled oscillation circuit 500 configured as described above will be described. Since the basic operation is the same as that of the first embodiment, description thereof is omitted.

  The bias voltage generation circuit 501 outputs a reference voltage VR from a reference voltage source 510 connected between the power supply VDD and the ground GND. The reference voltage source 510 generates a reference voltage VR from the power supply VDD and the ground GND, and the resistor R301 and the n-type MOS between the power supply VDD and the ground GND as described with reference to FIG. 1 in the first embodiment. A method of generating a reference voltage VR by connecting a forward diode of the transistor N310 is also included.

  The reference voltage VR from the bias voltage generation circuit 501 is input to the voltage-voltage conversion circuit 101. The reference voltage VR generated by the bias voltage generation circuit 501 is input to the voltage-voltage conversion circuit 101, and the n-type MOS transistor N111. Is applied to the gate. The n-type MOS transistor N111 forms a differential circuit 115 together with the n-type MOS transistor N110, and is used as a reference voltage VR for the differential circuit 115. On the other hand, a control voltage VIN is applied to the gate of the n-type MOS transistor N110, and a resistor R100 is connected between the sources of the n-type MOS transistor N110 and the n-type MOS transistor N111 and the ground GND. Control current IIN = IR + IM is generated from the drains of n-type MOS transistor N110 and n-type MOS transistor N111 connected to each other.

  This control current IIN is supplied as a mirror current to the ring oscillator 201 by a current mirror circuit 210 including a diode-connected p-type MOS transistor P110 and the p-type MOS transistors P211, P212, and P213 of the ring oscillator 201. The ring oscillator 201 oscillates at a frequency corresponding to the magnitude of the control current IIN by the mirror current, and outputs an output VOUT from the output terminal VO.

  The relationship between the control current IIN and the oscillation frequency of the ring oscillator 201 with respect to the control voltage VIN of the voltage controlled oscillation circuit 500 is the same as that described in the first embodiment. For the same reason, the ring oscillator 201 of the voltage controlled oscillation circuit 500 can oscillate stably from the control voltage VIN of 0V.

(Embodiment 4)
The ring oscillator 201 used in the first to third embodiments may have any configuration.

  FIG. 5 is a circuit diagram showing the configuration of the ring oscillator of the voltage controlled oscillator circuit according to the fourth embodiment of the present invention. The ring oscillator 601 of the present embodiment may be used instead of the ring oscillator 201 of the first to third embodiments.

  In FIG. 5, the ring oscillator 601 includes a first inverter 611 including an n-type MOS transistor N211 and p-type MOS transistors P211 and P611, and a second inverter including an n-type MOS transistor N212 and p-type MOS transistors P212 and P612. 612, an n-type MOS transistor N213, and a third inverter 613 composed of p-type MOS transistors P213 and P613 are connected in an odd number of stages in a ring shape. The node 120 of the voltage-voltage conversion circuit 101 is connected to the gate terminals of the p-type MOS transistors P211, P212, P213, and the output VOUT of the third inverter 213 is the n-type MOS transistor N211 of the first inverter 611 and p It is fed back to the gate terminal of the type MOS transistor P611.

  In the ring oscillator 601 of FIG. 5, first to third inverters 611 to 613 are connected in three stages in a ring shape, and with respect to the sources of the p-type MOS transistor P611, the p-type MOS transistor P612, and the p-type MOS transistor P613, Each of the ring oscillators is supplied with an operating current from the drains of the p-type MOS transistor P211, the p-type MOS transistor P212, and the p-type MOS transistor P213, and the oscillation frequency changes depending on the magnitude of the operating current.

  Even if the ring oscillator 601 shown in FIG. 5 is used, the voltage controlled oscillation circuit according to the present invention can be realized.

(Embodiment 5)
Embodiments 1 to 4 are examples in which the voltage conversion circuit is applied to a voltage control type oscillation circuit. However, the voltage conversion circuit of the present invention is not limited to the voltage control type oscillation circuit, and does not use a constant current circuit. Any circuit that generates a control current that does not depend on the value of the power supply voltage can be applied.

  The fifth embodiment is an example in which the voltage conversion circuit of the present invention is applied to a level shift circuit.

  FIG. 6 is a diagram showing a configuration of a semiconductor circuit according to the fifth embodiment of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals, and description of overlapping portions is omitted.

  In FIG. 6, a semiconductor circuit 700 includes a voltage-voltage conversion circuit 101 that converts a control current IIN according to the control voltage VIN, and a level shift circuit 701 that level-shifts the control current IIN generated by the voltage-voltage conversion circuit 101. And a bias voltage generation circuit 301 for applying a reference voltage VR to the voltage-voltage conversion circuit 101.

  A reference voltage VR is applied from the bias voltage generation circuit 301 to the gate of the n-type MOS transistor N111 of the voltage-voltage conversion circuit 101.

  The semiconductor circuit 700 is used for an input / output circuit, for example.

  The voltage-voltage conversion circuit 101 changes the output voltage of the level shift circuit 701 by changing the potential difference generated from the power supply VDD by IIN × R301 depending on the magnitude of the generated control current IIN.

  The level shift circuit 701 includes a p-type MOS transistor P710, an n-type MOS transistor N710 connected in series to the p-type MOS transistor P710, and an n-type MOS transistor N711 commonly connected to the gate and drain of the n-type MOS transistor N710. The resistor R701 is connected between the power supply VDD and the n-type MOS transistor N711.

  The node 120 of the voltage-voltage conversion circuit 101 is connected to the gate terminal of the p-type MOS transistor P710 of the level shift circuit 701, and the p-type MOS transistor P110 of the voltage-voltage conversion circuit 101 and the p-type MOS transistor of the level shift circuit 701. P710 constitutes a current mirror circuit 720.

  In addition, the n-type MOS transistor N710 and the n-type MOS transistor N711 of the level shift circuit 701 constitute a current mirror circuit 730.

  Hereinafter, the operation of the semiconductor circuit 700 configured as described above will be described. The operations of the voltage-voltage conversion circuit 101 and the bias voltage generation circuit 301 are the same as those in the first embodiment.

  The control current IIN of the p-type MOS transistor P110 is mirrored to the n-type MOS transistor N710 by the current mirror circuit 720 configured by the p-type MOS transistor P110 of the voltage-voltage conversion circuit 101 and the p-type MOS transistor P710 of the level shift circuit 701. Supplied as current.

  Further, the control current IIN of the n-type MOS transistor N710 is supplied as a mirror current to the n-type MOS transistor N711 by the current mirror circuit 730 including the n-type MOS transistor N710 and the n-type MOS transistor N711 of the level shift circuit 701. . As a result, the control current IIN flows through the resistor R701, and a voltage lower than the power supply VDD by IIN × R701 is generated at the output terminal VOUT as shown in the following equation (4).

VOUT = VDD−IIN × R701 (4)
For example, assuming that the control voltage VIN = 0V as an initial state, a current of IIN = IR flows through the resistor R701, so that the initial voltage of VOUT of the level shift circuit 701 takes a maximum value, and the expression (4) to the following expression (5) It becomes.

VOUT = VDD−IIN × IR (5)
Next, when the control voltage VIN rises, the control current IIN increases, and the potential difference generated by IIN × IR increases, so the VOUT potential with respect to the ground GND decreases.

  Therefore, in the state where the control voltage VIN = 0V, variation in the voltage value of VOUT of the level shift circuit 701 occurs due to variations in absolute value in manufacturing the resistor R701, but as described above, when the control voltage VIN = 0V. VOUT is set higher than a desired potential, and the control voltage VIN is increased. As a result, VOUT is lowered to a desired potential and the control voltage VIN at that time is fixed. Thereby, the absolute value accuracy of VOUT finally obtained can be improved.

  Thus, according to the fifth embodiment, the semiconductor circuit 700 includes the voltage-voltage conversion circuit 101 and the level shift circuit 701 for level-shifting the control current IIN generated by the voltage-voltage conversion circuit 101. Therefore, the control current IIN independent of the value of the power supply voltage can be generated even when the control voltage VIN is equal to or lower than the gate threshold voltage including 0 V without using a complicated and expensive constant current circuit. As described above, by setting VOUT when the control voltage VIN = 0V to be higher than a desired potential and increasing the control voltage VIN, the absolute value accuracy of the finally obtained VOUT can be improved.

  The above description is an illustration of a preferred embodiment of the present invention, and the scope of the present invention is not limited to this. For example, the first to fourth embodiments described above are cases of a voltage-controlled oscillation circuit, and the fifth embodiment is an example of a semiconductor circuit including a level shift circuit, but a voltage conversion circuit that converts a control voltage into a control current. The same effect can be obtained also in the case of all semiconductor circuits including the above, and a PLL circuit using the same.

  In each of the above embodiments, the name of the voltage control type oscillation circuit is used. However, this is for convenience of explanation and includes a voltage control type oscillator, a semiconductor integrated circuit device, a voltage-current conversion circuit, a level conversion circuit, and the like. Of course, it may be.

  Further, the circuit units constituting the voltage conversion circuit and the voltage control type oscillation circuit, for example, the type, number and connection method of the ring oscillator are not limited to the above-described embodiments.

  Further, the type and polarity of the MOS transistor are not limited to those of the above embodiments. For example, in each circuit, the polarities of the n-type MOS transistor and the p-type MOS transistor may all be reversed (however, the power supply configuration is different).

  Further, the present invention can be applied not only to a MOS transistor configured on a normal silicon substrate but also to a semiconductor integrated circuit configured by a MOS transistor having an SOI (Silicon On Insulator) structure.

  For example, when an n-type MOS transistor and a p-type MOS transistor are formed on a silicon substrate having an SOI structure as well as a MOS transistor configured on a normal silicon substrate, there is an advantage that latch-up does not occur. Further, the present invention can also be implemented for a semiconductor integrated circuit in which all MOS transistors are formed on a silicon substrate having an SOI structure.

  The voltage controlled oscillation circuit and the voltage conversion circuit according to the present invention can be used as a voltage controlled oscillator used in a PLL semiconductor integrated circuit. Further, the present invention can be widely applied not only to a voltage controlled oscillator but also to various circuit elements of a semiconductor circuit such as a level shift circuit or an input / output circuit.

The figure which shows the structure of the voltage controlled oscillation circuit which concerns on Embodiment 1 of this invention. Oscillation frequency characteristic diagram showing the relationship between the control current and the oscillation frequency of the ring oscillator with respect to the control voltage of the voltage controlled oscillation circuit according to the first embodiment. The figure which shows the structure of the voltage controlled oscillation circuit which concerns on Embodiment 2 of this invention. The figure which shows the structure of the voltage controlled oscillation circuit which concerns on Embodiment 3 of this invention. Circuit diagram showing a configuration of a ring oscillator of a voltage controlled oscillation circuit according to a fourth embodiment of the present invention The figure which shows the structure of the semiconductor circuit which concerns on Embodiment 5 of this invention. Circuit diagram of conventional voltage controlled oscillator Circuit diagram showing the configuration of a constant current source of a conventional voltage controlled oscillator The figure which shows the characteristic of the oscillation frequency of the conventional voltage control type oscillator

Explanation of symbols

100, 400, 500 Voltage controlled oscillation circuit 101 Voltage-voltage conversion circuit 115 Differential circuit 120 Node 201, 601 Ring oscillator 210, 720, 730 Current mirror circuit 211, 611 First inverter 212, 612 Second inverter 213 , 613 Third inverter 301 Bias voltage generation circuit 510 Reference voltage source 700 Semiconductor circuit N110, N111, N211, N212, N213, N310, N710, N711 n-type MOS transistors P110, P211, P212, P213, P611, P612, P613 , P710 p-type MOS transistors R100, R301, R401, R402, R701 Resistors

Claims (16)

A voltage controlled oscillation circuit that oscillates at a frequency according to a control voltage,
A voltage conversion circuit for converting the control voltage into a control current;
A reference voltage generation circuit for supplying a reference voltage to the voltage conversion circuit;
An oscillation circuit that oscillates at a frequency corresponding to a current value through which an operating current corresponding to the control current generated by the voltage conversion circuit is passed;
The voltage conversion circuit includes:
A first MOS transistor receiving the control voltage at its gate terminal;
A second MOS transistor that receives the reference voltage at a gate terminal;
The first MOS transistor and the second MOS transistor share a drain terminal and a source terminal, apply the control voltage to the gate terminal of the first MOS transistor, and apply the control voltage to the second MOS transistor. Configure a differential circuit that applies the reference voltage to the gate terminal of the transistor,
A resistor is connected between the common source terminal of the first MOS transistor and the second MOS transistor and the first power supply,
A voltage controlled oscillation circuit, wherein a sum of a drain current of the first MOS transistor and a drain current of the second MOS transistor forms the control current. The first MOS transistor constitutes a source follower in which a source terminal of the first MOS transistor is connected to the first power supply via the resistor when the second MOS transistor is OFF,
The second MOS transistor constitutes a source follower in which a source terminal of the second MOS transistor is connected to the first power supply via the resistor when the first MOS transistor is OFF. 2. The voltage controlled oscillator circuit according to claim 1, wherein   2. The voltage controlled oscillation circuit according to claim 1, wherein the second MOS transistor is turned on to allow a drain current to flow even when the control voltage is smaller than the reference voltage.   2. The voltage controlled oscillation circuit according to claim 1, wherein the second MOS transistor is turned on by receiving the reference voltage at a gate terminal even when the control voltage is zero, and allows a drain current to flow. 3.   When the control voltage is smaller than the reference voltage, the sum of the drain current of the first MOS transistor and the drain current of the second MOS transistor forms an offset current for starting the oscillation circuit. The voltage controlled oscillator circuit according to claim 1. The reference voltage generation circuit includes a second power source, a second resistor connected in series to the first power source, and a forward MOS diode connected in series to the second resistor,
2. The voltage controlled oscillation circuit according to claim 1, wherein a potential at a connection point between the second resistor and the forward MOS diode is output as the reference voltage. The reference voltage generation circuit includes a third plurality of resistors connected between a second reference voltage and the first power source,
2. The voltage according to claim 1, wherein a potential obtained by dividing an arbitrary voltage between the second reference voltage and the first power supply by the third plurality of resistors and outputting the divided voltage is output as the reference voltage. Control type oscillation circuit.   7. The voltage controlled oscillator circuit according to claim 6, wherein the first power source is a ground voltage, and the second power source is a high potential side power source.   8. The voltage controlled oscillator circuit according to claim 7, wherein the reference voltage is the second reference voltage.   2. The voltage controlled oscillation circuit according to claim 1, wherein the oscillation circuit is a ring oscillator including an odd number of logic gates. A voltage conversion circuit for converting a control voltage into a control current,
A first MOS transistor receiving the control voltage at its gate terminal;
A second MOS transistor that receives a reference voltage at its gate terminal;
The first MOS transistor and the second MOS transistor share a drain terminal and a source terminal, and apply the control voltage to the gate terminal of the first MOS transistor, so that the second MOS transistor Configure a differential circuit that applies the reference voltage to the gate terminal of the transistor,
A resistor is connected between the common source terminal of the first MOS transistor and the second MOS transistor and the first power supply,
The voltage conversion circuit according to claim 1, wherein a sum of a drain current of the first MOS transistor and a drain current of the second MOS transistor forms the control current. The first MOS transistor constitutes a source follower in which a source terminal of the first MOS transistor is connected to the first power supply via the resistor when the second MOS transistor is OFF,
The second MOS transistor constitutes a source follower in which a source terminal of the second MOS transistor is connected to the first power supply via the resistor when the first MOS transistor is OFF. The voltage conversion circuit according to claim 11, wherein:   12. The voltage conversion circuit according to claim 11, wherein the second MOS transistor is turned on to allow a drain current to flow even when the control voltage is smaller than the reference voltage.   12. The voltage conversion circuit according to claim 11, wherein the second MOS transistor is turned on by receiving the reference voltage at a gate terminal even when the control voltage is zero, and causes the drain current to flow. A reference voltage generating circuit for supplying the reference voltage;
The reference voltage generation circuit includes a second power source, a second resistor connected in series to the first power source, and a forward MOS diode connected in series to the second resistor,
12. The voltage conversion circuit according to claim 11, wherein a potential at a connection point between the second resistor and the forward MOS diode is output as the reference voltage. A reference voltage generating circuit for supplying the reference voltage;
The reference voltage generation circuit includes a third plurality of resistors connected between a second reference voltage and the first power source,
12. The voltage according to claim 11, wherein a potential obtained by dividing an arbitrary voltage between the second reference voltage and the first power source by the third plurality of resistors and outputting the divided voltage is output as the reference voltage. Conversion circuit.

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