JP2010016316A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the malfunction of a semiconductor device and to simplify its manufacturing process. <P>SOLUTION: The semiconductor device includes a semiconductor substrate 1, a pair of impurity-diffused layers 2A, 2B formed in the semiconductor device 1, a gate-insulating layer 3 formed on the semiconductor substrate between the impurity-diffused layers 2A, 2B, a gate electrode 4 formed on the gate-insulating layer 3, and two contacts 5A, 5B each formed on a pair of impurity-diffused layers 2A, 2B. The gate electrode 4 and two contacts 5A, 5B are formed of the same material. The upper end of the gate electrode 4 is as high as the upper ends of the contacts 5A, 5B from the surface of the semiconductor substrate 1. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a structure of a gate electrode and a contact of a field effect transistor. The present invention also relates to a method for manufacturing the field effect transistor.

Semiconductor integrated circuits such as logic circuits and nonvolatile semiconductor memories (for example, flash memories) are mounted on various electronic devices.
A field effect transistor (FET) is used as one of constituent elements of a semiconductor integrated circuit. A MOSFET (hereinafter MOSFET) having a MOS (Metal-Oxide-Semiconductor) structure has a structure in which a gate electrode is provided on a gate insulating film formed on the surface of a semiconductor substrate. The gate electrode is covered with an interlayer insulating film deposited on the semiconductor substrate. A step is generated between the upper end of the gate electrode and the surface of the semiconductor substrate, and in order to eliminate the step, a planarization process is performed on the upper surface of the interlayer insulating film by a CMP (Chemical Mechanical Polishing) method (for example, Patent Documents). 1).

  The flatness of the planarization treatment by the CMP method depends on the coverage of the wiring pattern (for example, the gate electrode pattern) on the semiconductor substrate surface, and the flatness of the upper surface of the interlayer insulating film cannot be maintained in a portion where the wiring pattern is small. Thinning and dishing occur. This causes a wiring defect such as a short circuit between the wirings due to a residue of the wiring material or a disconnection of the wiring.

  Further, due to the step between the upper end of the gate electrode and the surface of the semiconductor substrate (source / drain diffusion layer), contact holes having different depths must be formed in the contact formation process, and the etching conditions become complicated. In order to avoid this, it is necessary to form the contact hole / contact in separate steps for the gate electrode and the source / drain diffusion layer, which increases the number of manufacturing steps.

  In a manufacturing process of a semiconductor device, a method of forming a source / drain diffusion layer using a gate electrode material as a mask after forming a gate insulating film is used. This diffusion layer has an LDD (Lightly doped drain) structure in order to suppress the short channel effect. The source / drain diffusion layer of the LDD structure has a role of reducing the Schottky phenomenon between the silicide compound and the high concentration well in the semiconductor substrate, and is therefore doped with impurities. In order to bond the doped impurities and the constituent atoms of the semiconductor substrate, a high temperature annealing treatment at 700 to 1100 ° C. is required.

When a high dielectric material is used for the gate insulating film, the characteristics of the gate insulating film are changed by this high temperature heating process, so that the driving characteristics of the MOSFET are deteriorated.
JP-A-9-82925

  The present invention proposes a technique capable of preventing malfunction of a semiconductor device and simplifying a manufacturing process of the semiconductor device.

  A semiconductor device according to an example of the present invention includes a semiconductor substrate, a pair of impurity diffusion layers provided in the semiconductor substrate, a gate insulating film provided on a surface of the semiconductor substrate between the pair of impurity diffusion layers, and the gate A gate electrode provided on the insulating film; and a contact provided on each of the pair of impurity diffusion layers, wherein the gate electrode and the contact are made of the same material, and the gate electrode upper end and the contact upper end Are provided with the same height from the surface of the semiconductor substrate.

  A method of manufacturing a semiconductor device according to an example of the present invention includes a step of forming two impurity diffusion layers in a semiconductor substrate, a step of forming a gate insulating film on the surface of the semiconductor substrate, and an opening in the gate insulating film. And exposing the surfaces of the two impurity diffusion layers, forming a conductive layer on the gate insulating film and on the two impurity diffusion layers, and separating the conductive layers, Forming a gate electrode on the gate insulating film between two impurity diffusion layers, and forming a pair of contacts on the two impurity diffusion layers.

  According to the example of the present invention, malfunction of the semiconductor device can be prevented, and the manufacturing process of the semiconductor device can be simplified.

  Hereinafter, some embodiments for carrying out examples of the present invention will be described in detail with reference to the drawings.

1. Embodiment
[1] Basic example
(A) Structure
The structure of the semiconductor device according to the embodiment of the present invention will be described with reference to FIG.

  FIG. 1 shows the structure of the semiconductor device according to this embodiment. The semiconductor device according to this embodiment is a MOSFET. 1A shows the planar structure of the MOSFET of the present embodiment, FIG. 1B shows a cross-sectional structure along the line AA of the planar structure, and FIG. 1C shows the planar structure. The cross-sectional structure which follows the BB line of is shown. The cross section along the line AA is a cross sectional view along the xx direction, which corresponds to the channel length direction of the MOSFET. The cross section along the line BB is a cross sectional view along the yy direction, which corresponds to the channel width direction of the MOSFET.

  As shown in FIG. 1, the MOSFET is formed in an active region surrounded by an element isolation region STI (Shallow Trench Isolation) in the semiconductor substrate 1. The active region is provided in a well region (not shown) formed in the semiconductor substrate 1. An element isolation insulating film 10 is embedded in the element isolation region STI.

  In the active region (semiconductor substrate 1), two impurity diffusion layers 2A and 2B functioning as source / drain regions of the MOSFET are provided. Hereinafter, the two impurity diffusion layers 2A and 2B are referred to as source / drain diffusion layers 2A and 2B.

  The active region between the two source / drain diffusion layers 2A and 2B becomes a channel region. A gate insulating film 3 is provided on the surface of the semiconductor substrate 1 in the channel region. The gate insulating film 3 is, for example, a high dielectric insulating film made of an oxide or oxynitride containing at least one of hafnium (Hf), aluminum (Al), lanthanum (La), tantalum (Ta), and the like. It is. However, the insulating film is not limited to the high dielectric insulating film, and another insulating film such as a silicon oxide film or a silicon nitride film may be used for the gate insulating film 3.

  A gate electrode 4 is provided on the gate insulating film 3. The gate electrode 4 is composed of a silicide layer, for example. The silicide layer to be the gate electrode is a compound of at least one metal and silicon among nickel (Ni), cobalt (Co), titanium (Ti), tungsten (W), molybdenum (Mo), and the like. The size of the gate electrode 4 in the x direction (channel length direction) is, for example, smaller than the size of the gate insulating film 3 in the x direction (channel length direction).

  The first contacts 5A and 5B are formed so as to sandwich the gate electrode 4. The first contacts 5A and 5B are provided in direct contact with the two source / drain diffusion layers 2A and 2B through the openings formed in the gate insulating film 3, respectively. The first contacts 5 </ b> A and 5 </ b> B are formed simultaneously with the gate electrode 4 and are made of the same material as the gate electrode 4. For this reason, the first contacts 5A and 5B are composed of, for example, a silicide layer.

  The upper ends of the contacts 5A and 5B and the upper end of the gate electrode 4 are substantially the same in height from the surface of the semiconductor substrate 1.

  Openings in the gate insulating film 3 for contacting the first contacts 5A, 5B and the source / drain diffusion layers 2A, 2B are provided so as not to contact the end portions of the element isolation insulating film 10. According to this, since the first contacts 5A and 5B are not in contact with the element isolation insulating film 10, the junction leakage at the end of the element isolation insulating film 10 is reduced, and the operating characteristics of the MOSFET are improved.

  The gate electrode 4 and the first contacts 5A and 5B may be made of the same conductive material, and are not limited to silicide. For example, they may be polycrystalline silicon doped with impurities at a high concentration, or may be a metal material.

  The first contacts 5A, 5B and the source / drain diffusion layers 2A, 2B are electrically connected via, for example, impurity layers 6A, 6B provided in the source / drain diffusion layers 2A, 2B. The impurity layers 6A, 6B contain the same impurities as the impurities contained in the first contacts 5A, 5B. When the first contacts 5A, 5B are silicide layers, the impurity layers 6A, 6B are also Ni, Co, Ti , W, Mo and the like. When the semiconductor substrate 1 is a silicon substrate, the surface of the semiconductor substrate 1 is salicided, and the impurity layers 6A and 6B are also silicide layers.

  The impurity concentration of the impurity layers (first regions) 6A and 6B is higher than the impurity concentration of the regions (second regions) other than the impurity layers 6A and 6B in the source / drain diffusion layers 2A and 2B. Therefore, the resistivity of the impurity layers 6A and 6B is lower than the resistivity of the source / drain diffusion layers 2A and 2B, and the contact resistance between the first contacts 5A and 5B and the source / drain diffusion layers 2A and 2B. Can be reduced. Thus, the source / drain diffusion layers 2A and 2B have a so-called LDD structure having a region with a high impurity concentration (impurity layers 6A and 6B) and a region with a low impurity concentration surrounding the region.

The first contacts 5A and 5B and the gate electrode 4 are covered with, for example, the insulating film 11. The insulating film 11 is embedded between the contacts 5A and 5B and the gate electrode 4.
The second contacts CPA, CPB, CPC are provided on the first contacts 5A, 5B and the gate electrode 4, respectively, and are electrically connected thereto. The second contacts CPA, CPB, CPC are embedded in the insulating film 11 and the interlayer insulating films 12, 13 (for example, silicon oxide) that cover the first contacts 5A, 5B and the gate electrode 4. The second contacts CPA, CPB, CPC are made of any one of metal materials such as Mo, W, Al, and copper (Cu), for example. The second contacts CPA, CPB, CPC are connected to wiring layers MLA, MLB, MLC (for example, Al or Cu) provided in the interlayer insulating film 13.
The second contacts CPA, CPB, and CPC are connected to the gate electrode 4 and the first contact through a barrier metal (for example, titanium nitride (TiN)) formed in the contact hole in the interlayer insulating films 12 and 13. It may be connected to 5A and 5B. Further, here, an example in which one second contact CPA, CPB, CPC is provided for one first contact 5A, 5B and one gate electrode 4 is illustrated. However, the present invention is not limited to this, and a plurality of second contacts CPA, CPB, CPC may be provided for one first contact 5A, 5B and one gate electrode 4.

  Thus, in the MIS transistor MOSFET of this embodiment, the contacts 5A and 5B using silicide and the metal material are used between the wiring layers MLA and MLB and the source / drain diffusion layers 2A and 2B. The contacts CPA and CPB are provided. When the layer in which the first contacts 5A and 5B are provided and the layer in which the second contacts CPA and CPB are provided are different wiring layers, the first contacts 5A and 5B and the gate electrode 4 are provided in the same wiring layer. The second contacts CPA and CPB have a multilayer wiring structure provided in a layer above the first contacts 5A and 5B.

The MOSFET according to the embodiment of the present invention is characterized in that the contacts (first contacts) 5A and 5B contacting the gate electrode 4 and the source / drain diffusion layers are made of the same material. As in this embodiment, the gate electrode 4 and the contacts 5A and 5B made of the same material are provided in the same wiring layer and are formed in the same process.
Further, in the gate electrode 4 and the contacts 5A and 5B of the present embodiment, the height from the surface of the semiconductor substrate 1 at the upper end of the gate electrode 4 and the surface of the semiconductor substrate 1 at the upper end of the contacts 5A and 5B provided on the source / drain diffusion layers. The heights are almost the same. That is, in the MOSFET of this embodiment, the step between the upper end of the gate electrode 4 and the upper ends of the contacts 5A and 5B is reduced.

  As described above, since the wiring pattern (contacts 5A and 5B) is provided on the source / drain diffusion layer, the coverage in the active region is improved and the steps on the upper surfaces of the interlayer insulating films 12 and 13 are reduced. . Therefore, even if the interlayer insulating films 12 and 13 are planarized by the CMP method, dishing and thinning do not occur in the insulating films 12 and 13 above the source / drain diffusion layers 2A and 2B and the gate electrode 4. As a result, the residue of the wiring material and the excessive grinding of the wiring material can be suppressed, and wiring defects such as a short circuit between wires and disconnection can be prevented.

  In addition, since the upper end of the gate electrode 4 and the upper ends of the first contacts 5A and 5B from the surface of the semiconductor substrate 1 coincide with each other, the second contacts CPA, CPB and CPC contacting the gate electrode 4 and the first contacts 5A and 5B, respectively. Can be formed simultaneously. That is, since the contact hole has the same dimension in the depth direction, it is easy to control the processing, and the contact hole reaching the surface of the gate electrode 4 and the first contacts 5A and 5B can be formed simultaneously under the same etching conditions. Thus, the second contacts CPA, CPB, CPC can be simultaneously formed in the contact hole (interlayer insulating film). According to this, it is possible to prevent the number of manufacturing steps of the semiconductor device from increasing.

  In addition, according to the MOSFET manufacturing process described later, the gate insulating film 3 is formed after high-temperature annealing for activating the impurities of the source / drain diffusion layers 2A and 2B. Therefore, in particular, damage due to high-temperature heat treatment can be avoided for the gate insulating film 3 when a high dielectric insulating film is used, and the change in characteristics of the gate insulating film can be suppressed.

  Therefore, the MOSFET according to the embodiment of the present invention can prevent the malfunction of the semiconductor device. Further, the MOSFET according to the embodiment of the present invention can simplify the manufacturing process of the semiconductor device.

(B) Manufacturing method
A method for manufacturing the MOSFET shown in FIG. 1 will be described below with reference to FIGS. 2 to 7 show process drawings of the AA cross section and the BB cross section of FIG. 1, respectively.

  First, as shown in FIG. 2, a sacrificial oxide film 20 that is a barrier material for impurity doping is formed on the surface of the semiconductor substrate 1. A resist is applied on the sacrificial oxide film 20, and the resist is patterned using a photolithography technique so that a portion where the source / drain diffusion layer of the MOSFET is formed is opened. It is formed. Then, using the resist mask 30 as a mask, the source / drain diffusion layers 2A and 2B are formed by ion implantation, for example. After the formation of the source / drain diffusion layers 2A and 2B, the semiconductor substrate is subjected to high temperature annealing at 700 ° C. to 1000 ° C., and the impurities contained in the formed diffusion layers are activated. In addition to the source / drain diffusion layers 2A and 2B, impurity regions (shown) serving as a well region and a channel region are formed in the semiconductor substrate 1. Impurities contained in these impurity regions are also activated by high temperature annealing.

Next, after removing the resist mask and the sacrificial oxide film, as shown in FIG. 3, an element isolation insulating film 10 is buried in the semiconductor substrate 1 to form an element isolation region and an active region. Then, the gate insulating film 3 is formed on the semiconductor substrate 1. The gate insulating film 3 is a high dielectric insulating film, for example, and is formed using a CVD (Chemical Vapor Deposition) method. The high dielectric insulating film is made of an oxide or oxynitride containing at least one of hafnium (Hf), aluminum (Al), tantalum (Ta), lanthanum (La), and the like. However, the gate insulating film 3 is not limited to a high dielectric insulating film, and may be, for example, a silicon oxide film formed using a thermal oxidation method, or another insulating film such as a nitride film.
As described above, in the manufacturing method of this embodiment, the activation of impurities contained in the well region, the channel region, and the source / drain diffusion layer is performed before the gate insulating film forming step. Therefore, damage to the formed gate insulating film 3 due to high temperature heating can be prevented. Therefore, changes in the characteristics of the gate insulating film can be prevented.

  Then, as shown in FIG. 4, a resist mask 32 is formed on the gate insulating film 3. The resist mask 32 is patterned so that an opening Q is formed above the surface of the source / drain diffusion layers 2A and 2B. Using the resist mask 32 as a mask, the gate insulating film 3 is etched by RIE (Reactive Ion Etching). As a result, an opening Q is formed in the gate insulating film 3, and the surfaces of the source / drain diffusion layers 2A and 2B are exposed.

  Subsequently, as shown in FIG. 5, a conductive layer is formed on the gate insulating film 3 and the diffusion layers 2A and 2B by using, for example, a CVD method. A resist mask 34 is formed on the conductive layer, the conductive layer is etched using the resist mask 34 as a mask, and the conductive layer is separated. As a result, conductive layers 40A and 40B in contact with the source / drain diffusion layers 2A and 2B, respectively, and a conductive layer 40C provided above the channel region are formed. The conductive layers 40A, 40B, and 40C are made of, for example, polysilicon.

After the resist mask 34 is removed, as shown in FIG. 6, a metal material 42 is formed using, for example, a sputtering method so as to cover the surfaces of the conductive layers 40A, 40B, and 40C. The metal material 42 is, for example, any one of Ni, Co, Ti, W, and Mo.
Then, heat treatment (for example, 500 ° C. to 600 ° C.) for silicidation is performed on the entire semiconductor substrate 1, and the conductive layers (polysilicon) 40A, 40B, 40C and the metal material 42 undergo a solid phase reaction.

  Then, as shown in FIG. 7, silicide layers 4, 5A, 5B are formed. The silicide layer 4 on the gate insulating film 3 becomes the gate electrode 4. The silicide layers 5A and 5B become the first contacts 5A and 5B with the source / drain diffusion layers 2A and 2B.

  Thus, the gate electrode 4 and the first contacts 5A and 5B are formed simultaneously. For this reason, the gate electrode 4 and the first contacts 5A and 5B are made of the same material and are provided in the same wiring layer. Further, the heights of the upper end of the gate electrode 4 and the upper ends of the first contacts 5A and 5B from the surface of the semiconductor substrate 1 substantially coincide. However, the gate insulating film 3 is interposed between the gate electrode 4 and the semiconductor substrate 1. The thickness of the gate insulating film 3 (for example, 3 to 10 nm) is very thin compared to the thickness of the gate insulating film 4 and the contacts 5A and 5B. For this reason, the level | step difference resulting from the film thickness of the gate insulating film 3 is very small.

  Further, the metal atoms of the metal material are diffused into the diffusion layers 2A and 2B (semiconductor substrate 1) through the first contacts (silicides) 5A and 5B by the heat treatment. As a result, the metal atoms and the constituent atoms of the semiconductor substrate 1 undergo a solid phase reaction, and impurity layers 6A and 6B are formed in the diffusion layers 2A and 2B. When the semiconductor substrate 1 is a silicon substrate, the source / drain diffusion layer surface is salicided (Self-align silicide), and the impurity layers 6A and 6B are made of silicide. The impurity concentration of the impurity layers 6A and 6B is higher than the impurity concentration of the diffusion layers 2A and 2B. Since the first contacts 5A and 5B are connected to the diffusion layers 2A and 2B via the impurity layers 6A and 6B having a high impurity concentration, that is, a low resistivity, the contact resistance between the contact-source / drain diffusion layers is reduced. Can be reduced.

  Although the example in which the gate electrode 4 and the first contacts 5A and 5B are silicide layers has been described here, these may be formed of the same material and in the same process, for example, high impurity concentration silicon. . In this case, the impurity layers 6 </ b> A and 6 </ b> B are formed by diffusing impurities contained in the high impurity concentration silicon serving as gate electrodes and contacts into the diffusion layers 2 </ b> A and 2 </ b> B by heat treatment.

  After the gate electrode 4 and the contacts 5A and 5B are formed, the metal film that has not reacted with silicon is removed. An insulating film 11 is formed so as to cover the surfaces of the gate electrode 4 and the contacts 5A and 5B, and a gap between the gate electrode 4 and the contacts 5A and 5B is filled with the insulating film 11. Further, the interlayer insulating film 12 is formed on the insulating film 11 by, for example, the CVD method. The upper end of the interlayer insulating film 12 is planarized to a height that matches the upper end of the insulating film 11 by using, for example, a CMP (Chemical Mechanical Polishing) method. At this time, the contacts 5A and 5B are provided on the source / drain diffusion layers 2A and 2B, and the heights of the upper end of the gate electrode 1 and the upper end of the first contact from the surface of the semiconductor substrate 1 coincide with each other. Dishing and thinning do not occur on the top surfaces of 11 and 12.

  Thereafter, as shown in FIG. 1, an interlayer insulating film 13 is formed on the insulating film 11 and the interlayer insulating film 12. A plurality of contact holes are formed in the insulating film 11 and the interlayer insulating film 13 so as to contact the gate electrode 4 and the contacts 5A and 5B. Since these contact holes are at a height at which the upper end of the gate electrode 4 and the upper ends of the first contacts 5A and 5B coincide, the dimensions in the depth direction of these contact holes are the same, and the processing (etching) control is controlled. It is easy and a plurality of contact holes can be formed simultaneously under the same etching conditions.

When the first contacts 5A and 5B are not provided on the source / drain diffusion layers 2A and 2B, a step corresponding to the thickness of the gate electrode 4 is formed between the upper end of the gate electrode 4 and the upper ends of the source / drain diffusion layers 2A and 2B. Occurs. Therefore, since the depths of the contact holes are different, the contact holes must be formed in different processes under different etching conditions.
On the other hand, the MOSFET manufacturing method of this embodiment can simultaneously form the contact holes as described above. Therefore, according to this embodiment, a manufacturing process can be reduced. Since the upper end of the interlayer insulating film 12 is flat, it is not necessary to perform the planarization process on the upper surface of the interlayer insulating film 13.

  Second contacts CPA, CPB, CPC (for example, W, Mo, Al, or Cu) are embedded in the formed contact holes. Then, a metal material (for example, Al, Cu) is deposited in the interlayer insulating film 13 by, for example, a sputtering method, and wiring layers MLA, MLB, MLC are formed. These wiring layers MLA, MLB, MLC are connected to contacts 5A, 5B (source / drain diffusion layers 2A, 2B) and gate electrode 4 through second contacts CPA, CPB, CPC, respectively. Note that the second contact CPA, CPB, CPC may be formed after a barrier metal such as TiN is formed in the contact hole.

  The MOSFET according to this embodiment is completed through the above steps.

  In the MOSFET manufacturing method according to the embodiment of the present invention, the contacts 5A and 5B that are in contact with the gate electrode 4 and the source / drain diffusion layers 2A and 2B are simultaneously formed, are made of the same material, and are provided in the same wiring layer.

  Since the contact portions 5A and 5B whose upper ends are substantially coincident with the height of the upper end of the gate electrode 4 are provided on the source / drain diffusion layers 2A and 2B, the insulating films 11, 12, and 13 above the gate electrode 4 are provided. Even when the planarization process is performed by the CMP method, dishing or thinning does not occur in the insulating films 11, 12, 13 above the source / drain diffusion layers 2A, 2B and the gate electrode 4. As a result, in the dishing and thinning portions, it is possible to prevent the occurrence of a short circuit between the wirings due to the wiring material residue and the disconnection due to the excessive polishing of the wiring material.

  Further, the high-temperature annealing treatment for activating the impurities contained in the source / drain diffusion layers 2A and 2B, the channel region, and the well region is performed before the gate insulating film 3 is formed. Therefore, particularly when the gate insulating film 3 is composed of a high dielectric insulating film, impurities (boron (B) and phosphorus (P)) contained in the semiconductor substrate 1 are diffused in the gate insulating film 3, It is possible to suppress changes in characteristics of the gate insulating film 3 and the channel region by diffusing metal atoms (for example, Hf) included in the gate insulating film 3 into the semiconductor substrate 1. Therefore, according to the MOSFET manufacturing method of the present embodiment, it is possible to prevent malfunction of the semiconductor device.

  Further, the opening Q formed in the gate insulating film 3 is formed before the gate electrode or the interlayer insulating film is deposited on the semiconductor substrate. In this case, since the dimension in the depth direction is small, the influence of the aspect ratio is reduced, and the size of the opening Q can be increased. As a result, the contact area between the source / drain diffusion layers 2A and 2B and the contact can be increased, and the on-current characteristics of the MOSFET can be improved. In addition, since the opening Q is formed when no other member is formed, the degree of freedom of the layout of the opening, that is, the layout of the contact is improved, and the circuit design is facilitated.

  In addition, as described above, in the MOSFET manufacturing method according to the present embodiment, the upper ends of the gate electrodes 4 and the upper ends of the first contacts 5A and 5B contacting the source / drain diffusion layers 2A and 2B are from the surface of the semiconductor substrate. It is formed with almost the same height. According to this, the dimension in the depth direction of the contact hole formed for the gate electrode 4 and the contacts 5A and 5B is the same. That is, since the contact hole can be formed simultaneously under the same conditions, the contact CPC connected to the gate electrode 4 and the second contacts CPA and CPB connected to the first contacts 5A and 5B can be formed simultaneously. This can contribute to facilitating the processing control of the semiconductor device and reducing the manufacturing process.

  As described above, the method for manufacturing a semiconductor device (MOSFET) according to the embodiment of the present invention can provide a semiconductor device that can prevent malfunction.

  Moreover, the manufacturing method of the semiconductor device (MOSFET) according to the embodiment of the present invention can simplify the manufacturing process of the semiconductor device.

[2] Structure example
Hereinafter, a structural example of the MOSFET according to the present embodiment will be described with reference to FIGS. The same members as those in the basic example MOSFET shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

(1) First structure example
The MOSFET of the first structure example will be described with reference to FIG. FIGS. 8A and 8B respectively show views corresponding to an AA cross section (x direction cross section) and a BB cross section (y direction cross section) of the MOSFET.

  The MOSFET of this example shown in FIG. 8 has an insulating film 8 having a lower dielectric constant than the interlayer insulating films 12 and 13 (hereinafter referred to as a low dielectric constant insulating film) between the gate electrode 4 and the first contacts 5A and 5B. Is provided. When the interlayer insulating films 12 and 13 are, for example, silicon oxide films, the low dielectric constant insulating film 8 is, for example, silicon oxide containing fluorine (F) or carbon (C), an organic insulator, or silicon nitride. It is composed of a film.

  As shown in FIG. 8, by providing the low dielectric constant insulating film 8 between the gate electrode 4 and the first contacts 5A and 5B, which are configured by the same material and in the same process and have the same height at the upper end, The parasitic capacitance between the gate and the contact is reduced, and the RC delay can be suppressed.

  Therefore, by providing the insulating film 8 having a dielectric constant lower than that of the interlayer insulating film between the gate electrode 4 and the first contacts 5A and 5B, the operation of the MOSFET can be improved. Therefore, even in the MOSFET shown in the first structure example, malfunction can be suppressed.

(2) Second structure example
The MOSFET of the second structure example will be described with reference to FIG. FIGS. 9A and 9B show views corresponding to the AA cross section (x direction cross section) and the BB cross section (y direction cross section) of the MOSFET.

  The MOSFET of this example shown in FIG. 9 is formed of the same material and the same process, and an air gap 9 is provided between the gate electrode 4 and the first contacts 5A and 5B whose upper ends are coincident with each other. ing. That is, the space between the gate and the contact is filled with a vacuum.

  For example, when the film thickness Tox of the gate insulating film is 3 to 10 nm, the distance between the gate electrode 4 and the first contacts 5A and 5B is approximately the same as the film thickness Tox, that is, about 3 to 10 nm. The normal operation of the MOSFET can be ensured.

  For example, in the film formation technique such as the CVD method, when the interval between adjacent members is reduced, a film is hardly formed in the gap. Therefore, in the MOSFET having the structure shown in FIG. 9, if the distance between the gate electrode 4 and the first contacts 5A and 5B is about the thickness Tox (for example, 3 to 10 nm) of the gate insulating film, the gap between the gate and the contact In addition, the insulating film is not embedded. Therefore, the air gap 9 can be formed by forming the insulating film 11 and the interlayer insulating films 12 and 13 after separating the gate electrode and the contact with an interval about the film thickness Tox of the gate insulating film.

  The dielectric constant of the air gap 9, that is, the vacuum is smaller than the dielectric constant of the oxide film or the nitride film. Therefore, the MOSFET in which the air gap 9 is provided between the contact and the gate can further reduce the parasitic capacitance between the gate and the contact. Further, by providing the air gap 9, it is possible to avoid drain-gate interference. Furthermore, by providing the air gap 9, electron traps such as HCI (Highly Charge Ion) can be reduced.

  Therefore, as shown in FIG. 9, the operation of the MOSFET can be improved by providing the air gap 9 between the gate electrode 4 and the first contacts 5A and 5B. Therefore, also in the MOSFET shown in the second structure example, the malfunction of the semiconductor device can be suppressed.

[3] Application examples
The MOSFET according to the embodiment of the present invention is used in, for example, a semiconductor memory.

  For example, in the flash memory 100, as shown in FIG. 10, a driver 120 that controls a word line, a sense amplifier circuit 130 that detects stored data, and a memory chip 100 are disposed around a memory cell array 110 that stores data. Peripheral circuits such as a control circuit 140 for controlling the overall operation are included.

In a NAND flash memory as an example of the flash memory 100, the memory cell array 110 includes a plurality of NAND cell units. One NAND cell unit is composed of a plurality of memory cells (referred to as NAND strings) connected in series, and select transistors provided at one end and the other end thereof.
In the peripheral circuits 120, 130, and 140, the MOSFET according to the present embodiment is used as the peripheral transistor PeriTr.
Hereinafter, application examples of the MOSFET according to the embodiment of the present invention will be described by taking a NAND flash memory as an example.

(A) Structure
The structure of a NAND flash memory as an application example of the MOSFET according to the embodiment of the present invention will be described with reference to FIGS.

  FIG. 11 shows a cross-sectional structure of the memory cell array 110, and shows a cross-sectional structure in the x direction (channel length direction) of one NAND cell unit.

  The memory cell MC is, for example, a stacked gate structure MOS transistor that accumulates charges in a floating gate electrode. Gate insulating film 70 (tunnel insulating film) of memory cell MC is provided on the surface of semiconductor substrate 1 (channel region) between two source / drain diffusion layers 71. A floating gate electrode (for example, a polysilicon film) 72 is provided on the gate insulating film 70. The control gate electrode (for example, silicide layer) 74 is provided on the floating gate electrode 74 through an inter-gate insulating film (for example, ONO film or high dielectric insulating film) 73.

  In the NAND flash memory, a plurality of memory cells MC having the same structure are connected in series while sharing the source / drain diffusion layer 71 to form one NAND string.

  Select transistors STD and STS are provided at one end and the other end of the NAND string, thereby forming one NAND cell unit. The select transistors STD and STS are connected to the NAND string by sharing the source / drain diffusion layer 71 with the memory cell MC adjacent in the x direction.

  Since the select transistors STD and STS are formed simultaneously with the memory cell MC, the select transistors STD and STS have a structure approximate to that of the memory cell. The gate structure of the selection transistor is that an opening is formed in the inter-gate insulating film 73A of the selection transistors STD and STS, and the lower gate electrode 72A and the upper gate electrode 7B are in direct contact via this opening. This is different from the gate structure of the memory cell MC. The lower gate electrode 72A is formed simultaneously with the floating gate electrode, and the upper gate electrode 74A is formed simultaneously with the control gate electrode 74.

  In the select transistor STD on the drain side of the memory cells (NAND strings) connected in series, the drain diffusion layer 71D is connected to the bit line BL via the contact CPD. Further, in the selection transistor STS on the source side of the memory cells connected in series, the source diffusion layer 71S is connected to the source line SL via the contact CPS.

  In this application example, the MOSFET according to the embodiment of the present invention used as the peripheral transistor PeriTr is formed simultaneously with, for example, the memory cell MC and the selection transistors STD and STS.

  Therefore, as shown in FIG. 12, the gate structure of the peripheral transistor PeriTr is a stack gate structure, and the gate electrode 4 of the peripheral transistor passes through the opening in the inter-gate insulating film 73B, like the select transistors STD and STS. Thus, the lower gate electrode 72B and the upper gate electrode 74B are connected.

  Even in this case, in the peripheral transistor PeriTr of the application example of this embodiment, the gate electrode 4 and the contacts 5A and 5B are made of the same material and are provided in the same wiring layer. The heights of the upper end of the gate electrode 4 and the upper ends of the contacts 5A and 5B from the surface of the semiconductor substrate 1 are substantially the same.

  As a result, the same effect as the MOSFET of the present embodiment described above can be obtained.

  Therefore, the MOSFET (peripheral transistor) according to the application example of the embodiment of the present invention can prevent the malfunction of the semiconductor device and can simplify the manufacturing process of the semiconductor device.

(B) Manufacturing method
A method for manufacturing a MOSFET (peripheral transistor) according to an application example of the embodiment of the present invention will be described with reference to FIGS. Here, only the manufacturing process of the peripheral transistor of this application example is shown, and the manufacturing process of the memory cell and the selection transistor is not shown. The steps substantially the same as those in FIGS. 2 to 7 will be described with reference to those drawings.

  First, as shown in FIG. 13, the source / drain diffusion layer 2 </ b> A of the peripheral transistor is formed in the semiconductor substrate 1 by the same process as that shown in FIGS. 2 and 3. At this time, the surface of the semiconductor substrate in the memory cell array is covered with, for example, a resist. Subsequently, an element isolation insulating film 10 is formed in the element isolation region. Thus, an active region (hereinafter referred to as a peripheral transistor formation region) where peripheral transistors are formed is partitioned, and at the same time, the memory cell array and the peripheral circuit region are separated by an element isolation region (insulating film). Then, a gate insulating film (for example, a high dielectric insulating film) 3 is formed on the surface of the semiconductor substrate 1 in the peripheral transistor formation region.

  Further, after the gate insulating film of the memory cell and the select transistor is formed on the surface of the semiconductor substrate 1 in the memory cell array in a step different from the gate insulating film forming step of the peripheral transistor, the gate insulating film and the gate of the peripheral transistor are formed. A conductive material 72 (for example, polysilicon) to be a floating gate electrode is formed on the insulating film. On this conductive material 72, an insulating material 73 (for example, ONO or a high dielectric insulator) to be an inter-gate insulating film is deposited.

  Then, as shown in FIG. 14, an opening is formed in the insulating material 73 by using the photolithography technique and the RIE method in the gate electrode formation scheduled region and the contact formation scheduled region in the peripheral transistor formation region. At this time, an opening is formed in the insulating material to be an inter-gate insulating film also in the select transistor formation scheduled region.

  Subsequently, the conductive material 72 and the insulating film 3 in the contact formation scheduled region are selectively removed by the RIE method. Thereafter, the conductive material is formed in direct contact with the source / drain diffusion layers 2A and 2B. In the memory cell array, this conductive material is formed on an insulating material that becomes an inter-gate insulating film.

Then, the conductive material, the insulating film 73, and the conductive material 72 are processed so as to have a predetermined shape by using the photolithography technique and the RIE method. As a result, in the peripheral transistor formation region, the stacked bodies 40C and 72 serving as gate electrodes are formed on the gate insulating film 3 (above the channel region), and the first contact is formed on the source / drain diffusion layers 2A and 2B. Conductive layers 40A and 40B are formed. Thereafter, a metal material 42 (for example, Ni) is deposited on the surfaces of the conductive layers 40A and 40B and the stacked bodies 40C and 72.
Note that the step of separating the conductive material into the stacked bodies 40C and 72 and the conductive layers 40A and 40B may be performed simultaneously with the gate processing of the memory cell and the selection transistor in the memory cell array, or the peripheral transistor forming region and the memory cell array. And may be performed in different steps.

  In the memory cell array, after gate processing, source / drain diffusion layers of memory cells and select transistors are formed.

  Thereafter, in a step corresponding to the steps shown in FIGS. 7 and 8, the conductive layers 40A and 40B and the stacked bodies 40C and 72 are subjected to silicide treatment, and as shown in FIG. The peripheral electrode gate electrode 4 and the first contacts 5A and 5B are formed in the same wiring layer. In this silicidation process, the control gate electrode of the memory cell may be subjected to the silicidation process at the same time.

  Then, the interlayer insulating film and the wiring are formed, and the peripheral transistor PeriTr and the flash memory having the peripheral transistor of the application example of the present embodiment are completed.

  As described above, the peripheral transistor PeriTr as an application example of the present embodiment is formed using a process common to the memory cell array.

  Also in this application example, the tops of the first contacts 5A, 5B and the tops of the gate electrodes 4 that are in contact with the source / drain diffusion layers 2A, 2B of the peripheral transistors have substantially the same height from the surface of the semiconductor substrate 1. Therefore, when flattening treatment by CMP is performed, dishing and thinning on the upper surface of the interlayer insulating film can be suppressed, and residue of wiring material and disconnection of wiring can be suppressed.

  In addition, since the contact hole / contact can be formed simultaneously with respect to the gate electrode 4 of the peripheral transistor and the first contacts 5A and 5B, the number of manufacturing steps of the semiconductor device can be reduced. In this case, since the depth dimension of the contact hole is the same, it is easy to control the processing of the contact hole.

  Therefore, in the application example of the embodiment of the present invention, it is possible to provide a peripheral transistor of a semiconductor memory (for example, a flash memory) that can prevent a malfunction of the semiconductor device and can simplify the manufacturing process of the semiconductor device.

2. Other
The semiconductor device according to the embodiment of the present invention can prevent malfunction of the semiconductor device and can simplify the manufacturing process of the semiconductor device.

  In the embodiment of the present invention, a NAND flash memory has been described as an example of application of the MOSFET of the example of the present invention. However, the MOSFET of the example of the present invention is not used only in the NAND flash memory, but is a volatile semiconductor memory such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory), or MRAM (Magnetoresistive Random Access). The present invention may be applied to a semiconductor memory or a logic circuit (semiconductor integrated circuit) using a resistance change element such as a memory), a ReRAM (Resistive Random Access Memory), or a PRAM (Phase change Random Access Memory). Even when applied to these semiconductor memories and semiconductor integrated circuits, it is needless to say that the same effect as the example of the present invention can be obtained.

  The example of the present invention is not limited to the above-described embodiment, and can be embodied by modifying each component without departing from the gist thereof. Various inventions can be configured by appropriately combining a plurality of constituent elements disclosed in the above-described embodiments. For example, some constituent elements may be deleted from all the constituent elements disclosed in the above-described embodiments, or constituent elements of different embodiments may be appropriately combined.

The figure which shows the structure of MOSFET which concerns on embodiment of this invention. The figure which shows 1 process of the manufacturing process of MOSFET which concerns on embodiment of this invention. The figure which shows 1 process of the manufacturing process of MOSFET which concerns on embodiment of this invention. The figure which shows 1 process of the manufacturing process of MOSFET which concerns on embodiment of this invention. The figure which shows 1 process of the manufacturing process of MOSFET which concerns on embodiment of this invention. The figure which shows 1 process of the manufacturing process of MOSFET which concerns on embodiment of this invention. The figure which shows 1 process of the manufacturing process of MOSFET which concerns on embodiment of this invention. The figure which shows the structure of MOSFET which concerns on embodiment of this invention. The figure which shows the structure of MOSFET which concerns on embodiment of this invention. The figure for demonstrating the example of application of embodiment of this invention. The figure for demonstrating the example of application of embodiment of this invention. The figure which shows the structure of MOSFET of the example of application of embodiment of this invention. The figure which shows 1 process of the manufacturing process of the example of application of embodiment of this invention. The figure which shows 1 process of the manufacturing process of the example of application of embodiment of this invention.

Explanation of symbols

  1: semiconductor substrate, 2A, 2B: source / drain diffusion layer, 3: gate insulating film, 4: gate electrode, 5A, 5B: first contact, 6A, 6B: impurity layer, 8: low dielectric insulating film, 9 : Air gap, 10, 11: insulating film, 12, 13: interlayer insulating film, 70: gate insulating film (tunnel insulating film), 71: source / drain diffusion layer, 72, 72A, 72B: floating gate electrode (lower gate) Electrode), 73, 73A, 73B: inter-gate insulating film, 74, 74A, 74B: control gate electrode (upper gate electrode), MC: memory cell, STD, STS: selection transistor, PeriTr: peripheral transistor, 100: flash memory .

Claims (5)

A semiconductor substrate;
A pair of impurity diffusion layers provided in the semiconductor substrate;
A gate insulating film provided on the semiconductor substrate between the pair of impurity diffusion layers;
A gate electrode provided on the gate insulating film;
Contacts provided respectively on the pair of impurity diffusion layers;
Comprising
The gate electrode and the contact are made of the same material, and the upper end of the gate electrode and the upper end of the contact have the same height from the surface of the semiconductor substrate.   The pair of impurity diffusion layers are in contact with the contact, and include a first region having a predetermined impurity concentration, and a second region surrounding the first region and having an impurity concentration lower than the predetermined impurity concentration. The semiconductor device according to claim 1, comprising: An interlayer insulating film provided on the contact and on the gate electrode;
An insulating film provided between the contact and the gate electrode, having a lower dielectric constant than the interlayer insulating film;
The semiconductor device according to claim 1, further comprising:   The semiconductor device according to claim 1, wherein an air gap is provided between the contact and the gate electrode. Forming two impurity diffusion layers in the semiconductor substrate;
Forming a gate insulating film on the semiconductor substrate surface;
Forming an opening in the gate insulating film and exposing the surfaces of the two impurity diffusion layers;
Forming a conductive layer on the gate insulating film and the two impurity diffusion layers;
Separating the conductive layer, forming a gate electrode on the gate insulating film between the two impurity diffusion layers, and forming a pair of contacts on the two impurity diffusion layers;
A method for manufacturing a semiconductor device, comprising:

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