JP2010010349A - Nonvolatile semiconductor storage device, and manufacturing method of the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device with a memory cell having an appropriate threshold voltage regardless of use of a metal material of high process matching property for a control gate electrode, and to provide a manufacturing method thereof. <P>SOLUTION: The device includes a semiconductor substrate 1, source and drain regions 4a, 4b disposed on the semiconductor substrate apart from each other, a first insulating film 12 formed on a part serving as a channel region 6 between the source and drain regions on the semiconductor substrate, a charge accumulation film 13 formed on the first insulating film, a second insulating film 14 formed on the charge accumulation film and the control gate electrode 18 formed on the second insulating film and containing at least any one of the elements selected from the group of Ni, Co, Pd and Pt, and Si and O. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device having a memory cell having a stacked gate structure and a method for manufacturing the same.

  In recent years, MONOS memory cells have been actively researched and developed as memory cells of NAND nonvolatile semiconductor memory devices. The MONOS type memory cell is a stack structure in which a tunnel insulating film (Oxide), a charge trapping film (Nitride), a charge blocking film (Oxide), and a control gate electrode (Metal) are formed in this order on a semiconductor substrate (Silicon). This is a semiconductor device having a gate. In a memory cell of a NAND type nonvolatile semiconductor memory device, a threshold voltage generated by applying a high voltage to a tunnel insulating film, injecting electrons into the charge trapping film from the silicon substrate side, and trapping charges in the charge trapping film Voltage shift is used to store information. At this time, as a property of the charge blocking film, it is desirable that the electric capacity is large and that the insulating property is high and the leakage current is small.

Therefore, it has been studied to increase the physical film thickness without reducing the coupling ratio by increasing the dielectric constant (high-k) of SiO ₂ that has been used as a charge blocking film. Al ₂ O ₃ is considered most promising as a material having a high rate and a high potential barrier against electrons.

On the other hand, n ⁺ type polysilicon has conventionally been used for the control gate electrode. However, in recent years, a decrease in electric field of the tunnel insulating film due to depletion of polysilicon at the time of writing to the memory cell has been a problem. In order to prevent this, it has been studied to introduce a metal material such as TaN as a control gate electrode (see, for example, Non-Patent Document 1).
CH Lee et al., IEDM Tech. Dig., 613 (2003)

  As described above, in a nonvolatile semiconductor memory device having a memory cell having a stack gate structure, it has been studied to use a metal material for a control gate electrode of the memory cell. However, as described later, when a metal material having high process consistency is used for the control gate electrode, it is difficult to obtain an appropriate threshold voltage.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a nonvolatile semiconductor memory device including a memory cell having an appropriate threshold voltage and a method for manufacturing the same.

  A nonvolatile semiconductor memory device according to a first aspect of the present invention includes a semiconductor substrate, a source region and a drain region that are provided apart from the semiconductor substrate, and a channel region between the source region and the drain region. A first insulating film provided on the semiconductor substrate, a charge storage film provided on the first insulating film, a second insulating film provided on the charge storage film, and the second insulating film And a control gate electrode including any one element selected from a group of Ni, Co, Pd, and Pt, Si, and O.

  According to a second aspect of the present invention, there is provided a non-volatile semiconductor memory device manufacturing method comprising: forming a first insulating film on a semiconductor substrate; forming a charge storage film on the first insulating film; Forming a second insulating film on the charge storage film; and on the second insulating film, any one element selected from the group of Ni, Co, Pd, and Pt, Si, and O And a step of forming the control gate electrode including sputtering by sputtering.

  According to the present invention, it is possible to provide a nonvolatile semiconductor memory device including a memory cell having an appropriate threshold voltage and a method for manufacturing the same even when a metal material having high process consistency is used for the control gate electrode.

  Before describing embodiments of the present invention, the background to the present invention and the outline of the present invention will be described.

In the MONOS structure, the control gate electrode is in contact with a sidewall oxide film formed on the side portion of the electrode. For this reason, when TaN or TaC having low oxidation resistance is used as the control gate electrode, there is a concern that oxidation may occur during the formation of the sidewall oxide film, resulting in problems such as film peeling. Therefore, it is desirable to use a metal with high oxidation resistance for the control gate electrode. Further, it is desirable that the formation process of the control gate electrode has high affinity with the formation process of the CMOS logic and can be easily integrated. Examples of the metal material for the control gate electrode that satisfies the above conditions include Ni-FUSI (Ni _x Si) and Co-FUSI (Co _x Si). Particularly with respect to Ni _x Si, Ni is a material that is normally used in CMOS logic, and has the advantage that it does not require the introduction of a new material and the cost can be reduced.

In order to put the MONOS memory cell using Ni _x Si or Co _x Si as the control gate electrode and Al ₂ O ₃ as the charge blocking film into practical use, there are two points to be noted.

The first is a threshold variation between memory cells accompanying the miniaturization of the area of the control gate electrode. At present, the minimum processing size of a MONOS type memory cell is becoming 50 nm or less. The threshold value of the memory cell is not limited to Ni _x Si or Co _x Si, but depends on the work function of the control gate electrode, and the work function depends on the crystal orientation on the charge blocking film. Therefore, if the area of the control gate electrode is about the same as the grain size of the silicide grains (crystal grains), the control gate electrode is formed with one grain, and the memory cells have different orientations. The threshold value varies between the two. In order to prevent this, it is effective to average the work function by making the grains sufficiently small with respect to 50 nm and orienting them randomly. On the other hand, a technique is known that can selectively form a micro-columnar structure with a grain size of about 10 nm by forming a metal by sputtering with controlled pressure and temperature (literature, JA Thornton, J Vac. Sci. Technol., 11, 666 (1974)). By applying this technique, it is possible to suppress variations in threshold values between memory cells.

The second point is that the neutral threshold voltage V _thi is higher than that of a conventional MONOS type memory cell using n ⁺ type polysilicon (work function: about 4.17 eV) for the control gate electrode. The neutral threshold voltage V _thi is the threshold voltage V _th of the memory cell in a state where charges are not trapped in the charge trap film (charge storage film). The same phenomenon is considered to occur not only with Ni _x Si or Co _x Si but also with TaN having a work function higher than that of n ⁺ type polysilicon.

Next, the reason why there is an optimum value for the neutral threshold voltage V _thi will be described. In the NAND flash memory, the circuit operation is performed by setting a state where V _th <0 as an erase state. When an erasing voltage is applied to the MONOS type memory cell, the threshold voltage _Vth is lowered by injecting holes from the substrate into the charge trapping film, but electrons are back-tunneled from the control gate electrode through the charge blocking film. The threshold voltage _Vth is saturated where both components are balanced. Therefore, the upper limit value for the neutral threshold voltage V _thi that is the threshold voltage before erasure is determined depending on the tunneling characteristics of electrons from the control gate electrode. On the other hand, since the threshold voltage V _th is also saturated in the write operation, there is a lower limit value required for the neutral threshold voltage V _thi . As a result, there exists an optimum value range of the neutral threshold voltage V _thi .

Therefore, when using Ni _x Si or Co _x Si for the control electrode, it is desirable to reduce the neutral threshold voltage V _thi by some method. Here, as a method of modulating the neutral threshold voltage V _thi , there are a method of changing the impurity concentration in the substrate and a method of changing the work function of the electrode. With respect to the impurity concentration of the substrate, it is necessary to increase the impurity concentration in order to suppress the short channel effect, but if it is too high, there is a problem that self-boost becomes difficult. Therefore, the impurity concentration of the substrate cannot be changed without restriction, and it is desirable to make the threshold value of the metal electrode as close as possible to the work function of n ⁺ -type polysilicon. However, with respect to the work functions of Ni _x Si and Co _x Si, even the NiSi ₂ and CoSi ₂ structures with the lowest work function are 4.55 eV and 4.45 eV, respectively, and 4.17 eV of n ⁺ -type polysilicon. Is a higher work function.

  The above points are not characteristics required only for the MONOS type memory cell. Also in the floating gate type memory cell, the metalization of the control gate electrode and the high dielectric constant (high-k) of the interelectrode insulating film have been advanced in recent years, and the control gate electrode has the same characteristics as those of the MONOS type. Is desirable.

Therefore, as a result of diligent research, the inventors have reduced the work function by about 0.35 eV from that of the conventional structure by adding a small amount of oxygen to NiSi ₂ by reactive sputtering, and n ^A work function close to that of ⁺ type polysilicon was obtained. Details will be described below.

In the manufacturing method according to an embodiment of the present invention, NiSi ₂ was formed by Ni and Si co-sputtering. According to Thornton's report, the crystal structure of the sputtered thin film is determined by the Ar pressure during deposition and the substrate temperature T _s [K] (literature, JA Thornton, J. Vac. Sci. Technol., 11, 666 ( 1974). As an electrode material for the control gate electrode, a thin film having a low electrical resistance and having fine columnar grains having a particle size of about 10 nm as described above is desirable. For this purpose, the Ar pressure is about 1 mTorr to 4.5 mTorr, and the melting point of the thin film is T _m [K], sputtering may be performed under the condition of T _s / T _m <0.3. Here, NiSi ₂ and a melting point _{T m} of a CoSi _2, respectively 993 ° C., since at 1326 ° C., _{T s} is about 100 ° C. Each of the above conditions, it is sufficient 200 ° C. or less.

In the manufacturing method according to an embodiment of the present invention, a minute amount of oxygen was added to NiSi ₂ by performing reactive sputtering in an atmosphere containing oxygen while satisfying the above-described conditions. Here, in Thornton's report, conditions for Ar pressure are shown as conditions for obtaining a desired crystal structure. Essentially, the total pressure during film formation is considered to be an important condition. Therefore, in one embodiment of the present invention, it is considered that the total pressure of Ar and O ₂ should be within the range of about 1 mTorr to 4.5 mTorr. Moreover, regarding the oxygen partial pressure, the flow rates of Ar and O ₂ are adjusted so as to be on the order of 10 ⁻⁴ Pa. When the oxygen partial pressure is higher than this, there is a concern that NiSi ₂ oxide is formed and the conductivity is significantly lowered.

FIG. 1 shows a transmission electron microscope (TEM) image of NiSi ₂ with added oxygen formed by the manufacturing method according to an embodiment of the present invention. As a comparative example, FIG. 2 shows a cross-sectional TEM image of NiSi ₂ formed by a solid phase reaction process of Si and Ni. In both figures, a white dotted line is drawn at the grain boundary. As shown in FIG. 2, it was found that NiSi ₂ formed by the solid phase reaction process was polycrystalline, and the grain size in the lateral direction was 50 nm or more. On the other hand, FIG. 1 shows that NiSi ₂ to which oxygen is formed, which is formed by the manufacturing method of one embodiment of the present invention, is polycrystalline, but its grains are micro-columnar. Further, the grain size in the lateral direction was 10 nm or less. Furthermore, there is a white contrast region that is not observed in a normal sputtered film at the grain boundary of NiSi ₂ grains to which oxygen is added. This is considered to be a region where the density is reduced by adding oxygen.

FIG. 3 shows a result obtained by measuring a plurality of locations of NiSi ₂ to which oxygen is added formed by the manufacturing method according to an embodiment of the present invention by a micro electron diffraction method and superimposing the obtained electron diffraction patterns. The numbers in the figure indicate the reference data (JCPDS43-0989) of the plane orientation of the cubic NiSi ₂ crystal. Both diffraction images coincide with the peak of NiSi ₂ . Moreover, since this diffraction pattern does not have periodicity, it turns out that it is oriented to some extent at random.

FIG. 4 shows the results of X-ray diffraction measurement of NiSi ₂ to which oxygen is added and NiSi ₂ to which oxygen is not added, formed by the manufacturing method according to one embodiment of the present invention. A Cu Kα ray is used as the X-ray source. Since the grain diameters of the two samples are different, the half widths of the peaks are different, but it can be seen that the positions of the peaks are the same for both samples, and the surface spacing is the same. Therefore, in NiSi ₂ to which oxygen is added, it is considered that oxygen exists mainly at grain boundaries rather than grains.

FIG. 5 shows the work functions of Ni _x Si to which oxygen is added (x = 0.5, 1, 2) and Ni _x Si to which oxygen is not formed, formed by the manufacturing method according to an embodiment of the present invention. This work function was estimated as follows. First, a MOS capacitor having a Ni _x Si / SiO ₂ / Si structure was formed, and the flat band voltage V _fb was estimated from the CV characteristics. Next, V _fb -T plots were created for samples with different SiO ₂ film thicknesses T, and the work function was extracted from linear extrapolation. FIG. 5 shows that the work function value of Ni _x Si of any composition is reduced by adding oxygen.

This mechanism is considered as follows. Considering a simple substance, as shown in FIG. 6, when the density of atoms on the surface of the substance is low, the charge density is smoothed in the direction parallel to the substance surface (Smoluchowski smoothing), and the electrons are Wigner-Seitz. Move to the vacuum area between cells. As a result, a charge bias as shown in FIG. 6 occurs and a work function is lowered. A similar phenomenon is considered to occur at the interface between materials. That is, in the manufacturing method according to an embodiment of the present invention, oxygen enters the grain boundary, and as a result, a region having a low atomic density is formed at the interface between NiSi ₂ and the insulating film, resulting in a decrease in the work function of NiSi _2. It is thought that. As shown in FIG. 5, this phenomenon is observed not only in NiSi ₂ but also in Ni ₂ Si and NiSi having different compositions. A similar phenomenon is estimated to occur in other silicides, but if the oxidation resistance of the silicide is too low, oxygen may be taken into the grains and become an insulator. Here, a work function is mentioned as one index of oxidation resistance, and it is thought that oxidation resistance is so high that a work function is large. Therefore, regarding the silicide of Co, Pd, and Pt having a work function of 5 eV or more, it is considered that the same phenomenon as NiSi ₂ occurs.

  Embodiments of the present invention will be described below with reference to the drawings. In addition, the same code | symbol shall be attached | subjected to a common structure through embodiment, and the overlapping description is abbreviate | omitted. Each figure is a schematic diagram for promoting explanation and understanding of the invention, and its shape, dimensions, ratio, and the like are different from those of an actual device. However, these are in consideration of the following explanation and known techniques. The design can be changed as appropriate.

(First embodiment)
A nonvolatile semiconductor memory device according to a first embodiment of the present invention will be described. The nonvolatile semiconductor memory device of this embodiment is a NAND nonvolatile semiconductor memory device, and has a plurality of memory cells M as shown in FIG. The plurality of memory cells M are connected in series so that adjacent ones share a source / drain to form a NAND string. Such NAND strings are arranged in a matrix to form a memory cell array.

  The drain on one end side of the NAND column arranged in the column direction of the memory cell array is connected in common to the bit line BL via the selection transistor S1, and the source on the other end is also a common source line (not shown) via the selection transistor S2. ). The control gates of the memory cells M arranged in the horizontal direction shown in FIG. 14 are commonly connected to the word line WL. Similarly, the gates of the selection transistors S1 and S2 are commonly connected to the selection gate lines SSL and GSL. A range of NAND strings driven by one word line constitutes a NAND string block. Usually, a plurality of such NAND column blocks are arranged in the bit line direction to constitute a memory cell array.

  In this embodiment, each memory cell is a MONOS type memory cell, and its cross-sectional structure is shown in FIGS. 7 (a) and 7 (b). 7A is a cross-sectional view in a direction parallel to the bit line, and FIG. 7B is a cross-sectional view in a direction parallel to the word line. The control gate electrode of each memory cell is a word line. FIG. 7A and FIG. 7B show cross sections orthogonal to each other.

  As shown in FIG. 7A, a source region 4a and a drain region 4b are formed in a p-type silicon substrate 1. On the p-type silicon substrate 1 which becomes the channel region 6 between the source region 4a and the drain region 4b, a gate 10 having a MONOS structure is formed. The gate 10 has a laminated structure in which a tunnel insulating film 12, a charge trapping film (also referred to as a charge storage film) 13, a charge blocking film 14 made of an insulator that blocks charges, and a control gate electrode 18 are formed in this order. Have. In the present embodiment, the mask material 19 is formed on the control gate electrode 18, but the mask material 19 may be omitted.

In this embodiment, a SiO ₂ film is used as the tunnel insulating film 12, but it may be a SiON film or a laminated film of SiO ₂ / SiN / SiO ₂ (hereinafter referred to as ONO film). Further, although a SiN film is used as the charge trapping film 13, it may be a high-k film such as an HfO ₂ film or an HfON film. Further, an Al ₂ O ₃ film is used as the charge blocking film 14, and a NiSi ₂ film containing oxygen is used as the control gate electrode 18.

  The top and side surfaces of the gate 10 are covered with a silicon oxide film 21 called a sidewall oxide film, and an interlayer insulating film 22 is formed so as to cover the entire surface. As shown in FIG. 7B, the channel region 6 of adjacent memory cells and the stacked portion from the tunnel insulating film 12 to the charge block film 14 are separated from each other by an element isolation region 27 composed of a silicon oxide film. Yes. Each memory cell arranged in the word line direction has a common control electrode 18, which extends on the element isolation region 27. That is, the word line is the control electrode 18.

  Next, with reference to FIGS. 8A to 11B, a method for manufacturing the nonvolatile semiconductor memory device of this embodiment will be described. 8 (a) to 11 (b), FIGS. 8 (a), 9 (a), 10 (a), and 11 (a) are similar to FIGS. 7 (a) and 7 (b). Cross-sectional views in the direction parallel to the bit lines, FIGS. 8B, 9B, 10B, and 11B show the cross-sectional views in the direction parallel to the word lines.

First, for example, a 3 nm to 5 nm thick SiO ₂ film to be the tunnel insulating film 12 is formed on the surface of the p-type silicon substrate 1 by thermal oxidation. Here, the tunnel insulating film 12 may be a SiON film or ONO film having an EOT (Equivalent Oxide Thickness) of 3 nm to 5 nm formed by a CVD method or the like. Next, a SiN film having a thickness of 4 nm to 10 nm is formed as the charge trapping film 13 by a CVD method or the like. Here, the charge trapping film 13 may be a high-k film such as HfO ₂ having a film thickness of 15 nm to 25 nm formed by CVD or sputtering. Further, an Al ₂ O ₃ film having a film thickness of 10 nm to ₂₀ nm is formed as the charge blocking film 14 by sputtering or the like, and a mask material 15 for element isolation is deposited by CVD. Thereafter, the mask material 15, the charge block film 14, the charge trap film 13, and the tunnel insulating film 12 are sequentially etched by RIE using a resist mask (not shown), and the exposed region of the silicon substrate 1 is further etched. Thus, an element isolation trench 26 having a depth of 60 nm is formed (see FIGS. 8A and 8B).

  Next, a silicon oxide film to be an element isolation region 27 is deposited on the entire surface to completely fill the element isolation groove 26, and thereafter, the silicon oxide film on the surface portion is removed by a CMP (Chemical Mechanical Polishing) method. Is flattened (see FIGS. 9A and 9B). At this time, the material used for the element isolation region 27 is not limited to the silicon oxide film, but may be an insulator containing silicon and oxygen, and may be a silicon oxynitride film, for example.

  Next, the exposed mask material 15 is selectively removed by etching, and then the exposed surface of the element isolation region 27 is etched away with a diluted hydrofluoric acid solution to flatten the surfaces of the element isolation region 27 and the charge blocking film 14 ( Not shown).

After forming the flat surface, a NiSi ₂ film having a thickness of 100 nm is formed on the entire surface by co-sputtering Ni and Si as the control gate electrode 18 at a temperature of room temperature to 100 ° C. Co-sputtering is carried out in a mixed gas atmosphere of Ar and _{O 2,} by adjusting the flow rate ratio of Ar and _{O 2,} a total pressure of about 1mTorr~4.5mTorr, _{O 2} partial pressure is ¹⁰ -4 Pa stand Like that. Further, nickel silicide sputtering may be used instead of co-sputtering. Here, NiSi ₂ has been described as an example, but the control gate electrode 18 may be CoSi ₂ , and the film formation temperature in this case is in the range of room temperature to 200 ° C. Subsequently, a mask material 19 for element isolation is deposited by the CVD method (see FIGS. 10A and 10B).

  Thereafter, the mask material 19, the control gate electrode 18, the charge blocking film 14, the charge trapping film 13, and the tunnel insulating film 12 are sequentially etched by RIE using a resist mask (not shown) to form word lines. A slit portion 29 is formed along the direction (see FIGS. 11A and 11B).

  Finally, as shown in FIGS. 7A and 7B, a silicon oxide film 21 called a sidewall oxide film is formed on the exposed surface by a CVD method. Thereafter, the source region 4a and the drain region 4b are formed on the silicon substrate 1 by using an ion implantation method. Further, the interlayer insulating film 22 is formed by the CVD method so as to cover the entire surface, and thereafter, a wiring layer and the like are formed by a known method to complete the nonvolatile semiconductor memory device.

In the nonvolatile semiconductor memory device of this embodiment formed as described above, a NiSi ₂ film to which oxygen is added is used as a control gate electrode, and this NiSi ₂ film has a micro-columnar structure with a grain size of about 10 nm. The added oxygen is mainly present at the grain boundaries.

  Thereby, the nonvolatile semiconductor memory device of this embodiment can have an appropriate threshold voltage.

(Second Embodiment)
Next, a nonvolatile semiconductor memory device according to a second embodiment of the present invention is described. The nonvolatile semiconductor memory device of the present embodiment is a NAND nonvolatile semiconductor memory device, and includes a NAND string in which a plurality of memory cells are connected in series as shown in FIG. 14 as in the first embodiment. ing. In this embodiment, each memory cell is a MONOS type memory cell, and its cross-sectional structure is shown in FIGS. 12 (a) and 12 (b). 12A is a cross-sectional view in a direction parallel to the bit line, and FIG. 12B is a cross-sectional view in a direction parallel to the word line. 12A and 12B show cross sections orthogonal to each other.

Conventionally, it is known that polycrystalline silicon and Al ₂ O ₃ react. In the first embodiment, since the control gate electrode 18 made of silicide is directly formed on the charge block film 14 made of Al ₂ O ₃ , the Si in the control gate electrode 18 made of silicide is formed. Then, there is a possibility that the charge blocking film 14 made of Al ₂ O ₃ reacts. Therefore, in the second embodiment, the reaction preventing film 17 made of, for example, SiN is formed between the control gate electrode 18 and the charge blocking film 14. Thereby, the reaction between Si in the control gate electrode 18 and Al ₂ O ₃ in the charge blocking film 14 can be prevented.

Regarding the manufacture of the nonvolatile semiconductor memory device of this embodiment shown in FIGS. 12A and 12B, basically, FIGS. 8A to 11B described in the first embodiment are used. It can be formed by applying the process shown. As a part different from the process method described in the first embodiment, after forming the charge block film 14 made of Al ₂ O ₃ , a SiN film having a thickness of 1 nm to ₃ nm is formed by a CVD method or the like. Further, after the mask material 15 for element isolation is deposited by the CVD method, the nonvolatile semiconductor shown in FIGS. 12A and 12B is used by using a method similar to the manufacturing method described in the first embodiment. A memory device can be manufactured.

Similarly to the first embodiment, the nonvolatile semiconductor memory device of this embodiment uses a NiSi ₂ film to which oxygen is added as a control gate electrode, and this NiSi ₂ film has a micro-columnar structure with a grain size of about 10 nm. Since the added oxygen is mainly present at the grain boundary, it can have an appropriate threshold voltage.

(Third embodiment)
Next, a non-volatile semiconductor memory device according to a third embodiment of the present invention is described. The nonvolatile semiconductor memory device of the present embodiment is a NAND nonvolatile semiconductor memory device, and includes a NAND string in which a plurality of memory cells are connected in series as shown in FIG. 14 as in the first embodiment. ing. In this embodiment, each memory cell is a floating gate type memory cell, and its cross-sectional structure is shown in FIGS. 13 (a) and 13 (b). 13A is a cross-sectional view in a direction parallel to the bit line, and FIG. 13B is a cross-sectional view in a direction parallel to the word line. FIG. 13A and FIG. 13B show cross sections orthogonal to each other.

  The floating gate type memory cell according to the present embodiment has a configuration in which the gate 10 of the MONOS type memory cell according to the first and second embodiments shown in FIGS. 7A and 12A is replaced with a gate 10A. It has become. This gate 10A has a laminated structure in which a tunnel insulating film 12, a floating gate electrode (charge accumulating film) 33 for accumulating charges, an interelectrode insulating film 34, and a control gate electrode 18 are laminated in this order on the channel region 6. is doing.

When forming the floating gate type memory cell according to the present embodiment, after forming the tunnel insulating film 12, an n ⁺ type polysilicon having a thickness of 60 nm is formed as the floating gate electrode 33, and a mask material (FIG. (Not shown) is formed by a CVD method. Thereafter, the mask material (not shown), the floating gate electrode 33 and the tunnel insulating film 12 are sequentially etched by RIE using a resist mask (not shown), and the exposed region of the silicon substrate 1 is further etched. Then, an element isolation trench (not shown) having a depth of 60 nm is formed.

  Next, a silicon oxide film to be an element isolation region 27 is deposited on the entire surface to completely fill the element isolation groove, and then the surface portion of the silicon oxide film is removed by CMP to planarize the surface. At this time, the material used for the element isolation region 27 is not limited to the silicon oxide film, but may be an insulator containing silicon and oxygen, and may be a silicon oxynitride film, for example.

  Subsequently, the exposed mask material is selectively removed by etching, and the exposed surface of the element isolation region 27 is removed by etching with a diluted hydrofluoric acid solution, and then the interelectrode insulating film 34, the control gate electrode 18, and the mask material 19 are deposited. . Thereafter, by using a method similar to the method for manufacturing the MONOS type semiconductor memory device described in the first embodiment, the memory cell according to this embodiment shown in FIGS. 13A and 13B can be manufactured. it can.

Similarly to the first embodiment, the nonvolatile semiconductor memory device of this embodiment uses a NiSi ₂ film to which oxygen is added as a control gate electrode, and this NiSi ₂ film has a micro-columnar structure with a grain size of about 10 nm. Since the added oxygen is mainly present at the grain boundary, it can have an appropriate threshold voltage.

Cross-sectional TEM photograph of NiSi ₂ manufactured by the manufacturing method according to an embodiment of the present invention. Cross-sectional TEM photograph of NiSi ₂ manufactured by the manufacturing method of the comparative example. Photograph showing an electron beam diffraction pattern of NiSi ₂ manufactured by the manufacturing method of an embodiment of the present invention. And NiSi ₂ which oxygen is added, shows a X-ray diffraction spectrum of NiSi ₂ that oxygen is not added. Shows a Ni x _Si which oxygen is added, the work function when the oxygen is changing the composition x of not added Ni x _Si. The figure explaining Smolchowski smoothing. 1 is a cross-sectional view of a nonvolatile semiconductor memory device according to a first embodiment. Sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device by 1st Embodiment. Sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device by 1st Embodiment. Sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device by 1st Embodiment. Sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device by 1st Embodiment. Sectional drawing of the non-volatile semiconductor memory device by 2nd Embodiment. Sectional drawing of the non-volatile semiconductor memory device by 3rd Embodiment. 1 is a diagram showing a memory cell array of a NAND type nonvolatile semiconductor memory device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 4a Source region 4b Drain region 6 Channel region 10 MONOS structure gate 12 Tunnel insulating film 13 Charge trap film 14 Charge block film 15 Mask material 17 Reaction prevention film 18 Control gate electrode 19 Mask material 21 Silicon oxide film 22 Interlayer insulation Film 26 Element isolation groove 27 Element isolation region 29 Slit portion 33 Floating gate electrode 34 Interelectrode insulating film

Claims (8)

A semiconductor substrate;
A source region and a drain region provided apart from the semiconductor substrate;
A first insulating film provided on the semiconductor substrate to be a channel region between the source region and the drain region;
A charge storage film provided on the first insulating film;
A second insulating film provided on the charge storage film;
A control gate electrode provided on the second insulating film and including any one element selected from the group of Ni, Co, Pd, and Pt, Si, and O;
A non-volatile semiconductor memory device comprising:   The control gate electrode has a polycrystalline structure having columnar crystal grains containing any one element selected from the group of Ni, Co, Pd, and Pt and Si, and the grains of the crystal grains 2. The nonvolatile semiconductor memory device according to claim 1, wherein O is segregated at the boundary.   3. The nonvolatile semiconductor memory device according to claim 1, wherein the charge storage film is an insulator charge trap film for trapping charges. The second insulating film includes Al ₂ O ₃ ;
4. The nonvolatile semiconductor memory device according to claim 3, wherein a third insulating film made of a material different from that of the second insulating film is provided between the second insulating film and the control gate electrode.   3. The nonvolatile semiconductor memory device according to claim 1, wherein the charge storage film is a polycrystalline silicon film. Forming a first insulating film on the semiconductor substrate;
Forming a charge storage film on the first insulating film;
Forming a second insulating film on the charge storage film;
Forming a control gate electrode including any one element selected from the group of Ni, Co, Pd, and Pt, Si, and O on the second insulating film by sputtering;
A method for manufacturing a nonvolatile semiconductor memory device, comprising: 7. The non-volatile semiconductor according to claim 6, wherein the step of forming the control gate electrode by sputtering is performed in an atmosphere containing Ar and O ₂ and at a total pressure in the range of 1 mTorr to 4.5 mTorr. A method for manufacturing a storage device. The step of forming the control gate electrode by sputtering is performed in an atmosphere containing Ar and O _2, and the partial pressure of O ₂ is on the order of 10 ⁻⁴ Pa. A method for manufacturing a nonvolatile semiconductor memory device.