JP2010009132A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device, capable of setting an optional protection area while suppressing increase in chip size. <P>SOLUTION: The semiconductor storage device includes a nonvolatile memory having a plurality of blocks each of which is a minimum unit in which data can be independently erased; a volatile memory which serves as a buffer of the nonvolatile memory; a protection SRAM capable of holding protection information for limiting executable operation to each of the blocks; a register capable of reading the protection information corresponding to a block address input from the outside from the protection SRAM and setting it; and a control part which determines, based on the protection information set to the register, whether an operation requested to the block is limited or not. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, for example, a system product having a protect function.

  2. Description of the Related Art Conventionally, there has been known a memory system that holds data write permission / prohibition information in a separate storage area for each block constituting a nonvolatile memory. When the host device writes to the memory area set in the memory system, the write operation is performed if the information is permitted, and the write operation is not performed if the information is prohibited. Similarly, in the erasing operation, erasure permission / prohibition information is held for each block, and if the information is permitted, the erasing operation is performed.

  For example, when holding data write permission / prohibition information for each block, it is expected that the number of blocks will increase as the capacity of the nonvolatile memory increases, and the area for holding the protection information will inevitably be large. Become. In order to avoid this, a memory system is disclosed in which only the “start block address” and “end block address” of the write area are held in the status register (see, for example, Patent Document 1).

However, when adopting a method that retains only the “start block address” and “end block address” of the write area in the status register, the degree of freedom of address setting of the block holding the protect information becomes low, and any block can be set. For users who want to execute protection, this leads to a decrease in convenience.
JP 2004-103219 A

  The present invention provides a semiconductor memory device capable of setting an arbitrary protected area while suppressing an increase in chip size.

  A semiconductor memory device according to one embodiment of the present invention includes a nonvolatile memory having a plurality of blocks, which are minimum units that can be independently erased, a volatile memory that functions as a buffer of the nonvolatile memory, and each of the blocks It is possible to read and set the protection SRAM that can hold protection information that restricts the operations that can be performed on the memory and the protection information corresponding to the block address input from the outside. And a control unit for determining whether or not to restrict the operation requested for the block based on the protection information set in the register.

  According to the present invention, it is possible to provide a semiconductor memory device capable of setting an arbitrary protected area while suppressing an increase in chip size.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing a system configuration of the semiconductor memory device according to the present embodiment. The semiconductor memory device according to the present embodiment relates to a memory system including a nonvolatile semiconductor memory represented by, for example, OneNAND (registered trademark).

<Overall configuration of memory system>
The memory system 1 according to this embodiment includes a NAND flash memory 2, a RAM unit 3, and a controller unit 4. The NAND flash memory 2, the RAM unit 3, and the controller unit 4 are formed on the same semiconductor substrate and integrated on one chip. Details of each block will be described below.

<NAND flash memory 2>
The NAND flash memory 2 functions as a main storage unit of the memory system 1. As shown in the figure, the NAND flash memory 2 includes a memory cell array 10, a row decoder 11, a page buffer 12, a voltage generation circuit 13, a sequencer 14, and oscillators 15 and 16.

  The memory cell array 10 includes a plurality of memory cell transistors that can hold data. FIG. 2 is an equivalent circuit diagram of the memory cell array 10. As shown in the figure, the memory cell array 10 includes a first region 17 and a second region 18. The first area 17 holds net data such as user data (hereinafter referred to as main data). On the other hand, the second area 18 is used as a spare area of the first area 17 and holds, for example, error correction information (parity or the like).

  Each of the first region 17 and the second region 18 includes a plurality of memory cell units 19. Each of the memory cell units 19 includes, for example, 32 memory cell transistors MT0 to MT31 and select transistors ST1 and ST2. Hereinafter, when the memory cell transistors MT0 to MT31 are not distinguished, they are simply referred to as memory cell transistors MT.

  The memory cell transistor MT includes a charge storage layer (for example, a floating gate) formed on a semiconductor substrate with a gate insulating film interposed therebetween, and a control gate formed on the charge storage layer with an inter-gate insulating film interposed therebetween. A laminated gate structure having The number of memory cell transistors MT is not limited to 32, and may be 8, 16, 64, 128, 256, etc., and the number is not limited. The memory cell transistor MT may have a MONOS (Metal Oxide Nitride Oxide Silicon) structure using a method of trapping electrons in a nitride film.

  Adjacent ones of the memory cell transistors MT share a source and a drain. And it arrange | positions so that the current path may be connected in series between selection transistor ST1, ST2. The drain on one end side of the memory cell transistors MT connected in series is connected to the source of the select transistor ST1, and the source on the other end side is connected to the drain of the select transistor ST2.

  The control gates of the memory cell transistors MT in the same row are commonly connected to any one of the word lines WL0 to WL31. The gates of the select transistors ST1 and ST2 in the same row are commonly connected to select gate lines SGD and SGS, respectively. For simplification of description, the word lines WL0 to WL31 are sometimes simply referred to as word lines WL below.

  The drains of the select transistors ST1 in the same column in the first region 17 are commonly connected to bit lines BL0 to BLn (n is a natural number). In addition, the drains of the select transistors ST1 in the same column in the second region 18 are commonly connected to the bit lines BL (n + 1) to BLm (m is a natural number). The bit lines BL0 to BLm may also be simply referred to as bit lines BL. The sources of the selection transistors ST2 are commonly connected to the source line SL. Note that both the selection transistors ST1 and ST2 are not necessarily required, and only one of them may be provided as long as the memory cell unit 11 can be selected.

  In the above configuration, data is written or read all at once to a plurality of memory cell transistors MT connected to the same word line WL, and this unit is called a page. Further, data is erased collectively from a plurality of memory cell units 19 in the same row, and this unit is called a block. Memory cell array 10 includes a plurality of blocks.

  Each memory cell transistor MT can hold 1-bit data in accordance with, for example, a change in the threshold voltage of the transistor due to the amount of electrons injected into the floating gate. Note that the threshold voltage control may be subdivided so that each memory cell transistor MT holds data of 2 bits or more.

  The row decoder 11 selects the word line WL and the select gate lines SGD and SGS during data write, read, and erase operations. Then, a predetermined voltage necessary for each operation is applied to the word line WL and the select gate lines SGD, SGS.

  The page buffer 12 can hold data of a page size (for example, 2 KB + 64 B), and temporarily holds data supplied from the RAM unit 3 and writes data to the memory cell array 10 during a data write operation. On the other hand, during the read operation, data read from the memory cell array 10 is temporarily held and transferred to the RAM unit 3. A part of the page buffer 12 is used for holding main data, and the rest is used for holding parity and the like. In the following, it is loaded that data read from the memory cell array 10 to the page buffer 12 is transferred to the RAM unit 3 (Load), and the data transferred from the RAM unit 3 to the page buffer 12 is written to the memory cell array 10 (Program). ).

  The voltage generation circuit 13 generates a voltage necessary for data writing, reading, and erasing by boosting or stepping down a voltage applied from the outside. The generated voltage is supplied to, for example, the row decoder 11. The voltage generated by the voltage generation circuit 13 is applied to the word line WL.

  The sequencer 14 manages the overall operation of the NAND flash memory 2. That is, when a program command, a load command, or an erase command (not shown) is received from the controller unit 4, a sequence for executing data writing, reading, and erasing is executed in response thereto. Then, according to this sequence, the operations of the voltage generation circuit 13 and the page buffer 12 are controlled.

  The oscillator 15 generates an internal clock ICLK. That is, it functions as a clock generator. The oscillator 15 supplies the generated internal clock ICLK to the sequencer 14. The sequencer 14 operates in synchronization with the internal clock ICLK.

  The oscillator 16 generates an internal clock ACLK. That is, it functions as a clock generator. The oscillator 16 supplies the generated internal clock ACLK to the controller unit 4 and the RAM unit 4. The internal clock ACLK is a clock serving as a reference for operations of the controller unit 4 and the RAM unit 3.

<RAM unit 3>
Next, the RAM unit 3 will be described. The RAM unit 3 includes an ECC unit 20, an SRAM (Static Random Access Memory) 30, an interface unit 40, and an access controller 50. Each will be described below.

<< ECC part 20 >>
The ECC unit 20 performs error detection and error correction for data, and generation of parity (hereinafter, these may be collectively referred to as ECC processing). That is, when data is loaded, an error is detected and corrected for the data read from the NAND flash memory 2. On the other hand, when data is programmed, parity is generated for the data to be programmed. The ECC unit 20 includes an ECC buffer 21 and an ECC engine 22.

  The ECC buffer 21 is connected to the page buffer 12 of the NAND flash memory 2 through a NAND bus, and is connected to the SRAM 30 through an ECC bus. These bus widths are equal, for example, 64 bits. When data is loaded, the data transferred from the page buffer 12 via the NAND bus is held, and the ECC processed data is transferred to the SRAM 30 via the ECC bus. On the other hand, when data is programmed, the data transferred from the SRAM 30 via the ECC bus is held, and the transferred data and parity are transferred to the page buffer 12 via the NAND bus.

  The ECC engine 22 performs ECC processing using data held in the ECC buffer 21. The ECC engine uses, for example, a 1-bit correction method using a Hamming code. The ECC engine 22 generates a syndrome from the parity at the time of data loading, and thereby performs error detection. If an error is found, correct it. On the other hand, during data programming, parity is generated and added to the main data.

<< SRAM 30 >>
Next, the SRAM 30 will be described. In the memory system 1, the SRAM 30 functions as a buffer memory for the NAND flash memory 2. As shown in the figure, the SRAM 30 includes a DQ buffer 31, a plurality of (two in this embodiment) data RAM, and one boot RAM.

  The DQ buffer 31 temporarily holds data when data is written to or read from the data RAM or the boot RAM. The DQ buffer 31 can transfer data to and from the ECC buffer 21 via the ECC bus. The DQ buffer 31 can transfer data to and from the interface unit 40 using a RAM / Register bus having a 64-bit bus width, for example. Similar to the page buffer 12, the DQ buffer 31 includes an area for holding main data and an area for holding parity.

  The boot RAM temporarily holds a boot code for starting the memory system 1, for example. The data RAM temporarily holds data (main data and parity bits) other than the boot code, and the capacity corresponds to the capacity of the page buffer 12 of the NAND flash memory 2. Each of the data RAM and the boot RAM includes a memory cell array 32, a sense amplifier 33, and a row decoder 34.

  The memory cell array 32 includes a plurality of SRAM cells capable of holding data. Each SRAM cell is connected to a word line and a bit line. Similar to the memory cell array 10, the memory cell array 32 also includes an area for holding main data and an area for holding parity. The sense amplifier 33 senses and amplifies data read from the SRAM cell to the bit line. The sense amplifier 33 also functions as a load when data in the DQ buffer 31 is written to the SRAM cell. The row decoder 34 selects a word line in the memory cell array 32.

<< Interface section 40 >>
Next, the interface unit 40 will be described. As illustrated, the interface unit 40 includes a plurality (two in this embodiment) of burst buffers 41 and 42 and an interface 43.

  The interface 43 supports the same interface standard as the NOR flash memory. The interface 43 can be connected to a host device outside the memory system 1 and controls input / output of various signals such as data, control signals, and address Add <15: 0> with the host device. Examples of control signals include a chip enable signal / CE for activating the entire memory system 1, an address valid signal / AVD for latching an address, a clock CLK for burst read, and a write for activating a write operation. An enable signal / WE, an output enable signal / OE for activating the output of data to the outside, and the like.

  The interface 43 is connected to the burst buffers 41 and 42 by a DIN / DOUT bus having a bus width of 16 bits, for example. At the time of reading (Read), a control signal related to a read request from the host device is transferred to the access controller 50, and the data in the burst buffers 41 and 42 is output to the host device. Further, at the time of writing (Write), a control signal related to a write request from the host device is transferred to the access controller 50, and data given from the host device is transferred to the burst buffers 41 and 42.

  The burst buffers 41 and 42 can transfer data with the DQ buffer 31 and the controller unit 4 through the RAM / Register bus, and can transfer data with the interface 43 through the DIN / DOUT bus described above. Then, data given from the host device via the interface 43 or data given from the DQ buffer 31 is temporarily held.

<< Access Controller 50 >>
The access controller 50 receives a control signal and an address from the interface 43. Then, the SRAM 30 and the controller unit 4 are controlled so as to execute an operation that satisfies the request of the host device.

  More specifically, the access controller 50 activates the SRAM 30 in response to a write command or a read command (Write / Read) received from the host device. The access controller 50 distributes a write request or a read request (Write / Read) to the SRAM 30. Under these controls, the SRAM 30 starts operating.

  Further, the access controller 50 activates the register 60 included in the controller unit 4. Further, the access controller 50 distributes a program command or a load command (Program / Load) received from the host device and sets it in the register. When these commands are set in the register 60, the controller unit 4 starts operation.

<Controller unit 4>
Next, the controller unit 4 will be described. The controller unit 4 controls operations of the NAND flash memory 2 and the RAM unit 3. That is, the memory system 1 has a function of supervising internal operations as a whole. As illustrated, the controller unit 4 includes a register 60, a command user interface 61, a state machine 62, an address / command generation circuit 63, an address / timing generation circuit 64, and a protection SRAM 65. I have.

  The register 60 is provided for setting the operation state of the memory system 1. That is, the program command or the load command is set in the register 60 via the interface unit 40 as described above. A part of the external address space is allocated to the register 60.

  The command user interface 61 recognizes that the operation execution command is given to the memory system 1 by setting the command in the register 60 of the predetermined address. Then, an internal command signal (Command) necessary for each operation is issued and output to the state machine 62.

  The state machine 62 controls the sequence operation in the memory system 1 based on the internal command signal given from the command user interface 61. There are many functional operations supported by the state machine 62, such as loading, programming, and erasing, and the operations of the NAND flash memory 2 and the RAM unit 3 are controlled so as to execute these operations.

  The address / command generation circuit 63 controls the operation of the NAND flash memory 2 based on the control of the state machine 62. More specifically, an internal address of the NAND flash memory 2, a command according to the interface standard of the NAND flash memory 2, and the like are generated and output to the NAND flash memory 2. The address / command generation circuit 63 outputs these addresses and commands in synchronization with the internal clock ACLK generated by the oscillator 16.

  The address / timing generation circuit 64 controls the operation of the RAM unit 3 based on the control of the state machine 62. More specifically, the RAM unit 3 issues necessary addresses and commands and outputs them to the access controller 50 and the ECC engine 22. The address / timing generation circuit 64 issues an address and a command necessary for controlling a protection SRAM 65 described later, and outputs it to the access controller 50.

  The protect SRAM 65 is provided corresponding to the register 60 and can set permission / prohibition of the write / erase operation for each block of the memory cell array 10 constituting the storage area in the NAND flash memory 2. is there. That is, the memory system 1 according to the present embodiment includes an SRAM that holds write permission / prohibition and erase permission / prohibition information at an address corresponding to the block address of the NAND flash memory 2 that is a nonvolatile memory in the chip. Have. Details of the protect function will be described later.

<Operation of Memory System 1>
Next, the operation of the memory system 1 having the above configuration will be briefly described. In the memory system 1 according to the present embodiment, the data program to the NAND flash memory 2 and the data load from the NAND flash memory 2 are performed via the SRAM 30.

  That is, when programming data, the host device first designates the address of the SRAM 30 and temporarily stores the data in the data RAM. Thereafter, the host device issues a program command to the memory system 1. In the memory system 1 that has received the program command from the host device, the data stored in the SRAM 30 is transferred to the page buffer 12 in a batch unit and written to the memory cell array 10.

  When loading data, the data is read from the memory cell array 10 to the page buffer 12 according to the address of the NAND flash memory 2 designated by the host device, and temporarily stored in the data RAM. Thereafter, the host device designates the address of the SRAM 30 and reads data held in the data RAM via the interface unit 40.

<Protect function>
The memory system 1 according to the present embodiment supports a protect function for each block constituting the memory cell array 10. FIG. 3 schematically shows the transition of the operation state of each block. In FIG. 3, only three blocks, block 0, block 1, and block 2, are shown for simplicity. Each block constituting the memory cell array 10 is set to any one of three states of “Unlock”, “Lock”, and “Lock-high”, for example.

  A block set to the “Unlock” state can be programmed and erased. The host device can set a block in the “Unlock” state to the “Lock” state by inputting “Lock block Command” (see block 1). When a reset signal is input from the host device to the memory system 1 and a system reset is performed, all blocks constituting the memory cell array 10 are initialized to the “Lock” state.

  For a block set in the “Lock” state, neither programming nor erasing is possible. The host device can set the block in the “Lock” state to the “Unlock” state by inputting “Unblock block Command” (see block 1). Further, the host device can set all the blocks in the “Lock” state to the “Unlock” state at the same time by inputting “All Block Unlock Command”. When the memory system 1 is powered on, all the blocks constituting the memory cell array 10 are set to the “Lock” state. As a result, it is possible to prevent unintended loss of internal data.

  For a block set in the “Lock-high” state, neither programming nor erasing is possible, and it is impossible to transition to another state unless a system reset is performed. is there. The “Lock-light” state can be set only when the host device designates the address of the block set in the “Lock” state and inputs “Lock-light block Command” (see block 1). ).

  The operation state of each block is held in the protection SRAM 65 as 2-bit data. FIG. 4 shows a correspondence table between data held in the SRAM cell and operation restrictions applied to each block. In the present embodiment, for example, the data “11” is associated with the “Lock” state, the data “10” is associated with the “UnLock” state, and the data “01” is associated with the “Lock-high” state. The data “00” is “Reserve”.

  In this embodiment, a case where writing and erasing are simultaneously permitted / prohibited for each block will be described. For example, writing is permitted and erasing is prohibited, erasing is permitted, and writing is performed. It is also possible to separately define a state in which the password is prohibited. If there is one new state to be defined, the data “00” that is “Reserve” may be used. If there are two or more states to be newly defined, data of 3 bits or more may be associated.

  FIG. 5 schematically shows the correspondence between each block constituting the memory cell array 10 and the SRAM cell associated with the block address of each block. In this embodiment, since the operation state (protection state) of each block is determined by 2 bits, for example, the state of the block 0 may be determined by cell0 and cell1 of the protection SRAM 65. The state of the block 1 may be determined by the cells 2 and 3 of the protection SRAM 65. When n blocks exist in the memory cell array 10, the number of SRAM cells necessary to determine the operation state of each block is 2n.

<Operation example using the protect function>
An operation example when data written in the data RAM of the RAM unit 3 is written into the NAND flash memory 2 (program) will be described below.

  When the host device makes a write request to the NAND flash memory 2, the block address of the block including the memory cell transistor MT to be written is input to the memory system 1 and set in the register 60. The access controller 50 that has received a write request from the host device sets a program command in the register 60.

  Next, the state machine 65 that has received the program command for the block via the command user interface 61 reads the 2-bit data indicating the protection state of the block to be written from the protection SRAM 65 and sets it in the register 60. The register 60 decodes the data indicating the protected state, and the state machine 62 that receives the decoding result determines whether or not to write to the NAND flash memory 2.

  For example, when the data read from the protection SRAM 65 is “11”, writing to the block is prohibited, so the state machine 62 does not issue a write request to the NAND flash memory 2 and the writing is an error. It becomes. If the data read from the protect SRAM 65 is “10”, writing to the block is permitted, and the state machine 62 issues a write request to the NAND flash memory 2. If the data read from the protection SRAM 65 is “01”, writing to the block is prohibited, so the state machine 62 does not issue a write request to the NAND flash memory 2 and writing is an error. It becomes.

  Also, when the host device makes an erase request to the NAND flash memory 2, the same processing as described above is performed.

<Protect SRAM Configuration Example 1>
FIGS. 6A, 6B, and 6C show layout images when the SRAM having protection information and the other data holding SRAM have the same operation (when there is a possibility of simultaneous access). In such a case, since the peripheral circuit of the SRAM cell cannot be shared, it is necessary to separately configure the protection SRAM and the other data holding SRAM as shown in FIG.

  In FIG. 6B, the SRAM cell SC2 is connected to the sense amplifier SA via the selector S. In this embodiment, since the operation state of each block is limited by 2-bit data, the sense amplifier SA is also arranged for 2 bits corresponding to this. The selector S switches cells according to the block address specified by the host device and connects to the sense amplifier SA.

  Considering the layout and work efficiency, if the SRAM having the protection information has the same operation as another SRAM, for example, the SRAM that exchanges data with the outside, the block of the NAND flash memory can be configured as shown in FIG. Even when the number is changed, it is possible to cope with the problem by changing only the capacity of the memory cell without changing the portion other than the SRAM cell region.

  For example, even if the capacity of the SRAM cell is reduced as shown in FIG. 6B from FIG. 6A, it is not necessary to change the configuration of the selector S and the sense amplifier SA. Similarly, even when the capacity of the SRAM cell is increased as shown in FIGS. 6B to 6C, it is not necessary to change the configuration of the select S and the sense amplifier SA.

<Protection SRAM Configuration Example 2>
FIG. 7 shows a layout image when the SRAM having protection information and the other data holding SRAM do not have the same operation (there is no possibility of simultaneous access) and can be operated independently. In such a case, since the peripheral circuit of the SRAM cell can be shared, unlike FIG. 1, it is possible to arrange the protection SRAM and the other data holding SRAM in the same area.

  FIG. 7 shows an example in which a protection SRAM is arranged in the same area as the SRAM 30 in the RAM unit 3 shown in FIG. In FIG. 7, the protection SRAM and the data RAM 0 can be selected independently by the row decoder 34 and share the sense amplifier 33. The selector S outputs the read data to the data bus as it is when accessing the data RAM0. The selector S selects 2-bit data corresponding to the access target block in the NAND flash memory 2 and outputs the selected data to the data bus when accessing the protection SRAM.

  That is, when an SRAM having protect information does not have the same operation as another data holding SRAM, a control circuit such as a sense amplifier is shared with another SRAM by providing the protect information in a redundant area of the other SRAM. Therefore, the layout can be reduced.

<Effect>
As described above, since the memory system 1 according to the present embodiment holds the protect information of each block in the SRAM in the memory system 1, the protect information for each block is set while minimizing the area penalty. It is possible. Therefore, protect information can be stored for an arbitrary block, and user convenience can be maintained at the same time.

  As described above, the present invention has been described using this embodiment, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention in the implementation stage. . Further, the present embodiment includes inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent elements are deleted from all the constituent elements shown in the present embodiment, at least one of the problems described in the column of the problem to be solved by the invention can be solved, and described in the column of the effect of the invention. In a case where at least one of the obtained effects can be obtained, a configuration in which this configuration requirement is deleted can be extracted as an invention.

The block diagram which shows the structure of a memory system. The equivalent circuit diagram of the memory cell array of NAND type flash memory. The schematic diagram which shows the transition of the operation state of each block which comprises the memory cell array of NAND type flash memory. 5 is a correspondence table between data held in an SRAM cell and operation restrictions applied to each block. The schematic diagram which shows the SRAM cell matched with the block address of each block. FIG. 3 is a block diagram showing a configuration example of a protection SRAM. FIG. 3 is a block diagram showing a configuration example of a protection SRAM.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Memory system 2 NAND type flash memory 3 RAM part 4 Controller part 10 Memory cell array 11 Row decoder 12 Page buffer 13 Voltage generation circuit 14 Sequencer 15 and 16 Oscillator 17 1st area | region 18 2nd area | region 19 Memory cell unit 20 ECC part 21 ECC Buffer 22 ECC engine 30 SRAM
31 DQ buffer 32 Memory cell array 33 Sense amplifier 34 Row decoder 40 Interface unit 41, 42 Burst buffer 43 Interface 50 Access controller 60 Register 61 Command user interface 62 State machine 63 Address / command setting circuit 64 Address / timing generation circuit 65 Protecting SRAM
MT Memory cell transistor ST Select transistor SGD, SGS Select gate line WL Word line BL Bit line SL Source line SC1 SRAM cell S Selector SA Sense amplifier

Claims (5)

A non-volatile memory having a plurality of blocks, which are the smallest unit capable of independently erasing data, and
A volatile memory that functions as a buffer for the nonvolatile memory;
A protection SRAM capable of holding protection information that restricts operations that can be performed on each of the blocks;
A register capable of reading out and setting the protection information corresponding to a block address inputted from the outside from the protection SRAM;
Based on the protection information set in the register, a control unit that determines whether or not to restrict the operation requested for the block;
A semiconductor memory device comprising:   2. The semiconductor memory device according to claim 1, wherein the protect information includes information for restricting an erasing operation of data held in the block.   3. The semiconductor memory device according to claim 2, wherein the protect information includes information for restricting an operation of writing data held in the volatile memory to the block.   4. The semiconductor memory device according to claim 3, wherein the protection information is 2-bit data, and the protection SRAM is connected to a 2-bit sense amplifier circuit via a selector.   2. The semiconductor memory device according to claim 1, wherein the volatile memory is an SRAM, and the protection SRAM shares a sense amplifier with the volatile memory.

Images